S34ML08G1
General Description
The SkyHigh S34ML08G1 8-Gb NAND is offered in 3.3 VCC
with x8 I/O interface. This document contains information for
the S34ML08G1 device, which is a dual-die stack of two S34ML04G1 die. For detailed specifications,
please refer to the
discrete diedatasheet:
S34ML04G1.
Distinctive Characteristics
Density
– 8 Gb (4 Gb 2)
Architecture (For each 4 Gb device)
– Input / Output Bus Width: 8-bits
– Page Size: (2048 + 64) bytes; 64 bytes is spare area
– Block Size: 64 Pages or (128k + 4k) bytes
– Plane Size
– 2048 Blocks per Plane or (256M + 8M) bytes
–Device Size
– 2 Planes per Device or 512 Mbyte
NAND Flash Interface
– Open NAND Flash Interface (ONFI) 1.0 compliant
– Address, Data and Commands multiplexed
Supply Voltage
– 3.3 V device: Vcc = 2.7 V ~ 3.6 V
Security
– One Time Programmable (OTP) area
– Hardware program/erase disabled during power transition
Additional Features
– Supports Multiplane Program and Erase commands
– Supports Copy Back Program
– Supports Multiplane Copy Back Program
– Supports Read Cache
Electronic Signature
– Manufacturer ID: 01h
Operating Temperature
– Industrial: 40 °C to 85 °C
– Automotive: 40 °C to 105 °C
Performance
Page Read / Program
– Random access: 25 µs (Max)
– Sequential access: 25 ns (Min)
– Program time / Multiplane Program time: 200 µs (Typ)
Block Erase / Multiplane Erase (S34ML04G1)
– Block Erase time: 3.5 ms (Typ)
Reliability
– 100,000 Program / Erase cycles (Typ)
(with 1 bit / 512 + 16 byte ECC)
– 10 Year Data retention (Typ)
– Blocks zero and one are valid and will be valid for at least
1000 program-erase cycles with ECC
Package Options
– Lead Free and Low Halogen
– 48-Pin TSOP 12 20 1.2 mm
– 63-Ball BGA 9 11 1 mm
SkyHigh Memory Limited
Document Number: 002-00483 Rev. *L
Suite 4401-02, 44/F One Island East,
18 Westlands Road Hong Kong
www.skyhighmemory.com
Revised May 06, 2019
8Gb, 3 V, 1-bit ECC, x8 I/O, SLC NAND
Flash Memory for Embedded
S34ML08G1
Contents
Connection Diagram1. .................................................... 3
Pin Description2. ............................................................. 5
3. Block Diagrams............................................................ 6
4. Addressing ................................................................... 8
5. Read Status Enhanced ................................................ 8
6. Extended Read Status................................................. 8
7. Read ID.......................................................................... 9
7.1 Read Parameter Page ................................................. 10
8. Electrical Characteristics........................................... 12
8.1 Valid Blocks .................................................................. 12
8.2 Recommended Operating Conditions........................... 12
8.3 DC Characteristics........................................................ 13
8.4 Pin Capacitance............................................................ 13
Power Consumptions and Pin Capacitance8.5
for Allowed Stacking Configurations ............................. 13
Physical Interface9. ....................................................... 14
Physical Diagram............................................9.1 .............. 14
Ordering Information10. .................................................. 16
Appendix A — Errata11. .................................................. 17
Document History12. ....................................................... 18
Document Number: 002-00483 Rev. *L
Page 2 of 19
S34ML08G1
1. Connection Diagram
Figure 1.1 48-Pin TSOP1 Contact x8 Device (1 CE 8 Gb)
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Figure 1.2 48-Pin TSOP1 Contact x8 Device (2 CE 8 Gb)
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
VSS
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
VCC
NC
VCC
VSS
NC
VCC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
VSS
12
13
37
36
25
481
24
NAND Flash
TSOP1
(x8)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Document Number: 002-00483 Rev. *L
Page 3 of 19
S34ML08G1
Figure 1.3 63-BGA Contact, x8 Device, Single CE (Top View)
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
F8F4F3 F7F5 F6
E8E4E3 E7E5 E6
D7D6D5D4D3 D8
C3 C4 C5 C6 C7 C8
RB#WE#CE#VSSALEWP#
NCNCNCCLERE#VCC
NCNCNCNCNCNC
G4G3 G7G5 G6 G8
NCVSSNCNCNCNC
H3 H4 H5 H6 H7 H8
Vcc
NCNCNCI/O0NC
B9
A9
NC
NC
A2
NC
NCNCNCNCVCCNC
B10
A10
NC
NC
B1
A1
NC
NC
J3 J4 J5 J6 J7 J8
I/O7I/O5VCC
NCI/O1NC
K3 K4 K5 K6 K7 K8
VSS
I/O6I/O4I/O3I/O2VSS
L9
NC
L2
NC
L10
NC
L1
NC
M9
NC
M2
NC
M10
NC
M1
NC
(1)
(1)
(1)
Document Number: 002-00483 Rev. *L
Page 4 of 19
S34ML08G1
2. Pin Description
Notes:
1. A 0.1 µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB
track widths must be sufficient to carry the currents required during program and erase operations.
2. An internal voltage detector disables all functions whenever VCC is below 1.8V to protect the device from any involuntary program/erase during power transitions.
Table 2.1 Pin Description
DescriptionPin Name
I/O0 - I/O7 Inputs/Outputs. The I/O pins are used for command input, address input, data input, and data output. The
I/O pins float to High-Z when the device is deselected or the outputs are disabled.
CLE Command Latch Enable. This input activates the latching of the I/O inputs inside the Command Register on the rising
edge of Write Enable (WE#).
ALE Address Latch Enable. This input activates the latching of the I/O inputs inside the Address Register on the rising
edge of Write Enable (WE#).
CE# Chip Enable. This input controls the selection of the device. When the device is not busy CE# low selects the memory.
WE# Write Enable. This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of WE#.
RE# Read Enable. The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE# which also increments the internal column address counter by one.
WP# Write Protect. The WP# pin, when low, provides hardware protection against undesired data modification
(program / erase).
R/B# Ready Busy. The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VCC Supply Voltage. The VCC supplies the power for all the operations (Read, Program, Erase). An internal lock circuit
prevents the insertion of Commands when VCC is less than VLKO.
VSS Ground.
NC Not Connected.
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Page 5 of 19
S34ML08G1
3. Block Diagrams
Figure 3.1 Functional Block Diagram — 4 Gb
Address
Register/
Counter
Controller
Command
Interface
Logic
Command
Register
Data
Register
RE#
I/O Buffer
Y Decoder
Page Buffer
X
D
E
C
O
D
E
R
NAND Flash
Memory Array
WP#
CE#
WE#
CLE
ALE
I/O0~I/O7
Program Erase
HV Generation
4096 Mbit + 128 Mbit (4 Gb Device)
Document Number: 002-00483 Rev. *L
Page 6 of 19
S34ML08G1
Figure 3.2 Block Diagram — 1 CE (4 Gb x 8)
Figure 3.3 Block Diagram — 2 CE (4 Gb x 8)
IO0~IO7
CE#
WE# R/B#
RE#
VSS
ALE
VCC
CLE
WP#
IO0~IO7 IO0~IO7
CE# CE#
WE# R/B#WE# R/B#
RE# RE#
VSS VSS
ALE ALE
VCC VCC
CLE CLE
WP# WP#
4 Gb x8
NAND Flash
Memory#1
4 Gb x8
NAND Flash
Memory#2
IO0~IO7
CE#2 CE#
WE# R/B# R/B#2
RE#
VSS
ALE
VCC
CLE
WP#
IO0~IO7 IO0~IO7
CE#1 CE#
WE# WE# R/B# R/B#1
RE# RE#
VSS VSS
ALE ALE
VCC VCC
CLE CLE
WP# WP#
4 Gb x8
NAND Flash
Memory#1
4 Gb x8
NAND Flash
Memory#2
Document Number: 002-00483 Rev. *L
Page 7 of 19
S34ML08G1
4. Addressing
Notes:
1. CAx = Column Address bit.
2. PAx = Page Address bit.
3. PLA0 = Plane Address bit zero.
4. BAx = Block Address bit.
5. Block address concatenated with page address and plane address = actual page address, also known as the row address.
6. A30 for 8 Gb (4 Gb x 2 – DDP) (1CE).
For the address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18: plane address (for multiplane operations) / block address (for normal operations)
A19 - A30: block address
5. Read Status Enhanced
Read Status Enhanced is used to retrieve the status value for a previous operation in the following cases:
In the case of concurrent operations on a multi-die stack.
When two dies are stacked to form a dual-die package (DDP), it is possible to run one operation on the first die, then activate a
different operation on the second die, for example: Erase while Read, Read while Program, etc.
In the case of multiplane operations in the same die.
6. Extended Read Status
Multi-die stack devices support the Extended Read Status operation. When two operations are active in separate dies at the same
time, this feature allows the host to check the status of a given die. For example, the first die could be executing a Page Program
while the second die is performing a Page Read. Refer to Table 6.1 for a description of each command.
Table 4.1 Address Cycle Map
I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0Bus Cycle
A5 (CAA4 (CA4)A3 (CA3)A2 (CA2)A1 (CA1)A0 (CA0)1st / Col. Add. 1 A7 (CA7)A6 (CA6)5)
LLowLowLowA11 (CA11)A10 (CA10)A9 (CA9)A8 (CA8)2nd / Col. Add. 2 ow
A1A16 (PA4)A15 (PA3)A14 (PA2)A13 (PA1)A12 (PA0)3rd / Row Add. 1 A19 (BA0)A18 (PLA0)7 (PA5)
A2A24 (BA5)A23 (BA4)A22 (BA3)A21 (BA2)A20 (BA1)4th / Row Add. 2 A27 (BA8)A26 (BA7)5 (BA6)
5th / Row Add. 3
(6) LowLowLowLowLowA30 (BA11)A29 (BA10)A28 (BA9)
Table 6.1 Extended Read Status
Row Address with 4 Gb DiesDieCommand
0 to 3FFFFhFirstF2h
40000h to 7FFFFhSecondF3h
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Page 8 of 19
S34ML08G1
7. Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h.
Note: If you want to execute Read Status command (0x70) after Read ID sequence, you should input dummy command (0x00)
before Read Status command (0x70).
For the S34ML04G1 device, five read cycles sequentially output the manufacturer code (01h), and the device code and 3rd, 4th, and
5th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it.
Note:
1. See See Appendix A — Errata on page 17. for information on READ ID in MCPs.
Figure 7.1 Read ID Operation Timing — 8 Gb
Table 7.1 Read ID for Supported Configurations (1)
VOrgDensity CC 5th4th3rd2nd1st
54h95h90hDCh01h3.3Vx84 Gb
8 Gb
(4 Gb x 2 – DDP with
two CE#)
54h95h90hDCh01h3.3Vx8
8 Gb
(4 Gb x 2 – DDP with
one CE#) (1)
58h95hD1hD3h01h3.3Vx8
CE#
WE#
CLE
RE#
ALE
tWHR
tAR
tREA
Read ID
Command
Address 1
Cycle
Maker
Code
Device
Code
3rd Cycle 4th Cycle 5th Cycle
I/Ox 01h D3h D1h 95h
8 Gb Device
(4 Gb x 2 - DDP with one CE#)
58h
90h 00h
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Page 9 of 19
S34ML08G1
5th ID Data
Table 7.2 Read ID Byte 5 Description — S34ML04G1
I/O0I/O1I/O3 I/O2I/O6 I/O5 I/O4I/O7Description
Plane Number
1
2
4
8
0 0
0 1
1 0
1 1
Plane Size
(without spare area)
64 Mb
128 Mb
256 Mb
512 Mb
1 Gb
2 Gb
4 Gb
8 Gb
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
000Reserved
7.1
Read Parameter Page
The device supports the ONFI Read Parameter Page operation, initiated by writing ECh to the command register, followed by an
address input of 00h. The command register remains in Parameter
Page mode until further commands are issued to it.
Table
7.3
explains the parameter fields.
Note:
For 41nm 2Gb/4Gb SkyHigh NAND, for a particular condition, the
Read Parameter Page command
does not give the
correct values. To overcome this issue, the host must issue a Reset command before the Read Parameter Page command.
Issuance of
Reset before the Read Parameter Page command will provide the correct values and will not output 00h values. This
does not apply to 48nm 1Gb.
Table 7.3
Parameter Page Description (Sheet 1 of 3)
ValuesDescriptionO/MByte
Revision Information and Features Block
M0-3
Parameter page signature
Byte 0: 4Fh, “O”
Byte 1: 4Eh, “N”
Byte 2: 46h, “F”
Byte 3: 49h, “I”
4Fh, 4Eh, 46h, 49h
M4-5
Revision number
Reserved (0)2-15
1 = supports ONFI version 1.01
0 Reserved (0)
02h, 00h
M6-7
Features supported
5-15 Reserved (0)
4 1 = supports odd to even page Copyback
3 1 = supports interleaved operations
2 1 = supports non-sequential page programming
1 1 = supports multiple LUN operations
0 1 = supports 16-bit data bus width
1Eh, 00h
M8-9
Optional commands supported
6-15 Reserved (0)
5 1 = supports Read Unique ID
4 1 = supports Copyback
3 1 = supports Read Status Enhanced
2 1 = supports Get Features and Set Features
1 1 = supports Read Cache commands
0 1 = supports Page Cache Program command
1Bh, 00h
00hReserved (0)10-31
Document Number: 002-00483 Rev. *L
Page 10 of 19
S34ML08G1
Manufacturer Information Block
Device manufacturer (12 ASCII characters)M32-43 53h, 50h, 41h, 4Eh, 53h, 49h,
4Fh, 4Eh, 20h, 20h, 20h, 20h
Device model (20 ASCII characters)M44-63
53h, 33h, 34h, 4Dh, 4Ch, 30h,
38h, 47h, 31h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h
01hJEDEC manufacturer IDM64
00hDate codeO65-66
00hReserved (0)67-79
Memory Organization Block
00h, 08h, 00h, 00hNumber of data bytes per pageM80-83
40h, 00hNumber of spare bytes per pageM84-85
00h, 02h, 00h, 00Number of data bytes per partial pageM86-89 h
10h, 00hNumber of spare bytes per partial pageM90-91
40h, 00h, 00h, 00hNumber of pages per blockM92-95
00h, 10h, 00h,Number of blocks per logical unit (LUN)M96-99 00h
02hNumber of logical units (LUNs)M100
M101
Number of address cycles
Column address cycles4-7
Row address cycles0-3
23h
01hNumber of bits per cellM102
50h, 00hBad blocks maximum per LUNM103-104
01h, 05hBlock enduranceM105-106
01hGuaranteed valid blocks at beginning of targetM107
01h, 03hBlock endurance for guaranteed valid blocksM108-109
04hNumber of programs per pageM110
M111
Partial programming attributes
Reserved5-7
1 = partial page layout is partial page data followed by4
partial page spare
1-3 Reserved
0 1 = partial page programming has constraints
00h
01hNumber of bits ECC correctabilityM112
M113
Number of interleaved address bits
Reserved (0)4-7
Number of interleaved address bits0-3
01h
O114
Interleaved operation attributes
4-7 Reserved (0)
3 Address restrictions for program cache
2 1 = program cache supported
1 1 = no block address restrictions
0 Overlapped / concurrent interleaving support
04h
00hReserved (0)115-127
Electrical Parameters Block
0AhI/O pin capacitanceM128
M129-130
Timing mode support
Reserved (0)6-15
1 = supports timing mode 55
1 = supports timing mode 44
1 = supports timing mode 33
1 = supports timing mode 22
1 = supports timing mode 11
1 = supports timing mode 0, shall be 10
1Fh, 00h
Table 7.3 Parameter Page Description (Sheet 2 of 3)
ValuesDescriptionO/MByte
Document Number: 002-00483 Rev. *L
Page 11 of 19
S34ML08G1
Note:
1. O” Stands for Optional, “M” for Mandatory.
8. Electrical Characteristics
8.1 Valid Blocks
Note:
1. Each 4 Gb has maximum 80 bad blocks.
8.2 Recommended Operating Conditions
O131-132
Program cache timing mode support
Reserved (0)6-15
1 = supports timing mode 55
4 1 = supports timing mode 4
3 1 = supports timing mode 3
2 1 = supports timing mode 2
1 1 = supports timing mode 1
0 1 = supports timing mode 0
1Fh, 00h
tM133-134 PROG BCh, 02hMaximum page program time (µs)
tM135-136 BERS 10h, 27hMaximum block erase time (µs)
tM137-138 R19h, 00hMaximum page read time (µs)
tM139-140 CCS 64h, 00hMinimum Change Column setup time (ns)
00hReserved (0)141-163
Vendor Block
00hVendor specific Revision numberM164-165
00hVendor specific166-253
7Bh, 09hIntegrity CRCM254-255
Redundant Parameter Pages
Repeat Value of bytes 0-255Value of bytes 0-255M256-511
Repeat Value of bytes 0-255Value of bytes 0-255M512-767
FFhAdditional redundant parameter pagesO768+
Table 8.1 Valid Blocks — 4 Gb
UnitMaxTypMinSymbolDevice
NS34ML04G1 VB Blocks4096—4016
NS34ML08G1 VB 8032 (1) Blocks8192—
Table 8.2 Recommended Operating Conditions
UnitsMaxTypMinSymbolParameter
V3.63.32.7VccVcc Supply Voltage
V000VssGround Supply Voltage
Table 7.3 Parameter Page Description (Sheet 3 of 3)
ValuesDescriptionO/MByte
Document Number: 002-00483 Rev. *L
Page 12 of 19
S34ML08G1
DC Characteristics8.3
Notes:
1. All VCC pins, and VSS pins respectively, are shorted together.
2. Values listed in this table refer to the complete voltage range for VCC and to a single device in case of device stacking.
3. All current measurements are performed with a 0.1 µF capacitor connected between the VCC Supply Voltage pin and the VSS Ground pin.
4. Standby current measurement can be performed after the device has completed the initialization process at power-up.
8.4 Pin Capacitance
Note:
1. For the stacked devices version the Input is 10 pF x [number of stacked chips] and the Input/Output is 10 pF x [number of stacked chips].
8.5 Power Consumptions and Pin Capacitance for Allowed Stacking
Configurations
When multiple dies are stacked in the same package, the power consumption of the stack will increase according to the number of
chips. As an example, the standby current is the sum of the standby currents of all the chips, while the active power consumption
depends on the number of chips concurrently executing different operations.
When multiple dies are stacked in the same package the pin/ball capacitance for the single input and the single input/output of the
combo package must be calculated based on the number of chips sharing that input or that pin/ball.
Table 8.3 DC Characteristics and Operating Conditions
(Values listed are for each 4 Gb NAND, 8 Gb (4 Gb x 2) will be additive accordingly)
UnitsMaxTypMinTest ConditionsSymbolParameter
IPower-On Current CC0 mA3015—Power up Current
Operating Current
ISequential Read CC1
tRC = tRC (min), CE# =
VIL,
IOUT = 0 mA
mA3015—
IProgram CC2
mA30——Normal
mA40——Cache
IErase CC3 mA3015——
IStandby current, (TTL) CC4
CE# = VIH,
WP# = 0V/Vcc mA1——
IStandby current, (CMOS) CC5
CE# = VCC-0.2,
WP# = 0/VCC
µA5010—
IInput Leakage Current LI VIN µA±10——= 0 to 3.6V
IOutput Leakage Current LO VOUT µA±10——= 0 to 3.6V
VInput High Voltage IH V— CC V—x 0.8 CC V+ 0.3
VInput Low Voltage IL V—-0.3— CC Vx 0.2
VOutput High Voltage OH IOH V——2.4= -400 µA
VOutput Low Voltage OL IOL V0.4——= 2.1 mA
IOutput Low Current (R/B#) OL(R/B#) VOL mA—108= 0.4V
VErase and Program Lockout Voltage LKO V—1.8——
Table 8.4 Pin Capacitance (TA = 25°C, f=1.0 MHz)
UnitMaxMinTest ConditionSymbolParameter
CInput IN VIN pF10—= 0V
CInput / Output IO VIL pF10—= 0V
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Page 13 of 19
S34ML08G1
9. Physical Interface
9.1 Physical Diagram
9.1.1 48-Pin Thin Small Outline Package (TSOP1)
Figure 9.1 48-pin TSOP (18.4 × 12.0 × 1.2 mm) Package Outline, 51-85183
51-85183 *F
4
5
SEE DETAIL A
SEE DETAIL B
STANDARD PIN OUT (TOP VIEW)
REVERSE PIN OUT (TOP VIEW)
3
2X (N/2 TIPS)
B
B
N/2
0.20
D
D1
A
1
2
5
E
A
N/2 +1
2X
2X
B
N
0.10
0.10
SEATING PLANE
C
A1
e9
2X (N/2 TIPS)
0.10 C
A2
DETAIL A
A-BC0.08MM M
SECTION B-B
7c
b1
SEATING PLANE
PARALLEL TO
b6
0°
DETAIL B
BASE METAL
e/2
X = A OR B
X
GAUGE PLAN
E
0.25 BASIC
WITH PLATING
7
L
C
R
(c)
8
c1
1N
N/2 N/2 +1
3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS (mm).
2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
1.051.000.95
A2
N
R
0
L
e
c
D1
E
D
b
c1
b1
0.50 BASIC
0.60
0°
0.08
0.50
48
0.20
8
0.70
0.22
0.20
20.00 BASIC
18.40 BASIC
12.00 BASIC
0.10
0.17
0.10
0.17
0.21
0.27
0.16
0.23
A1
A
0.05 0.15
1.20
SYMBOL
MAX.MIN.
DIMENSIONS
NOM.
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
0.10mm AND 0.25mm FROM THE LEAD TIP.
SEATING PLANE.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
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Page 14 of 19
S34ML08G1
63-Pin Ball Grid Array (BGA)9.1.2
Figure 9.2 63-ball VFBGA (11.00 × 9.00 × 1.00 mm) Package Outline, 002-19064
002-19064 **
Document Number: 002-00483 Rev. *L
Page 15 of 19
S34ML08G1
10. Ordering Information
The ordering part number is formed by a valid combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
Note:
1. BGA package marking omits the leading “S34” and the Packing Type designator from the ordering part number.
000IFT01108GS34ML
Packing Type
0
=
Tray
3
=
13” Tape and Reel
Model Number
00
=
Standard Interface / ONFI (x8)
20
=
Two Chip Enables with Standard ONFI (x8)
Temperature Range
A
= Industrial with AECQ-100 and GT Grade (-40˚C to +85˚C)
B
= Industrial Plus with AECQ-100 and GT Grade (-40˚C to +105˚C)
I
= Industrial (–40°C to + 85°C)
V
= Industrial Plus (–40°C to + 105°C)
Materials Set
F
=
Lead (Pb)-free
H
=
Lead (Pb)-free and Low Halogen
Package
B
=
BGA
T
=
TSOP
Bus Width
00
=
x8 NAND, single die
04
=
x16 NAND, single die
01
=
x8 NAND, dual die
05
=
x16 NAND, dual die
Technology
1
=
SkyHigh NAND Revision 1 (4x nm)
Density
01G=1
Gb
02G=2
Gb
04G=4
Gb
08G=8
Gb
Device Family
S34ML
SkyHigh SLC NAND Flash Memory for Embedded
Valid Combinations
Device
Family TechnologyDensity Bus
Width
Package
Type
Temperature
Range
Additional
Ordering Options
Packing
Type
Package
Description
01108GS34ML TF A, B, I, V 00, 20 0, 3 TSOP
BGA00BH (1)
Document Number: 002-00483 Rev. *L
Page 16 of 19
S34ML08G1
11.
Appendix A — Errata
For SkyHigh NAND MCPs
(Multi-Chip Package)
like the 8 Gb (2 x 4
Gb), due to the internal bonding, READ ID automatically
changes to the hard-wired values and currently there is no way
to change it electrically. Therefore, the SkyHigh NAND 8 Gb with
one
CE# will not follow the same methodology of READ ID as SDPs (Single Die Package). The READ ID values for the 8-Gb
SkyHigh NAND with one CE#
will be as follows:
1st Byte: 01h
2nd Byte: D3h
3rd Byte: D1h
4th Byte: 95h
5th Byte: 58h
Currently, SkyHigh does not plan to fix the problem. If there are any issues related to this,
please contact SkyHigh
NAND Product Marketing for further questions.
5th Byte4th Byte3rd Byte2nd Byte1st Byte
8 Gb with one CE#
(Currently with error) 58h95hD1hD3h01h
8 Gb with one CE#
(SkyHigh methodology) 54h95h91hDCh01h
Document Number: 002-00483 Rev. *L
Page 17 of 19
S34ML08G1
12. Document History
Document Title: S34ML08G1, 8 Gb, 1-bit ECC, ×8 I/O, 3 V VCC, NAND Flash Memory for Embedded
Document Number: 002-00483
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Initial release08/23/2012XILA–**
Addressing:10/01/2012XILA–*A
Address Cycle Map table: corrected data
Read ID:
Read ID for Supported Configurations table: added row – 8 Gb (4 Gb x 2 –
DDP with two CE#)
Read Parameter Page:
Parameter Page Description table
corrected Electrical Parameters Block values for bytes 129-130 and bytes
131-132
corrected Vendor Block values for bytes 254-255
Appendix A:
Added text
Ordering Information:11/29/2012XILA–*B
Added Model Number
Read Parameter Page:12/19/2012XILA–*C
Parameter Page Description table
corrected Description for Bytes 129-130 and bytes 131-132
DC Characteristics:
DC Characteristics and Operating Conditions table
corrected Test Conditions for ICC1
Output High Voltage: removed IOH = 100 µA row
Output Low Voltage: removed IOL = 100 µA row
Output Low Current (R/B#): removed VOL = 0.1V row
Ordering Information:
Valid Combinations table: removed Bus Width 05
Distinctive Characteristics:08/09/2013XILA–*D
Security - Removed Serial number (unique ID)
Operating Temperature - removed Commercial and Extended temperatures
Performance:
Updated Reliability
Connection Diagram:
Added figure - 48-Pin TSOP1 Contact x8 Device (1 CE 8 Gb)
Addressing:
Address Cycle Map table - appended Note
Added text to Bus Cycle column
Extended Read Status:
Extended Read Status table - removed Commands F4h and F5h
Read Parameter Page:
Parameter Page Description table - corrected Byte 44-63, 100, and 254-255
Values
Valid Blocks:
Valid Blocks table - clarified Device values
Document Number: 002-00483 Rev. *L
Page 18 of 19
S34ML08G1
08/09/201XILA–*D (cont.) DC Characteristics:3
DC Characteristics and Operating Conditions table - added row, ‘VCC Supply
Voltage’
Physical Interface:
Updated figures
TS2 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package
Outline
VLD063 — 63-Pin BGA, 11 mm x 9 mm Package
Ordering Information:
Updated Materials Set: H = Low Halogen to H = Lead (Pb)-free and Low
Halogen
Valid Combinations table: removed 04G; Added Note
Order04/01/2014XILA–*E ing Information:
Updated Temperature Range to include A (-40°C to 85°C GT Grade), B (-
40°C to 105°C GT Grade), and V (-40°C to 105°C)
Valid Combinations table - added A, B, V to Temperature Range
Global:01/14/2015XILA–*F
Changed data sheet designation from Advance Information to Full
Production
Updated10/14/2015XILA4953915*G to Cypress template.
Updated11/20/2015XILA5022236*H General Description:
Updated description.
Completing Sunset Review.
Updated04/25/2016XILA5160512*I Read ID:
Updated Read Parameter Page:
Updated description.
Updated Electrical Characteristics:
Added Recommended Operating Conditions.
Updated DC Characteristics:
Updated Table 8.3 (Replaced “VCC supply Voltage (erase and program
lockout)” with “Erase and Program Lockout voltage”).
Updated Ordering Information:
Updated details.
Updated to new template.
U06/13/2017AESATMP85770454*J pdated logo and Copyright.
Updated01/23/2019MNAD6455270*K Physical Interface:
Updated Physical Diagram:
Updated 48-Pin Thin Small Outline Package (TSOP1):
Removed existing spec (f16-038).
Added spec 51-85183 *F.
Updated 63-Pin Ball Grid Array (BGA):
Removed existing spec (16-038.28).
Added spec 002-19064 **.
Updated to new template.
Completing Sunset Review.
Document Title: S34ML08G1, 8 Gb, 1-bit ECC, ×8 I/O, 3 V VCC, NAND Flash Memory for Embedded
Document Number: 002-00483
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 002-00483 Rev. *L
Page 19 of 19
*L MNAD 05/06/2019 Updated to SkyHigh format