MCF54451CVM180 - FREESCALE - Datasheet.Directory

Freescale Semiconductor

Data Sheet: Advance Information Document Number: MCF54455

Rev. 8, 02/2012

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

MCF54455

MAPBGA–256

17mm x 17mm TEPBGA–360

23mm x 23mm

Features

• Version 4 ColdFire Core with MMU and EMAC

• Up to 410 Dhrystone 2.1 MIPS @ 266 MHz

• 16-KBytes instruction cache and 16-KBytes data cache

• 32-KBytes internal SRAM

• Support for booting from SPI-compatible flash, EEPROM,

and FRAM devices

• Crossbar switch technology (XBS) for concurrent access to

peripherals or RAM from multiple bus masters

• 16-channel DMA controller

• 16-bit 133-MHz DDR/mobile-DDR/DDR2 controller

• USB 2.0 On-the-Go controller with ULPI su pport

• 32-bit PCI controller @ 66MHz

• ATA/ATAPI controller

• 2 10/100 Ethernet MACs

• Coprocessor for acceleration of the DES, 3DES, AES,

MD5, and SHA-1 algorithms

• Random number generator

• Synchronous serial interface (SSI)

• 4 periodic interrupt timers (PIT)

• 4 32-bit timers with DMA support

• DMA-supported serial peripheral interface (DSPI)

• 3 UARTs

•I

2C bus interface

MCF5445x ColdFire

Microprocessor Data Sheet

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor2

Table of Contents

1 MCF5445x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4

2 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3 Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . . .5

3.1 Analog Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.2 Oscillator Power Filtering . . . . . . . . . . . . . . . . . . . . . . . .6

3.3 Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . .6

3.3.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . .7

3.3.2 Power-Down Sequence. . . . . . . . . . . . . . . . . . . .7

4 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .7

4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4.2 Pinout—256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .15

4.3 Pinout—360 TEPBGA. . . . . . . . . . . . . . . . . . . . . . . . . .16

5 Electrical Characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .17

5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18

5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .19

5.5 ClockTiming Specifications. . . . . . . . . . . . . . . . . . . . . .20

5.6 Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . .22

5.7 FlexBus Timing Specifications . . . . . . . . . . . . . . . . . . .23

5.8 SDRAM AC Timing Characteristics. . . . . . . . . . . . . . . .25

5.9 PCI Bus Timing Specifications . . . . . . . . . . . . . . . . . . .27

5.9.1 Overshoot and Undershoot . . . . . . . . . . . . . . . 28

5.10 ULPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 29

5.11 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 30

5.12 I2C Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 32

5.13 Fast Ethernet Timing Specifications . . . . . . . . . . . . . . 33

5.13.1 Receive Signal Timing Specifications . . . . . . . 33

5.13.2 Transmit Signal Timing Specifications . . . . . . . 34

5.13.3 Asynchronous Input Signal Timing

Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.13.4 MII Serial Management Timing Specifications. 35

5.14 32-Bit Timer Module Timing Specifications . . . . . . . . . 35

5.15 ATA Interface Timing Specifications. . . . . . . . . . . . . . . 36

5.16 DSPI Timing Specifications. . . . . . . . . . . . . . . . . . . . . 36

5.17 SBF Timing Specifications. . . . . . . . . . . . . . . . . . . . . . 38

5.18 General Purpose I/O Timing Specifications. . . . . . . . . 39

5.19 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 40

5.20 Debug AC Timing Specifications. . . . . . . . . . . . . . . . . 42

6 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 3

Figure 1. MCF54455 Block Diagram

Version 4 ColdFire Core

LEGEND

2 INTCs

DSPI

EPORT

3 UARTs

I2C

Watchdog

4 DMA

RTC

ATA – Advanced Technology Attachment Controller

BDM – Background debug module

CAU – Cryptography acceleration unit

DSPI – DMA serial peripheral interface

eDMA – Enhanced direct memory access

EMAC – Enchance multiply-accumulate unit

EPORT – Edge port module

FEC – Fast Ethernet controller

GPIO – General Purpose Input/Output

I2C– Inter-Intergrated Circuit

INTC – Interrupt controller

JTAG – Joint Test Action Group interface

MMU – Memory management unit

PCI – Peripheral Component Interconnect

PIT – Programmable interrupt timers

PLL – Phase locked loop module

RNG – Random Number Generator

RTC – Real time clock

SSI – Synchronous Serial Interface

USB OTG – Universal Serial Bus On-the-Go controller

MCF54455

EMAC 2 FECs

Crossbar Switch (XBS)

32K

SRAM

Peripheral Bridge

CAU

16K

Instruction

Cache

16K

Data

Cache

Timers

BDM

ATA SDRAM

Controller FlexBus

eDMA

USB OT G

4 PITs

SSI RNG GPIO

MMU

Hardware

Divide

Oscillator PLLJTAG

PCI Serial Boot

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

MCF5445x Family Comparison

Freescale Semiconductor4

1 MCF5445x Family Comparison

The following table compares the various device derivatives avail able wit hin the MCF5445x family.

Table 1. MCF5445x Family Configurations

Module MCF54450 MCF54451 MCF54452 MCF54453 MCF54454 MCF54455

ColdFire Version 4 Core with EMAC

(Enhanced Multiply-Accumulate Unit) ••••••

Core (System) Clock up to 240 MHz up to 266 MHz

Peripheral Bus Clock

(Core clock  2) up to 120 MHz up to 133 MHz

External Bus Clock

(Core clock  4) up to 60 MHz up to 66 MHz

Performance (Dhrystone/2.1 MIPS) up to 370 up to 410

Independent Data/Instruction Cache 16 Kbytes each

Static RAM (SRAM) 32 Kbytes

PCI Controller ——••••

Cryptography Acceleration Unit (CAU) — • — • — •

ATA Controller ———— • •

DDR SDRAM Controller ••••••

FlexBus External Interface ••••••

USB 2.0 On-the-Go ••••••

UTMI+ Low Pin Interface (ULPI) ••••••

Synchronous Serial Interface (SSI) ••••••

Fast Ethernet Controller (FEC) 112222

UARTs 333333

I2C ••••••

DSPI ••••••

Real Time Clock ••••••

32-bit DMA Timers 444444

Watchdog Timer (WDT) ••••••

Periodic Interrupt Timers (PIT) 444444

Edge Po rt Module (EPORT) ••••••

Interrupt Controllers (INTC) 222222

16-channel Direct Memory Access (DMA)••••••

General Purpose I/O (GPIO) ••••••

JTAG - IEEE® 1149.1 Test Access Port ••••••

Package 256 MAPBGA 360 TEPBGA

Ordering Information

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 5

2 Ordering Information

3 Hardware Design Considerations

3.1 Analog Power Filtering

To further enhance noise isolati on, an extern al filter is strongly recommended for the analog VDD pins (VDD_A_PLL,

VDD_RTC). The filter shown in Figure 2 should be connected between the board IVDD and the analog pins. The resistor and

capacitors should be placed as close to the dedicated analog VDD pin as possible. The 10- resistor in the given filter is required.

Do not implement the filter ci rcuit using only capacitors. The analog power pins draw very little current . Concerns regarding

voltage loss across the 10-ohm resistor are not valid.

Figure 2. System Analog VDD Power Filter

Table 2. Orderable Part Numbers

Freescale Part

Number Description Package Speed Temperature

MCF54450CVM180 MCF54450 Microprocessor

256 MAPBGA

180 MHz –40 to +85 C

MCF54450VM24 0 240 MHz 0 to +70 C

MCF54451CVM180 MCF54451 Microprocessor 180 MHz –40 to +85 C

MCF54451VM24 0 240 MHz 0 to +70 C

MCF54452CVR200

MCF54452 Microprocessor

360 TEPBGA

200 MHz –40 to +85 C

MCF54452YVR200 200 MHz –40 to +105 C

MCF54452VR266 266 MHz 0 to +70 C

MCF54453CVR200 MCF54453 Microprocesso r 200 MHz –40 to +85 C

MCF54453VR266 266 MHz 0 to +70 C

MCF54454CVR200 MCF54454 Microprocesso r 200 MHz –40 to +85 C

MCF54454VR266 266 MHz 0 to +70 C

MCF54455CVR200 MCF54455 Microprocesso r 200 MHz –40 to +85 C

MCF54455VR266 266 MHz 0 to +70 C

Board IVDD 10 

0.1 µF

Analog VDD Pin

10 µF

GND

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Hardware Design Considerations

Freescale Semiconductor6

3.2 Oscillator Power Filtering

Figure 3 shows an example for isolating the oscillator power supply from th e I/O supply (EVD D) and ground.

Figure 3. Oscillator Power Filter

3.3 Supply Voltage Sequencing

Figure 4 shows situations in sequencing th e I/O VDD (EVDD), SDRAM VDD (SDVDD), PLL VDD (PVDD), and internal

logic/core VDD (IVDD).

Figure 4. Supply Voltage Sequencing and Separation Cautions

The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. SDVDD (2.5 V or

1.8V) and EVDD are specified relative to IVDD.

VDD_OSC 10 

0.1 µF

EVDD Pin

1 µF

GND

VSS_OSC 100 MHz

EVDD (3.3V)

IVDD, PVDD

Time

3.3V

1.5V

DC Power Supply Voltage

Notes:

1Input voltage must not be greater than the supply voltage (EVDD, SD VDD, IVDD, or PVDD) b y more than 0.5V

at any time, including during power-up.

2Use 50 V/millisecond or slower rise time for all supplies.

2.5V

Supplies Stable

SDVDD (2.5V — DDR)

1.8V SDVDD (1.8V — DDR2)

Pin Assignments and Res et States

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 7

3.3.1 Power-Up Sequence

If EVDD/SDVDD are powered up with the IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected

to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD

must power up. The rise times on the power supp lies shoul d be slower than 50 V/millisecond to avo id turnin g on the internal

ESD protection clamp diodes.

3.3.2 Power-Down Sequence

If IVDD/PVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.

There is no limit on how long after IVDD and PVDD power down before EVDD or SDVDD must power down. There are no

requirements for the fall times of the power supplies.

4 Pin Assignments and Reset States

4.1 Signal Multiplexing

The following table lists all the MCF5445x pins grouped by function. The Dir column is the direction for the primary function

of the pin only. Refer to Section 4, “Pin Assignments and Reset States,” for package diagrams . For a more detailed discussion

of the MCF5445x signals, consult the MCF54455 Refer ence Manual (MCF54455RM).

NOTE

In this table and throughout this document, a single signal within a group is designat ed

without square brackets (i.e., FB_AD23), while designations for multiple signals within a

group use brackets (i.e., FB_AD[23:21]) and is meant to include all signals within the two

bracketed numbers when these numbers are separated by a colon.

NOTE

The primary functionality of a pin is not necessarily its default functionality . Most pins that

are muxed with GPIO default to their GPIO functionali ty. See Table 3 for a list of the

exceptions.

Table 3. Special-Case Default Signal Functionality

Pin 256 MAPBGA 360 TEPBGA

FB_AD[31:0] FB_AD[31:0] except when serial boot selects 0-bit

boot port size.

FB_BE/BWE[3:0] FB_BE/BWE[3:0]

FB_CS[3:1] FB_CS[3:1]

FB_OE FB_OE

FB_R/W FB_R/W

FB_TA FB_TA

FB_TS FB_TS

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Pin Assignments and Reset States

Freescale Semiconductor8

PCI_GNT[3:0] GPIO PCI_GNT[3:0]

PCI_REQ[3:0] GPIO PCI_REQ[3:0]

IRQ1 GPIO PCI_INTA and

configured as an agent.

ATA_RESET GPIO ATA reset

Table 4. MCF5445x Signal Information and Muxing

Signal Name GPIO Alternate 1 Alternate 2

Pull-up (U)1

Pull-down (D)

Direction2

Voltage Domain

MCF54450

MCF54451

256 MAPBGA

MCF54452

MCF54453

MCF54454

MCF54455

360 TEPBGA

Reset

RESET — — — U IEVDD L4 Y18

RSTOUT — — — — OEVDD M15 B17

Clock

EXTAL/PCI_CLK — — — — IEVDD M16 A16

XTAL — — — U3OEVDD L16 A17

Mode Selection

BOOTMOD[1:0] — — — — IEVDD M5, M7 AB17, AB21

FlexBus

FB_AD[31:24] PFBADH[7:0]4FB_D[31:24] — —I/O EVDD A14, A13, D12,

C12, B12, A12,

D11, C11

J2, K4, J1, K1–3,

L1, L4

FB_AD[23:16] PFBADMH[7:0]4FB_D[23:16] — —I/O EVDD B11, A11, D10,

C10, B10, A10, D9,

L2, L3, M1 –4 ,

N1–2

FB_AD[15:8] PFBADML[7:0]4FB_D[15:8] — —I/O EVDD B9, A9, D8, C8, B8,

A8, D7, C7 P1–2, R1–3, P4,

T1–2

FB_AD[7:0] PFBADL[7:0]4FB_D[7:0] — —I/O EVDD B7, A7, D6, C6, B6,

A6, D5, C5 T3–4, U1–3, V1–2,

FB_BE/BWE[3:2] PBE[3:2] FB_TSIZ[1:0] — —OEVDD B5, A5 Y1, W2

FB_BE/BWE[1:0] PBE[1:0] — — — OEVDD B4, A4 W3, Y2

FB_CLK — — — —OEVDD B13 J3

FB_CS[3:1] PCS[3:1] — — —OEVDD C2, D4, C3 W5, AA4, AB3

FB_CS0 —— ——OEVDD C4 Y4

FB_OE PFBCTL3 — — —OEVDD A2 AA1

FB_R/W PFBCTL2 — — — OEVDD B2 AA3

FB_TA PFBCTL1 — — U IEVDD B1 AB2

Table 3. Special-Case Default Signal Functionality (continued)

Pin 256 MAPBGA 360 TEPBGA

Pin Assignments and Res et States

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 9

FB_TS PFBCTL0 FB_ALE FB_TBST —OEVDD A3 Y3

PCI Controller5

PCI_AD[31:0] — FB_A[31:0] — —I/O EVDD — C11, D11, A10,

B10, J4, G2, G3,

F1, D12, C12, B12,

A11, B11, B9, D9,

D10, A8, B8, A5,

B5, A4, A3, B3, D4,

D3, E3–E1, F3, C2,

D2, C1

— — FB_A[23:0] — —I/O EVDD K14–13, J15–13,

H13–15, G15–13,

F14–13, E15–13,

D16, B16, C15,

B15, C14, D15,

C16, D14

—

PCI_CBE[3:0] — — — —I/O EVDD — G4, E4, D1, B1

PCI_DEVSEL —— ——OEVDD — F2

PCI_FRAME —— ——I/O EVDD — B2

PCI_GNT3 PPCI7 ATA_DMACK — — OEVDD — B7

PCI_GNT[2:1] PPCI[6:5] — — —OEVDD — C8, C9

PCI_GNT0/

PCI_EXTREQ PPCI4 — — —OEVDD — A9

PCI_IDSEL — — — —IEVDD — D5

PCI_IRDY —— ——I/O EVDD — C3

PCI_PAR — — — —I/O EVDD — C4

PCI_PERR —— ——I/O EVDD — B4

PCI_REQ3 PPCI3 ATA_INTRQ — —IEVDD — C7

PCI_REQ[2:1] PPCI[2:1] — — —IEVDD — D7, C5

PCI_REQ0/

PCI_EXTGNT PPCI0 — — —IEVDD — A2

PCI_RST —— ——OEVDD — B6

PCI_SERR —— ——I/O EVDD — A6

PCI_STOP —— ——I/O EVDD — A7

PCI_TRDY —— ——I/O EVDD — C10

SDRAM Controller

SD_A[13:0] — — — —OSDVDD R1, P1, N2, P2 ,

R2, T2, M4, N3,

P3, R3, T3, T4, R4,

V22, U20–22,

T19–22, R20–22,

N19, P20–21

Table 4. MCF5445x Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

Pull-up (U)1

Pull-down (D)

Direction2

Voltage Domain

MCF54450

MCF54451

256 MAPBGA

MCF54452

MCF54453

MCF54454

MCF54455

360 TEPBGA

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Pin Assignments and Reset States

Freescale Semiconductor10

SD_BA[1:0] — — — —OSDVDD P4, T5 P22, P19

SD_CAS —— ——OSDVDD T6 L19

SD_CKE — — — —OSDVDD N5 N22

SD_CLK — — — —OSDVDD T9 L22

SD_CLK —— ——OSDVDD T8 M22

SD_CS[1:0] — — — —OSDVDD P6, R6 L20, M20

SD_D[31:16] — — — —I/O SDVDD N6, T7, N7, P7, R7,

R8, P8, N8, N9,

T10, R1 0, P10,

N10, T11, R11,

P11

L21, K22, K21,

K20, J20, J19, J21,

J22, H20, G22,

G21, G20, G19,

F22, F21, F20

SD_DM[3:2] — — — —OSDVDD P9, N12 H21, E21

SD_DQS[3:2] — — — —OSDVDD R9, N11 H22, E22

SD_RAS —— ——OSDVDD P5 N21

SD_VREF — — — —ISDVDD M8 M21

SD_WE —— ——OSDVDD R5 N20

External Interrupts Port6

IRQ7 PIRQ7 — — — IEVDD L1 ABB13

IRQ4 PIRQ4 —SSI_CLKIN —IEVDD L2 ABB13

IRQ3 PIRQ3 — — — IEVDD L3 AB14

IRQ1 PIRQ1 PCI_INTA — — IEVDD F15 C6

FEC0

FEC0_MDC PFECI2C3 — — — OEVDD F3 AB8

FEC0_MDIO PFECI2C2 — — — I/O EVDD F2 Y7

FEC0_COL PFEC0H4 —ULPI_DATA7 —IEVDD E1 AB7

FEC0_CRS PFEC0H0 —ULPI_DATA6 —IEVDD F1 AA7

FEC0_RXCLK PFEC0H3 —ULPI_DATA1 —IEVDD G1 AA8

FEC0_RXDV PFEC0H2 FEC0_RMII_

CRS_DV — — IEVDD G2 Y8

FEC0_RXD[3:2] PFEC0L[3:2] —ULPI_DATA[5:4] —IEVDD G3, G4 AB9, Y9

FEC0_RXD1 PFEC0L1 FEC0_RMII_RXD1 — — IEVDD H1 W9

FEC0_RXD0 PFEC0H1 FEC0_RMII_RXD0 — — IEVDD H2 AB10

FEC0_RXER PFEC0L0 FEC0_RMII_RXER — — IEVDD H3 AA10

Table 4. MCF5445x Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

Pull-up (U)1

Pull-down (D)

Direction2

Voltage Domain

MCF54450

MCF54451

256 MAPBGA

MCF54452

MCF54453

MCF54454

MCF54455

360 TEPBGA

Pin Assignments and Res et States

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 11

FEC0_TXCLK PFEC0H7 FEC0_RMII_

REF_CLK — — IEVDD H4 Y10

FEC0_TXD[3:2] PFEC0L[7:6] —ULPI_DATA[3:2] —OEVDD J1, J2 W10, AB11

FEC0_TXD1 PFEC0L5 FEC0_RMII_TXD1 — — OEVDD J3 AA11

FEC0_TXD0 PFEC0H5 FEC0_RMII_TXD0 — — OEVDD J4 Y11

FEC0_TXEN PFEC0H6 FEC0_RMII_TXEN — — OEVDD K1 W11

FEC0_TXER PFEC0L4 —ULPI_DATA0 —OEVDD K2 AB12

FEC1

FEC1_MDC PFECI2C5 —ATA_DIOR —OEVDD —W20

FEC1_MDIO PFECI2C4 —ATA_DIOW —I/O EVDD —Y22

FEC1_COL PFEC1H4 —ATA_DATA7 —IEVDD —AB18

FEC1_CRS PFEC1H0 —ATA_DATA6 —IEVDD —AA18

FEC1_RXCLK PFEC1H3 —ATA_DATA5 —IEVDD —W14

FEC1_RXDV PFEC1H2 FEC1_RMII_

CRS_DV ATA_DATA15 —IEVDD —AB15

FEC1_RXD[3:2] PFEC1L[3:2] —ATA_DATA[4:3] —IEVDD —AA15, Y15

FEC1_RXD1 PFEC1L1 FEC1_RMII_RXD1 ATA_DATA14 —IEVDD —AA17

FEC1_RXD0 PFEC1H1 FEC1_RMII_RXD0 ATA_DATA13 —IEVDD —Y17

FEC1_RXER PFEC1L0 FEC1_RMII_RXER ATA_DATA12 —IEVDD —W17

FEC1_TXCLK PFEC1H7 FEC1_RMII_

REF_CLK ATA_DATA11 —IEVDD —AB19

FEC1_TXD[3:2] PFEC1L[7:6] —ATA_DATA[2:1] —OEVDD —Y19, W18

FEC1_TXD1 PFEC1L5 FEC1_RMII_TXD1 ATA_DATA10 —OEVDD —AA19

FEC1_TXD0 PFEC1H5 FEC1_RMII_TXD0 ATA_DATA9 —OEVDD —Y20

FEC1_TXEN PFEC1H6 FEC1_RMII_TXEN ATA_DATA8 —OEVDD —AA21

FEC1_TXER PFEC1L4 —ATA_DATA0 —OEVDD —AA22

USB On-the-Go

USB_DM — — — — OUSB

VDD F16 A14

USB_DP — — — — OUSB

VDD E16 A15

USB_VBUS_EN PUSB1 USB_PULLUP ULPI_NXT —OUSB

VDD E5 AA2

USB_VBUS_OC PUSB0 —ULPI_STP UD7IUSB

VDD B3 V4

Table 4. MCF5445x Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

Pull-up (U)1

Pull-down (D)

Direction2

Voltage Domain

MCF54450

MCF54451

256 MAPBGA

MCF54452

MCF54453

MCF54454

MCF54455

360 TEPBGA

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Pin Assignments and Reset States

Freescale Semiconductor12

ATA

ATA_BUFFER_EN PATAH5 — — — OEVDD —Y13

ATA_CS[1:0] PATAH[4:3] — — — OEVDD —W21, W22

ATA_DA[2:0] PATAH[2:0] — — — OEVDD —V19–21

ATA_RESET PATAL2 — — — OEVDD —W13

ATA_DMARQ PATAL1 — — — IEVDD —AA14

ATA_IORDY PATAL0 — — — IEVDD —Y14

Real Time Clock

EXTAL32K — — — — IEVDD J16 A13

XTAL32K — — — — OEVDD H16 A12

SSI

SSI_MCLK PSSI4 — — — OEVDD T13 D20

SSI_BCLK PSSI3 U1CTS — — I/O EVDD R13 E19

SSI_FS PSSI2 U1RTS — — I/O EVDD P12 E20

SSI_RXD PSSI1 U1RXD —UD IEVDD T12 D21

SSI_TXD PSSI0 U1TXD —UD OEVDD R12 D22

I2C

I2C_SCL PFECI2C1 —U2TXD UI/O EVDD K3 AA12

I2C_SDA PFECI2C0 —U2RXD UI/O EVDD K4 Y12

DMA

DACK1 PDMA3 —ULPI_DIR —OEVDD M14 C17

DREQ1 PDMA2 —USB_CLKIN UIEVDD P16 C18

DACK0 PDMA1 DSPI_PCS3 — — OEVDD N15 A18

DREQ0 PDMA0 — — U IEVDD N16 B18

DSPI

DSPI_PCS5/PCSS PDSPI6 — — — OEVDD N14 D18

DSPI_PCS2 PDSPI5 — — — OEVDD L13 A19

DSPI_PCS1 PDSPI4 SBF_CS — — OEVDD P14 B20

DSPI_PCS0/SS PDSPI3 — — U I/O EVDD R16 D17

DSPI_SCK PDSPI2 SBF_CK — — I/O EVDD R15 A20

Table 4. MCF5445x Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

Pull-up (U)1

Pull-down (D)

Direction2

Voltage Domain

MCF54450

MCF54451

256 MAPBGA

MCF54452

MCF54453

MCF54454

MCF54455

360 TEPBGA

Pin Assignments and Res et States

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 13

DSPI_SIN PDSPI1 SBF_DI —8IEVDD P15 B19

DSPI_SOUT PDSPI0 SBF_DO — — OEVDD N13 C20

UARTs

U1CTS PUART7 — — — IEVDD —V3

U1RTS PUART6 — — — OEVDD —U4

U1RXD PUART5 — — — IEVDD —P3

U1TXD PUART4 — — — OEVDD —N3

U0CTS PUART3 — — — IEVDD M3 Y16

U0RTS PUART2 — — — OEVDD M2 AA16

U0RXD PUART1 — — — IEVDD N1 AB16

U0TXD PUART0 — — — OEVDD M1 W15

Note: The UART1 and UART 2 signals are multiplexed on the DMA timers and I2C pins.

DMA Timers

DT3IN PTIMER3 DT3OUT U2RXD —IEVDD C13 H2

DT2IN PTIMER2 DT2OUT U2TXD —IEVDD D13 H1

DT1IN PTIMER1 DT1OUT U2CTS —IEVDD B14 H3

DT0IN PTIMER0 DT0OUT U2RTS —IEVDD A15 G1

BDM/JTAG9

PSTDDATA[7:0] — — — — OEVDD E2, D1, F4, E3, D2,

C1, E4, D3 AA6, AB6, AB5,

W6, Y6, AA5, AB 4,

JTAG_EN — — — D IEVDD M11 C21

PSTCLK —TCLK — — IEVDD P13 C22

DSI —TDI — U IEVDD T15 C19

DSO —TDO — — OEVDD T14 A21

BKPT —TMS — U IEVDD R14 B21

DSCLK —TRST — U IEVDD M13 B22

Test

TEST — — — D IEVDD M6 AB20

PLLTEST — — — — OEVDD K16 D15

Table 4. MCF5445x Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

Pull-up (U)1

Pull-down (D)

Direction2

Voltage Domain

MCF54450

MCF54451

256 MAPBGA

MCF54452

MCF54453

MCF54454

MCF54455

360 TEPBGA

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Pin Assignments and Reset States

Freescale Semiconductor14

Power Supplies

IVDD — — — — — — E6–12, F5, F12 D6, D8, D14, F4,

H4, N4, R4, W4,

W7, W8, W12,

W16, W19

EVDD — — — — — — G5, G12, H5, H12,

J5, J12, K5, K1 2,

L5–6, L12

D13, D19, G8,

G11, G14, G16, J7,

J16, L7, L16, N1 6,

P7, R16, T8, T12,

T14, T16

SD_VDD — — — — — — L7–11, M9, M10 F19, H19, K19,

M19, R19, U19

VDD_OSC — — — — — — L14 B16

VDD_A_PLL — — — — — — K15 C14

VDD_RTC — — — — — — M12 C13

VSS — — — — — — A1, A16, F6–11,

G6–11, H6–11,

J6–11, K6–11, T1,

T16

A1, A22, B14, G7,

G9–10, G12–13,

G15, H7, H16,

J9–14, K7, K9–14,

K16, L9–14, M7,

M9–M14, M16, N7,

N9–14, P9–14,

P16, R7, T7,

T9–11, T13, T15,

AB1, AB22

VSS_OSC — — — — — — L15 C16

1Pull-ups are generally only enabled on pins with their primary function, except as noted.

2Refers to pin’s primary function.

3Enabled only in oscillator bypass mode (internal crystal oscillator is disabled).

4Serial bo ot must select 0-bit boot port size to enable the GPIO mode on these pins.

5When the PCI is enabled, all PCI b us pins come up configured as such. This includes the PCI_GNT and PCI_REQ lines, which hav e

GPIO. The IRQ1/PCI_INTA signal is a special case. It comes up as PCI_INTA when booting as a PCI agent and as GPIO when booting

as a PCI host.

For the 360 TEPBGA, booting with PCI disabled results in all dedicated PCI pins being safe-stated. The PCI_GNT and PCI_REQ lines

and IRQ1/PCI_INTA come up as GPIO.

6GPIO functionality is determined by the edge port module. The pin multiple xing and control module is only responsible for assigning

the alternate functions.

7Depends on programmed polarity of the USB_VBUS_OC signal.

8Pull-up when the serial boot facility (SBF) controls the pin

9If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The pin multiplexing and control module is not

responsible for assigning these pins.

Table 4. MCF5445x Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

Pull-up (U)1

Pull-down (D)

Direction2

Voltage Domain

MCF54450

MCF54451

256 MAPBGA

MCF54452

MCF54453

MCF54454

MCF54455

360 TEPBGA

Pin Assignments and Res et States

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 15

4.2 Pinout—256 MAPBGA

The pinout for the MCF54450 and MCF54451 packages are shown below.

Figure 5. MCF54450 and MCF54451 Pinout (256 MAPBGA)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

AVSS FB_OE FB_TS FB_BE/

BWE0 FB_BE/

BWE2 FB_AD

2FB_AD

6FB_AD

10 FB_AD

14 FB_AD

18 FB_AD

22 FB_AD

26 FB_AD

30 FB_AD

31 T0IN VSS A

BFB_TA FB_R/W USB_

VBUS_

FB_BE/

BWE1 FB_BE/

BWE3 FB_AD

3FB_AD

7FB_AD

11 FB_AD

15 FB_AD

19 FB_AD

23 FB_AD

27 FB_CLK T1IN FB_A

4FB_A

CPST

DDATA2 FB_CS3 FB_CS1 FB_CS0 FB_AD

0FB_AD

4FB_AD

8FB_AD

12 FB_AD

16 FB_AD

20 FB_AD

24 FB_AD

28 T3IN FB_A

3FB_A

5FB_A

DPST

DDATA6 PST

DDATA3 PST

DDATA0 FB_CS2 FB_AD

1FB_AD

5FB_AD

9FB_AD

13 FB_AD

17 FB_AD

21 FB_AD

25 FB_AD

29 T2IN FB_A

0FB_A

2FB_A

EFEC0_

COL PST

DDATA7 PST

DDATA4 PST

DDATA1

USB_

VBUS_

EN IVDD IVDD IVDD IVDD IVDD IVDD IVDD FB_A

8FB_A

9FB_A

10 USB_

DP E

FFEC0_

CRS FEC0_

MDIO FEC0_

MDC PST

DDATA5 IVDD VSS VSS VSS VSS VSS VSS IVDD FB_A

11 FB_A

12 IRQ_1 USB_

DM F

GFEC0_

RXCLK FEC0_

RXDV FEC0_

RXD3 FEC0_

RXD2 EVDD VSS VSS VSS VSS VSS VSS EVDD FB_A

13 FB_A

14 FB_A

15 NC G

HFEC0_

RXD1 FEC0_

RXD0 FEC0_

RXER FEC0_

TXCLK EVDD VSS VSS VSS VSS VSS VSS EVDD FB_A

18 FB_A

17 FB_A

16 XTAL

32K H

JFEC0_

TXD3 FEC0_

TXD2 FEC0_

TXD1 FEC0_

TXD0 EVDD VSS VSS VSS VSS VSS VSS EVDD FB_A

19 FB_A

20 FB_A

21 EXTAL

32K J

KFEC0_

TXEN FEC0_

TXER I2C_

SCL I2C_

SDA EVDD VSS VSS VSS VSS VSS VSS EVDD FB_A

22 FB_A

23 VDD_A

_PLL PLL

TEST K

LIRQ_7 IRQ_4 IRQ_3 RESET EVDD EVDD SDVDD SDVDD SDVDD SDVDD SDVDD EVDD DSPI_

PCS2 VDD_

OSC VSS_

OSC XTAL L

MU0TXD U0RTS U0CTS SD_A7 BOOT

MOD1 TEST BOOT

MOD0 SD_

VREF SDVDD SDVDD JTAG_

EN VDD_

RTC TRST DACK1 RST

OUT EXTAL M

NU0RXD SD_A11 SD_A6 SD_A0 SD_

CKE SD_D31 SD_D29 SD_D24 SD_D23 SD_D19 SD_

DQS2 SD_DM2 DSPI_

SOUT DSPI_

PCS5 DACK0 DREQ0 N

PSD_A12 SD_A10 SD_A5 SD_BA1 SD_

RAS SD_

CS1 SD_D28 SD_D25 SD_

DM3 SD_D20 SD_D16 SSI_FS TCLK DSPI_

PCS1 DSPI_

SIN DREQ1 P

RSD_A13 SD_A9 SD_A4 SD_A1 SD_WE SD_

CS0 SD_D27 SD_D26 SD_

DQS3 SD_D21 SD_D17 SSI_TXD SSI_

BCLK TMS DSPI_

SCK DSPI_

PCS0 R

TVSS SD_A8 SD_A3 SD_A2 SD_BA0 SD_

CAS SD_D30 SD_

CLK SD_

CLK SD_D22 SD_D18 SSI_RXD SSI_

MCLK TDO TDI VSS T

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Pin Assignments and Reset States

Freescale Semiconductor16

4.3 Pinout—360 TEPBGA

The pinout for the MCF54452, MCF54453, MCF54454, and MCF54455 packages are shown below.

Figure 6. MCF54452, MCF54453, MCF54454, and MCF54455 Pinout (360 TEPBGA)

12345678910111213141516171819202122

AGND PCI_

REQ0 PCI_

AD10 PCI_

AD11 PCI_

AD13 PCI_

SERR PCI_

STOP PCI_

AD15 PCI_

GNT0 PCI_

AD29 PCI_

AD20 XTAL

32K EXTAL

32K USB_

DM USB_

DP EXTAL XTAL DACK0 DSPI_

PCS2 DSPI_

SCK TDO GND A

BPCI_

CBE0 PCI_

FRAME PCI_

AD9 PCI_

PERR PCI_

AD12 PCI_

RST PCI_

GNT3 PCI_

AD14 PCI_

AD18 PCI_

AD28 PCI_

AD19 PCI_

AD21 NC GND NC VDD_

OSC RST

OUT DREQ0 DSPI_

SIN DSPI_

PCS1 TMS TRST B

CPCI_

AD0 PCI_

AD2 PCI_

IRDY PCI_

PAR PCI_

REQ1 IRQ1 PCI_

REQ3 PCI_

GNT2 PCI_

GNT1 PCI_

TRDY PCI_

AD31 PCI_

AD22 VDD_

RTC VDD_

A_PLL NC VSS_

OSC DACK1 DREQ1 TDI DSPI_

SOUT JTAG_

EN TCLK C

DPCI_

CBE1 PCI_

AD1 PCI_

AD7 PCI_

AD8 PCI_

IDSEL IVDD PCI_

REQ2 IVDD PCI_

AD17 PCI_

AD16 PCI_

AD30 PCI_

AD23 EVDD IVDD PLL

TEST NC DSPI_

PCS0 DSPI_

PCS5 EVDD SSI_

MCLK SSI_

RXD SSI_

TXD D

EPCI_

AD4 PCI_

AD5 PCI_

AD6 PCI_

CBE2 SSI_

BCLK SSI_FS SD_

DM2 SD_

DQS2 E

FPCI_

AD24 PCI_DE

VSEL PCI_

AD3 IVDD SDVDD SD_D16 SD_D17 SD_D18 F

GT0IN PCI_

AD26 PCI_

AD25 PCI_

CBE3 GND EVDD GND GND EVDD GND GND EVDD GND EVDD SD_D19 SD_D20 SD_D21 SD_D22 G

HT2IN T3IN T1IN IVDD GND GND SDVDD SD_D23 SD_

DM3 SD_

DQS3 H

JFB_AD

29 FB_AD

31 FB_CLK PCI_

AD27 EVDD GND GND GND GND GND GND EVDD SD_D26 SD_D27 SD_D25 SD_D24 J

KFB_AD

28 FB_AD

27 FB_AD

26 FB_AD

30 GND GND GND GND GND GND GND GND SDVDD SD_D28 SD_D29 SD_D30 K

LFB_AD

25 FB_AD

23 FB_AD

22 FB_AD

24 EVDD GND GND GND GND GND GND EVDD SD_

CAS SD_

CS1 SD_D31 SD_

CLK L

MFB_AD

21 FB_AD

20 FB_AD

19 FB_AD

18 GND GND GND GND GND GND GND GND SDVDD SD_

CS0 SD_

VREF SD_

CLK M

NFB_AD

17 FB_AD

16 U1TXD IVDD GND GND GND GND GND GND GND EVDD SD_A2 SD_WE SD_

RAS SD_

CKE N

PFB_AD

15 FB_AD

14 U1RXD FB_AD

10 EVDD GND GND GND GND GND GND GND SD_

BA0 SD_A1 SD_A0 SD_

BA1 P

RFB_AD

13 FB_AD

12 FB_AD

11 IVDD GND EVDD SDVDD SD_A5 SD_A4 SD_A3 R

TFB_AD

9FB_AD

8FB_AD

7FB_AD

6GND EVDD GND GND GND EVDD GND EVDD GND EVDD SD_A9 SD_A8 SD_A7 SD_A6 T

UFB_AD

5FB_AD

4FB_AD

3U1RTS SDVDD SD_A12 SD_A11 SD_A10 U

VFB_AD

2FB_AD

1U1CTS USB_

VBUS_

ATA_

DA2 ATA_

DA1 ATA_

DA0 SD_A13 V

WFB_AD

0FB_BE/

BWE2 FB_BE/

BWE1 IVDD FB_CS3 PST

DDATA4 IVDD IVDD FEC0_

RXD1 FEC0_

TXD3 FEC0_

TXEN IVDD ATA_

RESET FEC1_

RXCLK U0TXD IVDD FEC1_

RXER FEC1_

TXD2 IVDD FEC1_

MDC ATA_

CS1 ATA_

CS0 W

YFB_BE/

BWE3 FB_BE/

BWE0 FB_TS FB_CS0 PST

DDATA0 PST

DDATA3 FEC0_

MDIO FEC0_

RXDV FEC0_

RXD2 FEC0_

TXCLK FEC0_

TXD0 I2C_

SDA

ATA_BU

FFER_

ATA_

IORDY FEC1_

RXD2 U0CTS FEC1_

RXD0 RESET FEC1_

TXD3 FEC1_

TXD0 NC FEC1_

MDIO Y

AA FB_OE USB_

VBUS_

EN FB_R/W FB_CS2 PST

DDATA2 PST

DDATA7 FEC0_

CRS FEC0_

RXCLK NC FEC0_

RXER FEC0_

TXD1 I2C_

SCL IRQ4 ATA_

DMARQ FEC1_

RXD3 U0RTS FEC1_

RXD1 FEC1_

CRS FEC1_

TXD1 NC FEC1_

TXEN FEC1_

TXER AA

AB GND FB_TA FB_CS1 PST

DDATA1 PST

DDATA5 PST

DDATA6 FEC0_

COL FEC0_

MDC FEC0_

RXD3 FEC0_

RXD0 FEC0_

TXD2 FEC0_

TXER IRQ7 IRQ3 FEC1_

RXDV U0RXD BOOT

MOD1 FEC1_

COL FEC1_

TXCLK TEST BOOT

MOD0 GND AB

12345678910111213141516171819202122

Electrical Characteristics

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 17

5 Electrical Characteristics

This document contains electrical specification tables and reference timing diagrams for the MCF54455 microprocessor. This

section contai ns detailed informa tion on DC/AC electrical characteristics and AC timing specifications.

The electrical specifications are preliminary and from previous designs or design simulations. These specifications may not be

fully tested or guaranteed at this early stage of the product life cycle. However , for production s ilicon, these specifications will

be met. Finalized specification s will be published after complete characterization and device qualifications have been

completed.

NOTE

The parameters specified in this MCU document supersede any values found in the module

specifications.

5.1 Absolute Maximum Ratings

Table 5. Absolute Maximum Ratings1, 2

1Functional operating conditions are given in Table 8. Absolute maximum ratings are stress ratings only, and functional

operation at the maximum is not guaranteed. Continued operation at these lev els may affect device reliability or cause

permanent damage to the device.

2This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, it is

advised that normal precautions be taken to av oid application of any v oltages higher than maximum-rated v oltages to this

high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage le v el

(e.g., VSS or EVDD).

Rating Symbol Pin Name Value Units

External I/O pad supply voltage EVDD EVDD -0.3 to +4.0 V

Internal oscillator supply voltage OSCVDD VDD_OSC -0.3 to +4.0 V

Real-time clock supply voltage RTCVDD VDD_RTC -0.5 to +2.0 V

Internal logic supply voltage IVDD IVDD -0.5 to +2.0 V

SDRAM I/O pad supply voltage SDVDD SD_VDD -0.3 to +4.0 V

PLL supply voltage PVDD VDD_A_PLL -0.5 to +2.0 V

Digit al input voltage3

3Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values for positive and negative clamp v oltages, and then use the larger of the two values.

VIN — -0.3 to +3.6 V

Instantaneous maximum current

Single pin limit (applies to all pins) 3, 4, 5

4All functional non-supply pins are internally clamped to VSS and EVDD.

5Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum

current conditions. If positiv e injection current (Vin > EVDD) is greater than IDD, the injection current may flo w out of EVDD

and could result in external power supply going out of regulation. Ensure the external EVDD load shunts current greater

than maximum injection current. This is the greatest risk when the MPU is not consuming power (e x; no clock). The power

supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current

conditions.

IDD —25mA

Operating temperature range (packaged) TA

(TL - TH)— -40 to +85 C

Storage temperature range Tstg — -55 to +150 C

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Electrical Characteristics

Freescale Semiconductor18

5.2 Thermal Characteristics

The average chip-junction temperature (TJ) in C can be obtained from:

Eqn. 1

Where:

TA= Ambient Temperature, C

QJMA = Package Thermal Resistance, Junction-to-Ambient, C/W

PD=P

INT + PI/O

PINT =I

DD  IVDD, Watts - Chip Internal Power

PI/O = Power Dissipation on Input and Output Pins — User Determined

For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:

Eqn. 2

Solving equations 1 and 2 for K giv e s:

Eqn. 3

Table 6. Thermal Characteristics

Characteristic Symbol 256

MAPBGA 360

TEPBGA Unit

Junction to ambient, natural convection Four layer board

(2s2p) JA 291,2

1JMA and jt parameters are simulated in conf ormance with EIA/JESD Standard 51-2 for natural convection.

Fr eescale recommends the use of JmA and power dissipation specifications in the system design to prevent

device junction temperatures from exceeding the rated specification. System designers should be aware that

device junction temperatures can be significantly influenced by board layout and surrounding devices.

Conformance to the device junction temperature specification can be verified by physical measurement in the

customer’s system using the jt param et er, the device power diss ip a ti o n, and th e me th od de scribed in

EIA/JESD Standard 51-2.

2Per JEDEC JESD51-6 with the board horizontal.

241,2 C / W

Junction to ambient (@200 ft/min) Four layer bo ard

(2s2p) JMA 251,2 211,2 C / W

Junction to board JB 183

3Ther mal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8.

Board temperature is measured on the top surface of the board near the package.

153C / W

Junction to case JC 104

4Ther mal resistance between the die and the case top surface as measured by the cold plate method (MIL

SPEC-883 Method 1012.1).

114C / W

Junction to top of package jt 21,5

5Ther mal characterization parameter indicating the temperature difference between package top and the

junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization

parameter is written in conformance with Psi-JT.

21,5 C / W

Maximum operating junction temperature Tj105 105 oC

TJTAPDJMA

+=

PDK

TJ273C+

---------------------------------

DTA273CQJMA PD

+=

Electrical Characteristics

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 19

where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium)

for a known T A. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively

for any value of TA.

5.3 ESD Protection

5.4 DC Electrical Specifications

Table 7. ESD Protection Characteristics1, 2

1All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for

Automotive Grade Integrated Circuits.

2A device is defined as a f ailure if after exposure to ESD pulses the device no longer meets

the device specification requirements. Complete DC parametric and functional testing is

performed per applicable device specification at room temperature followed by hot

temperature, unless specified otherwise in the device specification.

Characteristics Symbol Value Units

ESD Target for Human Body Model HBM 2000 V

Table 8. DC Electrical Specifications

Characteristic Symbol Min Max Units

Internal logic supply voltage1IVDD 1.35 1.65 V

PLL analog operation voltage range 1PVDD 1.35 1.65 V

External I/O pad supply voltage EVDD 3.0 3.6 V

Inter nal oscillator supply voltage OSCVDD 3.0 3.6 V

Real-time clock supply voltage RTCVDD 1.35 1.65 V

SDRAM I/O pad supply voltage — DDR mode SDVDD 2.25 2.75 V

SDRAM I/O pad supply voltage — DDR2 mode SDVDD 1.7 1.9 V

SDRAM I/O pad supply voltage — Mobile DDR mode SDVDD 1.7 1.9 V

SDRAM input reference voltage SDVREF 0.49 x SDVDD 0.51 x SDVDD V

Input High Voltage VIH 0.7 x EVDD 3.65 V

Input Lo w Voltage VIL VSS – 0.3 0.35 x EVDD V

Input Hysteresis VHYS 0.06 x EVDD —mV

Input Leakage Current2

Vin = VDD or VSS, In put-only pins Iin –2.5 2.5 A

Input Leakage Current3

Vin = VDD or VSS, In put-only pins Iin –5 5 A

High Impedance (Off-State) Leakage Curren t4

Vin = VDD or VSS, All input/output and output pins IOZ –10.0 10.0 A

Output High Voltage (All input/output and all output pins)

IOH = –5.0 mA VOH 0.85  EVDD __ V

Output Low Voltage (Al l input/output and all output pi ns)

IOL = 5.0mA VOL __ 0.15  EVDD V

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Electrical Characteristics

Freescale Semiconductor20

5.5 Clock Timing Specifications

The clock module configures the device for one of several clocking me thods. Clocking modes include in ternal phase-locked

loop (PLL) clocking with an external clock reference or an external crystal reference supported by an internal crystal amplifier.

The PLL can also be disabled, and an external oscillator can directly clock the device.

The specifications in Table 9 are for the CLKIN input pin (EXTAL input driven by an external clock reference). The duty cycle

specification is based on an acceptable tolerance for the PLL, which yields 50% duty-cycle internal clocks to all on-chip

peripherals. The MCF5445x devices use the input clock signal as its synchronous bus clock for PCI. A poor duty cycle on the

input clock, may affect the overall timing margin to external devices. If negative edge logic is used to interface to PCI, providing

a 50% duty-cycle input clock aids in simplifying overall system design.

Weak Internal Pull Up Device Current, tested at VIL Max.5IAPU –10 –130 A

Input Capacitance 6

All input-only pins

All input/output (three-state) pins

Cin —

—7

Load Capacitance

Low drive strength

High dr ive strength CL25

DC Injection Current 3, 7, 8, 9

VNEGCLAMP =VSS– 0.3 V, VPOSCLAMP = VDD + 0.3

Single Pin Limit

Total MCU Limit, Includes sum of all stressed pins

IIC

-1.0

-10 1.0

1IVDD and PVDD should be at the same voltage. PVDD should have a filtered input. Please see the PLL section of this

specification for an e xample circuit. There are three PVDD inputs, one for each PLL. A filter circuit should used on each

PVDD input.

2Valid for all parts, EXCEPT the MCF54452YVR200.

3Valid just the MCF54452YVR200 part number.

4Worst-case tristate leakage current with only one I/O pin high. Since all I/Os share power when high, the leakage current

is distributed among them. With all I/Os high, this spec reduces to ±2 A min/max.

5Refer to the MCF54455 Reference Manual signals description chapter for pins having weak internal pull-up devices.

6This parameter is characterized before qualification rather than 100% tested.

7All functional non-supply pins are internally clamped to VSS and their respective VDD.

8Input must be current limited to the value specified. To determ ine the value of the required current-limiting resistor,

calculate resistance values for posi ti ve and negative clamp voltages, then use the larger of the two values.

9Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum

current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD

and could result in e xternal power supply going out of regulation. Ensure the external VDD load shunts current greater

than the maximum injection current. This is the greatest risk when the MCU is not consuming power. Examples are: if

no system clock is present, or if clock rate is very low which would reduce ov erall power consumption. Also , at power-up ,

the system clock is not present during the power-up sequence until the PLL has attained lock.

Table 8. DC Electrical Specifications

Characteristic Symbol Min Max Units

Electrical Characteristics

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 21

Figure 7. Input Clock Timing Diagram

Table 9. Input Clock Timing Requirements

Item Specification Min Max Unit

C1 Cycle time 15 40 ns

1 / C1 Fr equency 25 66.66 MHz

C2 R ise time (20% of vdd to 80% of vdd) - 2 ns

C3 Fall time (80% of vdd to 20% of vdd) - 2 ns

C4 Duty cycle (at 50% of vdd) 40 60 %

Table 10. PLL Electrical Characteristics

Num Characteristic Symbol Min.

Value Max.

Value Unit

1 PLL Reference Freq uency Range

Crystal reference

External reference fref_crystal

fref_ext

16 40

66.66 MHz

MHz

2 Core/System Frequency fsys 512 Hz1266.67 MHz —

Core/System Clock Period tsys —1/f

sys ns

19 VCO Frequency (fvco = fref  PFDR) fvco 300 540 MHz

3 Crystal Start-up Time2, 3 tcst —10ms

4 EXTAL Input High Voltage

Crystal Mode4

All other modes (External, Limp) VIHEXT

VIHEXT

VXTAL + 0.4

EVDD/2 + 0.4 —

—V

5 EXTAL Input Low Voltage

Crystal Mode4

All other modes (External, Limp) VILEXT

VILEXT

—

—VXTAL - 0.4

EVDD/2 - 0.4 V

6 EXTAL Input Rise & Fall Time (20% to 80% EVDD)

(External, Limp) 12ns

7PLL Lock Time 3, 5 tlpll — 50000 CLKIN

8 Duty Cycle of reference 3 (External, Limp) t dc 40 60 %

9 XTAL Current IXTAL 13mA

10 Total on-chip stray capacitance on XTAL CS_XTAL —1.5pF

Input Clock (CLKIN)

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Electrical Characteristics

Freescale Semiconductor22

5.6 Reset Timing Specifications

Table 11 lists specifications for the reset timing paramet ers shown in Figure 8.

11 Total on-chip stray capacitance on EXTAL CS_EXTAL —1.5pF

12 Crystal capacitive load CLSee crystal spec

13 Discrete load capacitance for XTAL

Discrete load capacitance for EXTAL CL_XTAL

CL_EXTAL

—2(CL -

CS_XTAL -

CS_EXTAL -

CS_PCB)6

14 Frequency un-LOCK Range fUL -4.0 4.0 % fsys

15 Frequency LOCK Range fLCK -2.0 2.0 % fsys

17 CL KOUT Period Jitter, 3, 4, 7 Measured at fSYS Max

Peak-to-peak Jitter (Clock edge to clock edge)

Long Term Jitter

Cjitter —

—10

TBD % FB_CLK

% FB_CLK

1The minimum system frequency is the minimum input clock divided by the maximum lo w-po w er divider (16 MHz 32,768).

When the PLL is enabled, the minimum system frequency (fsys) is 150 MHz.

2This parameter is guaranteed by characterization before qualification rather than 100% tested. Applies to external clock

reference only.

3Proper PC board layout procedures must be followed to achieve specifications.

4This parameter is guaranteed by design rather than 100% tested.

5This specification is the PLL lock time only and does not include oscillator start-up time.

6CS_PCB is the measured PCB stray capacitance on EXTAL and XTAL.

7Jitter is the average deviation from the programmed frequency measure d over the specified interval at maximum fsys.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase the Cjitter

percentage for a given interval.

Table 11. Reset and Configuration Override Timing

Num Characteristic Min Max Unit

R11

1RESET and Configuration Override data lines are synchronized internally. Setup and hold times must be met only if

recognition on a particular clock is required.

RESET valid to CLKIN (setup) 9 — ns

R2 CLKIN to RESET invalid (hold) 1.5 — ns

R3 RESET valid time2

2During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously

to the system. Thus, RESET must be held a minimum of 100 ns.

5 — CLKIN cycles

R4 CLKIN to RSTOU T valid — 10 ns

R5 RSTOUT valid to Configuration Override inputs valid 0 — ns

R6 Configuration Override inputs valid to RSTOUT invalid (setup) 20 — CLKIN cycles

R7 Configuration Override inputs invalid after RSTOUT invalid (hold) 0 — ns

R8 RSTOUT inv alid to Configuration Override inputs High Impedance — 1 CLKIN cycles

Table 10. PLL Electrical Characteristics (continued)

Num Characteristic Symbol Min.

Value Max.

Value Unit

Electrical Characteristics

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 23

Figure 8. RESET and Configuration Override Timing

5.7 FlexBus Timing Specifications

A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up

to a maximum bus frequency of 66MHz. It can be directly connected to asynchronous or synchronous devices such as external

boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with litt le or no additional circuitry. For

asynchronous devices, a simple chip-select based interface can be used.

All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a

reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider

of that frequency.

The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock

(FB_CLK). All other timing relationships can be derived from these values.

NOTE

The processor drives the data lines during the first clock cycle of the transfer

with the full 32-bit address. This may be ignored by standard connected

devices using non-multiplexed address and data buses. However, some

applications may find this feature beneficial.

The address and data busses are muxed between the FlexBus and PCI

controller . At the end of the read and write bus cycles the address signals are

indeterminate.

Table 12. FlexBus AC Timing Specifications

Num Characteristic Min Max Unit Notes

Fr equency of Operation 25 66.66 MHz

FB1 Clock Period 15 40 ns

FB2 Output Valid — 7.0 ns 1

1Specification is valid for all FB_AD[31:0], FB_BS[3:0], FB_CS[3:0], FB_OE, FB_R /W, FB_TBST,

FB_TSIZ[1:0], and FB_TS.

FB3 Output Hold 1.0 — ns 1

FB4 Input Setup 3.0 — ns 2

2Specification is valid for all FB_AD[31:0] and FB_TA .

FB5 Input Hold 0 — ns 2

R1 R2

CLKIN

RESET

RSTOUT

R7R6R5

Configu r at i o n Overrides* :

(BOOTMOD[1:0],

Override pins])

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Electrical Characteristics

Freescale Semiconductor24

Figure 9. FlexBus Read Timing

Figure 10. Flexbus Write Timing

FB_CLK

FB_R/W

S0 S1 S2 S3

FB_ALE

FB_TSIZ[1:0] TSIZ[1:0]

Mux’d Bus

Non-Mux’d Bus FB_A[31:0]

FB_D[31:X]

FB_AD[Y:0]

FB_AD[31:X]

FB_CSn, FB_OE,

FB_BE/BWEn

FB_TA

DATA

ADDR[31:0]

ADDR[31:X]

ADDR[Y:0]

FB3

FB1

FB2 FB5

FB4

FB5

FB4

FB_CLK

FB_R/W

FB_ALE

FB_OE

S0 S2 S3

DATA

FB_TSIZ[1:0] TSIZ[1:0]

DATA

Mux’d Bus

Non-Mux’d Bus FB_A[31:0] ADDR[31:0]

FB_D[31:X]

ADDR[31:X]

FB_AD[Y:0]

FB_AD[31:X]

ADDR[Y:0]

FB_CSn, FB_BE/BWEn

FB_TA

FB3

FB1

FB2

FB5

FB4

Electrical Characteristics

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 25

5.8 SDRAM AC Timing Characteristics

The following timing numbers must be fol low ed to pro perly latch or drive data onto the SDRAM memory bus. All timin g

numbers are relative to the four DQS byte lanes.

Table 13. SDRAM Timing Specifications

Num Characteristic Symbol Min Max Unit Notes

Frequency of Operation 60 133.33 MHz 1

1The SDRAM interface operates at the same frequency as the internal system bus.

DD1 Clock Period tSDCK 7.5 16.67 ns

DD2 Pulse Width High tSDCKH 0.45 0.55 tSDCK 2

2Pulse width high plus pulse width low cannot exceed min and max clock period.

DD3 Pulse Width Low tSDCKL 0.45 0.55 tSDCK 3

DD4 Address , SD_CKE, SD_CAS, SD_RAS, SD_WE,

SD_CS[1:0] — Output Valid tCMV — (0.5 x tSDCK)

+ 1.0ns ns 3

3Command output valid should be 1/2 the memory bus clock (tSDCK) plus some minor adjustments for process, temperature, and

voltage variations.

DD5 Address , SD_CKE, SD_CAS, SD_RAS, SD_WE,

SD_CS[1:0] — Output Hold tCMH 2.0 — ns

DD6 Write Command to first DQS Latching Transition tDQSS (1.0 x tSDCK)

- 0.6ns (1.0 x tSDCK)

+ 0.6ns ns

DD7 Data and Data Mask Output Setup (DQ-->DQS)

Relative to DQS (DDR Write Mode) tQS 1.0 — ns 4

4This specification relates to the required input setup time of DDR memories. The microprocessor’s output setup should be larger

than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation.

SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relativ e to SD_DQS[2]

5The first data beat is valid bef ore the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid

for each subsequent DQS edge.

DD8 Data and Data Mask Output Hold (DQS-->DQ)

Relative to DQS (DDR Write Mode) tQH 1.0 — ns 6

6This specification relates to the required hold time of DDR memo ries.

SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relativ e to SD_DQS[2]

DD9 Input Data Skew Relative to DQS (Input Setup) tIS —1.0ns

7Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes

valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors).

DD10 Input Data Hold Relative to DQS. tIH (0.25 x tSDCK)

+ 0.5ns —ns

8Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes

invalid.

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Electrical Characteristics

Freescale Semiconductor26

Figure 11. DDR Write Timing

SD_CLK

SD_CSn,SD_WE,

SD_DM3/SD_DM2

SD_D[31:24]/SD_D[23:16]

SD_A[13:0]

SD_RAS, SD_CAS CMD

ROW

DD1

DD5

DD4

COL

WD1 WD2 WD3 WD4

DD7

SD_DQS3/SD_DQS2

DD8

DD7

SD_CLK

DD3

DD2

DD6

Electrical Characteristics

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 27

Figure 12. DDR Read Timing

5.9 PCI Bus Timing Specifications

The PCI bus on the device is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Refer to the

PCI 2.2 spec for a more detailed timing analysis.

Table 14. PCI Timing Specifications1,2

Num Characteristic 33 MHz366 MHz3

Min Max Min Max Unit

Fr equency of Operation — 33.33 33.33 66.66 MHz

P1 Clock Period 30 — 15 3 0 ns

P2 Bused PCI signals — input setup 7.0 — 3.0 — ns

P3 PCI_GNT[3:0]/PCI_REQ[3:0] — input setup 10.0 — 5.0 — ns

P4 All PCI signals — input hold 0 — 0 — ns

P5 Bused PCI signals — output valid — 11.0 — 6.0 ns

SD_CLK

SD_CSn,SD_WE,

SD_DQS3/SD_DQS2

D[31:24]/D[23:16]

SD_A[13:0]

SD_RAS, SD_CAS CMD

ROW

DD1

DD5

DD4

WD1WD2WD3WD4

SD_DQS3/SD_DQS2

DD9

SD_CLK

DD3

DD2

D[31:24]/D[23:16]

WD1 WD2 WD3 WD4

DD10

CL=2

CL=2.5

COL

DQS Read

Preamble DQS Read

Postamble

DQS Read

Preamble DQS Read

Postamble

CL = 2.5 CL = 2

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Electrical Characteristics

Freescale Semiconductor28

Figure 13. PCI Timing

5.9.1 Overshoot and Undershoot

Figure 14 shows the specification lim its for overshoot and undershoot for PCI I/O. To guarantee long term reliability, the

specification limits shown must be followed. Good transmission line design practices should be observed to gu arantee the

specification limits.

P6 PCI_REQ[3:0]/PCI_GNT[3:0] — output valid — 12.0 — 6.0 ns

P7 All PCI signals — output hold 2.0 — 1.0 — ns

1The PCI bus operates at the CLKIN frequency. All timings are relative to the input clock, CLKIN.

2All PCI signals are bused signals exce pt for PCI_GNT[3:0] and PCI_REQ[3:0]. These signals are defined as po int-to-point

signals by the PCI Specification.

3The 66-MHz parameters are only guaranteed when the 66-MHz PCI pad slew rates are selected. Like wise, the 33-MHz

parameters are only guaranteed when the 33-MHz PCI pad slew rates are selected.

Table 14. PCI Timing Specifications1,2 (continued)

Num Characteristic 33 MHz366 MHz3

Min Max Min Max Unit

CLKIN

Input

Setup/Hold

Output Valid

Input Valid

Output

Valid/Hold

Electrical Characteristics

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 29

Figure 14. Overshoot and Undershoot Limits

5.10 ULPI Timing Specifications

The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin Interface. Control and data timing

requirements for the ULPI pins are given in Table 15. These timings apply to synchronous mode only . All timings are measured

with respect to the clock as seen at the USB_CLKIN pin on the MCF5445x. The ULPI PHY is the source of the 60MHz clock.

NOTE

The USB controller requires a 60-MHz clock, even if using the on-chip FS/LS transceiver

instead of the ULPI interface . In this case , the 60-MHz clock can be generated by the PLL

or input on the USB_CLKIN pin.

Table 15. ULPI Interface Timing

Num Characteristic Min Nominal Max Units

USB_CLKIN operating frequency — 60 — MHz

USB_CLKIN duty cycle — 50 — %

U1 USB_CLKIN clock peri od — 16.67 — ns

U2 Input Setup (control and data) 5.0 — — ns

U3 Input Hold (control and data) 1.0 — — ns

U4 Output Valid (control and data) — — 9.5 ns

U5 Output Hold (control and data) 1.0 — —

Not to exceed 17%

of PCI Cycle

VDD + 0.9V

VDD + 0.5V

VDD

GND - 1.0V

GND - 0.5V

GND

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Electrical Characteristics

Freescale Semiconductor30

Figure 15. ULPI Timing Diagram

5.11 SSI Timing Specifications

This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given

for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync

(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings

remain valid by inverting the clock sign al (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the fi gures bel ow.

Table 16. SSI Timing — Master Modes1

1All timings specified with a capactive load of 25pF.

Num Description Symbol Min Max Units Notes

S1 SSI_MCLK cycle time tMCLK 2  tSYS —ns 2

2SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (fsys).

S2 SSI_MCLK pulse width high / low 45% 55% tMCLK

S3 SSI_BCLK cycle time tBCLK 8  tSYS —ns 3

3SSI_BCLK can be derived from SSI_CLKIN or a divided version of the internal system clock (fsys).

S4 SSI_BCLK pulse width 45% 55% tBCLK

S5 SSI_BCLK to SSI_FS output valid — 15 ns

S6 SSI_BCLK to SSI_FS output invalid 0 — ns

S7 SSI_BCLK to SSI_TXD valid — 15 ns

S8 SSI_ BCLK to SSI_TXD invalid / high impedence -2 — ns

S9 SSI_RXD / SSI_FS input setup before SSI_BCLK 10 — ns

S10 SSI_RXD / SSI_FS input hold after SSI_BCLK 0 — ns

ULPI_DATA[7:0]

(Data Output )

ULPI_DATA[7:0]

(Data Input )

ULPI_DIR / ULPI_NXT

(Control Input)

ULPI_STP

(Control Output)

USB_CLKIN U1

U4 U5

Electrical Characteristics

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 31

Figure 16. SSI Timing—Master Modes

Table 17. SSI Timing—Slave Modes1

1All timings specified with a capactive load of 25pF.

Num Description Symbol Min Max Units Notes

S11 SSI_BCLK cycle time t BCLK 8  tSYS —ns

S12 SSI_BCLK pulse width hig h / low 45% 55% tBCLK

S13 SSI_FS input setup before SSI_BCLK 10 — ns

S14 SSI_FS input hold after SSI_BCLK 2 — ns

S15 SSI_BCLK to SSI_TXD / SSI_FS output valid — 15 ns

S16 SSI_BCLK to SSI_TXD / SSI_FS output invalid / high

impedence 0— ns

S17 SSI_RXD setup before SSI_BCLK 10 — ns

S18 SSI_RXD hold after SSI_BCLK 2 — ns

SSI_MCLK

(Output)

SSI_BCLK

(Output)

SSI_FS

(Output)

SSI_TXD

SSI_RXD

S1 S2 S2

S4 S4

S5 S6

S7 S8 S8

S9 S10

SSI_FS

(Input)

S9 S10

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Electrical Characteristics

Freescale Semiconductor32

Figure 17. SSI Timing—Slave Modes

5.12 I2C Timing Specifications

Table 18 lists specifications for the I2C input timing paramete rs shown in Figure 18.

Table 19 lists specifications for the I2C output timing pa ram e ters shown in Figure 18.

Table 18. I2C Input Timing Specifications between SCL and SDA

Num Characteristic Min Max Units

I1 Start conditi on hold time 2 — tSYS

I2 Clock low per iod 8 — tSYS

I3 I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH =2.4 V) — 1 ms

I4 Data hold time 0 — ns

I5 I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL =0.5 V) — 1 ms

I6 Clock high time 4 — tSYS

I7 Data setup time 0 — ns

I8 Start condition setup time (for repeated start condition only) 2 — tSYS

I9 Stop condition setup time 2 — tSYS

Table 19. I2C Output Timing Specifications between SCL and SDA

Num Characteristic Min Max Units

I11Start condition hold time 6 — tSYS

I21Clock low period 10 — tSYS

I32I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH =2.4 V) — — µs

I41Data hold time 7 — tSYS

I53I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) — 3 ns

SSI_BCLK

(Input)

SSI_FS

(Input)

SSI_TXD

SSI_RXD

S11

S12 S12

S14

S15 S16 S16

S17 S18

S15

S13

SSI_FS

(Output)

S15 S16

Electrical Characteristics

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 33

Figure 18. I2C Input/Output Timings

5.13 Fast Ethernet Timing Specifications

The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing

specs/constraints for the physical interface.

5.13.1 Receive Signal Timing Specifications

The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices.

I61Clock high time 10 — tSYS

I71Data setup time 2 — tSYS

I81Start condition setup time (for repeated start condition only) 20 — tSYS

I91Stop condition setu p ti me 10 — tSYS

1Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum

frequency (IFDR = 0x20) results in minimum output timings as shown in Table 19. The I2C interface is

designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual

position is affected by the prescale and division values programme d into the IFDR. However, the numbers

given in Table 19 are minimum values.

2Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive

low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and

pull-up resistor values.

3Specified at a nominal 50-pF load.

Table 20. Receive Signal Timing

Num Characteristic MII Mode RMII Mode Unit

Min Max Min Max

— RXCLK frequency — 25 — 50 MHz

E1 RXD[n:0], RXDV, RXER to RXCLK setup1

1In MII mode, n = 3; In RMII mode, n = 1

5—4— ns

E2 RXCLK to RXD[n:0], RXDV, RXER hold15—2— ns

E3 RXCLK pulse width high 35% 65% 35% 65% RXCLK period

E4 RXCLK pulse width low 35% 65% 35% 65% RXCLK period

Table 19. I2C Output Timing Specifications between SCL and SDA (continued)

Num Characteristic Min Max Units

I2 I6

I1 I4 I7 I8 I9

I2C_SCL

I2C_SDA

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Electrical Characteristics

Freescale Semiconductor34

Figure 19. MII Receive Signal Timing Diagram

5.13.2 Transmit Signal Timing Specifications

Figure 20. MII Transmit Signal Timing Diagram

5.13.3 Asynchronous Input Signal Timing Specifications

Table 21. Transmit Signal Timing

Num Characteristic MII Mode RMII Mode Unit

Min Max Min Max

— TXCLK frequency — 25 — 50 MHz

E5 TXCLK to TXD[n:0], TXEN, TXER invalid1

1In MII mode, n = 3; In RMII mode, n = 1

5—5— ns

E6 TXCLK to TXD[n:0], TXEN, TXER va lid1— 25 — 14 ns

E7 TXCLK pulse width high 35% 65% 35% 65% tTXCLK

E8 TXCLK puls e width low 35% 65% 35% 65% tTXCLK

Table 22. MII Transmit Signal Timing

Num Characteristic Min Max Unit

E9 CRS, COL minimum pulse width 1.5 — TXCLK period

Valid Data

RXCLK (Input)

RXD[n:0]

RXDV,

RXER

E1 E2

Valid Data

TXCLK (Input)

TXD[n:0]

TXEN,

TXER

Electrical Characteristics

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 35

Figure 21. MII Async Inputs Timing Diagram

5.13.4 MII Serial Management Timing Specifications

Figure 22. MII Serial Management Channel TIming Diagram

5.14 32-Bit Timer Module Timing Specifications

Table 24 lists timer module AC tim in g s.

Table 23. MII Serial Management Channel Signal Timing

Num Characteristic Symbol Min Max Unit

E10 MDC cycle time tMDC 400 — ns

E11 MDC pulse width 40 60 % tMDC

E12 MDC to MDIO output valid — 375 ns

E13 MDC to MDIO output inva lid 25 — ns

E14 MDIO input to MDC setup 10 — ns

E15 MDIO input to MDC hold 0 — ns

Table 24. Timer Module AC Timing Specifications

Name Characteristic Min Max Unit

T1 DTnIN cycle time (n=0:3) 3 — t

sys/2

T2 DTnIN pulse width (n=0:3) 1 — t

sys/2

CRS, COL

MDC (Output)

E11

MDIO (Output)

MDIO (Input)

E11

E12 E13

Valid Data

E14 E15

Valid Data

E10

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Electrical Characteristics

Freescale Semiconductor36

5.15 ATA Interface Timing Specifications

The ATA controller is compatible with the ATA/ATAPI-6 industry standard. Refer to the ATA/ATAPI-6 Specficiation and the

ATA controller chapter of the MCF54455 Reference Manual for timing diagrams of the various modes of operation.

The timings of the various ATA data transfer modes are determ ined by a set of timing equations described in the ATA section

of the MCF54455 Reference Manual. These timing equations must be fulfilled for the ATA host to meet tim ing. Table 25

provides implementation specific timing parameters necessary to complete the timing equations.

5.16 DSPI Timing Specifications

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the

transfer attributes are programmable. Table 26 provides DSPI timing characteristics for classic SPI timing modes. Refer to the

DSPI chapter of the MCF54455 Reference Manual for information on the modified transfer formats used for communicating

with slower peripheral devices.

Table 25. ATA Interface Timing Specifications1,2

1These parameters are guaranteed by design and not testable.

2All timings specified with a capacitive load of 40pF.

Name Characteristic Symbol Min Max Unit Notes

A1 Setup time — ATA_IORDY to SYSCLK falling tSUI 4.0 — ns

A2 Hold time — ATA_IORDY from SYSCLK falling tHI 3.0 — ns

A3 Setup time — ATA_DATA[15:0] to SYSCLK rising tSU 4.0 — ns

A4 Propagation delay — SYSCLK rising to all outputs tCO —7.0ns 3

3Applies to ATA_CS[1:0], ATA_DA[2:0], ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA[15:0]

A5 Output skew tSKEW1 —1.5ns 3

A6 Setup time — ATA_DATA[15:0] valid to ATA_IORDY tI_DS 2.0 — ns 4

4Applies to Ultra DMA data-in burst only

A7 Hold time — ATA_IORDY to ATA_DATA[15:0] invalid tI_DH 3.5 — ns 4

Table 26. DSPI Module AC Timing Specifications1

Name Characteristic Symbol Min Max Unit Notes

DS1 D SPI_SCK Cycle Time tSCK 4 x tSYS —ns

DS2 D SPI_SCK Duty Cycle — (tsck 2) - 2.0 (tsck 2) + 2.0 ns 3

Master Mode

DS3 DSPI_PCSn to DSPI_SCK delay tCSC (2  tSYS) - 1.5 — ns 4

DS4 DSPI_SCK to DSPI_PCSn delay tASC (2  tSYS) - 3.0 — ns 5

DS5 DSPI_SCK to DSPI_SOUT valid — — 5 ns

DS6 DSPI_SCK to DSPI_SOUT invalid — -5 — ns

DS7 DSPI_SIN to DSPI_SCK input setup — 9 — n s

DS8 DSPI_SCK to DSPI_SIN input hold — 0 — ns

Slave Mode

DS9 D SPI_SCK to DSPI_SOUT valid — — 10 ns

Electrical Characteristics

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 37

Figure 23. DSPI Classic SPI Timing—Master Mode

DS10 DSPI_SCK to DSPI_SOUT invalid — 0 — ns

DS11 DSPI_SIN to DSPI_SCK input setup — 2 — ns

DS12 DSPI_SCK to DSPI_SIN input hold — 7 — ns

DS13 DSPI_SS active to DSPI_SOUT driven — — 10 ns

DS14 DSPI_SS inactive to DSPI_SOUT not driven — — 10 ns

1Timings shown are f or DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin

on the odd-numbered DSPI_SCK edge s and driven on the DSPI_SOUT pin on even -numbered DSPI edges.

2When in master mode, the baud rate is programmable in DCTARn[DBR], DCTARn[PBR], and DCTARn[BR].

3This specification assumes a 50/50 duty cycle setting. The duty cycle is programmable in DCTARn[DBR],

DCTARn[CPHA], and DCTARn[PBR].

4The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK].

5The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].

Table 26. DSPI Module AC Timing Specifications1 (continued)

Name Characteristic Symbol Min Max Unit Notes

DSPI_PCSn

DSPI_SCK

DSPI_SOUT

DSPI_SIN

DSPI_SCK

(DCTARn[CPOL] = 1)

(DCTARn[CPOL] = 0)

Data Last Data

First Data

First Data Data Last Data

DS1

DS2

DS3 DS4

DS5

DS6

DS7

DS8

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Electrical Characteristics

Freescale Semiconductor38

Figure 24. DSPI Classic SPI Timing—Slave Mode

5.17 SBF Timing Specifications

The Serial Boot Facility (SBF) provides a means to read configuration information and system boot code from a broad array of

SPI-compatible EEPROMs, flashes, FRAMs, nVSRAMs, etc. Table 27 provides the AC timing specifications for the SBF.

Table 27. SBF AC Timing Specifications

Name Characteristic Symbol Min Max Unit Notes

SB1 SBF_CK Cycle Time tSBFCK 40 — ns 1

1At reset, the SBF_CK cycle time is tREF  67. The first byte of data read from the serial memory contains a divider value

that is used to set the SBF_CK cycle time for the duration of the serial boot process.

SB2 SBF_CK High/Low Time — 3 0% — tSBFCK

SB3 SBF_CS to SBF_CK delay — tSBFCK - 2.0 — ns

SB4 SBF_CK to SBF_CS delay — tSBFCK - 2.0 — ns

SB5 SBF_CK to SBF_DO valid — -5 — ns

SB6 SBF_CK to SBF_DO inv a lid — 5 — ns

SB7 SBF_DI to SBF_SCK input setup — 10 — ns

SB8 SBF_CK to SBF_DI input hold — 0 — ns

DSPI_SS

DSPI_SCK

DSPI_SOUT

DSPI_SIN

DSPI_SCK

(DCTARn[CPOL] = 1)

(DCTARn[CPOL] = 0)

Last Data

First Data

Data

First Data Last Data

DS1

DS2

DS9

DS10

DS11 DS12

DS13 DS14

Electrical Characteristics

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 39

Figure 25. SBF Timing

5.18 General Purpose I/O Timing Specifications

Figure 26. GPIO Timing

Table 28. GPIO Timing1

1These general purpose specifications apply to the following signals: IRQn, all UART signals, all timer

signals, DACKn and DREQn, and all signals configured as GPIO.

Num Characteristic Min Max Unit

G1 FB_CLK High to GP IO Output Valid — 9 ns

G2 FB_CLK High to GPIO Output Invalid 1.5 — ns

G3 GPIO Input Valid to FB_CLK High 9 — ns

G4 FB_CLK High to GPIO Input Invalid 1.5 — ns

SBF_CS

SBF_DO

SBF_DI Data Last Data

First Data

First Data Data Last Data

SB3 SB4

SB5

SB6

SBF_CK

SB1

SB2 SB2

SB7 SB8

FB_CLK

GPIO Outputs

G3 G4

GPIO Input s

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Electrical Characteristics

Freescale Semiconductor40

5.19 JTAG and Boundary Scan Timing

Figure 27. Test Clock Input Timing

Table 29. JTAG and Boundary Scan Timing

Num Characteristics1

1JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.

Min Max Unit

J1 TCLK Frequency of Operation DC 20 MHz

J2 TCLK Cycle Per iod 50 — ns

J3 TCLK Clock Pulse Width 20 30 ns

J4 TCLK Rise and Fall Times — 3 ns

J5 Boundary Scan Input Data Setup Time to TCLK Rise 5 — ns

J6 Boun dary Scan Input Data Hold Time after TCLK Rise 20 — ns

J7 TCLK Low to Boundary Scan Output Data Valid — 33 ns

J8 TCLK Low to Boundary Scan Output High Z — 3 3 ns

J9 TMS, TDI Input Data Setup Time to TC L K Ris e 4 — ns

J10 TMS, TDI Input Data Hold Time after TCLK Rise 10 — ns

J11 TCLK Low to TDO Data Valid — 11 ns

J12 TCLK Low to TDO High Z — 11 ns

J13 TRST Assert Time 50 — ns

J14 TRST Setup Time (Negation) to TCLK High 10 — ns

TCLK VIL

VIH

J4 J4

(input)

J3 J3

Electrical Characteristics

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 41

Figure 28. Boundary Scan (JTAG) Timing

Figure 29. Test Access Port Timing

Figure 30. TRST Timing

Input Data Valid

Output Data Valid

TCLK

Data Inputs

Data Outputs

VIL VIH

J6J5

Input Data Valid

Output Data Valid

TCLK

TDI

TDO

TMS

VIL VIH

J9 J10

J11

J12

J11

TCLK

TRST

J13

J14

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Electrical Characteristics

Freescale Semiconductor42

5.20 Debug AC Timing Specifications

Table 30 lists specifications for the debug AC timing parameters shown in Figure 31 and Table 32.

Figure 31. Real-Time Trace AC Timing

Figure 3 2. BDM Serial Port AC Timing

Table 30. Debug AC Timin g Specification

Num Characteristic Min Max Units

D0 PSTCLK cycle time 1 1 tSYS

D1 PSTCLK rising to PSTDDATA valid — 3.0 ns

D2 PSTCLK rising to PSTDDATA invalid 1.5 — n s

D3 DSI-to-DSCLK setup 1 — PSTCLK

D41

1DSCLK and DSI are synchronized inter nally. D4 is measured from the synchronized

DSCLK input relative to the rising ed ge of PSTCLK.

DSCLK-to-DSO hold 4 — PSTCLK

D5 DSCLK cycle time 5 — PSTCLK

D6 BKPT assertion time 1 — PSTCLK

PSTCLK

PSTDDATA[7:0]

D1 D2

Past

Current

DSCLK

DSI

DSO

Current

Power Consumption

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 43

6 Power Consumption

All power consumption data is lab data measured on an M54455 EVB running the Freescale Linux BSP.

Figure 33. Power Consumption in Various Applications

Table 31. MCF4455 Application Power Consumption1

1All voltage rails at nominal values: IVDD = 1.5 V, EVDD = 3.3 V, and SDVDD = 1.8 V.

Core

Freq. Idle MP3

Playback TFTP

Download USB HS

File Copy Units

266 MHz

IVDD 215.6 288.8 274.4 263.7

mAEVDD 27.6 33.6 32.6 32.4

SDVDD 142.9 158.2 161.1 158.0

Total Power 672 829 809 787 mW

200 MHz

IVDD 163.8 228.0 213.8 207.9

mAEVDD 29.9 34.7 34.3 33.8

SDVDD 142.2 158.5 160.0 153.4

Total Power 601 742 722 699 mW

500

550

600

650

700

750

800

850

Idl e M P3 P la yba ck TF T P Download US B HS F i l e Copy

T o tal Po w er (m W)

266 MHz 200 MHz

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Power Consumption

Freescale Semiconductor44

All current consumption data is lab data measured on a single device using an evaluation board. Table 32 shows the typical

power consumption in low-power modes. These current measurements are taken after executing a STOP instruction.

Table 32. Current Consumption in Low-Power Modes1,2

1All values are measured on an M54455EVB with 1.5V IVDD power supply. Tests performed at room

temperature.

2Refer to the Power Management chapter in the MCF54455 Reference Manual for more information

on low-power modes.

Mode Voltage Supply System Frequency

166 (Typ)3

3All peripheral clocks are off e xcept U AR T0, INTC0, IA CK, edge port, reset controller , CCM, PLL, and

FlexBus pr ior to entering low-power mode.

200 (Typ)3233 (Typ)3266 (Typ)3266 (Peak)4

4All peripheral clocks on prior to entering low-power mode.

RUN IVDD (mA) 93.4 110.9 128.2 145.4 202.1

Power (mW) 140.1 166.3 192.4 218.1 303.2

WAIT/DOZE IVDD (mA) 28.0 32.7 37.5 41.1 100.2

Power (mW) 42.0 49.1 56.2 61.7 150.3

STOP 0 IVDD (mA) 17.1 19.8 22.5 25.2 25.2

Power (mW) 25.7 29.7 33.7 37.8 37.8

STOP 1 IVDD (mA) 17.9 19.8 22.4 25.1 25.1

Power (mW) 26.8 29.6 33.6 37.6 37.6

STOP 2 IVDD (mA)5.75.75.75.75.7

Power (mW) 8.6 8.6 8.6 8.6 8.6

STOP 3 IVDD (mA)1.81.81.81.81.8

Power (mW) 2.6 2.6 2.6 2.6 2.6

Package Information

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Freescale Semiconductor 45

Figure 34. IVDD Power Consumption in Low-Power Modes

7 Package Information

The latest package outline drawings are avail able on the product summary pages on http://www.freescale.com/coldfire.

Table 33 lists the case outline numbers per device. Use these numbers in the web page’ s keyword search engine to find the latest

package outline drawings.

8 Product Documentation

Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution

Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire.

Table 33. Package In format io n

Device Package Type Case Outline Numbers

MCF54450 256 MAPBGA 98ARH98219A

MCF54451

MCF54452

360 TEPBGA 98ARE10605D

MCF54453

MCF54454

MCF54455

0.0

25.0

50.0

75.0

100.0

125.0

150.0

175.0

200.0

225.0

250.0

275.0

300.0

325.0

166 200 233 266 266 (peak)

System Frequency (M Hz)

IVDD Power Consumpti on (m W)

Run

Wait/Doze

Stop 0

Stop 1

Stop 2

Stop 3

MCF5445x ColdFire Microprocessor Data Sheet, Rev. 8

Revision History

Freescale Semiconductor46

9 Re vision History

Table 34 summarizes revisions to this document.

Table 34. Revision History

Rev. No. Date Summary of Changes

0 Sept 17, 2007 Initial public release.

1 Feb 15, 2008 Corrected VSS pin locations in MCF5445x signal information and muxing table for the 360 TEPBGA

package: changed “...M9, M16, M17...” to “...M9–M14, M16...”

Updated FlexBus read and write timing dia grams and added two notes before them.

Change FB_A[23:0] to FB_A[31:0] in FlexBus read and write timing diagrams.

Added power consumption section.

2 May 1, 2008 In Family Configuration s table, added PCI as feature on 256-pin devices. On these devices the

PCI_AD bus is limited to 24-bits.

In Absolute Maximum Ratings table, changed RTCVDD specification from “-0.3 to +4.0” to “-0.5 to

+2.0”.

In DC Electrical Specifications table:

• Changed RTCVDD specification from 3.0–3.6 to 1.35–1.65.

• Changed High Impedance (Off-State) Leakage Current (IOZ) specification from ±1 to ±10A, and

added footnote to this spec: “Worst-case tristate leakage current with only one I/O pin high. Since

all I/Os share power when high, the leakage current is distributed among them. With all I/Os high,

this spec reduces to ±2 A min/max.“

3 Dec 1, 2008 Changed “360PBGA” heading to “360 TEPBGA” in Table 6.

Changed the following specs in Table 13:

• Minimum frequency of operation from — to 60MHz.

• Maximum clock period from — to 16.67 ns.

4 Apr 12, 2009 R escinded previous errata, the 256-pin devices do not contain the PCI bus controller:

•In Table 4, in PCI_ADn signal section, added a separate row for each package, with PCI_ADn

signals shown as — for 256-pin devices.

•In Figure 5, changed the PCI_ADn pins to their alternative function, FB_An.

5 Apr 27, 2009 In Table 2 changed MCF54450VM180 to MCF54450CVM180 and changed it’s temperature entry

from “0 to +70 C” to “–40 to +85 C”.

6 Oct 15, 2009 In Table 8 changed Input Leakag e Current (I in) from ±1.0 to ±2.5A.

7 Oct 18, 2011 In Table 2, added MCF54452YVR200 part number, with temperature range from –40 to +105 C.

In Table 8, added Input Leakage Cu rrent (Iin) values for MCF54452YVR200 part number.

8 Jan 18, 2012 In Table 4, added pin N7 in the VSS pin list for the 360 TEPBGA.

Document Number : MCF54455

Rev. 8

02/2012

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