ICOLL
V+
VAC
+
+
1
2
3
4
5 6
7
8
9
10
-
VLED
GND
VCC
FILTER
NC
NC
ISNS
GATE
NC
COFF
NC
LM3444
VLED-
D3
C7
C9
C10
D4 D8
D9
R2
D1
Q1
C5
C12
D2
D10
Q2
L2
Q3
R3
R4
C11
C4
U1
VBUCK
BR1
LINE VOLTAGE (VAC)
EFFICIENCY (%)
95.0
90.0
85.0
80.0
75.0
80 90 100 110 120 130 140
14 Series connected LEDs
10 Series connected LEDs
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
LM3444
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
LM3444 AC-DC Offline LED Driver
1 Features 3 Description
The LM3444 is an adaptive constant off-time AC/DC
1• Application Voltage Range: 80 VAC to 277 VAC buck (step-down) constant current controller that
• Capable of Controlling LED Currents provides a constant current for illuminating high
Greater than 1 A power LEDs. The high-frequency capable
architecture allows the use of small external passive
• Adjustable Switching Frequency components. A passive PFC circuit ensures good
• Low Quiescent Current power factor by drawing current directly from the line
• Adaptive Programmable Off-Time Allows for for most of the cycle, and provides a constant positive
Constant Ripple Current voltage to the buck regulator. Additional features
include thermal shutdown, current limit and VCC
• Thermal Shutdown undervoltage lockout. The LM3444 is available in a
• No Flicker at 120 Hz low profile 10-pin VSSOP package or an 8-lead SOIC
• Low-Profile 10-Pin VSSOP Package package.
or 8-Lead SOIC Package Device Information(1)
• Patented Drive Architecture PART NUMBER PACKAGE BODY SIZE (NOM)
2 Applications VSSOP (10) 3.00 mm × 3.00 mm
LM3444 SOIC (8) 3.91 mm × 4.90 mm
• Solid State Lighting
• Industrial and Commercial Lighting (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Residential Lighting
SPACE
Typical LM3444 LED Driver Application Circuit Efficiency vs Line Voltage
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3444
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 13
1 Features.................................................................. 18 Application and Implementation ........................ 14
2 Applications ........................................................... 18.1 Application Information............................................ 14
3 Description............................................................. 18.2 Typical Application ................................................. 20
4 Revision History..................................................... 29 Power Supply Recommendations...................... 25
5 Pin Configuration and Functions......................... 310 Layout................................................................... 25
6 Specifications......................................................... 410.1 Layout Guidelines ................................................. 25
6.1 Absolute Maximum Ratings ..................................... 410.2 Layout Example .................................................... 25
6.2 ESD Ratings.............................................................. 411 Device and Documentation Support................. 26
6.3 Recommended Operating Conditions....................... 411.1 Device Support .................................................... 26
6.4 Thermal Information.................................................. 411.2 Community Resources.......................................... 26
6.5 Electrical Characteristics........................................... 511.3 Trademarks........................................................... 26
6.6 Typical Characteristics.............................................. 611.4 Electrostatic Discharge Caution............................ 26
7 Detailed Description.............................................. 811.5 Glossary................................................................ 26
7.1 Overview................................................................... 812 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram......................................... 8Information........................................................... 26
7.3 Feature Description................................................... 8
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2013) to Revision D Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
Changes from Revision B (May 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 23
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1
4
3
2
10
7
8
9
ISNS
NC
GATE
NC
COFF
VCC
NC
NC
5 6FILTER GND
3
2
1
6
7
8
VCC
NC
NC
GND
COFF
FILTER
4 5
ISNS GATE
LM3444
www.ti.com
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
5 Pin Configuration and Functions
DGS Package D Package
10-Pin VSSOP 8-Lead SOIC
Top View Top View
Pin Functions
PIN I/O DESCRIPTION
NAME VSSOP SOIC
OFF time setting pin. A user set current and capacitor connected from the
COFF 4 8 I output to this pin sets the constant OFF time of the switching controller.
Filter input. A low pass filter tied to this pin can filter a PWM dimming signal to
supply a DC voltage to control the LED current. Can also be used as an analog
FILTER 5 2 I dimming input. If not used for dimming connect a 0.1-µF capacitor from this pin
to ground.
Power MOSFET driver pin. This output provides the gate drive for the power
GATE 8 5 O switching MOSFET of the buck controller.
GND 6 3 — Circuit ground connection
LED current sense pin. Connect a resistor from main switching MOSFET
ISNS 7 4 I source, ISNS to GND to set the maximum LED current.
NC 1, 2, 3, 10 1, 7 — No internal connection. Leave this pin open.
Input voltage pin. This pin provides the power for the internal control circuitry
VCC 9 6 O and gate driver.
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SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VCC and GATE to GND –0.3 14 V
ISNS to GND –0.3 2.5 V
FILTER and COFF to GND –0.3 7 V
COFF input current 60 mA
Continuous power dissipation(3) Internally limited
TJJunction temperature 150 °C
Maximum lead temperature (soldering) 260 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 165°C (typical) and
disengages at TJ= 145°C (typical).
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±1250
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions MIN MAX UNIT
VCC 8 13 V
TJJunction temperature –40 125 °C
6.4 Thermal Information LM3444
THERMAL METRIC(1) DGS (VSSOP) D (SOIC) UNIT
10 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 163.8 111.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 58.4 58.0 °C/W
RθJB Junction-to-board thermal resistance 83.6 51.1 °C/W
ψJT Junction-to-top characterization parameter 6.1 11.9 °C/W
ψJB Junction-to-board characterization parameter 82.3 51.0 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
6.5 Electrical Characteristics
All typical limits are for TJ= 25°C and all maximum and minimum limits apply over the full operating temperature range
(TJ=−40°C to 125°C). Minimum and maximum limits are specified through test, design, or statistical correlation. Typical
values represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VCC = 12 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC SUPPLY
IVCC Operating supply current 1.58 2.25 mA
Rising threshold 7.4 7.7
VCC-UVLO Falling threshold 6 6.4 V
Hysterisis 1
COFF
VCOFF Time-out threshold 1.225 1.276 1.327 V
RCOFF Off timer sinking impedance 33 60 Ω
tCOFF Restart timer 180 µs
CURRENT LIMIT
VISNS ISNS limit threshold 1.174 1.269 1.364 V
Leading edge blanking time 125 ns
tISNS Current limit reset delay 180 µs
ISNS limit to GATE delay ISNS = 0 to 1.75-V step 33 ns
CURRENT SENSE COMPARATOR
VFILTER FILTER open circuit voltage 720 750 780 mV
RFILTER FILTER impedance 1.12 MΩ
VOS Current sense comparator offset voltage –4 0.1 4 mV
GATE DRIVE OUTPUT
VDRVH GATE high saturation IGATE = 50 mA 0.24 0.5 V
VDRVL GATE low saturation IGATE = 100 mA 0.22 0.5
Peak souce current GATE = VCC/2 –0.77
IDRV A
Peak sink current GATE = VCC/2 0.88
Rise time Cload = 1 nF 15
tDV ns
Fall time Cload = 1 nF 15
THERMAL SHUTDOWN
Thermal shutdown temperature 165
TSD See (1) °C
Thermal shutdown hysteresis 20
(1) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design. In applications where high power dissipation
and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient
temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation
of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as
given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
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VBUCK (V)
NORMALIZED SW FREQ
1.50
1.25
1.00
0.75
0.50
0.250 50 100 150 200
3 LEDs
5 LEDs
7 LEDs
9 LEDs
Series
connected LEDs
UVLO (V)
8.0
7.5
7.0
6.5
6.0
-50 -25 0 25 50 75 100 125 150
UVLO (VCC) Rising
UVLO (VCC) Falling
TEMPERATURE (°C)
200.0
190.0
180.0
170.0
160.0
150.0
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
tON-MIN (ns)
LINE VOLTAGE (VAC)
fSW (Hz)
300k
250k
200k
150k
100k
50k
0
80 90 100 110 120 130 140
C11 = 2.2 nF, R3 = 348 k:
7 LEDs in Series (VO = 24.5V)
LINE VOLTAGE (VAC)
EFFICIENCY (%)
95.0
90.0
85.0
80.0
75.0
80 90 100 110 120 130 140
14 Series connected LEDs
10 Series connected LEDs
LM3444
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
www.ti.com
6.6 Typical Characteristics
Figure 1. fSW vs Input Line Voltage Figure 2. Efficiency vs Input Line Voltage
Figure 3. VCC UVLO vs Temperature Figure 4. Minimum On-Time (tON) vs Temperature
Figure 6. Normalized Variation in fSW Over VBUCK Voltage
Figure 5. Off Threshold (C11) vs Temperature
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LEADING EDGE BLANKING (ns)
NUMBER OF UNITS
15.0
10.0
5.0
0.0
80 100 120 140 160 180
Room (25°C) Hot (125°C)
Cold (-40°C)
100 units tested
LM3444
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SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
Typical Characteristics (continued)
Figure 7. Leading Edge Blanking Variation Over Temperature
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LM3444
VCC UVLO
S
R
Q
PWM
I-LIM
1.27V ISNS
COFF
MOSFET
DRIVER
PGND
GATE
FILTER
VCC
1.276V
THERMAL
SHUTDOWN
1M
1k
INTERNAL
REGULATORS
750 mV
33Ö
125 ns
LEADING EDGE BLANKING
COFF
LATCH
CONTROLLER
START
LM3444
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
www.ti.com
7 Detailed Description
7.1 Overview
The LM3444 device contains all the necessary circuitry to build a line-powered (mains powered) constant current
LED driver.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Theory of Operation
For an image of the LM3444 along with basic external circuitry, see Figure 8.
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ICOLL
V+
VAC
+
+
1
2
3
4
5 6
7
8
9
10
-
VLED
GND
VCC
FILTER
NC
NC
ISNS
GATE
NC
COFF
NC
LM3444
VLED-
D3
C7
C9
C10
D4 D8
D9
R2
D1
Q1
C5
C12
D2
D10
Q2
L2
Q3
R3
R4
C11
C4
U1
VBUCK
BR1
LM3444
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SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
Feature Description (continued)
Figure 8. LM3444 Schematic
7.3.2 Valley-Fill Circuit
VBUCK supplies the power which drives the LED string. Diode D3 allows VBUCK to remain high while V+ cycles on
and off. VBUCK has a relatively small hold capacitor C10 which reduces the voltage ripple when the valley fill
capacitors are being charged. However, the network of diodes and capacitors shown between D3 and C10 make
up a valley-fill circuit. The valley-fill circuit can be configured with two or three stages. The most common
configuration is two stages. Figure 9 illustrates a two- and three-stage valley-fill circuit.
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VVF-CAP = 2
VAC-RMS
2
+
+
D3
C7
C9
C10
D4 D8
VBUCK
V+
+
-
+
-
2
VBUCK
2
VBUCK
+
+
+
D3
C7
C8
C9
C10
D4 D5
D6
D7
D8
R7
R8
D9 R6
VBUCK
V+
+
+
D3
C7
C9
C10
D4 D8
D9
R7
R6
R8
VBUCK
V+
LM3444
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
www.ti.com
Feature Description (continued)
Figure 9. Two and Three Stage Valley Fill Circuit
The valley-fill circuit allows the buck regulator to draw power throughout a larger portion of the AC line. This
allows the capacitance needed at VBUCK to be lower than if there were no valley-fill circuit, and adds passive
power factor correction (PFC) to the application.
7.3.3 Valley-Fill Operation
When the input line is high, power is derived directly through D3. The term input line is high is explained as
follows. The valley-fill circuit charges capacitors C7 and C9 in series (Figure 10) when the input line is high.
Figure 10. Two Stage Valley-Fill Circuit When AC Line is High
The peak voltage of a two-stage valley-fill capacitor is given by Equation 1.
(1)
As the AC line decreases from its peak value every cycle, there is a point where the voltage magnitude of the AC
line is equal to the voltage that each capacitor is charged. At this point, diode D3 becomes reversed biased, and
the capacitors are placed in parallel to each other (Figure 11), and VBUCK equals the capacitor voltage.
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VVF-CAP = 2
VAC-RMS
3
+
+
D3
C7
C9
C10
D4 D8
D9
VBUCK
V+
+
-
+
-
VBUCK
VBUCK
LM3444
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SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
Feature Description (continued)
Figure 11. Two Stage Valley-Fill Circuit when AC Line is Low
A three stage valley-fill circuit performs exactly the same as two-stage valley-fill circuit, except now three
capacitors are charged in series when the line voltage decreases, as shown in Equation 2:
(2)
Diode D3 is reverse-biased and three capacitors are in parallel to each other.
The valley-fill circuit can be optimized for power factor, voltage hold-up, and overall application size and cost.
The LM3444 operates with a single-stage or a three-stage valley-fill circuit as well. Resistor R8 functions as a
current limiting resistor during start-up, and during the transition from series to parallel connection. Resistors R6
and R7 are 1-MΩbleeder resistors, and may or may not be necessary for each application.
7.3.4 Buck Converter
The LM3444 is a buck controller that uses a proprietary constant off-time method to maintain constant current
through a string of LEDs. While transistor Q2 is on, current ramps up through the inductor and LED string. A
resistor R3 senses this current and this voltage is compared to the reference voltage at FILTER. When this
sensed voltage is equal to the reference voltage, transistor Q2 is turned off and diode D10 conducts the current
through the inductor and LEDs. Capacitor C12 eliminates most of the ripple current seen in the inductor. Resistor
R4, capacitor C11, and transistor Q3 provide a linear current ramp that sets the constant off-time for a given
output voltage.
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= D = tON
tON + tOFF = tON x fSW
VO
VIN
L2
R3
C11
Q2
Q3
D10
ICOLL
4
6
7
8
R4
PGND
ISNS
GATE
COFF
LM3444
VBUCK
C12
LM3444
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
www.ti.com
Feature Description (continued)
Figure 12. LM3444 Buck Regulation Circuit
7.3.5 Overview Of Constant Off-Time Control
The conversion ratio of a buck converter is defined as given by Equation 3.
(3)
Constant off-time control architecture operates by simply defining the off-time and allowing the on-time, and
therefore the switching frequency, to vary as either VIN or VOchanges. The output voltage is equal to the LED
string voltage (VLED), and should not change significantly for a given application. The input voltage or VBUCK in
this analysis varies as the input line varies. The length of the on-time is determined by the sensed inductor
current through a resistor to a voltage reference at a comparator. During the on-time, denoted by tON, MOSFET
switch Q2 is on causing the inductor current to increase. During the on-time, current flows from VBUCK, through
the LEDs, through L2, Q2, and finally through R3 to ground. At some point in time, the inductor current reaches a
maximum (IL2-PK) determined by the voltage sensed at R3 and the ISNS pin. This sensed voltage across R3 is
compared against the voltage of FILTER, at which point Q2 is turned off by the controller.
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t
tOFF
tON
IL2 (t)
IAVE
IL2-PK
'iL
IL2-MIN
LM3444
www.ti.com
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
Feature Description (continued)
Figure 13. Inductor Current Waveform in CCM
During the off-period denoted by tOFF, the current through L2 continues to flow through the LEDs through D10.
7.3.6 Thermal Shutdown
Thermal shutdown limits total power dissipation by turning off the output switch when the IC junction temperature
exceeds 165°C. After thermal shutdown occurs, the output switch does not turn on until the junction temperature
drops to approximately 145°C.
7.4 Device Functional Modes
This device does not have any additional functional modes.
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D
tON
fSW =,and 1 - D
tOFF
fSW =
1
tOFF + tON
fSW =
D = tON
tON + tOFF =VLED
VBUCK
'¶=tOFF
tON + tOFF
tOFF = C11 x 1.276V x R4
VLED
dv
i = C dt
= D
1
K
VLED
VBUCK
u
= D = tON
tON + tOFF = tON x fSW
VLED
VBUCK
LM3444
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Determining Duty-Cycle (D)
Equation 4 shows the duty-cycle (D).
(4)
Equation 5 shows the duty-cycle with efficiency considered.
(5)
For simplicity, choose efficiency from 75% to 85%.
8.1.2 Calculating Off-Time
The off-time of the LM3444 is set by the user and remains fairly constant as long as the voltage of the LED stack
remains constant. Calculating the off-time is the first step in determining the switching frequency of the converter,
which is integral in determining some external component values.
PNP transistor Q3, resistor R4, and the LED string voltage define a charging current into capacitor C11. A
constant current into a capacitor creates a linear charging characteristic.
(6)
Resistor R4, capacitor C11 and the current through resistor R4 (iCOLL), which is approximately equal to VLED/R4,
are all fixed. Therefore, dv is fixed and linear, and dt (tOFF) can now be calculated as shown in Equation 7.
(7)
Common equations for determining duty-cycle and switching frequency in any buck converter are shown in
Equation 8.
(8)
Therefore, Equation 9 shows:
(9)
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VLED(MIN)
tON(MIN) = VBUCK(MAX) fSW
1
K
1u
VBUCK (V)
NORMALIZED SW FREQ
1.50
1.25
1.00
0.75
0.50
0.250 50 100 150 200
3 LEDs
5 LEDs
7 LEDs
9 LEDs
Series
connected LEDs
1
K
VLED
VBUCK
u¸
¹
·
¨
©
§
fSW =
1
tOFF
VLED = K u D
VBUCK
LM3444
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SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
Application Information (continued)
With efficiency of the buck converter in mind, Equation 10 shows:
(10)
Substituting and rearranging the equations, Equation 11 shows:
(11)
Off-time and switching frequency can now be calculated using the previous equations.
8.1.3 Setting the Switching Frequency
Selecting the switching frequency for nominal operating conditions is based on tradeoffs between efficiency
(better at low frequency) and solution size and cost (smaller at high frequency).
The input voltage to the buck converter (VBUCK) changes with both line variations and over the course of each
half-cycle of the input line voltage. The voltage across the LED string, however, remains constant, and therefore
the off-time remains constant.
The on-time, and therefore the switching frequency, varies as the VBUCK voltage changes with line voltage. A
good design practice is to choose a desired nominal switching frequency knowing that the switching frequency
decreases as the line voltage drops, and increases as the line voltage increases (Figure 14).
Figure 14. Graphical Illustration of Switching Frequency vs VBUCK
The off-time of the LM3444 can be programmed for switching frequencies ranging from 30 kHz to over 1 MHz. A
trade-off between efficiency and solution size must be considered when designing the LM3444 application.
The maximum switching frequency attainable is limited only by the minimum on-time requirement (200 ns).
Worst case scenario for minimum on time is when VBUCK is at its maximum voltage (AC high line) and the LED
string voltage (VLED) is at its minimum value, as shown in Equation 12.
(12)
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di
Q = L dt
-
C12
R3
Q2
-
D10
VLED
VBUCK
VL2
L2
VBUCK(MAX) = VAC-RMS(MAX) x2
LM3444
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
www.ti.com
Application Information (continued)
The maximum voltage seen by the Buck Converter is given by Equation 13.
(13)
8.1.4 Inductor Selection
The controlled off-time architecture of the LM3444 regulates the average current through the inductor (L2), and
therefore the LED string current. The input voltage to the buck converter (VBUCK) changes with line variations and
over the course of each half-cycle of the input line voltage. The voltage across the LED string is relatively
constant, and therefore the current through R4 is constant. This current sets the off-time of the converter and
therefore the output volt-second product (VLED × off-time) remains constant. A constant volt-second product
makes it possible to keep the ripple through the inductor constant as the voltage at VBUCK varies.
Figure 15. LM3444 External Components of the Buck Converter
Use Equation 14 to calculate an ideal inductor.
(14)
Given a fixed inductor value, L, Equation 14 states that the change in the inductor current over time is
proportional to the voltage applied across the inductor.
During the on-time, the voltage applied across the inductor is given in Equation 15.
VL(ON-TIME) = VBUCK - (VLED + VDS(Q2) + IL2 × R3) (15)
Because the voltage across the MOSFET switch (Q2) is relatively small, as is the voltage across sense resistor
R3, we can approximately simplify this as shown in Equation 16,
VL(ON-TIME) = VBUCK - VLED (16)
During the off-time, the voltage seen by the inductor is given by Equation 17.
VL(OFF-TIME) = VLED (17)
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t
tOFF
tON
IL2 (t)
IAVE
IL2-PK
'iL
IL2-MIN
L2 = fSW x 'i
VLED VLED
VBUCK
1 K
1u
VLED
tOFF = VBUCK
fSW
1 K
1u
L2 #tOFF x VLED
'i
'i #tOFF x VLED
L2
VL(OFF-TIME) = VLED = L x 'i
't
VL(OFF-TIME) = VLED = L x (I(MAX) - I(MIN))
't
LM3444
www.ti.com
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
Application Information (continued)
The value of VL(OFF-TIME) is relatively constant, because the LED stack voltage remains constant. If we rewrite the
equation for an inductor inserting what we know about the circuit during the off-time, Equation 18 shows that we
get:
(18)
Rearranging this gives Equation 19.
(19)
From this, we can see that the ripple current (Δi) is proportional to off-time (tOFF) multiplied by a voltage, which is
dominated by VLED divided by a constant (L2).
These equations can be rearranged to calculate the desired value for inductor L2, as shown in Equation 20.
(20)
The off time can be calculated using Equation 21:
(21)
Substituting toff in Equation 21 results in Equation 22:
(22)
See Typical Application to better understand the design process.
8.1.5 Setting the LED Current
The LM3444 constant off-time control loop regulates the peak inductor current (IL2). The average inductor current
equals the average LED current (IAVE). Therefore the average LED current is regulated by regulating the peak
inductor current.
Figure 16. Inductor Current Waveform in CCM
Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM3444
VBUCK
8.33 ms
30°
tX
t
150°
180°0°
VVF-CAP = 2
VAC(MAX)
#stages
IL-PK(UNDIM) = 750 mV
R3
IAVE(UNDIM) = IL2-PK(UNDIM) - 'iL
2
IL2-PK = IAVE + 'iL
2
LM3444
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
www.ti.com
Application Information (continued)
Knowing the desired average LED current, IAVE, and the nominal inductor current ripple, ΔiL, the peak current for
an application running in continuous conduction mode (CCM) is defined in Equation 23.
(23)
The LED current would then be calculated using Equation 24.
(24)
This is important to calculate because this peak current multiplied by the sense resistor R3 determines when the
internal comparator is tripped. The internal comparator turns the control MOSFET off once the peak sensed
voltage reaches 750 mV.
(25)
Current Limit: The trip voltage on the PWM comparator is 750 mV. However, if there is a short circuit or an
excessive load on the output, higher than normal switch currents cause a voltage greater than 1.27 V on the
ISNS pin which trip the I-LIM comparator. The I-LIM comparator resets the RS latch, turning off Q2. It also
inhibits the Start Pulse Generator and the COFF comparator by holding the COFF pin low. A delay circuit
prevents the start of another cycle for 180 µs.
8.1.6 Valley Fill Capacitors
Determining voltage rating and capacitance value of the valley-fill capacitors:
The maximum voltage seen by the valley-fill capacitors is calculated by Equation 26.
(26)
This is, of course, if the capacitors chosen have identical capacitance values and split the line voltage equally.
Often a 20% difference in capacitance could be observed between like capacitors. Therefore a voltage rating
margin of 25% to 50% should be considered.
8.1.7 Determining the Capacitance Value of the Valley-Fill Capacitors
The valley-fill capacitors must be sized to supply energy to the buck converter (VBUCK) when the input line is less
than its peak divided by the number of stages used in the valley fill (tX). The capacitance value must be
calculated for the maximum LED current.
Figure 17. Two Stage Valley-Fill VBUCK Voltage
18 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LM3444
VAC-RMS-PK 2
VAC
t
VPEAK
LM3444
www.ti.com
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
Application Information (continued)
From Figure 17 and the equation for current in a capacitor, i = C × dV/dt, the amount of capacitance needed at
VBUCK is calculated as follows.
At 60 Hz, and a valley-fill circuit of two stages, the hold-up time (tX) required at VBUCK is calculated as follows.
The total angle of an AC half cycle is 180° and the total time of a half AC line cycle is 8.33 ms. When the angle
of the AC waveform is at 30° and 150°, the voltage of the AC line is exactly ½ of its peak. With a two-stage
valley-fill circuit, this is the point where the LED string switches from power being derived from AC line to power
being derived from the hold up capacitors (C7 and C9). 60° out of 180° of the cycle or 1/3 of the cycle the power
is derived from the hold up capacitors (1/3 × 8.33 ms = 2.78 ms). This is equal to the hold up time (dt) from the
previous equation, and dv is the amount of voltage the circuit is allowed to droop. From Determining Maximum
Number of Series Connected LEDs Allowed, we know the minimum VBUCK voltage is about 45 V for a
90-VAC to 135-VAC line. At 90-VAC low-line operating condition input, ½ of the peak voltage is 64 V. Thus, with
some margin, the voltage at VBUCK can not droop more than about 15 V (dv). (i) is equal to (POUT/VBUCK), where
POUT is equal to (VLED × ILED). Total capacitance (C7 in parallel with C9) can now be calculated. See Typical
Application for further calculations of the valley-fill capacitors.
8.1.8 Determining Maximum Number of Series Connected LEDs Allowed
The LM3444 is an off-line buck topology LED driver. A buck converter topology requires that the input voltage
(VBUCK) of the output circuit must be greater than the voltage of the LED stack (VLED) for proper regulation. One
must determine what the minimum voltage observed by the buck converter is before the maximum number of
LEDs allowed can be determined. The following two variables must be determined to accomplish this:
1. AC line operating voltage. This is usually 90 VAC to 135 VAC for North America. Although the LM3444 can
operate at much lower and higher input voltages, a range is needed to illustrate the design process.
2. The number of stages implemented in the valley-fill circuit (1, 2, or 3).
In this example, the most common valley-fill circuit is used (two stages).
Figure 18. AC Line
Figure 18 shows the AC waveform. One can easily see that the peak voltage (VPEAK) is always given by
Equation 27.
(27)
The voltage at VBUCK with a valley-fill stage of two looks similar to the waveforms in Figure 17.
The purpose of the valley-fill circuit is to allow the buck converter to pull power directly off of the AC line when
the line voltage is greater than its peak voltage divided by two (two-stage valley-fill circuit). During this time, the
capacitors within the valley fill circuit (C7 and C8) are charged up to the peak of the AC line voltage. Once the
line drops below its peak divided by two, the two capacitors are placed in parallel and deliver power to the buck
converter. One can now see that if the peak of the AC line voltage is lowered due to variations in the line voltage,
the DC offset (VDC) lowers. VDC is the lowest value that voltage VBUCK encounters.
Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM3444
VLED(MIN)
1 -
ID = VBUCK(MAX) x ILED(AVE)
tVAC-RMS(MAX) 2
VD
VDS(MAX) = VAC-RMS(MAX) 2
VBUCK(MIN) = 2
90 2
x SIN(135o)= 45V
VBUCK(MIN) = 2
VAC-RMS(MIN)
#stagesx SIN(T)
LM3444
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
www.ti.com
Application Information (continued)
(28)
Example:
Line voltage = 90 VAC to 135 VAC
Valley-fill = two stage
(29)
Depending on what type and value of capacitors are used, some derating should be used for voltage droop when
the capacitors are delivering power to the buck converter. With this derating, the lowest voltage the buck
converter sees is about 42.5 V in this example.
To determine how many LEDs can be driven, take the minimum voltage the buck converter sees (42.5 V) and
divide it by the worst-case forward voltage drop of a single LED.
Example: 42.5 V / 3.7 V = 11.5 LEDs (11 LEDs with margin)
8.1.9 Output Capacitor
A capacitor placed in parallel with the LED or array of LEDs can be used to reduce the LED current ripple while
keeping the same average current through both the inductor and the LED array. With a buck topology, the output
inductance (L2) can now be lowered, making the magnetics smaller and less expensive. With a well designed
converter, you can assume that all of the ripple is seen by the capacitor, and not the LEDs. One must ensure
that the capacitor you choose can handle the RMS current of the inductor. See the manufacturer data sheets to
ensure compliance. Usually an X5R or X7R capacitor from 1 µF and 10 µF of the proper voltage rating is
sufficient.
8.1.10 Switching MOSFET
The main switching MOSFET should be chosen with efficiency and robustness in mind. As shown in
Equation 30, the maximum voltage across the switching MOSFET equals:
(30)
The average current rating should be greater than what is given in Equation 31.
IDS-MAX = ILED(-AVE)(DMAX) (31)
8.1.11 Recirculating Diode
The LM3444 buck converter requires a recirculating diode D10 (see Figure 8) to carry the inductor current during
the MOSFET Q2 off-time. The most efficient choice for D10 is a diode with a low forward drop and near-zero
reverse recovery time that can withstand a reverse voltage of the maximum voltage seen at VBUCK. For a
common 110 VAC ± 20% line, the reverse voltage could be as high as 190 V, as shown in Equation 32.
(32)
As shown in Equation 33, the current rating must be at least:
ID= (1 - DMIN) × ILED(AVE) (33)
Or as shown in Equation 34:
(34)
8.2 Typical Application
The following design example illustrates the process of calculating external component values.
20 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LM3444
L2
R3
C11
Q2
Q3
D3
ICOLL
V+
BR1
+
+
1
2
3
4
5 6
7
8
9
10
VLED R4
GND
VCC
FLTR2
NC
NC
ISNS
GATE
NC
COFF
NC
LM3444
VLED-
D10
C7
C9
D4
D8
V+
C1
C2
F1
D1
D2
D9
R2
Q1
C5
R8
R6
R7
C12
U1
C4
C10
RT1
R10
VAC
J1
VBUCK
L1
C15
L3
L4
TP3
D12
TP14
TP15
TP16
TP5
LED-
L5
TP4
LED+
TP7-9
LM3444
www.ti.com
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
Typical Application (continued)
Figure 19. LM3444 Design Example 1 Input = 90 VAC to 135 VAC
VLED = 7 × HB LED String Application at 400 mA
Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM3444
C11 = tOFF
1.276
VLED
R4 = 175 pF
VLED
R4 = = 360 k:
ICOLL
25.2V
135 2u 3.23 Ps = 638 ns
0.8
1u
tON (MIN) = 25.2V
135 2
1 0.8
1u
25.2V
115
(250 kHz) 2= 3.23 Ps
1 0.8
1u
tOFF =
VBUCK(MAX) = 135 2= 190V
VBUCK(MIN) = 2
90 2
x SIN(135o)= 45V
LM3444
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
www.ti.com
Typical Application (continued)
8.2.1 Design Requirements
Known:
1. Input voltage range (90 VAC to 135 VAC)
2. Number of LEDs in series = 7
3. Forward voltage drop of a single LED = 3.6 V
4. LED stack voltage = (7 × 3.6 V) = 25.2 V
Choose:
1. Nominal switching frequency, fSW-TARGET = 350 kHz
2. ILED(AVE) = 400 mA
3. Δi (usually 15% to 30% of ILED(AVE)) = (0.30 × 400 mA) = 120 mA
4. Valley-fill stages (1, 2, or 3) = 2
5. Assumed minimum efficiency = 80%
8.2.2 Detailed Design Procedure
Calculate:
1. Calculate minimum voltage VBUCK, as shown in Equation 35, which yields:
(35)
2. Calculate maximum voltage VBUCK, as shown in Equation 36, which yields:
(36)
3. Calculate tOFF at VBUCK nominal line voltage, as given by Equation 37.
(37)
4. Calculate tON(MIN) at high line to ensure that tON(MIN) > 200 ns, as given by Equation 38.
(38)
5. Calculate C11 and R4 in steps 6 through 9.
6. Choose current through R4 (from 50 µA to 100 µA): 70 µA as given by Equation 39.
(39)
7. Use a standard value of 365 kΩ.
8. Calculate C11 as given by Equation 40.
(40)
9. Use standard value of 120 pF.
10. Calculate ripple current: 400 mA × 0.30 = 120 mA
11. Calculate inductor value at tOFF = 3 µs as given by Equation 41.
22 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LM3444
LINE VOLTAGE (VAC)
EFFICIENCY (%)
95.0
90.0
85.0
80.0
75.0
80 90 100 110 120 130 140
14 Series connected LEDs
10 Series connected LEDs
dv
i = C dt
25.2V
115
(350 kHz x 0.1A)
L2 =2= 580 PH
25.2V 1 0.8
1u
LM3444
www.ti.com
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
Typical Application (continued)
(41)
12. Choose C10: 1 µF, 200 V
13. Calculate valley-fill capacitor values:
VAC low line = 90 VAC, VBUCK minimum equals 60 V. Set droop for 20-V maximum at full load and low line as
shown in Equation 42.
where
• i equals POUT/VBUCK (270 mA)
• dV equals 20 V
• dt equals 2.77 ms
• CTOTAL equals 37 µF (42)
Therefore, C7 = C9 = 22 µF
8.2.3 Application Curve
Figure 20. Efficiency vs Input Voltage
Table 1. Bill of Materials
MANUFACTURER PART
QTY DESIGNATOR DESCRIPTION MANUFACTURER NUMBER
1 U1 IC, CTRLR, DRVR-LED, VSSOP TI LM3444MM
1 BR1 Bridge Rectifiier, SMT, 400 V, 800 mA DiodesInc HD04-T
1 L1 Common mode filter DIP4NS, 900 mA, 700 µH Panasonic ELF-11090E
1 L2 Inductor, SHLD, SMT, 1 A, 470 µH Coilcraft MSS1260-474-KLB
2 L3, L4 Diff mode inductor, 500 mA 1 mH Coilcraft MSS1260-105KL-KLB
1 L5 Bead Inductor, 160 Ω, 6 A Steward HI1206T161R-10
3 C1, C2, C15 Cap, Film, X2Y2, 12.5 MM, 250 VAC, 20%, 10 nF Panasonic ECQ-U2A103ML
1 C4 Cap, X7R, 0603, 16 V, 10%, 100 nF Murata GRM188R71C104KA01D
2 C5, C6 Cap, X5R, 1210, 25 V, 10%, 22 µF Murata GRM32ER61E226KE15L
2 C7, C9 Cap, AL, 200 V, 105C, 20%, 33 µF UCC EKXG201ELL330MK20S
1 C10 Cap, Film, 250 V, 5%, 10 nF Epcos B32521C3103J
1 C12 Cap, X7R, 1206, 50 V, 10%, 1 µF Kemet C1206F105K5RACTU
Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LM3444
LM3444
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
www.ti.com
Typical Application (continued)
Table 1. Bill of Materials (continued)
MANUFACTURER PART
QTY DESIGNATOR DESCRIPTION MANUFACTURER NUMBER
1 C11 Cap, C0G, 0603, 100 V, 5%, 120 pF Murata GRM1885C2A121JA01D
1 D1 Diode, ZNR, SOT23, 15 V, 5% OnSemi BZX84C15LT1G
2 D2, D13 Diode, SCH, SOD123, 40 V, 120 mA NXP BAS40H
4 D3, D4, D8, D9 Diode, FR, SOD123, 200 V, 1 A Rohm RF071M2S
1 D10 Diode, FR, SMB, 400 V, 1 A OnSemi MURS140T3G
1 D12 TVS, VBR = 144 V Fairchild SMBJ130CA
1 R2 Resistor, 1206, 1%, 100 kΩPanasonic ERJ-8ENF1003V
1 R3 Resistor, 1210, 5%, 1.8ΩPanasonic ERJ-14RQJ1R8U
1 R4 Resistor, 0603, 1%, 576 kΩPanasonic ERJ-3EKF5763V
2 R6, R7 Resistor, 0805, 1%, 1 MΩRohm MCR10EZHF1004
2 R8, R10 Resistor, 1206, 0 ΩYageo RC1206JR-070RL
1 RT1 Thermistor, 120 V, 1.1 A, 50 Ωat 25°C Thermometrics CL-140
2 Q1, Q2 XSTR, NFET, DPAK, 300 V, 4 A Fairchild FQD7N30TF
1 Q3 XSTR, PNP, SOT23, 300 V, 500 mA Fairchild MMBTA92
1 J1 Terminal Block 2 pos Phoenix Contact 1715721
1 F1 Fuse, 125 V, 1.25 A bel SSQ 1.25
24 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LM3444
NC
NC
NC
COFF
FLTR2
NC
VCC
GATE
ISNS
GND
= VIA
GND
RECTIFIED AC INPUT LED+
LED-
LM3444
www.ti.com
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
9 Power Supply Recommendations
Use any AC power supply capable of the maximum application requirements for voltage and total power.
10 Layout
10.1 Layout Guidelines
Keep the low power components for FILTER and COFF close to the LM3444 with short traces. The ISNS trace
should also be as short and direct as possible. Keep the high current switching paths generated by R3, Q2, L2,
and D10 as short as possible to minimize generated switching noise and improve EMI.
10.2 Layout Example
Figure 21. Layout Recommendation
Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LM3444
LM3444
SNVS682D –NOVEMBER 2010–REVISED DECEMBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LM3444
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM3444MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L3444
MA
LM3444MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L3444
MA
LM3444MM/NOPB ACTIVE VSSOP DGS 10 1000 Green (RoHS
& no Sb/Br) NIPDAUAG | SN Level-1-260C-UNLIM -40 to 125 SZTB
LM3444MMX/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS
& no Sb/Br) NIPDAUAG | SN Level-1-260C-UNLIM -40 to 125 SZTB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM3444MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM3444MM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM3444MMX/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM3444MMX/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Jul-2020
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM3444MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM3444MM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0
LM3444MMX/NOPB VSSOP DGS 10 3500 364.0 364.0 27.0
LM3444MMX/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Jul-2020
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
5.05
4.75
1.1 MAX
8X 0.5
10X 0.27
0.17
2X
2
0.15
0.05
TYP
0.23
0.13
0 - 8
0.25
GAGE PLANE
0.7
0.4
A
NOTE 3
3.1
2.9
B
NOTE 4
3.1
2.9
4221984/A 05/2015
VSSOP - 1.1 mm max heightDGS0010A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
110
0.1 C A B
6
5
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 3.200
www.ti.com
EXAMPLE BOARD LAYOUT
(4.4)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
10X (1.45)
10X (0.3)
8X (0.5)
(R )
TYP
0.05
4221984/A 05/2015
VSSOP - 1.1 mm max heightDGS0010A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:10X
1
56
10
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(4.4)
8X (0.5)
10X (0.3)
10X (1.45)
(R ) TYP0.05
4221984/A 05/2015
VSSOP - 1.1 mm max heightDGS0010A
SMALL OUTLINE PACKAGE
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
56
10
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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