TP3054. TP3057
Enhanced Serial Interface CODEC/Filter COMBO Family
Literature Number: SNAS569
TL/H/5510
TP3054, TP3057 ‘‘Enhanced’’ Serial Interface CODEC/Filter COMBO Family
August 1994
TP3054, TP3057
‘‘Enhanced’’ Serial Interface
CODEC/Filter COMBOÉFamily
General Description
The TP3054, TP3057 family consists of m-law and A-law
monolithic PCM CODEC/filters utilizing the A/D and D/A
conversion architecture shown in
Figure 1
, and a serial PCM
interface. The devices are fabricated using National’s ad-
vanced double-poly CMOS process (microCMOS).
The encode portion of each device consists of an input gain
adjust amplifier, an active RC pre-filter which eliminates very
high frequency noise prior to entering a switched-capacitor
band-pass filter that rejects signals below 200 Hz and above
3400 Hz. Also included are auto-zero circuitry and a com-
panding coder which samples the filtered signal and en-
codes it in the companded m-law or A-law PCM format. The
decode portion of each device consists of an expanding
decoder, which reconstructs the analog signal from the
companded m-law or A-law code, a low-pass filter which
corrects for the sin x/x response of the decoder output and
rejects signals above 3400 Hz followed by a single-ended
power amplifier capable of driving low impedance loads.
The devices require two 1.536 MHz, 1.544 MHz or 2.048
MHz transmit and receive master clocks, which may be
asynchronous; transmit and receive bit clocks, which may
vary from 64 kHz to 2.048 MHz; and transmit and receive
frame sync pulses. The timing of the frame sync pulses and
PCM data is compatible with both industry standard formats.
Features
YComplete CODEC and filtering system (COMBO)
including:
Ð Transmit high-pass and low-pass filtering
Ð Receive low-pass filter with sin x/x correction
Ð Active RC noise filters
Ðm-law or A-law compatible COder and DECoder
Ð Internal precision voltage reference
Ð Serial I/O interface
Ð Internal auto-zero circuitry
Ym-law, 16-pinÐTP3054
YA-law, 16-pinÐTP3057
YDesigned for D3/D4 and CCITT applications
Yg5V operation
YLow operating powerÐtypically 50 mW
YPower-down standby modeÐtypically 3 mW
YAutomatic power-down
YTTL or CMOS compatible digital interfaces
YMaximizes line interface card circuit density
YDual-In-Line or surface mount packages
YSee also AN-370, ‘‘Techniques for Designing with
CODEC/Filter COMBO Circuits’’
Connection Diagrams
Dual-In-Line Package
TL/H/5510–1
Top View
Order Number TP3054J or TP3057J
See NS Package Number J16A
Order Number TP3054N or TP3057N
See NS Package Number N16A
Order Number TP3054WM or TP3057WM
See NS Package Number M16B
Plastic Chip Carriers
TL/H/5510–10
Top View
Order Number TP3057V
See NS Package Number V20A
COMBOÉand TRI-STATEÉare registered trademarks of National Semiconductor Corporation.
C1995 National Semiconductor Corporation RRD-B30M125/Printed in U. S. A.
Block Diagram
FIGURE 1 TL/H/5510–2
Pin Description
Symbol Function
VBB Negative power supply pin.
VBB eb
5V g5%.
GNDA Analog ground. All signals are referenced
to this pin.
VFRO Analog output of the receive power ampli-
fier.
VCC Positive power supply pin.
VCC ea
5V g5%.
FSRReceive frame sync pulse which enables
BCLKRto shift PCM data into DR.FS
Ris
an 8 kHz pulse train. See
Figures 2
and
3
for timing details.
DRReceive data input. PCM data is shifted
into DRfollowing the FSRleading edge.
BCLKR/CLKSEL The bit clock which shifts data into DRaf-
ter the FSRleading edge. May vary from
64 kHz to 2.048 MHz. Alternatively, may
be a logic input which selects either
1.536 MHz/1.544 MHz or 2.048 MHz for
master clock in synchronous mode and
BCLKXis used for both transmit and re-
ceive directions (see Table I).
MCLKR/PDN Receive master clock. Must be
1.536 MHz, 1.544 MHz or 2.048 MHz.
May be asynchronous with MCLKX, but
Symbol Function
should be synchronous with MCLKXfor best per-
formance. When MCLKRis connected continu-
ously low, MCLKXis selected for all internal tim-
ing. When MCLKRis connected continuously
high, the device is powered down.
MCLKXTransmit master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be asynchronous
with MCLKR. Best performance is realized from
synchronous operation.
FSXTransmit frame sync pulse input which enables
BCLKXto shift out the PCM data on DX.FS
Xis
an 8 kHz pulse train, see
Figures 2
and
3
for
timing details.
BCLKXThe bit clock which shifts out the PCM data on
DX. May vary from 64 kHz to 2.048 MHz, but
must be synchronous with MCLKX.
DXThe TRI-STATEÉPCM data output which is en-
abled by FSX.
TSXOpen drain output which pulses low during the
encoder time slot.
GSXAnalog output of the transmit input amplifier.
Used to externally set gain.
VFXIbInverting input of the transmit input amplifier.
VFXIaNon-inverting input of the transmit input amplifi-
er.
2
Functional Description
POWER-UP
When power is first applied, power-on reset circuitry initializ-
es the COMBO and places it into a power-down state. All
non-essential circuits are deactivated and the DXand VFRO
outputs are put in high impedance states. To power-up the
device, a logical low level or clock must be applied to the
MCLKR/PDN pin
and
FSXand/or FSRpulses must be pres-
ent. Thus, 2 power-down control modes are available. The
first is to pull the MCLKR/PDN pin high; the alternative is to
hold both FSXand FSRinputs continuously lowÐthe device
will power-down approximately 1 ms after the last FSXor
FSRpulse. Power-up will occur on the first FSXor FSR
pulse. The TRI-STATE PCM data output, DX, will remain in
the high impedance state until the second FSXpulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive di-
rections. In this mode, a clock must be applied to MCLKX
and the MCLKR/PDN pin can be used as a power-down
control. A low level on MCLKR/PDN powers up the device
and a high level powers down the device. In either case,
MCLKXwill be selected as the master clock for both the
transmit and receive circuits. A bit clock must also be ap-
plied to BCLKXand the BCLKR/CLKSEL can be used to
select the proper internal divider for a master clock of 1.536
MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation,
the device automatically compensates for the 193rd clock
pulse each frame.
With a fixed level on the BCLKR/CLKSEL pin, BCLKXwill be
selected as the bit clock for both the transmit and receive
directions. Table 1 indicates the frequencies of operation
which can be selected, depending on the state of BCLKR/
CLKSEL. In this synchronous mode, the bit clock, BCLKX,
may be from 64 kHz to 2.048 MHz, but must be synchro-
nous with MCLKX.
Each FSXpulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled DXoutput on the positive edge of BCLKX. After 8
bit clock periods, the TRI-STATE DXoutput is returned to a
high impedance state. With an FSRpulse, PCM data is
latched via the DRinput on the negative edge of BCLKX(or
BCLKRif running). FSXand FSRmust be synchronous with
MCLKX/R.
TABLE I. Selection of Master Clock Frequencies
BCLKR/CLKSEL
Master Clock
Frequency Selected
TP3057 TP3054
Clocked 2.048 MHz 1.536 MHz or
1.544 MHz
0 1.536 MHz or 2.048 MHz
1.544 MHz
1 2.048 MHz 1.536 MHz or
1.544 MHz
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive
clocks may be applied. MCLKXand MCLKRmust be
2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the
TP3054, and need not be synchronous. For best transmis-
sion performance, however, MCLKRshould be synchronous
with MCLKX, which is easily achieved by applying only static
logic levels to the MCLKR/PDN pin. This will automatically
connect MCLKXto all internal MCLKRfunctions (see Pin
Description). For 1.544 MHz operation, the device automati-
cally compensates for the 193rd clock pulse each frame.
FSXstarts each encoding cycle and must be synchronous
with MCLKXand BCLKX.FS
Rstarts each decoding cycle
and must be synchronous with BCLKR. BCLKRmust be a
clock, the logic levels shown in Table 1 are not valid in
asynchronous mode. BCLKXand BCLKRmay operate from
64 kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse or a
long frame sync pulse. Upon power initialization, the device
assumes a short frame mode. In this mode, both frame sync
pulses, FSXand FSR, must be one bit clock period long,
with timing relationships specified in
Figure 2
. With FSXhigh
during a falling edge of BCLKX, the next rising edge of
BCLKXenables the DXTRI-STATE output buffer, which will
output the sign bit. The following seven rising edges clock
out the remaining seven bits, and the next falling edge dis-
ables the DXoutput. With FSRhigh during a falling edge of
BCLKR(BCLKXin synchronous mode), the next falling edge
of BCLKRlatches in the sign bit. The following seven falling
edges latch in the seven remaining bits. All four devices
may utilize the short frame sync pulse in synchronous or
asynchronous operating mode.
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync pulses,
FSXand FSR, must be three or more bit clock periods long,
with timing relationships specified in
Figure 3
. Based on the
transmit frame sync, FSX, the COMBO will sense whether
short or long frame sync pulses are being used. For 64 kHz
operation, the frame sync pulse must be kept low for a mini-
mum of 160 ns. The DXTRI-STATE output buffer is enabled
with the rising edge of FSXor the rising edge of BCLKX,
whichever comes later, and the first bit clocked out is the
sign bit. The following seven BCLKXrising edges clock out
the remaining seven bits. The DXoutput is disabled by the
falling BCLKXedge following the eighth rising edge, or by
FSXgoing low, whichever comes later. A rising edge on the
receive frame sync pulse, FSR, will cause the PCM data at
DRto be latched in on the next eight falling edges of BCLKR
(BCLKXin synchronous mode). All four devices may utilize
the long frame sync pulse in synchronous or asynchronous
mode.
In applications where the LSB bit is used for signalling with
FSRtwo bit clock periods long, the decoder will interpret the
lost LSB as ‘‘(/2’’ to minimize noise and distortion.
3
Functional Description (Continued)
TRANSMIT SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
see
Figure 4
. The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be real-
ized. The op amp drives a unity-gain filter consisting of RC
active pre-filter, followed by an eighth order switched-ca-
pacitor bandpass filter clocked at 256 kHz. The output of
this filter directly drives the encoder sample-and-hold circuit.
The A/D is of companding type according to m-law
(TP3054) or A-law (TP3057) coding conventions. A preci-
sion voltage reference is trimmed in manufacturing to pro-
vide an input overload (tMAX) of nominally 2.5V peak (see
table of Transmission Characteristics). The FSXframe sync
pulse controls the sampling of the filter output, and then the
successive-approximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out through DX
at the next FSXpulse. The total encoding delay will be ap-
proximately 165 ms (due to the transmit filter) plus 125 ms
(due to encoding delay), which totals 290 ms. Any offset
voltage due to the filters or comparator is cancelled by sign
bit integration.
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz. The decoder is A-law (TP3057) or
m-law (TP3054) and the 5th order low pass filter corrects for
the sin x/x attenuation due to the 8 kHz sample/hold. The
filter is then followed by a 2nd order RC active post-filter/
power amplifer capable of driving a 600Xload to a level of
7.2 dBm. The receive section is unity-gain. Upon the occur-
rence of FSR, the data at the DRinput is clocked in on the
falling edge of the next eight BCLKR(BCLKX) periods. At
the end of the decoder time slot, the decoding cycle begins,
and 10 ms later the decoder DAC output is updated. The
total decoder delay is E10 ms (decoder update) plus
110 ms (filter delay) plus 62.5 ms((/2 frame), which gives
approximately 180 ms.
4
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
VCC to GNDA 7V
VBB to GNDA b7V
Voltage at any Analog Input
or Output VCCa0.3V to VBBb0.3V
Voltage at any Digital Input or
Output VCCa0.3V to GNDAb0.3V
Operating Temperature Range b25§Ctoa125§C
Storage Temperature Range b65§Ctoa
150§C
Lead Temperature (Soldering, 10 seconds) 300§C
ESD (Human Body Model) 2000V
Latch-Up Immunity e100 mA on any Pin
Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC
e5.0V g5%, VBB eb
5.0V g5%; TAe0§Cto70
§
C by correlation with 100% electrical testing at TAe25§C. All other limits
are assured by correlation with other production tests and/or product design and characterization. All signals referenced to
GNDA. Typicals specified at VCC e5.0V, VBB eb
5.0V, TAe25§C.
Symbol Parameter Conditions Min Typ Max Units
DIGITAL INTERFACE
VIL Input Low Voltage 0.6 V
VIH Input High Voltage 2.2 V
VOL Output Low Voltage DX,I
L
e
3.2 mA 0.4 V
SIGR,I
L
e
1.0 mA 0.4 V
TSX,I
L
e
3.2 mA, Open Drain 0.4 V
VOH Output High Voltage DX,I
H
eb3.2 mA 2.4 V
SIGR,I
H
eb1.0 mA 2.4 V
IIL Input Low Current GNDAsVINsVIL, All Digital Inputs b10 10 mA
IIH Input High Current VIHsVINsVCC b10 10 mA
IOZ Output Current in High Impedance DX, GNDAsVOsVCC b10 10 mA
State (TRI-STATE)
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)
IIXA Input Leakage Current b2.5VsVsa2.5V, VFXIaor VFXIbb200 200 nA
RIXA Input Resistance b2.5VsVsa2.5V, VFXIaor VFXIb10 MX
ROXA Output Resistance Closed Loop, Unity Gain 1 3 X
RLXA Load Resistance GSX10 kX
CLXA Load Capacitance GSX50 pF
VOXA Output Dynamic Range GSX,R
L
t
10 kXb2.8 2.8 V
AVXA Voltage Gain VFXIato GSX5000 V/V
FUXA Unity Gain Bandwidth 1 2 MHz
VOSXA Offset Voltage b20 20 mV
VCMXA Common-Mode Voltage CMRRXA l60 dB b2.5 2.5 V
CMRRXA Common-Mode Rejection Ratio DC Test 60 dB
PSRRXA Power Supply Rejection Ratio DC Test 60 dB
ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)
RORF Output Resistance Pin VFRO13X
R
L
RF Load Resistance VFROeg2.5V 600 X
CLRF Load Capacitance 500 pF
VOSRO Output DC Offset Voltage b200 200 mV
POWER DISSIPATION (ALL DEVICES)
ICC0 Power-Down Current No Load (Note) 0.5 1.5 mA
IBB0 Power-Down Current No Load (Note) 0.05 0.3 mA
ICC1 Power-Up Active Current No Load 5.0 9.0 mA
IBB1 Power-Up Active Current No Load 5.0 9.0 mA
Note: ICC0 and IBB0 are measured after first achieving a power-up state.
5
Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e
5.0V g5%, VBB eb
5.0V g5%; TAe0§Cto70
§
C by correlation with 100% electrical testing at TAe25§C. All other limits are
assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA.
Typicals specified at VCC e5.0V, VBB eb
5.0V, TAe25§C. All timing parameters are measured at VOH e2.0V and VOL e
0.7V. See Definitions and Timing Conventions section for test methods information.
Symbol Parameter Conditions Min Typ Max Units
1/tPM Frequency of Master Clocks Depends on the Device Used and the 1.536 MHz
BCLKR/CLKSEL Pin. 1.544 MHz
MCLKXand MCLKR2.048 MHz
tRM Rise Time of Master Clock MCLKXand MCLKR50 ns
tFM Fall Time of Master Clock MCLKXand MCLKR50 ns
tPB Period of Bit Clock 485 488 15725 ns
tRB Rise Time of Bit Clock BCLKXand BCLKR50 ns
tFB Fall Time of Bit Clock BCLKXand BCLKR50 ns
tWMH Width of Master Clock High MCLKXand MCLKR160 ns
tWML Width of Master Clock Low MCLKXand MCLKR160 ns
tSBFM Set-Up Time from BCLKXHigh First Bit Clock after the Leading 100 ns
to MCLKXFalling Edge Edge of FSX
tSFFM Set-Up Time from FSXHigh Long Frame Only 100 ns
to MCLKXFalling Edge
tWBH Width of Bit Clock High VIHe2.2V 160 ns
tWBL Width of Bit Clock Low VILe0.6V 160 ns
tHBFL Holding Time from Bit Clock Long Frame Only 0ns
Low to Frame Sync
tHBFS Holding Time from Bit Clock Short Frame Only 0ns
High to Frame Sync
tSFB Set-Up Time from Frame Sync Long Frame Only 80 ns
to Bit Clock Low
tDBD Delay Time from BCLKXHigh Loade150 pF plus 2 LSTTL Loads 0 140 ns
to Data Valid
tDBTS Delay Time to TSXLow Loade150 pF plus 2 LSTTL Loads 140 ns
tDZC Delay Time from BCLKXLow to CLe0 pF to 150 pF 50 165 ns
Data Output Disabled
tDZF Delay Time to Valid Data from CLe0 pF to 150 pF 20 165 ns
FSXor BCLKX, Whichever
Comes Later
tSDB Set-Up Time from DRValid to 50 ns
BCLKR/X Low
tHBD Hold Time from BCLKR/X Low to 50 ns
DRInvalid
tSF Set-Up Time from FSX/R to Short Frame Sync Pulse (1 Bit Clock 50 ns
BCLKX/RLow Period Long)
tHF Hold Time from BCLKX/R Low Short Frame Sync Pulse (1 Bit Clock 100 ns
to FSX/R Low Period Long)
tHBFl Hold Time from 3rd Period of Long Frame Sync Pulse (from 3 to 8 Bit 100 ns
Bit Clock Low to Frame Sync Clock Periods Long)
(FSXor FSR)
tWFL Minimum Width of the Frame 64k Bit/s Operating Mode 160 ns
Sync Pulse (Low Level)
6
Timing Diagrams
TL/H/5510–3
FIGURE 2. Short Frame Sync Timing
7
Timing Diagrams (Continued)
TL/H/5510–4
FIGURE 3. Long Frame Sync Timing
8
Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for
VCC e5.0V g5%, VBB eb
5.0V g5%; TAe0§Cto70
§
C by correlation with 100% electrical testing at TAe25§C. All other
limits are assured by correlation with other production tests and/or product design and characterization. GNDA e0V, f e
1.02 kHz, VIN e0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at VCC e5.0V, VBB
eb
5.0V, TAe25§C.
Symbol Parameter Conditions Min Typ Max Units
AMPLITUDE RESPONSE
Absolute Levels Nominal 0 dBm0 Level is 4 dBm
(Definition of Nominal Gain) (600X)
0 dBm0 1.2276 Vrms
tMAX Virtual Decision Valve Defined Max Overload Level
Per CCITT Rec. G711 TP3054 (3.17 dBm0) 2.501 VPK
TP3057 (3.14 dBm0) 2.492 VPK
GXA Transmit Gain, Absolute TAe25§C, VCCe5V, VBBeb5V
Input at GSXe0 dBm0 at 1020 Hz
TP3054/57 b0.15 0.15 dB
GXR Transmit Gain, Relative to GXA fe16 Hz b40 dB
fe50 Hz b30 dB
fe60 Hz b26 dB
fe200 Hz b1.8 b0.1 dB
fe300 Hzb3000 Hz b0.15 0.15 dB
fe3300 Hz b0.35 0.05 dB
fe3400 Hz b0.7 0 dB
fe4000 Hz b14 dB
fe4600 Hz and Up, Measure b32 dB
Response from 0 Hz to 4000 Hz
GXAT Absolute Transmit Gain Variation Relative to GXA b0.1 0.1 dB
with Temperature
GXAV Absolute Transmit Gain Variation Relative to GXA b0.05 0.05 dB
with Supply Voltage
GXRL Transmit Gain Variations with Sinusoidal Test Method
Level Reference Leveleb10 dBm0
VFXIaeb40 dBm0 to a3 dBm0 b0.2 0.2 dB
VFXIaeb50 dBm0 to b40 dBm0 b0.4 0.4 dB
VFXIaeb55 dBm0 to b50 dBm0 b1.2 1.2 dB
GRA Receive Gain, Absolute TAe25§C, VCCe5V, VBBeb5V
InputeDigital Code Sequence for
0 dBm0 Signal at 1020 Hz
TP3054/57 b0.15 0.15 dB
GRR Receive Gain, Relative to GRA fe0 Hz to 3000 Hz b0.15 0.15 dB
fe3300 Hz b0.35 0.05 dB
fe3400 Hz b0.7 0 dB
fe4000 Hz b14 dB
GRAT Absolute Receive Gain Variation Relative to GRA b0.1 0.1 dB
with Temperature
GRAV Absolute Receive Gain Variation Relative to GRA b0.05 0.05 dB
with Supply Voltage
GRRL Receive Gain Variations with Sinusoidal Test Method; Reference
Level Input PCM Code Corresponds to an
Ideally Encoded PCM Level
eb40 dBm0 to a3 dBm0 b0.2 0.2 dB
eb50 dBm0 to b40 dBm0 b0.4 0.4 dB
eb55 dBm0 to b50 dBm0 b1.2 1.2 dB
VRO Receive Output Drive Level RLe600Xb2.5 2.5 V
9
Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are
guaranteed for VCC e5.0V g5%, VBB eb
5.0V g5%; TAe0§Cto70
§
C by correlation with 100% electrical testing at TAe
25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA
e0V, f e1.02 kHz, VIN e0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at VCC e
5.0V, VBB eb
5.0V, TAe25§C.
Symbol Parameter Conditions Min Typ Max Units
ENVELOPE DELAY DISTORTION WITH FREQUENCY
DXA Transmit Delay, Absolute fe1600 Hz 290 315 ms
DXR Transmit Delay, Relative to DXA fe500 Hz– 600 Hz 195 220 ms
fe600 Hz– 800 Hz 120 145 ms
fe800 Hz– 1000 Hz 50 75 ms
fe1000 Hz– 1600 Hz 20 40 ms
fe1600 Hz– 2600 Hz 55 75 ms
fe2600 Hz– 2800 Hz 80 105 ms
fe2800 Hz– 3000 Hz 130 155 ms
DRA Receive Delay, Absolute fe1600 Hz 180 200 ms
DRR Receive Delay, Relative to DRA fe500 Hz– 1000 Hz b40 b25 ms
fe1000 Hz– 1600 Hz b30 b20 ms
fe1600 Hz– 2600 Hz 70 90 ms
fe2600 Hz– 2800 Hz 100 125 ms
fe2800 Hz– 3000 Hz 145 175 ms
NOISE
NXC Transmit Noise, C Message TP3054 12 15 dBrnC0
Weighted
NXP Transmit Noise, P Message TP3057 b74 b67 dBm0p
Weighted
NRC Receive Noise, C Message PCM Code is Alternating Positive
Weighted and Negative Zero Ð TP3054 8 11 dBrnC0
NRP Receive Noise, P Message PCM Code Equals Positive
Weighted Zero Ð TP3057 b82 b79 dBm0p
NRS Noise, Single Frequency fe0 kHz to 100 kHz, Loop Around b53 dBm0
Measurement, VFXIae0 Vrms
PPSRXPositive Power Supply Rejection, VFXIaeb
50 dBm0
Transmit VCCe5.0 VDCa100 mVrms
fe0 kHz– 50 kHz (Note 2) 40 dBC
NPSRXNegative Power Supply Rejection, VFXIaeb
50 dBm0
Transmit VBBeb5.0 VDCa100 mVrms
fe0 kHz– 50 kHz (Note 2) 40 dBC
PPSRRPositive Power Supply Rejection, PCM Code Equals Positive Zero
Receive VCCe5.0 VDCa100 mVrms
Measure VFR0
fe0 Hz– 4000 Hz 40 dBC
fe4 kHz– 25 kHz 40 dB
fe25 kHz– 50 kHz 36 dB
NPSRRNegative Power Supply Rejection, PCM Code Equals Positive Zero
Receive VBBeb5.0 VDCa100 mVrms
Measure VFR0
fe0 Hz– 4000 Hz 40 dBC
fe4 kHz– 25 kHz 40 dB
fe25 kHz– 50 kHz 36 dB
10
Transmission Characteristics (Continued) Unless otherwise noted, limits printed in BOLD characters are
guaranteed for VCC e5.0V g5%, VBB eb
5.0V g5%; TAe0§Cto70
§
C by correlation with 100% electrical testing at TAe
25§C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA
e0V, f e1.02 kHz, VIN e0 dBm0, transmit input amplifier connected for unity gain non-inverting. Typicals specified at VCC e
5.0V, VBB eb
5.0V, TAe25§C.
Symbol Parameter Conditions Min Typ Max Units
SOS Spurious Out-of-Band Signals Loop Around Measurement, 0 dBm0, b30 dB
at the Channel Output 300 Hz to 3400 Hz Input PCM Code Applied
at DR.
4600 Hz– 7600 Hz b30 dB
7600 Hz– 8400 Hz b40 dB
8400 Hz– 100,000 Hz b30 dB
DISTORTION
STDXSignal to Total Distortion Sinusoidal Test Method (Note 3)
STDRTransmit or Receive e3.0 dBm0Level 33 dBC
Half-Channel e0 dBm0 to b30 dBm0 36 dBC
XMT
eb40 dBm0 29 dBC
RCV 30 dBC
XMT
eb55 dBm0 14 dBC
RCV 15 dBC
SFDXSingle Frequency Distortion, b46 dB
Transmit
SFDRSingle Frequency Distortion, b46 dB
Receive
IMD Intermodulation Distortion Loop Around Measurement, b41 dB
VFXaeb4 dBm0 to b21 dBm0, Two
Frequencies in the Range
300 Hz– 3400 Hz
CROSSTALK
CTX-R Transmit to Receive Crosstalk, fe300 Hz–3400 Hz
0 dBm0 Transmit Level DReQuiet PCM Code b90 b75 dB
CTR-X Receive to Transmit Crosstalk, fe300 Hz–3400 Hz, VFXIeMultitone b90 b70 dB
0 dBm0 Receive Level (Note 2)
ENCODING FORMAT AT DXOUTPUT
TP3054 TP3057
m-Law A-Law
(Includes Even Bit Inversion)
VIN (at GSX)eaFull-Scale 10000000 10101010
V
IN (at GSX)e0V 11111111 11010101
Ð01111111 01010101
V
IN (at GSX)ebFull-Scale 00000000 00101010
Note 1: Measured by extrapolation from the distortion test result at b50 dBm0.
Note 2: PPSRX, NPSRX, and CTR-X are measured with a b50 dBm0 activation signal applied to VFXIa.
Note 3: Devices are measured using C message weighted filter for m-Law and psophometric weighted filter for A-Law.
11
Applications Information
POWER SUPPLIES
While the pins of the TP305X family are well protected
against electrical misuse, it is recommended that the stan-
dard CMOS practice be followed, ensuring that ground is
connected to the device before any other connections are
made. In applications where the printed circuit board may be
plugged into a ‘‘hot’’ socket with power and clocks already
present, an extra long ground pin in the connector should
be used.
All ground connections to each device should meet at a
common point as close as possible to the GNDA pin. This
minimizes the interaction of ground return currents flowing
through a common bus impedance. 0.1 mF supply decou-
pling capacitors should be connected from this common
ground point to VCC and VBB, as close to the device as
possible.
For best performance, the ground point of each CODEC/
FILTER on a card should be connected to a common card
ground in star formation, rather than via a ground bus.
This common ground point should be decoupled to VCC and
VBB with 10 mF capacitors.
RECEIVE GAIN ADJUSTMENT
For applications where a TP305X family CODEC/filter re-
ceive output must drive a 600Xload, but a peak swing lower
than g2.5V is required, the receive gain can be easily ad-
justed by inserting a matched T-pad or q-pad at the output.
Table II lists the required resistor values for 600Xtermina-
tions. As these are generally non-standard values, the equa-
tions can be used to compute the attenuation of the closest
practical set of resistors. It may be necessary to use un-
equal values for the R1 or R4 arms of the attenuators to
achieve a precise attenuation. Generally it is tolerable to
allow a small deviation of the input impedance from nominal
while still maintaining a good return loss. For example a 30
dB return loss against 600Xis obtained if the output imped-
ance of the attenuator is in the range 282Xto 319X(as-
suming a perfect transformer).
T-Pad Attenuator
R1 eZ1 #N2a1
N2b1Jb20Z1.Z2 #N
N2b1J
R2 e20Z1.Z2 #N
N2b1J
Where: N e0POWER IN
POWER OUT
and
Se0Z1
Z2
Also: Z e0ZSC #ZOC
Where ZSC eimpedance with short circuit termination
and ZOC eimpedance with open circuit termination
q-Pad Attenuator
TL/H/5510–5
R3 e0Z1.Z2
2#N2b1
NJ
R3 eZ1 #N2b1
N2b2NS a1J
Note: See Application Note 370 for further details.
12
Applications Information (Continued)
TABLE II. Attentuator Tables for Z1eZ2e300X
(All Values in X)
dB R1 R2 R3 R4
0.1 1.7 26k 3.5 52k
0.2 3.5 13k 6.9 26k
0.3 5.2 8.7k 10.4 17.4k
0.4 6.9 6.5k 13.8 13k
0.5 8.5 5.2k 17.3 10.5k
0.6 10.4 4.4k 21.3 8.7k
0.7 12.1 3.7k 24.2 7.5k
0.8 13.8 3.3k 27.7 6.5k
0.9 15.5 2.9k 31.1 5.8k
1.0 17.3 2.6l 34.6 5.2k
2 34.4 1.3k 70 2.6k
3 51.3 850 107 1.8k
4 68 650 144 1.3k
5 84 494 183 1.1k
6 100 402 224 900
7 115 380 269 785
8 379 284 317 698
9 143 244 370 630
10 156 211 427 527
11 168 184 490 535
12 180 161 550 500
13 190 142 635 473
14 200 125 720 450
15 210 110 816 430
16 218 98 924 413
18 233 77 1.17k 386
20 246 61 1.5k 366
Typical Synchronous Application
TL/H/5510–6
Note 1: XMIT gaine20clog #R1aR2
R2 Jwhere (R1aR2) l10 KX.
FIGURE 4
13
Connection Diagrams (Continued)
Plastic Chip Carrier
TL/H/5510–7
Top View
Order Number TP3057V
See NS Package Number V20A
14
Physical Dimensions inches (millimeters)
Cavity Dual-In-Line Package (J)
Order Number TP3054J or TP3057J
NS Package Number J16A
Molded Small Outline Package (WM)
Order Number TP3054WM or TP3057WM
NS Package Number M16B
15
TP3054, TP3057 ‘‘Enhanced’’ Serial Interface CODEC/Filter COMBO Family
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number TP3054N or TP3057N
NS Package Number N16A
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