SPC5602PEF0VLL6 - Freescale Semiconductor

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 1

Qorivva MPC5602P Microcontroller

Reference Manual

Devices Supported:

MPC5601P

MPC5602P

MPC5602PRM

Rev. 4

28 Feb 2012

MPC5602P Microcontroller Reference Manual, Rev. 4

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 3

Preface

Overview

The primary objective of this document is to define the functionality of the MPC5602P family of

microcontrollers for use by software and hardware developers. The MPC5602P family is built on

Power Architecture® technology and integrates technologies that are important for today’s electrical

hydraulic power steering (EHPS), electric power steering (EPS), airbag applications, anti-lock braking

systems (ABS), and motor control applications.

As with any technical documentation, it is the reader’s responsibility to be sure he or she is using the most

recent version of the documentation.

To locate any published errata or updates for this document, visit the Freescale Web site at

http://www.freescale.com/.

Audience

This manual is intended for system software and hardware developers and applications programmers who

want to develop products with the MPC5602P device. It is assumed that the reader understands operating

systems, microprocessor system design, basic principles of software and hardware, and basic details of the

Power Architecture.

Chapter organization and device-specific information

This document includes chapters that describe:

• The device as a whole

• The functionality of the individual modules on the device

In the latter, any device-specific information is presented in the section “Information Specific to This

Device” at the beginning of the chapter.

References

In addition to this reference manual, the following documents provide additional information on the

operation of the MPC5602P:

• IEEE-ISTO 5001™ - 2003 and 2010, The Nexus 5001™ Forum Standard for a Global Embedded

Processor Debug Interface

• IEEE 1149.1-2001 standard - IEEE Standard Test Access Port and Boundary-Scan Architecture

• Power Architecture Book E V1.0

(http://www.freescale.com/files/32bit/doc/user_guide/BOOK_EUM.pdf)

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Chapter 1

Introduction

1.1 The MPC5602P microcontroller family ..........................................................................................35

1.2 Target applications ..........................................................................................................................36

1.2.1 Application examples .....................................................................................................36

1.2.1.1 Electric power steering .....................................................................................36

1.2.1.2 Airbag ...............................................................................................................37

1.3 Features ...........................................................................................................................................38

1.4 Critical performance parameters .....................................................................................................41

1.5 Chip-level features ..........................................................................................................................41

1.6 Module features ...............................................................................................................................43

1.6.1 High performance e200z0 core processor ......................................................................43

1.6.2 Crossbar switch (XBAR) ................................................................................................43

1.6.3 Enhanced direct memory access (eDMA) ......................................................................44

1.6.4 Flash memory .................................................................................................................44

1.6.5 Static random access memory (SRAM) .........................................................................45

1.6.6 Interrupt controller (INTC) .............................................................................................46

1.6.7 System status and configuration module (SSCM) ..........................................................46

1.6.8 System clocks and clock generation ...............................................................................47

1.6.9 Frequency-modulated phase-locked loop (FMPLL) ......................................................47

1.6.10 Main oscillator ................................................................................................................47

1.6.11 Internal RC oscillator .....................................................................................................47

1.6.12 Periodic interrupt timer (PIT) .........................................................................................48

1.6.13 System timer module (STM) ..........................................................................................48

1.6.14 Software watchdog timer (SWT) ....................................................................................48

1.6.15 Fault collection unit (FCU) ............................................................................................48

1.6.16 System integration unit – Lite (SIUL) ............................................................................49

1.6.17 Boot and censorship .......................................................................................................49

1.6.17.1 Boot assist module (BAM) ..............................................................................49

1.6.18 Error correction status module (ECSM) .........................................................................50

1.6.19 Peripheral bridge (PBRIDGE) ........................................................................................50

1.6.20 Controller area network (FlexCAN) ...............................................................................50

1.6.21 Safety port (FlexCAN) ...................................................................................................51

1.6.22 Serial communication interface module (LINFlex) .......................................................51

1.6.23 Deserial serial peripheral interface (DSPI) .....................................................................52

1.6.24 Pulse width modulator (FlexPWM) ................................................................................53

1.6.25 eTimer .............................................................................................................................54

1.6.26 Analog-to-digital converter (ADC) module ...................................................................54

1.6.27 Cross triggering unit (CTU) ...........................................................................................55

1.6.28 Nexus Development Interface (NDI) .............................................................................56

1.6.29 Cyclic redundancy check (CRC) ....................................................................................56

1.6.30 IEEE 1149.1 JTAG controller .........................................................................................56

1.6.31 On-chip voltage regulator (VREG) ................................................................................57

1.7 Developer environment ...................................................................................................................57

1.8 Package ............................................................................................................................................57

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Chapter 2

MPC5602P Memory Map

Chapter 3

Signal Description

3.1 100-pin LQFP pinout ......................................................................................................................63

3.2 64-pin LQFP pinout ........................................................................................................................64

3.3 Pin description .................................................................................................................................64

3.3.1 Power supply and reference voltage pins .......................................................................64

3.3.2 System pins .....................................................................................................................66

3.3.3 Pin multiplexing .............................................................................................................66

3.4 CTU / ADC / FlexPWM / eTimer connections ..............................................................................75

Chapter 4

Clock Description

4.1 Clock architecture ...........................................................................................................................79

4.2 Available clock domains .................................................................................................................82

4.2.1 FMPLL input reference clock ........................................................................................82

4.2.2 Clock selectors ................................................................................................................82

4.2.2.1 System clock selector 0 for SYS_CLK ............................................................82

4.2.3 Auxiliary Clock Selector 0 .............................................................................................83

4.2.4 Auxiliary Clock Selector 1 .............................................................................................83

4.2.5 Auxiliary Clock Selector 2 .............................................................................................83

4.2.6 Auxiliary clock dividers .................................................................................................83

4.2.7 External clock divider .....................................................................................................83

4.3 Alternate module clock domains .....................................................................................................84

4.3.1 FlexCAN clock domains ................................................................................................84

4.3.2 SWT clock domains .......................................................................................................84

4.3.3 Cross Triggering Unit (CTU) clock domains .................................................................84

4.3.4 Peripherals behind the IPS bus clock sync bridge ..........................................................84

4.3.4.1 FlexPWM clock domain ..................................................................................84

4.3.4.2 eTimer_0 clock domain ....................................................................................84

4.3.4.3 ADC_0 clock domain .......................................................................................85

4.3.4.4 Safety Port clock domains ................................................................................85

4.4 Clock behavior in STOP and HALT mode ......................................................................................85

4.5 System clock functional safety ........................................................................................................85

4.6 IRC 16 MHz internal RC oscillator (RC_CTL) ..............................................................................86

4.7 XOSC external crystal oscillator .....................................................................................................87

4.7.1 Functional description ....................................................................................................87

4.7.2 Register description ........................................................................................................88

4.8 Frequency Modulated Phase Locked Loop (FMPLL) ....................................................................89

4.8.1 Introduction ....................................................................................................................89

4.8.2 Overview ........................................................................................................................89

4.8.3 Features ...........................................................................................................................89

4.8.4 Memory map ..................................................................................................................90

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4.8.5 Register description ........................................................................................................90

4.8.5.1 Control Register (CR) ......................................................................................90

4.8.5.2 Modulation Register (MR) ...............................................................................92

4.8.6 Functional description ....................................................................................................93

4.8.6.1 Normal mode ....................................................................................................93

4.8.6.2 Progressive clock switching .............................................................................93

4.8.6.3 Normal Mode with frequency modulation .......................................................94

4.8.6.4 Powerdown mode .............................................................................................96

4.8.7 Recommendations ..........................................................................................................96

4.9 Clock Monitor Unit (CMU) ............................................................................................................96

4.9.1 Overview ........................................................................................................................96

4.9.2 Main features ..................................................................................................................97

4.9.3 Functional description ....................................................................................................97

4.9.3.1 Crystal clock monitor .......................................................................................97

4.9.3.2 PLL clock monitor ...........................................................................................98

4.9.3.3 System clock monitor .......................................................................................98

4.9.3.4 Frequency meter ...............................................................................................99

4.9.4 Memory map and register description ............................................................................99

4.9.4.1 Control Status Register (CMU_0_CSR) ........................................................100

4.9.4.2 Frequency Display Register (CMU_0_FDR) ................................................101

4.9.4.3 High Frequency Reference Register FMPLL_0 (CMU_0_HFREFR_A) ......101

4.9.4.4 Low Frequency Reference Register FMPLL_0 (CMU_0_LFREFR_A) .......102

4.9.4.5 Interrupt Status Register (CMU_0_ISR) ........................................................102

4.9.4.6 Measurement Duration Register (CMU_0_MDR) ........................................103

Chapter 5

Clock Generation Module (MC_CGM)

5.1 Overview .......................................................................................................................................105

5.2 Features .........................................................................................................................................106

5.3 External Signal Description ..........................................................................................................107

5.4 Memory Map and Register Definition ..........................................................................................107

5.5 Register Descriptions ....................................................................................................................112

5.5.1 Output Clock Enable Register (CGM_OC_EN) ..........................................................112

5.5.2 Output Clock Division Select Register (CGM_OCDS_SC) ........................................113

5.5.3 System Clock Select Status Register (CGM_SC_SS) ..................................................114

5.5.4 System Clock Divider Configuration Register (CGM_SC_DC0) ................................114

5.5.5 Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) ......................................115

5.5.6 Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0) ......................116

5.5.7 Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) ......................................116

5.5.8 Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0) ......................117

5.5.9 Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) ......................................118

5.5.10 Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) ......................119

5.6 Functional Description ..................................................................................................................119

5.7 System Clock Generation ..............................................................................................................119

5.7.1 System Clock Source Selection ....................................................................................120

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5.7.2 System Clock Disable ...................................................................................................120

5.7.3 System Clock Dividers .................................................................................................120

5.8 Auxiliary Clock Generation ..........................................................................................................120

5.8.1 Auxiliary Clock Source Selection ................................................................................123

5.8.2 Auxiliary Clock Dividers .............................................................................................123

5.9 Dividers Functional Description ...................................................................................................123

5.10 Output Clock Multiplexing ...........................................................................................................124

5.11 Output Clock Division Selection ...................................................................................................124

Chapter 6

Power Control Unit (MC_PCU)

6.1 Introduction ...................................................................................................................................125

6.1.1 Overview ......................................................................................................................125

6.1.2 Features .........................................................................................................................126

6.2 External Signal Description ..........................................................................................................126

6.3 Memory Map and Register Definition ..........................................................................................126

6.3.1 Memory Map ................................................................................................................126

6.3.2 Register Descriptions ....................................................................................................127

6.3.2.1 Power Domain Status Register (PCU_PSTAT) ..............................................127

Chapter 7

Mode Entry Module (MC_ME)

7.1 Introduction ...................................................................................................................................129

7.1.1 Overview ......................................................................................................................129

7.1.2 Features .........................................................................................................................131

7.1.3 Modes of Operation ......................................................................................................131

7.2 External Signal Description ..........................................................................................................132

7.3 Memory Map and Register Definition ..........................................................................................132

7.3.1 Memory Map ................................................................................................................133

7.3.2 Register Description .....................................................................................................140

7.3.2.1 Global Status Register (ME_GS) ...................................................................140

7.3.2.2 Mode Control Register (ME_MCTL) ............................................................142

7.3.2.3 Mode Enable Register (ME_ME) ..................................................................143

7.3.2.4 Interrupt Status Register (ME_IS) .................................................................144

7.3.2.5 Interrupt Mask Register (ME_IM) .................................................................145

7.3.2.6 Invalid Mode Transition Status Register (ME_IMTS) ..................................146

7.3.2.7 Debug Mode Transition Status Register (ME_DMTS) ..................................147

7.3.2.8 RESET Mode Configuration Register (ME_RESET_MC) ...........................150

7.3.2.9 TEST Mode Configuration Register (ME_TEST_MC) .................................150

7.3.2.10 SAFE Mode Configuration Register (ME_SAFE_MC) ................................151

7.3.2.11 DRUN Mode Configuration Register (ME_DRUN_MC) .............................151

7.3.2.12 RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC) .................152

7.3.2.13 HALT0 Mode Configuration Register (ME_HALT0_MC) ...........................152

7.3.2.14 STOP0 Mode Configuration Register (ME_STOP0_MC) ............................153

7.3.2.15 Peripheral Status Register 0 (ME_PS0) .........................................................155

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7.3.2.16 Peripheral Status Register 1 (ME_PS1) .........................................................155

7.3.2.17 Peripheral Status Register 2 (ME_PS2) .........................................................156

7.3.2.18 Run Peripheral Configuration Registers (ME_RUN_PC0…7) .....................156

7.3.2.19 Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) .............157

7.3.2.20 Peripheral Control Registers (ME_PCTL0…143) .........................................158

7.4 Functional Description ..................................................................................................................159

7.4.1 Mode Transition Request ..............................................................................................159

7.4.2 Modes Details ...............................................................................................................160

7.4.2.1 RESET Mode .................................................................................................160

7.4.2.2 DRUN Mode ..................................................................................................161

7.4.2.3 SAFE Mode ....................................................................................................161

7.4.2.4 TEST Mode ....................................................................................................162

7.4.2.5 RUN0…3 Modes ...........................................................................................162

7.4.2.6 HALT0 Mode .................................................................................................163

7.4.2.7 STOP0 Mode ..................................................................................................163

7.4.3 Mode Transition Process ..............................................................................................164

7.4.3.1 Target Mode Request .....................................................................................164

7.4.3.2 Target Mode Configuration Loading .............................................................164

7.4.3.3 Peripheral Clocks Disable ..............................................................................165

7.4.3.4 Processor Low-Power Mode Entry ................................................................166

7.4.3.5 Processor and System Memory Clock Disable ..............................................166

7.4.3.6 Clock Sources Switch-On ..............................................................................166

7.4.3.7 Flash Modules Switch-On ..............................................................................167

7.4.3.8 Pad Outputs-On ..............................................................................................167

7.4.3.9 Peripheral Clocks Enable ...............................................................................167

7.4.3.10 Processor and Memory Clock Enable ............................................................167

7.4.3.11 Processor Low-Power Mode Exit ..................................................................167

7.4.3.12 System Clock Switching ................................................................................167

7.4.3.13 Pad Switch-Off ...............................................................................................168

7.4.3.14 Clock Sources (with no Dependencies) Switch-Off ......................................169

7.4.3.15 Clock Sources (with Dependencies) Switch-Off ...........................................169

7.4.3.16 Flash Switch-Off ............................................................................................169

7.4.3.17 Current Mode Update .....................................................................................169

7.4.4 Protection of Mode Configuration Registers ................................................................172

7.4.5 Mode Transition Interrupts ...........................................................................................172

7.4.5.1 Invalid Mode Configuration Interrupt ............................................................172

7.4.5.2 Invalid Mode Transition Interrupt ..................................................................172

7.4.5.3 SAFE Mode Transition Interrupt ...................................................................174

7.4.5.4 Mode Transition Complete Interrupt .............................................................174

7.4.6 Peripheral Clock Gating ...............................................................................................174

7.4.7 Application Example ....................................................................................................175

Chapter 8

Reset Generation Module (MC_RGM)

8.1 Introduction ...................................................................................................................................177

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8.1.1 Overview ......................................................................................................................177

8.1.2 Features .........................................................................................................................178

8.1.3 Reset Sources ................................................................................................................179

8.2 External Signal Description ..........................................................................................................180

8.3 Memory Map and Register Definition ..........................................................................................180

8.3.1 Register Descriptions ....................................................................................................182

8.3.1.1 Functional Event Status Register (RGM_FES) ..............................................182

8.3.1.2 Destructive Event Status Register (RGM_DES) ............................................184

8.3.1.3 Functional Event Reset Disable Register (RGM_FERD) ..............................185

8.3.1.4 Destructive Event Reset Disable Register (RGM_DERD) ............................186

8.3.1.5 Functional Event Alternate Request Register (RGM_FEAR) .......................187

8.3.1.6 Functional Event Short Sequence Register (RGM_FESS) ............................188

8.3.1.7 Functional Bidirectional Reset Enable Register (RGM_FBRE) ....................190

8.4 Functional Description ..................................................................................................................191

8.4.1 Reset State Machine .....................................................................................................191

8.4.1.1 PHASE0 Phase ...............................................................................................192

8.4.1.2 PHASE1 Phase ...............................................................................................193

8.4.1.3 PHASE2 Phase ...............................................................................................193

8.4.1.4 PHASE3 Phase ...............................................................................................193

8.4.1.5 IDLE Phase ....................................................................................................193

8.4.2 Destructive Resets ........................................................................................................194

8.4.3 External Reset ...............................................................................................................194

8.4.4 Functional Resets ..........................................................................................................195

8.4.5 Alternate Event Generation ..........................................................................................195

8.4.6 Boot Mode Capturing ...................................................................................................196

Chapter 9

Interrupt Controller (INTC)

9.1 Introduction ...................................................................................................................................197

9.2 Features .........................................................................................................................................197

9.3 Block diagram ...............................................................................................................................199

9.4 Modes of operation ........................................................................................................................199

9.4.1 Normal mode ................................................................................................................199

9.4.1.1 Software vector mode ....................................................................................199

9.4.1.2 Hardware vector mode ...................................................................................200

9.4.1.3 Debug mode ...................................................................................................200

9.4.1.4 Stop mode .......................................................................................................200

9.5 Memory map and registers description .........................................................................................201

9.5.1 Module memory map ...................................................................................................201

9.5.2 Registers description ....................................................................................................201

9.5.2.1 INTC Module Configuration Register (INTC_MCR) ...................................202

9.5.2.2 INTC Current Priority Register (INTC_CPR) ...............................................203

9.5.2.3 INTC Interrupt Acknowledge Register(INTC_IACKR) ...............................204

9.5.2.4 INTC End-of-Interrupt Register (INTC_EOIR) ............................................205

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9.5.2.5 INTC Software Set/Clear Interrupt Registers

(INTC_SSCIR0_3–INTC_SSCIR4_7) ................................................................................205

9.5.2.6 INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR220_221) ........206

9.6 Functional description ...................................................................................................................209

9.6.1 Interrupt request sources ...............................................................................................217

9.6.1.1 Peripheral interrupt requests ..........................................................................217

9.6.1.2 Software configurable interrupt requests .......................................................218

9.6.1.3 Unique vector for each interrupt request source ............................................218

9.6.2 Priority management ....................................................................................................218

9.6.2.1 Current priority and preemption ....................................................................218

9.6.2.2 Last-in first-out (LIFO) ..................................................................................219

9.6.3 Handshaking with processor .........................................................................................219

9.6.3.1 Software vector mode handshaking ...............................................................219

9.6.3.2 Hardware vector mode handshaking ..............................................................221

9.7 Initialization/application information ............................................................................................221

9.7.1 Initialization flow .........................................................................................................221

9.7.2 Interrupt exception handler ...........................................................................................222

9.7.2.1 Software vector mode ....................................................................................222

9.7.2.2 Hardware vector mode ...................................................................................223

9.7.3 ISR, RTOS, and task hierarchy .....................................................................................223

9.7.4 Order of execution ........................................................................................................224

9.7.5 Priority ceiling protocol ................................................................................................225

9.7.5.1 Elevating priority ...........................................................................................225

9.7.5.2 Ensuring coherency ........................................................................................225

9.7.6 Selecting priorities according to request rates and deadlines .......................................226

9.7.7 Software configurable interrupt requests ......................................................................226

9.7.7.1 Scheduling a lower priority portion of an ISR ...............................................226

9.7.7.2 Scheduling an ISR on another processor .......................................................227

9.7.8 Lowering priority within an ISR ..................................................................................227

9.7.9 Negating an interrupt request outside of its ISR ..........................................................228

9.7.9.1 Negating an interrupt request as a side effect of an ISR ................................228

9.7.9.2 Negating multiple interrupt requests in one ISR ............................................228

9.7.9.3 Proper setting of interrupt request priority .....................................................228

9.7.10 Examining LIFO contents ............................................................................................228

Chapter 10

System Status and Configuration Module (SSCM)

10.1 Introduction ...................................................................................................................................229

10.1.1 Overview ......................................................................................................................229

10.1.2 Features .........................................................................................................................229

10.1.3 Modes of operation .......................................................................................................230

10.2 Memory map and register description ...........................................................................................230

10.2.1 Memory map ................................................................................................................230

10.2.2 Register description ......................................................................................................230

10.2.2.1 System Status register (STATUS) ..................................................................231

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10.2.2.2 System Memory Configuration register (MEMCONFIG) .............................232

10.2.2.3 Error Configuration (ERROR) register ..........................................................233

10.2.2.4 Debug Status Port (DEBUGPORT) register ..................................................233

10.2.2.5 Password comparison registers ......................................................................236

10.3 Functional description ...................................................................................................................237

10.4 Initialization/application information ............................................................................................237

10.4.1 Reset .............................................................................................................................237

Chapter 11

System Integration Unit Lite (SIUL)

11.1 Introduction ...................................................................................................................................239

11.2 Overview .......................................................................................................................................239

11.3 Features .........................................................................................................................................240

11.3.1 Register protection ........................................................................................................241

11.4 External signal description ............................................................................................................241

11.4.1 Detailed signal descriptions ..........................................................................................241

11.4.1.1 General-purpose I/O pins (GPIO[0:66]) ........................................................241

11.4.1.2 External interrupt request input pins (EIRQ[0:24]) .......................................241

11.5 Memory map and register description ...........................................................................................242

11.5.1 SIUL memory map .......................................................................................................242

11.5.2 Register description ......................................................................................................243

11.5.2.1 MCU ID Register #1 (MIDR1) ......................................................................243

11.5.2.2 MCU ID Register #2 (MIDR2) ......................................................................245

11.5.2.3 Interrupt Status Flag Register (ISR) ...............................................................246

11.5.2.4 Interrupt Request Enable Register (IRER) .....................................................246

11.5.2.5 Interrupt Rising-Edge Event Enable Register (IREER) .................................247

11.5.2.6 Interrupt Falling-Edge Event Enable Register (IFEER) ................................247

11.5.2.7 Interrupt Filter Enable Register (IFER) .........................................................248

11.5.2.8 Pad Configuration Registers (PCR[0:71]) .....................................................248

11.5.2.9 Pad Selection for Multiplexed Inputs registers (PSMI[0_3:32_35]) .............250

11.5.2.10 GPIO Pad Data Output registers 0_3–68_71 (GPDO[0_3:68_71]) ...............254

11.5.2.11 GPIO Pad Data Input registers 0_3–68_71 (GPDI[0_3:68_71]) ...................254

11.5.2.12 Parallel GPIO Pad Data Out register 0–3 (PGPDO[0:3]) ..............................255

11.5.2.13 Parallel GPIO Pad Data In register 0–3 (PGPDI[0:3]) ..................................255

11.5.2.14 Masked Parallel GPIO Pad Data Out register 0–6 (MPGPDO[0:6]) .............256

11.5.2.15 Interrupt Filter Maximum Counter registers 0–24 (IFMC[0:24]) ..................257

11.5.2.16 Interrupt Filter Clock Prescaler Register (IFCPR) .........................................257

11.6 Functional description ...................................................................................................................259

11.6.1 General .........................................................................................................................259

11.6.2 Pad control ....................................................................................................................259

11.6.3 General purpose input and output pads (GPIO) ...........................................................259

11.6.4 External interrupts ........................................................................................................260

11.6.4.1 External interrupt management ......................................................................261

11.7 Pin muxing ....................................................................................................................................261

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Chapter 12

e200z0 and e200z0h Core

12.1 Overview .......................................................................................................................................263

12.2 Features .........................................................................................................................................263

12.2.1 Microarchitecture summary ..........................................................................................264

12.2.1.1 Block diagram ................................................................................................264

12.2.1.2 Instruction unit features .................................................................................266

12.2.1.3 Integer unit features .......................................................................................267

12.2.1.4 Load/Store unit features .................................................................................267

12.2.1.5 e200z0h system bus features ..........................................................................267

12.2.1.6 Nexus features ................................................................................................267

12.3 Core registers and programmer’s model .......................................................................................268

12.3.1 Unimplemented SPRs and read-only SPRs ..................................................................271

12.4 Instruction summary ......................................................................................................................271

Chapter 13

Peripheral Bridge (PBRIDGE)

13.1 Introduction ...................................................................................................................................273

13.1.1 Block diagram ..............................................................................................................273

13.1.2 Overview ......................................................................................................................273

13.1.3 Modes of operation .......................................................................................................274

13.2 Functional description ...................................................................................................................274

13.2.1 Access support ..............................................................................................................274

13.2.1.1 Peripheral Write Buffering .............................................................................274

13.2.1.2 Read cycles ....................................................................................................274

13.2.1.3 Write cycles ....................................................................................................274

13.2.2 General operation .........................................................................................................274

Chapter 14

Crossbar Switch (XBAR)

14.1 Introduction ...................................................................................................................................275

14.2 Block diagram ...............................................................................................................................275

14.3 Overview .......................................................................................................................................276

14.4 Features .........................................................................................................................................276

14.5 Modes of operation ........................................................................................................................276

14.5.1 Normal mode ................................................................................................................276

14.5.2 Debug mode ..................................................................................................................276

14.6 Functional description ...................................................................................................................277

14.6.1 Overview ......................................................................................................................277

14.6.2 General operation .........................................................................................................277

14.6.3 Master ports ..................................................................................................................278

14.6.4 Slave ports ....................................................................................................................278

14.6.5 Priority assignment .......................................................................................................278

14.6.6 Arbitration ....................................................................................................................278

14.6.6.1 Fixed priority operation .................................................................................279

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Chapter 15

Error Correction Status Module (ECSM)

15.1 Introduction ...................................................................................................................................281

15.2 Overview .......................................................................................................................................281

15.3 Features .........................................................................................................................................281

15.4 Memory map and registers description .........................................................................................281

15.4.1 Memory map ................................................................................................................282

15.4.2 Registers description ....................................................................................................283

15.4.2.1 Processor core type (PCT) register ................................................................283

15.4.2.2 Revision (REV) register .................................................................................283

15.4.2.3 Platform XBAR Master Configuration (PLAMC) .........................................284

15.4.2.4 Platform XBAR Slave Configuration (PLASC) ............................................284

15.4.2.5 IPS Module Configuration (IMC) register .....................................................285

15.4.2.6 Miscellaneous Reset Status Register (MRSR) ...............................................285

15.4.2.7 Miscellaneous Interrupt Register (MIR) ........................................................286

15.4.2.8 Miscellaneous User-Defined Control Register (MUDCR) ............................287

15.4.2.9 ECC registers .................................................................................................287

15.4.2.10 ECC Configuration Register (ECR) ...............................................................288

15.4.2.11 ECC Status Register (ESR) ............................................................................289

15.4.2.12 ECC Error Generation Register (EEGR) .......................................................290

15.4.2.13 Flash ECC Address Register (FEAR) ............................................................292

15.4.2.14 Flash ECC Master Number Register (FEMR) ...............................................293

15.4.2.15 Flash ECC Attributes (FEAT) register ...........................................................293

15.4.2.16 Flash ECC Data Register (FEDR) .................................................................294

15.4.2.17 RAM ECC Address Register (REAR) ...........................................................295

15.4.2.18 RAM ECC Syndrome Register (RESR) ........................................................296

15.4.2.19 RAM ECC Master Number Register (REMR) ..............................................298

15.4.2.20 RAM ECC Attributes (REAT) register ..........................................................298

15.4.2.21 RAM ECC Data Register (REDR) .................................................................299

15.4.3 ECSM_reg_protection ..................................................................................................300

Chapter 16

Internal Static RAM (SRAM)

16.1 Introduction ...................................................................................................................................303

16.2 SRAM operating mode ..................................................................................................................303

16.3 Module memory map ....................................................................................................................303

16.4 Register descriptions .....................................................................................................................303

16.5 SRAM ECC mechanism ................................................................................................................303

16.5.1 Access timing ...............................................................................................................304

16.5.2 Reset effects on SRAM accesses ..................................................................................305

16.6 Functional description ...................................................................................................................305

16.7 Initialization and application information .....................................................................................305

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Chapter 17

Flash Memory

17.1 Introduction ...................................................................................................................................307

17.2 Platform Flash controller ...............................................................................................................307

17.2.1 Introduction ..................................................................................................................307

17.2.1.1 Overview ........................................................................................................308

17.2.1.2 Features ..........................................................................................................308

17.2.2 Modes of operation .......................................................................................................309

17.2.3 External signal descriptions ..........................................................................................309

17.2.4 Memory map and registers description ........................................................................309

17.2.4.1 Memory map ..................................................................................................310

17.2.5 Functional description ..................................................................................................311

17.2.6 Basic interface protocol ................................................................................................312

17.2.7 Access protections ........................................................................................................312

17.2.8 Read cycles — buffer miss ...........................................................................................312

17.2.9 Read cycles — buffer hit ..............................................................................................313

17.2.10 Write cycles ..................................................................................................................313

17.2.11 Error termination ..........................................................................................................313

17.2.12 Access pipelining ..........................................................................................................314

17.2.13 Flash error response operation ......................................................................................314

17.2.14 Bank0 page read buffers and prefetch operation ..........................................................314

17.2.14.1 Instruction/data prefetch triggering ................................................................316

17.2.14.2 Per-master prefetch triggering ........................................................................316

17.2.14.3 Buffer allocation .............................................................................................316

17.2.14.4 Buffer invalidation .........................................................................................316

17.2.15 Bank1 temporary holding register ................................................................................317

17.2.16 Read-While-Write functionality ...................................................................................317

17.2.17 Wait state emulation .....................................................................................................319

17.2.18 Timing diagrams ...........................................................................................................320

17.3 Flash memory ................................................................................................................................327

17.3.1 Introduction ..................................................................................................................327

17.3.2 Main features ................................................................................................................327

17.3.3 Block diagram ..............................................................................................................327

17.3.3.1 Data Flash ......................................................................................................327

17.3.3.2 Code Flash ......................................................................................................328

17.3.4 Functional description ..................................................................................................329

17.3.4.1 Macrocell structure ........................................................................................329

17.3.4.2 Flash module sectorization .............................................................................330

17.3.5 Operating modes ...........................................................................................................333

17.3.5.1 Reset ...............................................................................................................333

17.3.5.2 User mode ......................................................................................................333

17.3.5.3 Low-power mode ...........................................................................................334

17.3.5.4 Power-down mode .........................................................................................335

17.3.6 Registers description ....................................................................................................336

17.3.7 Register map .................................................................................................................337

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17.3.7.1 Module Configuration Register (MCR) .........................................................339

17.3.7.2 Low/Mid Address Space Block Locking register (LML) ..............................344

17.3.7.3 Non-Volatile Low/Mid Address Space Block Locking register (NVLML) ...345

17.3.7.4 Secondary Low/Mid Address Space Block Locking register (SLL) .............346

17.3.7.5 Non-Volatile Secondary Low/Mid Address Space Block Locking register

(NVSLL) .........................................................................................................................347

17.3.7.6 Low/Mid Address Space Block Select register (LMS) ..................................349

17.3.7.7 Address Register (ADR) ................................................................................349

17.3.7.8 User Test 0 register (UT0) ..............................................................................357

17.3.7.9 User Test 1 register (UT1) ..............................................................................359

17.3.7.10 User Test 2 register (UT2) ..............................................................................360

17.3.7.11 User Multiple Input Signature Register 0 (UMISR0) ....................................360

17.3.7.12 User Multiple Input Signature Register 1 (UMISR1) ....................................361

17.3.7.13 User Multiple Input Signature Register 2 (UMISR2) ....................................362

17.3.7.14 User Multiple Input Signature Register 3 (UMISR3) ....................................362

17.3.7.15 User Multiple Input Signature Register 4 (UMISR4) ....................................363

17.3.7.16 Non-Volatile Private Censorship Password 0 register (NVPWD0) ...............364

17.3.7.17 Non-Volatile Private Censorship Password 1 register (NVPWD1) ...............364

17.3.7.18 Non-Volatile System Censoring Information 0 register (NVSCI0) ...............365

17.3.7.19 Non-Volatile System Censoring Information 1 register (NVSCI1) ...............366

17.3.7.20 Non-Volatile User Options register (NVUSRO) ............................................367

17.3.8 Code Flash programming considerations .....................................................................368

17.3.8.1 Modify operation ............................................................................................368

17.3.8.2 Error Correction Code (ECC) ........................................................................376

17.3.8.3 EEPROM emulation ......................................................................................376

17.3.8.4 Protection strategy ..........................................................................................377

Chapter 18

Enhanced Direct Memory Access (eDMA)

18.1 Introduction ...................................................................................................................................381

18.2 Overview .......................................................................................................................................381

18.3 Features .........................................................................................................................................382

18.4 Modes of operation ........................................................................................................................383

18.4.1 Normal mode ................................................................................................................383

18.4.2 Debug mode ..................................................................................................................383

18.5 Memory map and register definition .............................................................................................384

18.5.1 Memory map ................................................................................................................384

18.5.2 Register descriptions ....................................................................................................387

18.5.2.1 eDMA Control Register (EDMA_CR) ..........................................................387

18.5.2.2 eDMA Error Status Register (EDMA_ESR) .................................................388

18.5.2.3 eDMA Enable Request Register (EDMA_ERQRL) ......................................390

18.5.2.4 eDMA Enable Error Interrupt Register (EDMA_EEIRL) .............................391

18.5.2.5 eDMA Set Enable Request Register (EDMA_SERQR) ................................392

18.5.2.6 eDMA Clear Enable Request Register (EDMA_CERQR) ............................392

18.5.2.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEIR) .......................393

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18.5.2.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR) ...................393

18.5.2.9 eDMA Clear Interrupt Request Register (EDMA_CIRQR) ..........................394

18.5.2.10 eDMA Clear Error Register (EDMA_CERR) ...............................................395

18.5.2.11 eDMA Set START Bit Register (EDMA_SSBR) ..........................................395

18.5.2.12 eDMA Clear DONE Status Bit Register (EDMA_CDSBR) .........................396

18.5.2.13 eDMA Interrupt Request Register (EDMA_IRQRL) ....................................396

18.5.2.14 eDMA Error Register (EDMA_ERL) ............................................................397

18.5.2.15 DMA Hardware Request Status (DMAHRSL) ..............................................398

18.5.2.16 eDMA Channel n Priority Registers (EDMA_CPRn) ...................................399

18.5.2.17 Transfer Control Descriptor (TCD) ...............................................................400

18.6 Functional description ...................................................................................................................407

18.6.1 eDMA microarchitecture ..............................................................................................407

18.6.2 eDMA basic data flow ..................................................................................................409

18.6.3 eDMA performance ......................................................................................................411

18.7 Initialization / application information ..........................................................................................414

18.7.1 eDMA initialization ......................................................................................................414

18.7.2 DMA programming errors ............................................................................................416

18.7.3 DMA request assignments ............................................................................................417

18.7.4 DMA arbitration mode considerations .........................................................................417

18.7.4.1 Fixed-channel arbitration ...............................................................................417

18.7.4.2 Fixed-group arbitration, round-robin channel arbitration ..............................417

18.7.5 DMA transfer ................................................................................................................418

18.7.5.1 Single request .................................................................................................418

18.7.5.2 Multiple requests ............................................................................................419

18.7.5.3 Modulo feature ...............................................................................................420

18.7.6 TCD status ....................................................................................................................421

18.7.6.1 Minor loop complete ......................................................................................421

18.7.6.2 Active channel TCD reads .............................................................................422

18.7.6.3 Preemption status ...........................................................................................422

18.7.7 Channel linking ............................................................................................................422

18.7.8 Dynamic programming .................................................................................................423

18.7.8.1 Dynamic channel linking and dynamic scatter/gather ...................................423

Chapter 19

DMA Channel Mux (DMA_MUX)

19.1 Introduction ...................................................................................................................................425

19.1.1 Overview ......................................................................................................................425

19.1.2 Features .........................................................................................................................425

19.1.3 Modes of operation .......................................................................................................426

19.2 External signal description ............................................................................................................426

19.2.1 Overview ......................................................................................................................426

19.3 Memory map and register definition .............................................................................................426

19.3.1 Memory map ................................................................................................................426

19.3.2 Register descriptions ....................................................................................................428

19.3.2.1 Channel Configuration Registers ...................................................................428

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19.4 DMA request mapping ..................................................................................................................429

19.5 Functional description ...................................................................................................................430

19.5.1 DMA channels with periodic triggering capability ......................................................430

19.5.2 DMA channels with no triggering capability ...............................................................433

19.6 Initialization/application information ............................................................................................433

19.6.1 Reset .............................................................................................................................433

19.6.2 Enabling and configuring sources ................................................................................433

Chapter 20

Deserial Serial Peripheral Interface (DSPI)

20.1 Introduction ...................................................................................................................................437

20.2 Block diagram ...............................................................................................................................437

20.3 Overview .......................................................................................................................................438

20.4 Features .........................................................................................................................................438

20.5 Modes of operation ........................................................................................................................439

20.5.1 Master mode .................................................................................................................439

20.5.2 Slave mode ...................................................................................................................439

20.5.3 Module disable mode ...................................................................................................440

20.5.4 Debug mode ..................................................................................................................440

20.6 External signal description ............................................................................................................440

20.6.1 Signal overview ............................................................................................................440

20.6.2 Signal names and descriptions ......................................................................................441

20.6.2.1 Peripheral Chip Select / Slave Select (CS_0) ................................................441

20.6.2.2 Peripheral Chip Selects 1–3 (CS1:3) .............................................................441

20.6.2.3 Peripheral Chip Select 4 (CS4) ......................................................................441

20.6.2.4 Peripheral Chip Select 5/Peripheral Chip Select Strobe (CS_5) ....................441

20.6.2.5 Serial Input (SIN_x) .......................................................................................441

20.6.2.6 Serial Output (SOUT_x) ................................................................................441

20.6.2.7 Serial Clock (SCK_x) .....................................................................................442

20.7 Memory map and registers description .........................................................................................442

20.7.1 Memory map ................................................................................................................442

20.7.2 Registers description ....................................................................................................443

20.7.2.1 DSPI Module Configuration Register (DSPIx_MCR) ...................................443

20.7.2.2 DSPI Transfer Count Register (DSPIx_TCR) ...............................................446

20.7.2.3 DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn) ...........447

20.7.2.4 DSPI Status Register (DSPIx_SR) .................................................................453

20.7.2.5 DSPI DMA / Interrupt Request Select and Enable Register

(DSPIx_RSER) ....................................................................................................................455

20.7.2.6 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) ........................................456

20.7.2.7 DSPI POP RX FIFO Register (DSPIx_POPR) ..............................................458

20.7.2.8 DSPI Transmit FIFO Registers 0–4 (DSPIx_TXFRn) ...................................459

20.7.2.9 DSPI Receive FIFO Registers 0–4 (DSPIx_RXFRn) ....................................459

20.8 Functional description ...................................................................................................................460

20.8.1 Modes of operation .......................................................................................................461

20.8.1.1 Master mode ...................................................................................................461

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20.8.1.2 Slave mode .....................................................................................................462

20.8.1.3 Module disable mode .....................................................................................462

20.8.1.4 Debug mode ...................................................................................................462

20.8.2 Start and stop of DSPI transfers ...................................................................................462

20.8.3 Serial Peripheral Interface (SPI) configuration ............................................................463

20.8.3.1 SPI master mode ............................................................................................463

20.8.3.2 SPI slave mode ...............................................................................................464

20.8.3.3 FIFO disable operation ...................................................................................464

20.8.3.4 Transmit First In First Out (TX FIFO) buffering mechanism ........................464

20.8.3.5 Receive First In First Out (RX FIFO) buffering mechanism .........................465

20.8.4 DSPI baud rate and clock delay generation ..................................................................466

20.8.4.1 Baud rate generator ........................................................................................466

20.8.4.2 CS to SCK delay (tCSC) ..................................................................................467

20.8.4.3 After SCK delay (tASC) ..................................................................................467

20.8.4.4 Delay after transfer (tDT) ..............................................................................468

20.8.4.5 Peripheral Chip Select strobe enable (CS5_x) ...............................................468

20.8.5 Transfer formats ...........................................................................................................469

20.8.5.1 Classic SPI transfer format (CPHA = 0) ........................................................470

20.8.5.2 Classic SPI transfer format (CPHA = 1) ........................................................471

20.8.5.3 Modified SPI transfer format (MTFE = 1, CPHA = 0) ..................................472

20.8.5.4 Modified SPI transfer format (MTFE = 1, CPHA = 1) ..................................473

20.8.5.5 Continuous selection format ..........................................................................474

20.8.5.6 Clock polarity switching between DSPI transfers .........................................475

20.8.6 Continuous Serial communications clock ....................................................................476

20.8.7 Interrupts/DMA requests ..............................................................................................478

20.8.7.1 End of queue interrupt request (EOQF) .........................................................478

20.8.7.2 Transmit FIFO fill interrupt or DMA request (TFFF) ...................................478

20.8.7.3 Transfer complete interrupt request (TCF) ....................................................478

20.8.7.4 Transmit FIFO underflow interrupt request (TFUF) .....................................479

20.8.7.5 Receive FIFO drain interrupt or DMA request (RFDF) ................................479

20.8.7.6 Receive FIFO overflow interrupt request (RFOF) .........................................479

20.8.7.7 FIFO overrun request (TFUF) or (RFOF) ......................................................479

20.8.8 Power saving features ...................................................................................................479

20.8.8.1 Module disable mode .....................................................................................479

20.9 Initialization and application information .....................................................................................480

20.9.1 Managing queues ..........................................................................................................480

20.9.2 Baud rate settings .........................................................................................................480

20.9.3 Delay settings ...............................................................................................................482

20.9.4 MPC5602P DSPI compatibility with QSPI of the MPC500 MCUs ............................482

20.9.5 Calculation of FIFO pointer addresses .........................................................................483

20.9.5.1 Address calculation for first-in entry and last-in entry in TX FIFO ..............484

20.9.5.2 Address calculation for first-in entry and last-in entry in RX FIFO ..............484

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Chapter 21

LIN Controller (LINFlex)

21.1 Introduction ...................................................................................................................................487

21.2 Main features .................................................................................................................................487

21.2.1 LIN mode features ........................................................................................................487

21.2.2 UART mode features ....................................................................................................487

21.2.3 Features common to LIN and UART ...........................................................................487

21.3 General description .......................................................................................................................488

21.4 Fractional baud rate generation .....................................................................................................489

21.5 Operating modes ...........................................................................................................................491

21.5.1 Initialization mode ........................................................................................................492

21.5.2 Normal mode ................................................................................................................492

21.5.3 Low power mode (Sleep) .............................................................................................492

21.6 Test modes .....................................................................................................................................492

21.6.1 Loop Back mode ...........................................................................................................492

21.6.2 Self Test mode ..............................................................................................................493

21.7 Memory map and registers description .........................................................................................493

21.7.1 Memory map ................................................................................................................493

21.7.1.1 LIN control register 1 (LINCR1) ...................................................................495

21.7.1.2 LIN interrupt enable register (LINIER) .........................................................498

21.7.1.3 LIN status register (LINSR) ...........................................................................499

21.7.1.4 LIN error status register (LINESR) ...............................................................502

21.7.1.5 UART mode control register (UARTCR) ......................................................503

21.7.1.6 UART mode status register (UARTSR) .........................................................504

21.7.1.7 LIN timeout control status register (LINTCSR) ............................................506

21.7.1.8 LIN output compare register (LINOCR) .......................................................507

21.7.1.9 LIN timeout control register (LINTOCR) ......................................................508

21.7.1.10 LIN fractional baud rate register (LINFBRR) ...............................................508

21.7.1.11 LIN integer baud rate register (LINIBRR) ....................................................509

21.7.1.12 LIN checksum field register (LINCFR) .........................................................510

21.7.1.13 LIN control register 2 (LINCR2) ...................................................................510

21.7.1.14 Buffer identifier register (BIDR) ...................................................................511

21.7.1.15 Buffer data register LSB (BDRL) ..................................................................512

21.7.1.16 Buffer data register MSB (BDRM) ................................................................513

21.7.1.17 Identifier filter enable register (IFER) ...........................................................514

21.7.1.18 Identifier filter match index (IFMI) ...............................................................514

21.7.1.19 Identifier filter mode register (IFMR) ............................................................515

21.7.1.20 Identifier filter control register (IFCR2n) ......................................................516

21.7.1.21 Identifier filter control register (IFCR2n+ 1) ................................................517

21.8 Functional description ...................................................................................................................519

21.8.1 UART mode ..................................................................................................................519

21.8.1.1 Buffer in UART mode ....................................................................................519

21.8.1.2 UART transmitter ...........................................................................................520

21.8.1.3 UART receiver ...............................................................................................520

21.8.1.4 Clock gating ...................................................................................................521

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21.8.2 LIN mode ......................................................................................................................521

21.8.2.1 Master mode ...................................................................................................521

21.8.2.2 Slave mode .....................................................................................................523

21.8.2.3 Slave mode with identifier filtering ...............................................................525

21.8.2.4 Slave mode with automatic resynchronization ..............................................527

21.8.2.5 Clock gating ...................................................................................................529

21.8.3 8-bit timeout counter ....................................................................................................529

21.8.3.1 LIN timeout mode ..........................................................................................529

21.8.3.2 Output compare mode ....................................................................................530

21.8.4 Interrupts .......................................................................................................................531

Chapter 22

FlexCAN

22.1 Introduction ...................................................................................................................................533

22.1.1 Overview ......................................................................................................................533

22.1.2 FlexCAN module features ............................................................................................534

22.1.3 Modes of operation .......................................................................................................535

22.2 External signal description ............................................................................................................536

22.2.1 Overview ......................................................................................................................536

22.2.2 Signal Descriptions .......................................................................................................536

22.2.2.1 RXD ...............................................................................................................536

22.2.2.2 TXD ...............................................................................................................536

22.3 Memory map and registers description .........................................................................................536

22.3.1 FlexCAN memory mapping .........................................................................................536

22.3.2 Message buffer structure ..............................................................................................539

22.3.3 Rx FIFO structure .........................................................................................................542

22.3.4 Registers description ....................................................................................................544

22.3.4.1 Module Configuration Register (MCR) .........................................................544

22.3.4.2 Control Register (CTRL) ...............................................................................548

22.3.4.3 Free Running Timer (TIMER) .......................................................................551

22.3.4.4 Rx Global Mask register (RXGMASK) .........................................................552

22.3.4.5 Rx 14 Mask (RX14MASK) ...........................................................................552

22.3.4.6 Rx 15 Mask (RX15MASK) ...........................................................................553

22.3.4.7 Error Counter Register (ECR) ........................................................................554

22.3.4.8 Error and Status Register (ESR) ....................................................................555

22.3.4.9 Interrupt Masks 1 Register (IMASK1) ..........................................................558

22.3.4.10 Interrupt Flags 1 Register (IFLAG1) .............................................................558

22.3.4.11 Rx Individual Mask Registers (RXIMR0–RXIMR31) ..................................559

22.4 Functional description ...................................................................................................................562

22.4.1 Overview ......................................................................................................................562

22.4.2 Transmit process ...........................................................................................................562

22.4.3 Arbitration process .......................................................................................................563

22.4.4 Receive process ............................................................................................................564

22.4.5 Matching process ..........................................................................................................565

22.4.6 Data coherence .............................................................................................................566

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22.4.6.1 Transmission abort mechanism ......................................................................566

22.4.6.2 Message Buffer deactivation ..........................................................................567

22.4.6.3 Message Buffer lock mechanism ...................................................................568

22.4.7 Rx FIFO ........................................................................................................................569

22.4.8 CAN protocol related features ......................................................................................570

22.4.8.1 Remote frames ...............................................................................................570

22.4.8.2 Overload frames .............................................................................................570

22.4.8.3 Time stamp .....................................................................................................570

22.4.8.4 Protocol timing ...............................................................................................571

22.4.8.5 Arbitration and matching timing ....................................................................573

22.4.9 Modes of operation details ...........................................................................................574

22.4.9.1 Freeze mode ...................................................................................................574

22.4.9.2 Module disable mode .....................................................................................574

22.4.9.3 Stop mode .......................................................................................................575

22.4.10 Interrupts .......................................................................................................................575

22.4.11 Bus interface .................................................................................................................576

22.5 Initialization/application information ............................................................................................576

22.5.1 FlexCAN initialization sequence ..................................................................................576

Chapter 23

Analog-to-Digital Converter (ADC)

23.1 Overview .......................................................................................................................................579

23.1.1 Device-specific features ...............................................................................................579

23.1.2 Device-specific pin configuration features ...................................................................580

23.1.3 Device-specific implementation ...................................................................................580

23.2 Introduction ...................................................................................................................................580

23.3 Functional description ...................................................................................................................581

23.3.1 Analog channel conversion ..........................................................................................581

23.3.1.1 Normal conversion .........................................................................................581

23.3.1.2 Start of normal conversion .............................................................................581

23.3.1.3 Normal conversion operating modes .............................................................582

23.3.1.4 Injected channel conversion ...........................................................................583

23.3.1.5 Abort conversion ............................................................................................584

23.3.2 Analog clock generator and conversion timings ..........................................................584

23.3.3 ADC sampling and conversion timing .........................................................................585

23.3.3.1 ADC_0 ...........................................................................................................585

23.3.4 ADC CTU (Cross Triggering Unit) ..............................................................................587

23.3.4.1 Overview ........................................................................................................587

23.3.4.2 CTU in control mode .....................................................................................587

23.3.5 Programmable analog watchdog ..................................................................................588

23.3.5.1 Introduction ....................................................................................................588

23.3.5.2 Analog watchdog functionality ......................................................................589

23.3.6 DMA functionality .......................................................................................................589

23.3.7 Interrupts .......................................................................................................................589

23.3.8 Power-down mode ........................................................................................................590

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23.3.9 Auto-clock-off mode ....................................................................................................591

23.4 Register descriptions .....................................................................................................................591

23.4.1 Introduction ..................................................................................................................591

23.4.2 Control logic registers ..................................................................................................593

23.4.2.1 Main Configuration Register (MCR) .............................................................593

23.4.2.2 Main Status Register (MSR) ..........................................................................594

23.4.3 Interrupt registers ..........................................................................................................596

23.4.3.1 Interrupt Status Register (ISR) .......................................................................596

23.4.3.2 Interrupt Mask Register (IMR) ......................................................................596

23.4.3.3 Watchdog Threshold Interrupt Status Register (WTISR) ..............................598

23.4.3.4 Watchdog Threshold Interrupt Mask Register (WTIMR) ..............................599

23.4.4 DMA registers ..............................................................................................................600

23.4.4.1 DMA Enable (DMAE) register ......................................................................600

23.4.4.2 DMA Channel Select Register (DMAR[0]) ...................................................601

23.4.5 Threshold registers .......................................................................................................602

23.4.5.1 Introduction ....................................................................................................602

23.4.5.2 Threshold Control Register (TRCx, x = [0..3]) ..............................................602

23.4.5.3 Threshold Register (THRHLR[0:3]) ..............................................................603

23.4.6 Conversion Timing Registers CTR[0] ..........................................................................604

23.4.7 Mask registers ...............................................................................................................604

23.4.7.1 Introduction ....................................................................................................604

23.4.7.2 Normal Conversion Mask Registers (NCMR[0]) ..........................................604

23.4.7.3 Injected Conversion Mask Registers (JCMR[0]) ...........................................606

23.4.8 Delay registers ..............................................................................................................607

23.4.8.1 Power-Down Exit Delay Register (PDEDR) .................................................607

23.4.9 Data registers ................................................................................................................607

23.4.9.1 Introduction ....................................................................................................607

23.4.9.2 Channel Data Registers (CDR[0..15]) ...........................................................607

Chapter 24

Cross Triggering Unit (CTU)

24.1 Introduction ...................................................................................................................................609

24.2 CTU overview ...............................................................................................................................609

24.3 Functional description ...................................................................................................................610

24.3.1 Trigger events features .................................................................................................610

24.3.2 Trigger generator subunit (TGS) ..................................................................................611

24.3.3 TGS in triggered mode .................................................................................................611

24.3.4 TGS in sequential mode ...............................................................................................612

24.3.5 TGS counter ..................................................................................................................613

24.4 Scheduler subunit (SU) .................................................................................................................614

24.4.1 ADC commands list .....................................................................................................616

24.4.2 ADC commands list format ..........................................................................................616

24.4.3 ADC results ..................................................................................................................618

24.5 Reload mechanism ........................................................................................................................618

24.6 Power safety mode ........................................................................................................................620

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24.6.1 MDIS bit .......................................................................................................................620

24.6.2 STOP mode ..................................................................................................................620

24.7 Interrupts and DMA requests ........................................................................................................620

24.7.1 DMA support ................................................................................................................620

24.7.2 CTU faults and errors ...................................................................................................620

24.7.3 CTU interrupt/DMA requests .......................................................................................621

24.8 Memory map .................................................................................................................................623

24.8.1 Trigger Generator Sub-unit Input Selection Register (TGSISR) .................................627

24.8.2 Trigger Generator Sub-unit Control Register (TGSCR) ..............................................629

24.8.3 Trigger x Compare Register (TxCR, x= 0...7) .............................................................630

24.8.4 TGS Counter Compare Register (TGSCCR) ...............................................................630

24.8.5 TGS Counter Reload Register (TGSCRR) ...................................................................631

24.8.6 Commands list control register 1 (CLCR1) ..................................................................631

24.8.7 Commands list control register 2 (CLCR2) ..................................................................632

24.8.8 Trigger handler control register 1 (THCR1) .................................................................632

24.8.9 Trigger handler control register 2 (THCR2) .................................................................634

24.8.10 Commands list register x (x = 1,...,24) (CLRx) ............................................................636

24.8.11 FIFO DMA control register (FDCR) ............................................................................637

24.8.12 FIFO control register (FCR) .........................................................................................638

24.8.13 FIFO threshold register (FTH) .....................................................................................639

24.8.14 FIFO status register (FST) ............................................................................................640

24.8.15 FIFO Right aligned data x (x= 0,...,3) (FRx) ...............................................................641

24.8.16 FIFO signed Left aligned data x (x= 0,...,3) (FLx) ......................................................642

24.8.17 Cross triggering unit error flag register (CTUEFR) .....................................................642

24.8.18 Cross triggering unit interrupt flag register (CTUIFR) ................................................643

24.8.19 Cross triggering unit interrupt/DMA register (CTUIR) ...............................................644

24.8.20 Control ON time register (COTR) ................................................................................645

24.8.21 Cross triggering unit control register (CTUCR) ...........................................................647

24.8.22 Cross triggering unit digital filter (CTUDF) ................................................................648

24.8.23 Cross triggering unit power control register (CTUPCR) .............................................648

Chapter 25

FlexPWM

25.1 Overview .......................................................................................................................................649

25.2 Features .........................................................................................................................................649

25.3 Modes of operation ........................................................................................................................650

25.4 Block diagrams ..............................................................................................................................651

25.4.1 Module level .................................................................................................................651

25.4.2 PWM submodule ..........................................................................................................652

25.5 External signal descriptions ..........................................................................................................653

25.5.1 PWMA[n] and PWMB[n] — external PWM pair ........................................................653

25.5.2 PWMX[n] — auxiliary PWM signal ............................................................................653

25.5.3 FAULT[n] — fault inputs .............................................................................................653

25.5.4 EXT_SYNC — external synchronization signal ..........................................................653

25.5.5 EXT_FORCE — external output force signal ..............................................................653

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25.5.6 OUT_TRIG0[n] and OUT_TRIG1[n] — output triggers ............................................653

25.5.7 EXT_CLK — external clock signal .............................................................................653

25.6 Memory map and registers ............................................................................................................654

25.6.1 FlexPWM module memory map ..................................................................................654

25.6.2 Register descriptions ....................................................................................................657

25.6.3 Submodule registers .....................................................................................................657

25.6.3.1 Counter Register (CNT) .................................................................................657

25.6.3.2 Initial Count Register (INIT) .........................................................................657

25.6.3.3 Control 2 Register (CTRL2) ..........................................................................658

25.6.3.4 Control 1 Register (CTRL1) ..........................................................................660

25.6.3.5 Value register 0 (VAL0) .................................................................................662

25.6.3.6 Value register 1 (VAL1) .................................................................................663

25.6.3.7 Value register 2 (VAL2) .................................................................................663

25.6.3.8 Value register 3 (VAL3) .................................................................................664

25.6.3.9 Value register 4 (VAL4) .................................................................................664

25.6.3.10 Value register 5 (VAL5) .................................................................................665

25.6.3.11 Output Control register (OCTRL) ..................................................................665

25.6.3.12 Status register (STS) ......................................................................................666

25.6.3.13 Interrupt Enable register (INTEN) .................................................................667

25.6.3.14 DMA Enable register (DMAEN) ...................................................................668

25.6.3.15 Output Trigger Control register (TCTRL) .....................................................669

25.6.3.16 Fault Disable Mapping register (DISMAP) ...................................................670

25.6.3.17 Deadtime Count registers (DTCNT0, DTCNT1) ..........................................670

25.6.4 Configuration registers .................................................................................................671

25.6.4.1 Output Enable register (OUTEN) ..................................................................671

25.6.4.2 Mask register (MASK) ...................................................................................672

25.6.4.3 Software Controlled Output Register (SWCOUT) ........................................673

25.6.4.4 Deadtime Source Select Register (DTSRCSEL) ...........................................674

25.6.4.5 Master Control Register (MCTRL) ................................................................676

25.6.5 Fault channel registers ..................................................................................................677

25.6.5.1 Fault Control Register (FCTRL) ....................................................................677

25.6.5.2 Fault Status Register (FSTS) ..........................................................................678

25.6.5.3 Fault Filter Register (FFILT) .........................................................................679

25.6.5.4 Input filter considerations ..............................................................................679

25.7 Functional description ...................................................................................................................681

25.7.1 Center-aligned PWMs ..................................................................................................681

25.7.2 Edge-aligned PWMs .....................................................................................................682

25.7.3 Phase-shifted PWMs ....................................................................................................682

25.7.4 Double switching PWMs ..............................................................................................684

25.7.5 ADC triggering .............................................................................................................685

25.7.6 Synchronous switching of multiple outputs .................................................................687

25.8 Functional details ..........................................................................................................................688

25.8.1 PWM clocking ..............................................................................................................688

25.8.2 Register reload logic .....................................................................................................689

25.8.3 Counter synchronization ...............................................................................................690

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26 Freescale Semiconductor

25.8.4 PWM generation ...........................................................................................................691

25.8.5 Output compare capabilities .........................................................................................692

25.8.6 Force out logic ..............................................................................................................692

25.8.7 Independent or complementary channel operation .......................................................694

25.8.8 Deadtime insertion logic ...............................................................................................695

25.8.9 Top/bottom correction ..................................................................................................696

25.8.10 Manual correction .........................................................................................................698

25.8.11 Output logic ..................................................................................................................699

25.8.12 Fault protection .............................................................................................................700

25.8.13 Fault pin filter ...............................................................................................................701

25.8.14 Automatic fault clearing ...............................................................................................702

25.8.15 Manual fault clearing ....................................................................................................702

25.8.16 Fault testing ..................................................................................................................703

25.9 PWM generator loading ................................................................................................................703

25.9.1 Load enable ..................................................................................................................703

25.9.2 Load frequency .............................................................................................................704

25.9.3 Reload flag ....................................................................................................................705

25.9.4 Reload errors ................................................................................................................705

25.9.5 Initialization ..................................................................................................................705

25.10 Clocks ............................................................................................................................................706

25.11 Interrupts .......................................................................................................................................706

25.12 DMA ..............................................................................................................................................706

Chapter 26

eTimer

26.1 Introduction ...................................................................................................................................709

26.2 Features .........................................................................................................................................709

26.3 Module block diagram ..................................................................................................................711

26.4 Channel block diagram ..................................................................................................................712

26.5 External signal descriptions ..........................................................................................................712

26.5.1 ETC[5:0]—eTimer input/outputs .................................................................................712

26.6 Memory map and registers ............................................................................................................712

26.6.1 Overview ......................................................................................................................712

26.6.2 Timer channel registers ................................................................................................716

26.6.2.1 Compare register 1 (COMP1) ........................................................................716

26.6.2.2 Compare register 2 (COMP2) ........................................................................717

26.6.2.3 Capture register 1 (CAPT1) ...........................................................................717

26.6.2.4 Capture register 2 (CAPT2) ...........................................................................718

26.6.2.5 Load register (LOAD) ....................................................................................718

26.6.2.6 Hold register (HOLD) ....................................................................................719

26.6.2.7 Counter register (CNTR) ...............................................................................719

26.6.2.8 Control register 1 (CTRL1) ............................................................................720

26.6.2.9 Control register 2 (CTRL2) ............................................................................722

26.6.2.10 Control register 3 (CTRL3) ............................................................................724

26.6.2.11 Status register (STS) ......................................................................................725

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26.6.2.12 Interrupt and DMA enable register (INTDMA) ............................................726

26.6.2.13 Comparator Load register 1 (CMPLD1) ........................................................727

26.6.2.14 Comparator Load register 2 (CMPLD2) ........................................................728

26.6.2.15 Compare and Capture Control register (CCCTRL) .......................................728

26.6.2.16 Input Filter Register (FILT) ...........................................................................730

26.6.2.17 Input filter considerations ..............................................................................731

26.6.3 Watchdog timer registers ..............................................................................................731

26.6.3.1 Watchdog Time-Out registers (WDTOL and WDTOH) ................................731

26.6.4 Configuration registers .................................................................................................732

26.6.4.1 Channel Enable register (ENBL) ...................................................................732

26.6.4.2 DMA Request Select registers (DREQ0, DREQ1) ........................................732

26.7 Functional description ...................................................................................................................733

26.7.1 General .........................................................................................................................733

26.7.2 Counting modes ............................................................................................................734

26.7.2.1 STOP mode ....................................................................................................734

26.7.2.2 COUNT mode ................................................................................................734

26.7.2.3 EDGE-COUNT mode ....................................................................................735

26.7.2.4 GATED-COUNT mode ..................................................................................735

26.7.2.5 QUADRATURE-COUNT mode ....................................................................735

26.7.2.6 SIGNED-COUNT mode ................................................................................735

26.7.2.7 TRIGGERED-COUNT mode ........................................................................735

26.7.2.8 ONE-SHOT mode ..........................................................................................736

26.7.2.9 CASCADE-COUNT mode ............................................................................736

26.7.2.10 PULSE-OUTPUT mode ................................................................................737

26.7.2.11 FIXED-FREQUENCY PWM mode ..............................................................737

26.7.2.12 VARIABLE-FREQUENCY PWM mode ......................................................737

26.7.2.13 Usage of compare registers ............................................................................738

26.7.2.14 Usage of Compare Load registers ..................................................................738

26.7.2.15 MODULO COUNTING mode ......................................................................739

26.7.3 Other features ...............................................................................................................739

26.7.3.1 Redundant OFLAG checking .........................................................................739

26.7.3.2 Loopback checking ........................................................................................739

26.7.3.3 Input capture mode .........................................................................................739

26.7.3.4 Master/Slave mode .........................................................................................740

26.7.3.5 Watchdog timer ..............................................................................................740

26.8 Clocks ............................................................................................................................................740

26.9 Interrupts .......................................................................................................................................741

26.10 DMA ..............................................................................................................................................741

Chapter 27

Functional Safety

27.1 Introduction ...................................................................................................................................743

27.2 Register protection module ...........................................................................................................743

27.2.1 Overview ......................................................................................................................743

27.2.2 Features .........................................................................................................................743

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27.2.3 Modes of operation .......................................................................................................744

27.2.4 External signal description ...........................................................................................744

27.2.5 Memory map and registers description ........................................................................744

27.2.5.1 Register protection memory map ...................................................................745

27.2.5.2 Registers description ......................................................................................746

27.2.6 Functional description ..................................................................................................748

27.2.6.1 General ...........................................................................................................748

27.2.6.2 Change lock settings ......................................................................................748

27.2.6.3 Access errors ..................................................................................................751

27.2.7 Reset .............................................................................................................................752

27.3 Software Watchdog Timer (SWT) .................................................................................................752

27.3.1 Overview ......................................................................................................................752

27.3.2 Features .........................................................................................................................752

27.3.3 Modes of operation .......................................................................................................752

27.3.4 External signal description ...........................................................................................753

27.3.5 SWT memory map and registers description ...............................................................753

27.3.5.1 SWT Control Register (SWT_CR) ................................................................754

27.3.5.2 SWT Interrupt Register (SWT_IR) ................................................................755

27.3.5.3 SWT Time-Out register (SWT_TO) ..............................................................756

27.3.5.4 SWT Window Register (SWT_WN) ..............................................................756

27.3.5.5 SWT Service Register (SWT_SR) .................................................................757

27.3.5.6 SWT Counter Output register (SWT_CO) .....................................................757

27.3.5.7 SWT Service Key Register (SWT_SK) .........................................................758

27.3.6 Functional description ..................................................................................................758

Chapter 28

Fault Collection Unit (FCU)

28.1 Introduction ...................................................................................................................................761

28.1.1 Overview ......................................................................................................................761

28.1.1.1 General description ........................................................................................761

28.1.2 Features .........................................................................................................................764

28.1.3 Modes of operation .......................................................................................................764

28.1.3.1 Normal mode ..................................................................................................764

28.1.3.2 Test mode .......................................................................................................764

28.2 Memory map and register definition .............................................................................................764

28.2.1 Memory map ................................................................................................................765

28.2.2 Register summary .........................................................................................................765

28.2.3 Register descriptions ....................................................................................................767

28.2.3.1 Module Configuration Register (FCU_MCR) ...............................................767

28.2.3.2 Fault Flag Register (FCU_FFR) ....................................................................768

28.2.3.3 Frozen Fault Flag Register (FCU_FFFR) ......................................................770

28.2.3.4 Fake Fault Generation Register (FCU_FFGR) ..............................................771

28.2.3.5 Fault Enable Register (FCU_FER) ................................................................771

28.2.3.6 Key Register (FCU_KR) ................................................................................772

28.2.3.7 Timeout Register (FCU_TR) .........................................................................773

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28.2.3.8 Timeout Enable Register (FCU_TER) ...........................................................773

28.2.3.9 Module State Register (FCU_MSR) ..............................................................774

28.2.3.10 Microcontroller State Register (FCU_MCSR) ...............................................774

28.2.3.11 Frozen MC State Register (FCU_FMCSR) ...................................................776

28.3 Functional description ...................................................................................................................777

28.3.1 State machine ................................................................................................................778

28.3.2 Output generation protocol ...........................................................................................779

28.3.2.1 Dual-rail protocol ...........................................................................................779

28.3.2.2 Time switching protocol ................................................................................780

28.3.2.3 Bi-Stable protocol ..........................................................................................781

Chapter 29

Wakeup Unit (WKPU)

29.1 Overview .......................................................................................................................................783

29.2 Features .........................................................................................................................................783

29.3 External signal description ............................................................................................................783

29.4 Memory map and registers description .........................................................................................783

29.4.1 Memory map ................................................................................................................783

29.4.2 Registers description ....................................................................................................784

29.4.2.1 NMI Status Flag Register (NSR) ...................................................................784

29.4.2.2 NMI Configuration Register (NCR) ..............................................................784

29.5 Functional description ...................................................................................................................785

29.5.1 General .........................................................................................................................785

29.5.2 Non-Maskable Interrupts ..............................................................................................786

29.5.2.1 NMI management ..........................................................................................786

Chapter 30

Periodic Interrupt Timer (PIT)

30.1 Introduction ...................................................................................................................................789

30.1.1 Overview ......................................................................................................................789

30.1.2 Features .........................................................................................................................789

30.2 Signal description ..........................................................................................................................790

30.3 Memory map and registers description .........................................................................................790

30.3.1 Memory map ................................................................................................................790

30.3.2 Registers description ....................................................................................................791

30.3.2.1 PIT Module Control Register (PITMCR) ......................................................791

30.3.2.2 Timer Load Value Register n (LDVALn) .......................................................792

30.3.2.3 Current Timer Value Register n (CVALn) .....................................................792

30.3.2.4 Timer Control Register n (TCTRLn) .............................................................793

30.3.2.5 Timer Flag Register n (TFLGn) .....................................................................794

30.4 Functional description ...................................................................................................................794

30.4.1 General .........................................................................................................................794

30.4.1.1 Timers ............................................................................................................795

30.4.1.2 Debug mode ...................................................................................................796

30.4.2 Interrupts .......................................................................................................................796

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30 Freescale Semiconductor

30.5 Initialization and application information .....................................................................................796

30.5.1 Example configuration .................................................................................................796

Chapter 31

System Timer Module (STM)

31.1 Overview .......................................................................................................................................799

31.2 Features .........................................................................................................................................799

31.3 Modes of operation ........................................................................................................................799

31.4 External signal description ............................................................................................................799

31.5 Memory map and registers description .........................................................................................799

31.5.1 Memory map ................................................................................................................799

31.5.2 Registers description ....................................................................................................800

31.5.2.1 STM Control Register (STM_CR) .................................................................800

31.5.2.2 STM Count Register (STM_CNT) ................................................................801

31.5.2.3 STM Channel Control Register (STM_CCRn) ..............................................802

31.5.2.4 STM Channel Interrupt Register (STM_CIRn) .............................................802

31.5.2.5 STM Channel Compare Register (STM_CMPn) ...........................................803

31.6 Functional description ...................................................................................................................804

Chapter 32

Cyclic Redundancy Check (CRC)

32.1 Introduction ...................................................................................................................................805

32.1.1 Glossary ........................................................................................................................805

32.2 Main features .................................................................................................................................805

32.2.1 Standard features ..........................................................................................................805

32.3 Block diagram ...............................................................................................................................805

32.3.1 IPS bus interface ...........................................................................................................806

32.4 Functional description ...................................................................................................................806

32.5 Memory map and registers description .........................................................................................808

32.5.1 CRC Configuration Register (CRC_CFG) ...................................................................809

32.5.2 CRC Input Register (CRC_INP) ..................................................................................810

32.5.3 CRC Current Status Register (CRC_CSTAT) ..............................................................810

32.5.4 CRC Output Register (CRC_OUTP) ............................................................................811

32.6 Use cases and limitations ..............................................................................................................811

Chapter 33

Boot Assist Module (BAM)

33.1 Overview .......................................................................................................................................817

33.2 Features .........................................................................................................................................817

33.3 Boot modes ....................................................................................................................................817

33.4 Memory map .................................................................................................................................817

33.5 Functional description ...................................................................................................................818

33.5.1 Entering boot modes .....................................................................................................818

33.5.2 MPC5602P boot pins ....................................................................................................819

33.5.3 Reset Configuration Half Word (RCHW) ....................................................................820

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33.5.4 Single chip boot mode ..................................................................................................821

33.5.4.1 Boot and alternate boot ..................................................................................822

33.5.5 Boot through BAM .......................................................................................................822

33.5.5.1 Executing BAM .............................................................................................822

33.5.5.2 BAM software flow .......................................................................................823

33.5.5.3 BAM resources ..............................................................................................824

33.5.5.4 Download and execute the new code .............................................................825

33.5.5.5 Download 64-bit password and password check ...........................................825

33.5.5.6 Download start address, VLE bit and code size .............................................827

33.5.5.7 Download data ...............................................................................................828

33.5.5.8 Execute code ..................................................................................................828

33.5.6 Boot from UART—autobaud disabled .........................................................................828

33.5.6.1 Configuration .................................................................................................828

33.5.6.2 UART boot mode download protocol ............................................................829

33.5.7 Bootstrap with FlexCAN—autobaud disabled .............................................................829

33.5.7.1 Configuration .................................................................................................829

33.6 FlexCAN boot mode download protocol ......................................................................................830

33.6.1 Autobaud feature ..........................................................................................................830

33.6.1.1 Configuration .................................................................................................831

33.6.1.2 Boot from UART with autobaud enabled ......................................................833

33.6.1.3 Boot from FlexCAN with autobaud enabled .................................................837

33.6.2 Interrupt ........................................................................................................................842

33.7 Censorship .....................................................................................................................................842

33.7.0.1 Censorship password registers (NVPWD0 and NVPWD1) ..........................842

33.7.0.2 Nonvolatile System Censorship Control registers (NVSCI0 and NVSCI1) ..843

33.7.0.3 Censorship configuration ...............................................................................843

Chapter 34

Voltage Regulators and Power Supplies

34.1 Voltage regulator ...........................................................................................................................849

34.1.1 High Power or Main Regulator (HPREG) ....................................................................849

34.1.2 Low Voltage Detectors (LVD) and Power On Reset (POR) .........................................849

34.1.3 VREG digital interface .................................................................................................850

34.1.4 Registers Description ....................................................................................................851

34.1.4.1 Voltage Regulator Control Register (VREG_CTL) .......................................851

34.1.4.2 Voltage Regulator Status register (VREG_STATUS) ....................................852

34.2 Power supply strategy ...................................................................................................................852

Chapter 35

IEEE 1149.1 Test Access Port Controller (JTAGC)

35.1 Introduction ...................................................................................................................................855

35.2 Block diagram ...............................................................................................................................855

35.3 Overview .......................................................................................................................................855

35.4 Features .........................................................................................................................................856

35.5 Modes of operation ........................................................................................................................856

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35.5.1 Reset .............................................................................................................................856

35.5.2 IEEE 1149.1-2001 defined test modes .........................................................................856

35.5.2.1 Bypass mode ..................................................................................................857

35.5.2.2 TAP sharing mode ..........................................................................................857

35.6 External signal description ............................................................................................................857

35.7 Memory map and registers description .........................................................................................857

35.7.1 Instruction register ........................................................................................................858

35.7.2 Bypass register ..............................................................................................................858

35.7.3 Device identification register .......................................................................................858

35.7.4 Boundary scan register .................................................................................................859

35.8 Functional description ...................................................................................................................859

35.8.1 JTAGC reset configuration ...........................................................................................859

35.8.2 IEEE 1149.1-2001 (JTAG) Test Access Port (TAP) .....................................................859

35.8.3 TAP controller state machine .......................................................................................860

35.8.3.1 Selecting an IEEE 1149.1-2001 register ........................................................862

35.8.4 JTAGC instructions ......................................................................................................862

35.8.4.1 BYPASS instruction .......................................................................................863

35.8.4.2 ACCESS_AUX_TAP_x instructions .............................................................863

35.8.4.3 CLAMP instruction ........................................................................................863

35.8.4.4 EXTEST — external test instruction .............................................................863

35.8.4.5 HIGHZ instruction .........................................................................................864

35.8.4.6 IDCODE instruction ......................................................................................864

35.8.4.7 SAMPLE instruction ......................................................................................864

35.8.4.8 SAMPLE/PRELOAD instruction ..................................................................864

35.8.5 Boundary scan ..............................................................................................................864

35.9 e200z0 OnCE controller ................................................................................................................865

35.9.1 e200z0 OnCE controller block diagram .......................................................................865

35.9.2 e200z0 OnCE controller functional description ...........................................................865

35.9.2.1 Enabling the TAP controller ...........................................................................865

35.9.3 e200z0 OnCE controller registers description ..............................................................866

35.9.3.1 OnCE Command register (OCMD) ...............................................................866

35.10 Initialization/Application Information ..........................................................................................867

Chapter 36

Nexus Development Interface (NDI)

36.1 Introduction ...................................................................................................................................869

36.2 Information specific to this device ................................................................................................869

36.2.1 Features not supported ..................................................................................................869

36.3 Block diagram ...............................................................................................................................870

36.4 Features .........................................................................................................................................870

36.5 Modes of operation ........................................................................................................................871

36.5.1 Nexus reset ...................................................................................................................871

36.5.2 NDI modes ....................................................................................................................871

36.5.2.1 Censored mode ...............................................................................................871

36.5.2.2 Stop mode .......................................................................................................871

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 33

36.6 External signal description ............................................................................................................871

36.7 Memory map and registers description .........................................................................................872

36.8 Interrupts and Exceptions ..............................................................................................................872

36.9 Debug support overview ...............................................................................................................873

36.9.1 Software Debug Facilities ............................................................................................873

36.9.1.1 Power Architecture technology compatibility ...............................................873

36.9.2 Additional Debug Facilities ..........................................................................................874

36.9.3 Hardware Debug Facilities ...........................................................................................874

36.9.4 Sharing Debug Resources by Software/Hardware .......................................................874

36.9.4.1 Simultaneous Hardware and Software Debug Event Handing ......................875

36.10 Software Debug Events and Exceptions .......................................................................................876

36.10.1 Instruction Address Compare Event .............................................................................877

36.10.2 Data Address Compare Event ......................................................................................878

36.10.2.1 Data Address Compare Event Status Updates ...............................................879

36.10.3 Linked Instruction Address and Data Address Compare Event ...................................881

36.10.4 Trap Debug Event .........................................................................................................881

36.10.5 Branch Taken Debug Event ..........................................................................................881

36.10.6 Instruction Complete Debug Event ..............................................................................881

36.10.7 Interrupt Taken Debug Event .......................................................................................882

36.10.8 Critical Interrupt Taken Debug Event ..........................................................................882

36.10.9 Return Debug Event .....................................................................................................882

36.10.10 Critical Return Debug Event ........................................................................................883

36.10.11 External Debug Event ...................................................................................................883

36.10.12 Unconditional Debug Event .........................................................................................883

36.11 Debug Registers ............................................................................................................................883

36.11.1 Debug Address and Value Registers .............................................................................884

36.11.2 Debug Control and Status Registers .............................................................................885

36.11.2.1 Debug Control Register 0 (DBCR0) ..............................................................885

36.11.2.2 Debug Control Register 1 (DBCR1) ..............................................................887

36.11.2.3 Debug Control Register 2 (DBCR2) ..............................................................890

36.11.2.4 Debug Control Register 4 (DBCR4) ..............................................................894

36.11.2.5 Debug Status Register (DBSR) ......................................................................895

36.11.3 Debug External Resource Control Register (DBERC0) ..............................................897

36.12 External Debug Support ................................................................................................................903

36.12.1 OnCE Introduction .......................................................................................................904

36.12.2 JTAG/OnCE Pins ..........................................................................................................907

36.12.3 OnCE Internal Interface Signals ...................................................................................907

36.12.3.1 CPU Debug Request (dbg_dbgrq) .................................................................907

36.12.3.2 CPU Debug Acknowledge (cpu_dbgack) ......................................................908

36.12.3.3 CPU Address, Attributes ................................................................................908

36.12.3.4 CPU Data .......................................................................................................908

36.12.4 OnCE Interface Signals ................................................................................................908

36.12.4.1 OnCE Enable (jd_en_once) ...........................................................................908

36.12.4.2 OnCE Debug Request/Event (jd_de_b, jd_de_en) ........................................908

36.12.4.3 e200z0h OnCE Debug Output (jd_debug_b) .................................................909

MPC5602P Microcontroller Reference Manual, Rev. 4

34 Freescale Semiconductor

36.12.4.4 e200z0h CPU Clock On Input (jd_mclk_on) .................................................909

36.12.4.5 Watchpoint Events (jd_watchpt[0:5]) ............................................................909

36.12.5 e200z0h OnCE Controller and Serial Interface ............................................................909

36.12.5.1 e200z0h OnCE Status Register ......................................................................910

36.12.5.2 e200z0h OnCE Command Register (OCMD) ...............................................911

36.12.5.3 e200z0h OnCE Control Register (OCR) ........................................................915

36.12.6 Access to Debug Resources ..........................................................................................917

36.12.7 Methods of Entering Debug Mode ...............................................................................919

36.12.7.1 External Debug Request During RESET .......................................................919

36.12.7.2 Debug Request During RESET ......................................................................919

36.12.7.3 Debug Request During Normal Activity .......................................................919

36.12.7.4 Debug Request During Waiting, Halted or Stopped State .............................919

36.12.7.5 Software Request During Normal Activity ....................................................920

36.12.8 CPU Status and Control Scan Chain Register (CPUSCR) ...........................................920

36.12.8.1 Instruction Register (IR) ................................................................................921

36.12.8.2 Control State Register (CTL) .........................................................................922

36.12.8.3 Program Counter Register (PC) .....................................................................925

36.12.8.4 Write-Back Bus Register (WBBRlow, WBBRhigh) ......................................925

36.12.8.5 Machine State Register (MSR) ......................................................................926

36.13 Watchpoint Support .......................................................................................................................926

36.14 Basic Steps for Enabling, Using, and Exiting External Debug Mode ...........................................927

36.15 Functional description ...................................................................................................................929

36.15.1 Enabling Nexus clients for TAP access ........................................................................929

36.15.2 Debug mode control .....................................................................................................929

Chapter 37

Document Revision History

Appendix A

Registers Under Protection

Chapter 1 Introduction

MPC5602P Microcontroller Ref e ren ce Man u al, Rev. 4

Freescale Semiconductor 35

Chapter 1

Introduction

1.1 The MPC5602P microcontroller family

The Qorivva MPC5602P microcontroller, a SafeAssure solution, is built on the Power Architecture®

platform. The Power Architecture based 32-bit microcontrollers represent the latest achievement in

integrated automotive application controllers. This device family integrates the most advanced and

up-to-date motor control design features.

The safety features included in MPC5602P (such us fault collection unit, safety port or flash memory and

SRAM with ECC) support the design of system applications where safety is a requirement.

The MPC5602P addresses low-end chassis applications and implements the Harvard bus interface version

of the e200z0h core.

The e200 processor family is a set of CPU cores that implement low-cost versions of the Power

Architecture Book E architecture. The e200 processors are designed for deeply embedded control

applications that require low cost solutions rather than maximum performance. The e200z0h processor

integrates an integer execution unit, branch control unit, instruction fetch and load/store units, and a

multi-ported register file capable to sustaining three read and two write operations per clock. Most integer

instructions execute in a single clock cycle. Branch tar get prefetching is performed by branch unit to allow

single-cycle branches in some cases. The e200z0h core is a single-issue, 32-bit Power Architecture

technology VLE only design with 32-bit general purpose registers (GPRs). All arithmetic instructions that

execute in the core operate on data in the general purpose registers (GPRs). Instead of the base Power

Architecture instruction set support, the e200z0h core only implements the VLE (variable length

encoding) APU, providing improved code density.

The MPC5602P has a single level of memory hierarchy consisting of 20 KB on-chip SRAM and 320 KB

(256 KB program + 64 KB data) of on-chip flash memory . Both the SRAM and the flash memory can hold

instructions and data.

The timer functions of the MPC5602P are performed by the eTimer Modular Timer System and

FlexPWM. The eTimer module implements enhanced timer features (six channels) including dedicated

motor control quadrature decode functionality and DMA support; the FlexPWM module consists of four

submodules controlling a pair of PWM channels each: three submodules may be used to control the three

phases of a motor and the additional pair to support DC-DC converter width modulation control.

Off-chip communication is performed by a suite of serial protocols including CANs, enhanced SPIs

(DSPI), and SCIs (LINFlex).

The System Integration Unit Lite (SIUL) performs several chip-wide configuration functions. Pad

configuration and general-purpose input/output (GPIO) are controlled from the SIUL. External interrupts

and reset control are also found in the SIUL. The internal multiplexer sub-block (IOMUX) provides

multiplexing of daisy chaining the DSPIs and external interrupt signal.

As the MPC5602P is built on a wider legacy of Power Architecture-based devices, when applicable and

possible, reuse or enhancement of existing IP, design and concepts is adopted.

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MPC5602P Microcontroller Reference Manual, Rev. 4

36 Freescale Semiconductor

1.2 Target applications

The MPC5602P belongs to an expanding range of automotive-focused products designed to address and

target the following chassis and safety market segments:

• Electric hydraulic power steering (EHPS)

• Lower end of electric power steering (EPS)

• Airbag applications

• Anti-lock braking systems (ABS)

• Motor control applications

EHPS and EPS systems typically feature sophisticated and advanced electrical motor control periphery

with special enhancements in the area of pulse width modulation, highly flexible timers, and functional

safety.

1.2.1 Application examples

1.2.1.1 Electric power steering

Figure 1-1 outlines a typical electric power steering application built around the MPC5602P

microcontroller.

Chapter 1 Introduction

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 37

Figure 1-1. Electric power steering application

1.2.1.2 Airbag

Figure 1-2 outlines a typical airbag application built around the MPC5602P microcontroller.

Position Sensor

Gearbox

Sensor

Load

Position Sensor

Physical Layer Torque

Relay

Relay Driver

Signal

Conditioning

Circuitry

Driver

PWM

3-phase Low Voltage Power Stage PMSM

Signal

Conditioning

Circuitry

Driver

Reverse Bat

Protection

Fast ADC

<1 µs, 10-bit Timer

Safety Port

Core

FlexCAN

Faults

Motor

Control

PWM

10 ns res

DSPI

MPC5602P

Vcc

Vanalog

Vref

Vcc

Vanalog

Vref

System

Basis

Chip

Windowed

Watchdog

Hi-speed CAN

Physical Layer CAN

Complex

Hardware

Watchdog

Input

Modules

Output Drivers

(Valves, Pump) Sensors

Safety Relay

U DC Bus

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MPC5602P Microcontroller Reference Manual, Rev. 4

38 Freescale Semiconductor

Figure 1-2. Airbag application

1.3 Features

Table 1-1 provides a summary of different members of the MPC5602P family and their features to enable

a comparison among the family members and an understanding of the range of functionality offered within

this family.

Table 1-1. MPC5602P device comparison

Feature MPC5601P MPC5602P

Code flash memory (with ECC) 192 KB 256 KB

Data flash memory / EE option (with ECC) 64 KB (optional feature)

SRAM (with ECC) 12 KB 20 KB

Processor core 32-bit e200z0h

Instruction set VLE (variable length encoding)

CPU performance 0–64 MHz

FMPLL (frequency-modulated phase-locked loop)

module

INTC (interrupt controller) channels 120

PIT (periodic interrupt timer) 1 (with four 32-bit timers)

eDMA (enhanced direct memory access) channels 16

FlexCAN (controller area network) 11,2 21,2

SPI

Physical

Interface

Physical

Interface

Physical

Interface

Physical

Interface

Satellite I/F

Buckle I/F

VIGN

Safing Unit

Power Supply Control Chain

DSPI

ADC

FlexCAN

LINFlex

DSPI DSPI

X/Y - accel.

CAN Physical

Layer

LIN Physical

Layer

Body network (dashboard)

Occupant detection

4-ch Squib

Driver

VBOOST

Squib 1

Squib 2

Squib 3

Squib 4

Custom

Device

VBOOST

VBUCK

VLOGIC

VIO

MPC5602P

Chapter 1 Introduction

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 39

Figure 1.4 shows a top-level block diagram of the MPC5602P microcontroller.

Safety port Yes (via FlexCAN module) Yes (via second FlexCAN

module)

FCU (fault collection unit) Yes

CTU (cross triggering unit) No Yes

eTimer 1 (16-bit, 6 channels)

FlexPWM (pulse-width modulation) channels No 8

(capture capability not

supported)

Analog-to-digital converter (ADC) 1 (10-bit, 16 channels)

LINFlex 1

(1 × Master/Slave)

(1 × Master/Slave,

1 × Master only)

DSPI (deserial serial peripheral interface) 1 3

CRC (cyclic redundancy check) unit Yes

Junction temperature sensor No

JTAG controller Yes

Nexus port controller (NPC) Yes (Nexus Class 1)

Supply Digital power supply 3.3 V or 5 V single supply with external transistor

Analog power supply 3.3 V or 5 V

Internal RC oscillator 16 MHz

External crystal oscillator 4–40 MHz

Packages 64 LQFP

100 LQFP

Temperature Standard ambient temperature –40 to 125 °C

1Each FlexCAN module has 32 message buffers.

2One FlexCAN module can act as a safety port with a bit rate as high as 8 Mbit/s at 64 MHz.

Table 1-1. MPC5602P device comparison (continued)

Feature MPC5601P MPC5602P

Chapter 1 Introduction

MPC5602P Microcontroller Reference Manual, Rev. 4

40 Freescale Semiconductor

Figure 1-3. MPC5602P block diagram

SRAM

(with ECC)

Slave SlaveSlave

Code Flash

(with ECC)

Data Flash

(with ECC)

PIT

STM

SWT

MC_RGM

MC_CGM

MC_ME

BAM

SIUL

WKPU

CRC

ECSM

e200z0 Core

32-bit

general

purpose

registers

Special

purpose

registers

Integer

execution

unit

Exception

handler

Variable

length

encoded

instructions

Instruction

unit

Load/store

unit

Branch

prediction

unit

JTAG

1.2 V regulator

control

XOSC

16 MHz

RC oscillator

FMPLL_0

(System)

Nexus port

controller

Interrupt

controller

eDMA

16 channels

Master Master

Instruction

32-bit

Master

Data

32-bit

Crossbar switch (XBAR, AMBA 2.0 v6 AHB)

Peripheral bridge

FCU

Legend:

ADC Analog-to-digital converter

BAM Boot assist module

CRC Cyclic redundancy check

CTU Cross triggering unit

DSPI Deserial serial peripheral interface

ECSM Error correction status module

eDMA Enhanced direct memory access

eTimer Enhanced timer

FCU Fault collection unit

Flash Flash memory

FlexCAN Controller area network

FlexPWM Flexible pulse width modulation

FMPLL Frequency-modulated phase-locked loop

INTC Interrupt controller

JTAG JTAG controller

LINFlex Serial communication interface (LIN support)

MC_CGM Clock generation module

MC_ME Mode entry module

MC_PCU Power control unit

MC_RGM Reset generation module

PIT Periodic interrupt timer

SIUL System Integration unit Lite

SRAM Static random-access memory

SSCM System status and configuration module

STM System timer module

SWT Software watchdog timer

WKPU Wakeup unit

XOSC External oscillator

XBAR Crossbar switch

External ballast

Nexus 1

eDMA

16 channels

FlexPWM

CTU

3×

eTimer

DSPI

2×

FlexCAN

LINFlex

Safety port

ADC

(6 ch)

SSCM

(10 bit, 16 ch)

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 41

1.4 Critical performance parameters

• Fully static operation, 0–64 MHz

• –40 °C to 150 °C junction temperature

• Low power design

— Less than 450 mW power dissipation

— Halt and STOP mode available for power reduction

— Resuming from Halt/STOP mode can be initiated via external pin

• Fabricated in 90 nm process

• 1.2 V nominal internal logic

• Nexus pins operate at VDDIO (no dedicated power supply)

— Unused pins configurable as GPIO

• 10-bit ADC conversion time < 1 µs

• Internal voltage regulator (VREG) with external ballast transistor enables control with a single

input rail

— 3.0 V–3.6 V or 4.5 V–5.5 V input supply voltage

• Configurable pins

— Selectable slew rate for EMI reduction

— Selectable pull-up, pull-down, or no pull on all pins

— Selectable open drain

— Support for 3.3 V or 5 V I/O levels

1.5 Chip-level features

On-chip modules available within the family include the following features:

• Up to 64 MHz, single issue, 32-bit CPU core complex (e200z0h)

— Compliant with Power Architecture embedded category

— Variable Length Encoding (VLE)

• Memory organization

— Up to 256 KB on-chip code flash memory with ECC and erase/program controller

— Optional: additional 64 (4 × 16) KB on-chip data flash memory with ECC for EEPROM

emulation

— Up to 20 KB on-chip SRAM with ECC

• Fail-safe protection

— Programmable watchdog timer

— Non-maskable interrupt

— Fault collection unit

• Nexus Class 1 interface

• Interrupts and events

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MPC5602P Microcontroller Reference Manual, Rev. 4

42 Freescale Semiconductor

— 16-channel eDMA controller

— 16 priority level controller

— Up to 25 external interrupts

— PIT implements four 32-bit timers

— 120 interrupts are routed via INTC

• General purpose I/Os

— Individually programmable as input, output or special function

— 37 on 64 LQFP

— 64 on 100 LQFP

• 1 general purpose eTimer unit

— 6 timers each with up/down capabilities

— 16-bit resolution, cascadeable counters

— Quadrature decode with rotation direction flag

— Double buffer input capture and output compare

• Communications interfaces

— Up to 2 LINFlex modules (1× Master/Slave, 1× Master only)

— Up to 3 DSPI channels with automatic chip select generation (up to 8/4/4 chip selects)

— 1 FlexCAN interface (2.0B Active) with 32 message buffers

— 1 safety port based on FlexCAN with 32 message buffers and up to 8 Mbit/s at 64 MHz

capability usable as second CAN when not used as safety port

• One 10-bit analog-to-digital converter (ADC)

— Up to 16 input channels (16 ch on 100 LQFP and 12 ch on 64 LQFP)

— Conversion time < 1 µs including sampling time at full precision

— Programmable Cross Triggering Unit (CTU)

— 4 analog watchdogs with interrupt capability

• On-chip CAN/UART bootstrap loader with Boot Assist Module (BAM)

• 1 FlexPWM unit

— 8 complementary or independent outputs with ADC synchronization signals

— Polarity control, reload unit

— Integrated configurable dead time unit and inverter fault input pins

— 16-bit resolution

— Lockable configuration

• Clock generation

— 4–40 MHz main oscillator

— 16 MHz internal RC oscillator

— Software-controlled FMPLL capable of up to 64 MHz

• Voltage supply

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 43

— 3.3 V or 5 V supply for I/Os and ADC

— On-chip single supply voltage regulator with external ballast transistor

• Operating temperature ranges: –40 to 125 °C or –40 to 105 °C

1.6 Module features

1.6.1 High performance e200z0 core processor

The e200z0 Power Architecture core provides the following features:

• High performance e200z0 core processor for managing peripherals and interrupts

• Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU

• Harvard architecture

• Variable length encoding (VLE), allowing mixed 16- and 32-bit instructions

— Results in smaller code size footprint

— Minimizes impact on performance

• Branch processing acceleration using lookahead instruction buffer

• Load/store unit

— 1-cycle load latency

— Misaligned access support

— No load-to-use pipeline bubbles

• Thirty-two 32-bit general purpose registers (GPRs)

• Separate instruction bus and load/store bus Harvard architecture

• Hardware vectored interrupt support

• Reservation instructions for implementing read-modify-write constructs

• Long cycle time instructions, except for guarded loads, do not increase interrupt latency

• Extensive system development support through Nexus debug port

• Non-maskable interrupt support

1.6.2 Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between three master ports and

three slave ports. The crossbar supports a 32-bit address bus width and a 32-bit data bus width.

The crossbar allows for two concurrent transactions to occur from any master port to any slave port; but

one of those transfers must be an instruction fetch from internal flash memory. If a slave port is

simultaneously requested by more than one master port, arbitration logic will select the higher priority

master and grant it ownership of the slave port. All other masters requesting that slave port will be stalled

until the higher priority master completes its transactions. Requesting masters will be treated with equal

priority and will be granted access a slave port in round-robin fashion, based upon the ID of the last master

to be granted access.

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MPC5602P Microcontroller Reference Manual, Rev. 4

44 Freescale Semiconductor

The crossbar provides the following features:

• 3 master ports:

— e200z0 core complex instruction port

— e200z0 core complex Load/Store Data port

—eDMA

• 3 slave ports:

— Flash memory (Code and Data)

—SRAM

— Peripheral bridge

• 32-bit internal address, 32-bit internal data paths

• Fixed Priority Arbitration based on Port Master

• Temporary dynamic priority elevation of masters

1.6.3 Enhanced direct memory access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module capable of

performing complex data movements via 16 programmable channels, with minimal intervention from the

host processor. The hardware micro architecture includes a DMA engine which performs source and

destination address calculations, and the actual data movement operations, along with an SRAM-based

memory containing the transfer control descriptors (TCD) for the channels.

The eDMA module provides the following features:

• 16 channels support independent 8-, 16- or 32-bit single value or block transfers

• Supports variable-sized queues and circular queues

• Source and destination address registers are independently configured to either post-increment or

to remain constant

• Each transfer is initiated by a peripheral, CPU, or eDMA channel request

• Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single

value or block transfer

• DMA transfers possible between system memories, DSPIs, ADC, FlexPWM, eTimer and CTU

• Programmable DMA channel multiplexer allows assignment of any DMA source to any available

DMA channel with as many as 30 request sources

• eDMA abort operation through software

1.6.4 Flash memory

The MPC5602P provides 320 KB of programmable, non-volatile, flash memory. The non-volatile

memory (NVM) can be used for instruction and/or data storage. The flash memory module is interfaced

to the system bus by a dedicated flash memory controller. It supports a 32-bit data bus width at the system

bus port, and a 128-bit read data interface to flash memory. The module contains four 128-bit wide prefetch

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 45

buffers. Prefetch buffer hits allow no-wait responses. Normal flash memory array accesses are registered

and are forwarded to the system bus on the following cycle, incurring two wait-states.

The flash memory module provides the following features:

• As much as 320 KB flash memory

— 6 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 128 KB) code flash memory

— 4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash memory

— Full Read-While-Write (RWW) capability between code flash memory and data flash memory

• Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch buffers can be

configured to prefetch code or data or both)

• Typical flash memory access time: no wait-state for buffer hits, 2 wait-states for page buffer miss

at 64 MHz

• Hardware managed flash memory writes handled by 32-bit RISC Krypton engine

• Hardware and software configurable read and write access protections on a per-master basis

• Configurable access timing allowing use in a wide range of system frequencies

• Multiple-mapping support and mapping-based block access timing (up to 31 additional cycles)

allowing use for emulation of other memory types

• Software programmable block program/erase restriction control

• Erase of selected block(s)

• Read page sizes

— Code flash memory: 128 bits (4 words)

— Data flash memory: 32 bits (1 word)

• ECC with single-bit correction, double-bit detection for data integrity

— Code flash memory: 64-bit ECC

— Data flash memory: 32-bit ECC

• Embedded hardware program and erase algorithm

• Erase suspend and program abort

• Censorship protection scheme to prevent flash memory content visibility

• Hardware support for EEPROM emulation

1.6.5 Static random access memory (SRAM)

The MPC5602P SRAM module provides up to 20 KB of general-purpose memory.

ECC handling is done on a 32-bit boundary and is completely software compatible with MPC55xx family

devices containing an e200z6 core and 64-bit wide ECC.

The SRAM module provides the following features:

• Supports read/write accesses mapped to the SRAM from any master

• Up to 20 KB general purpose SRAM

• Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory

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46 Freescale Semiconductor

• Typical SRAM access time: no wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit

writes if back-to-back with a read to same memory block

1.6.6 Interrupt controller (INTC)

The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt requests,

suitable for statically scheduled hard real-time systems. The INTC handles 128 selectable-priority

interrupt sources.

For high-priority interrupt requests, the time from the assertion of the interrupt request by the peripheral

to the execution of the interrupt service routine (ISR) by the processor has been minimized. The INTC

provides a unique vector for each interrupt request source for quick determination of which ISR has to be

executed. It also provides a wide number of priorities so that lower priority ISRs do not delay the execution

of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority

of each interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC

supports the priority ceiling protocol (PCP) for coherent accesses. By providing a modifiable priority

mask, the priority can be raised temporarily so that all tasks which share the same resource can not preempt

each other.

The INTC provides the following features:

• Unique 9-bit vector for each separate interrupt source

• 8 software triggerable interrupt sources

• 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source

• Ability to modify the ISR or task priority: modifying the priority can be used to implement the

priority ceiling protocol for accessing shared resources.

• 1 external high priority interrupt (NMI) directly accessing the main core and I/O processor (IOP)

critical interrupt mechanism

1.6.7 System status and configuration module (SSCM)

The system status and configuration module (SSCM) provides central device functionality.

The SSCM includes these features:

• System configuration and status

— Memory sizes/status

— Device mode and security status

— Determine boot vector

— Search code flash for bootable sector

— DMA status

• Debug status port enable and selection

• Bus and peripheral abort enable/disable

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 47

1.6.8 System clocks and clock generation

The following list summarizes the system clock and clock generation on the MPC5602P:

• Lock detect circuitry continuously monitors lock status

• Loss of clock (LOC) detection for PLL outputs

• Programmable output clock divider (1, 2, 4, 8)

• FlexPWM module and eTimer module running at the same frequency as the e200z0h core

• Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency trimming by

user application

1.6.9 Frequency-modulated phase-locked loop (FMPLL)

The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input clock. Further,

the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication

factor, output clock divider ratio are all software configurable.

The FMPLL has the following major features:

• Input clock frequency: 4–40 MHz

• Maximum output frequency: 64 MHz

• Voltage controlled oscillator (VCO)—frequency 256–512 MHz

• Reduced frequency divider (RFD) for reduced frequency operation without forcing the FMPLL to

relock

• Frequency-modulated PLL

— Modulation enabled/disabled through software

— Triangle wave modulation

• Programmable modulation depth (±0.25% to ±4% deviation from center frequency):

programmable modulation frequency dependent on reference frequency

• Self-clocked mode (SCM) operation

1.6.10 Main oscillator

The main oscillator provides these features:

• Input frequency range: 4–40 MHz

• Crystal input mode or oscillator input mode

• PLL reference

1.6.11 Internal RC oscillator

This device has an RC ladder phase-shift oscillator. The architecture uses constant current charging of a

capacitor. The voltage at the capacitor is compared by the stable bandgap reference voltage.

The RC oscillator provides these features:

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MPC5602P Microcontroller Reference Manual, Rev. 4

48 Freescale Semiconductor

• Nominal frequency 16 MHz

• ±5% variation over voltage and temperature after process trim

• Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock

is detected by the PLL

• RC oscillator is used as the default system clock during startup

1.6.12 Periodic interrupt timer (PIT)

The PIT module implements these features:

• 4 general-purpose interrupt timers

• 32-bit counter resolution

• Clocked by system clock frequency

• Each channel usable as trigger for a DMA request

1.6.13 System timer module (STM)

The STM implements these features:

• One 32-bit up counter with 8-bit prescaler

• Four 32-bit compare channels

• Independent interrupt source for each channel

• Counter can be stopped in debug mode

1.6.14 Software watchdog timer (SWT)

The SWT has the following features:

• 32-bit time-out register to set the time-out period

• Programmable selection of window mode or regular servicing

• Programmable selection of reset or interrupt on an initial time-out

• Master access protection

• Hard and soft configuration lock bits

• Reset configuration inputs allow timer to be enabled out of reset

1.6.15 Fault collection unit (FCU)

The FCU provides an independent fault reporting mechanism even if the CPU is malfunctioning.

The FCU module has the following features:

• FCU status register reporting the device status

• Continuous monitoring of critical fault signals

• User selection of critical signals from different fault sources inside the device

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• Critical fault events trigger 2 external pins (user selected signal protocol) that can be used

externally to reset the device and/or other circuitry (for example, a safety relay)

• Faults are latched into a register

1.6.16 System integration unit – Lite (SIUL)

The MPC5602P SIUL controls MCU pad configuration, external interrupt, general purpose I/O (GPIO),

and internal peripheral multiplexing.

The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block

provides uniform and discrete input/output control of the I/O pins of the MCU.

The SIUL provides the following features:

• Centralized general purpose input output (GPIO) control of up to 49 input/output pins and 16

analog input-only pads (package dependent)

• All GPIO pins can be independently configured to support pull-up, pull-down, or no pull

• Reading and writing to GPIO supported both as individual pins and 16-bit wide ports

• All peripheral pins, except ADC channels, can be alternatively configured as both general purpose

input or output pins

• ADC channels support alternative configuration as general purpose inputs

• Direct readback of the pin value is supported on all pins through the SIUL

• Configurable digital input filter that can be applied to some general purpose input pins for noise

elimination

• Up to 4 internal functions can be multiplexed onto 1 pin

1.6.17 Boot and censorship

Different booting modes are available in the MPC5602P: booting from internal flash memory and booting

via a serial link.

The default booting scheme uses the internal flash memory (an internal pull-down resistor is used to select

this mode). Optionally, the user can boot via FlexCAN or LINFlex (using the boot assist module software).

A censorship scheme is provided to protect the content of the flash memory and offer increased security

for the entire device.

A password mechanism is designed to grant the legitimate user access to the non-volatile memory.

1.6.17.1 Boot assist module (BAM)

The BAM is a block of read-only memory that is programmed once and is identical for all MPC560xP

devices that are based on the e200z0h core. The BAM program is executed every time the device is

powered on if the alternate boot mode has been selected by the user.

The BAM provides the following features:

• Serial bootloading via FlexCAN or LINFlex

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• Ability to accept a password via the used serial communication channel to grant the legitimate user

access to the non-volatile memory

1.6.18 Error correction status module (ECSM)

The ECSM provides a myriad of miscellaneous control functions regarding program-visible information

about the platform configuration and revision levels, a reset status register, a software watchdog timer,

wakeup control for exiting sleep modes, and information on platform memory errors reported by

error-correcting codes and/or generic access error information for certain processor cores.

The Error Correction Status Module supports a number of miscellaneous control functions for the

platform. The ECSM includes these features:

• Registers for capturing information on platform memory errors if error-correcting codes (ECC) are

implemented

• For test purposes, optional registers to specify the generation of double-bit memory errors are

enabled on the MPC5602P.

The sources of the ECC errors are:

• Flash memory

•SRAM

1.6.19 Peripheral bridge (PBRIDGE)

The PBRIDGE implements the following features:

• Duplicated periphery

• Master access privilege level per peripheral (per master: read access enable; write access enable)

• Write buffering for peripherals

• Checker applied on PBRIDGE output toward periphery

• Byte endianess swap capability

1.6.20 Controller area network (FlexCAN)

The MPC5602P MCU contains one controller area network (FlexCAN) module. This module is a

communication controller implementing the CAN protocol according to Bosch Specification version 2.0B.

The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific

requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle,

cost-effectiveness and required bandwidth. The FlexCAN module contains 32 message buffers.

The FlexCAN module provides the following features:

• Full implementation of the CAN protocol specification, version 2.0B

— Standard data and remote frames

— Extended data and remote frames

— Up to 8-bytes data length

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— Programmable bit rate up to 1 Mbit/s

• 32 message buffers of up to 8-bytes data length

• Each message buffer configurable as Rx or Tx, all supporting standard and extended messages

• Programmable loop-back mode supporting self-test operation

• 3 programmable mask registers

• Programmable transmit-first scheme: lowest ID or lowest buffer number

• Time stamp based on 16-bit free-running timer

• Global network time, synchronized by a specific message

• Maskable interrupts

• Independent of the transmission medium (an external transceiver is assumed)

• High immunity to EMI

• Short latency time due to an arbitration scheme for high-priority messages

• Transmit features

— Supports configuration of multiple mailboxes to form message queues of scalable depth

— Arbitration scheme according to message ID or message buffer number

— Internal arbitration to guarantee no inner or outer priority inversion

— Transmit abort procedure and notification

• Receive features

— Individual programmable filters for each mailbox

— 8 mailboxes configurable as a 6-entry receive FIFO

— 8 programmable acceptance filters for receive FIFO

• Programmable clock source

— System clock

— Direct oscillator clock to avoid PLL jitter

1.6.21 Safety port (FlexCAN)

The MPC5602P MCU has a second CAN controller synthesized to run at high bit rates to be used as a

safety port. The CAN module of the safety port provides the following features:

• Identical to the FlexCAN module

• Bit rate up to 8 Mbit/s at 64 MHz CPU clock using direct connection between CAN modules (no

physical transceiver required)

• 32 message buffers of up to 8-bytes data length

• Can be used as a second independent CAN module

1.6.22 Serial communication interface module (LINFlex)

The LINFlex (local interconnect network flexible) on the MPC5602P features the following:

• Supports LIN Master mode (both instances), LIN Slave mode (only one instance) and UART mode

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• LIN state machine compliant to LIN1.3, 2.0 and 2.1 specifications

• Handles LIN frame transmission and reception without CPU intervention

• LIN features

— Autonomous LIN frame handling

— Message buffer to store Identifier and up to 8 data bytes

— Supports message length of up to 64 bytes

— Detection and flagging of LIN errors (sync field, delimiter, ID parity, bit framing, checksum,

and time-out)

— Classic or extended checksum calculation

— Configurable Break duration of up to 36-bit times

— Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)

— Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection

— Interrupt-driven operation with 16 interrupt sources

• LIN slave mode features:

— Autonomous LIN header handling

— Autonomous LIN response handling

— Optional discarding of irrelevant LIN responses using ID filter

• UART mode:

— Full-duplex operation

— Standard non return-to-zero (NRZ) mark/space format

— Data buffers with 4-byte receive, 4-byte transmit

— Configurable word length (8-bit or 9-bit words)

— Error detection and flagging

— Parity, Noise and Framing errors

— Interrupt-driven operation with four interrupt sources

— Separate transmitter and receiver CPU interrupt sources

— 16-bit programmable baud-rate modulus counter and 16-bit fractional

— 2 receiver wake-up methods

1.6.23 Deserial serial peripheral interface (DSPI)

The deserial serial peripheral interface (DSPI) module provides a synchronous serial interface for

communication between the MPC5602P MCU and external devices.

The DSPI modules provide these features:

• Full duplex, synchronous transfers

• Master or slave operation

• Programmable master bit rates

• Programmable clock polarity and phase

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• End-of-transmission interrupt flag

• Programmable transfer baud rate

• Programmable data frames from 4 to 16 bits

• Up to 8 chip select lines available:

— 8 on DSPI_0

— 4 each on DSPI_1 and DSPI_2

• 8 clock and transfer attributes registers

• Chip select strobe available as alternate function on one of the chip select pins for deglitching

• FIFOs for buffering up to 4 transfers on the transmit and receive side

• Queueing operation possible through use of the I/O processor or eDMA

• General purpose I/O functionality on pins when not used for SPI

1.6.24 Pulse width modulator (FlexPWM)

The pulse width modulator module (PWM) contains four PWM submodules each of which is set up to

control a single half-bridge power stage. There are also three fault channels.

This PWM is capable of controlling most motor types: AC induction motors (ACIM), permanent magnet

AC motors (PMAC), both brushless (BLDC) and brush DC motors (BDC), switched (SRM) and variable

reluctance motors (VRM), and stepper motors.

The FlexPWM block implements the following features:

• 16-bit resolution for center, edge-aligned, and asymmetrical PWMs

• Clock frequency same as that used for e200z0h core

• PWM outputs can operate as complementary pairs or independent channels

• Can accept signed numbers for PWM generation

• Independent control of both edges of each PWM output

• Synchronization to external hardware or other PWM supported

• Double buffered PWM registers

— Integral reload rates from 1 to 16

— Half cycle reload capability

• Multiple ADC trigger events can be generated per PWM cycle via hardware

• Write protection for critical registers

• Fault inputs can be assigned to control multiple PWM outputs

• Programmable filters for fault inputs

• Independently programmable PWM output polarity

• Independent top and bottom deadtime insertion

• Each complementary pair can operate with its own PWM frequency and deadtime values

• Individual software-control for each PWM output

• All outputs can be programmed to change simultaneously via a “Force Out” event

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• PWMX pin can optionally output a third PWM signal from each submodule

• Channels not used for PWM generation can be used for buffered output compare functions

• Channels not used for PWM generation can be used for input capture functions

• Enhanced dual-edge capture functionality

• eDMA support with automatic reload

• 2 fault inputs

• Capture capability for PWMA, PWMB, and PWMX channels not supported

1.6.25 eTimer

The MPC5602P includes one eTimer module which provides six 16-bit general purpose up/down

timer/counter units with the following features:

• Clock frequency same as that used for the e200z0h core

• Individual channel capability

— Input capture trigger

— Output compare

— Double buffer (to capture rising edge and falling edge)

— Separate prescaler for each counter

— Selectable clock source

— 0–100% pulse measurement

— Rotation direction flag (quad decoder mode)

• Maximum count rate

— External event counting: max. count rate = peripheral clock/2

— Internal clock counting: max. count rate = peripheral clock

• Counters are:

— Cascadable

— Preloadable

• Programmable count modulo

• Quadrature decode capabilities

• Counters can share available input pins

• Count once or repeatedly

• Pins available as GPIO when timer functionality not in use

1.6.26 Analog-to-digital converter (ADC) module

The ADC module provides the following features:

Analog part:

• 1 on-chip analog-to-digital converter

— 10-bit AD resolution

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— 1 sample and hold unit

— Conversion time, including sampling time, less than 1 µs (at full precision)

— Typical sampling time is 150 ns minimum (at full precision)

— DNL/INL ±1 LSB

— TUE < 1.5 LSB

— Single-ended input signal up to 3.3 V/5.0 V

— 3.3 V/5.0 V input reference voltage

— ADC and its reference can be supplied with a voltage independent from VDDIO

— ADC supply can be equal or higher than VDDIO

— ADC supply and ADC reference are not independent from each other (both internally bonded

to same pad)

— Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

Digital part:

• 16 input channels

• 4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before

results are stored in the appropriate ADC result location

• 2 modes of operation: Motor Control mode or Regular mode

• Regular mode features

— Register based interface with the CPU: control register, status register and 1 result register per

channel

— ADC state machine managing 3 request flows: regular command, hardware injected command

and software injected command

— Selectable priority between software and hardware injected commands

— DMA compatible interface

• CTU-controlled mode features

— Triggered mode only

— 4 independent result queues (1×16 entries, 2×8 entries, 1×4 entries)

— Result alignment circuitry (left justified and right justified)

— 32-bit read mode allows to have channel ID on one of the 16-bit part

— DMA compatible interfaces

1.6.27 Cross triggering unit (CTU)

The cross triggering unit allows automatic generation of ADC conversion requests on user selected

conditions without CPU load during the PWM period and with minimized CPU load for dynamic

configuration.

It implements the following features:

• Double buffered trigger generation unit with up to 8 independent triggers generated from external

triggers

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• Trigger generation unit configurable in sequential mode or in triggered mode

• Each trigger can be appropriately delayed to compensate the delay of external low pass filter

• Double buffered global trigger unit allowing eTimer synchronization and/or ADC command

generation

• Double buffered ADC command list pointers to minimize ADC-trigger unit update

• Double buffered ADC conversion command list with up to 24 ADC commands

• Each trigger capable of generating consecutive commands

• ADC conversion command allows to control ADC channel, single or synchronous sampling,

independent result queue selection

1.6.28 Nexus Development Interface (NDI)

The NDI (Nexus Development Interface) block is compliant with Nexus Class 1 of the IEEE-ISTO

5001-2003 standard. This development support is supplied for MCUs without requiring external address

and data pins for internal visibility. The NDI block is an integration of several individual Nexus blocks that

are selected to provide the development support interface for this device. The NDI block interfaces to the

host processor and internal busses to provide development support as per the IEEE-ISTO 5001-2003

Nexus Class 1 standard. The development support provided includes access to the MCU’s internal memory

map and access to the processor’s internal registers.

The NDI provides the following features:

• Configured via the IEEE 1149.1

• All Nexus port pins operate at VDDIO (no dedicated power supply)

• Nexus Class 1 supports Static debug

1.6.29 Cyclic redundancy check (CRC)

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC module

features:

• Support for CRC-16-CCITT (x25 protocol):

—x16 + x12 + x5 + 1

• Support for CRC-32 (Ethernet protocol):

—x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

• Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the

maximum frequency

1.6.30 IEEE 1149.1 JTAG controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while

remaining transparent to system logic when not in test mode. All data input to and output from the JTAGC

block is communicated in serial format. The JTAGC block is compliant with the IEEE standard.

The JTAG controller provides the following features:

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• IEEE test access port (TAP) interface 4 pins (TDI, TMS, TCK, TDO)

• Selectable modes of operation include JTAGC/debug or normal system operation.

• 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

—BYPASS

—IDCODE

—EXTEST

—SAMPLE

— SAMPLE/PRELOAD

• 5-bit instruction register that supports the additional following public instructions:

— ACCESS_AUX_TAP_NPC

— ACCESS_AUX_TAP_ONCE

• 3 test data registers:

— Bypass register

— Boundary scan register (size parameterized to support a variety of boundary scan chain lengths)

— Device identification register

• TAP controller state machine that controls the operation of the data registers, instruction register

and associated circuitry

1.6.31 On-chip voltage regulator (VREG)

The on-chip voltage regulator module provides the following features:

• Uses external NPN (negative-positive-negative) transistor

• Regulates external 3.3 V/5.0 V down to 1.2 V for the core logic

• Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V

1.7 Developer environment

The MPC5602P MCU tools and third-party developers are similar to those used for the Freescale

MPC5500 product family, offering a widespread, established network of tool and software vendors.

The following development support is available:

• Automotive Evaluation Boards (EVBs) featuring CAN, LIN interfaces, and more

• Compilers

• Debuggers

• JTAG and Nexus interfaces

• Autocode generation tools

• Initialization tools

1.8 Package

MPC5602P family members are offered in the following package types:

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58 Freescale Semiconductor

• 64-pin LQFP, 0.5 mm pitch, 10 mm × 10 mm outline

• 100-pin LQFP, 0.5 mm pitch, 14 mm × 14 mm outline

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Freescale Semiconductor 59

Chapter 2

MPC5602P Memory Map

Table 2-1 shows the memory map for the MPC5602P. All addresses on the MPC5602P, including those

that are reserved, are identified in the table. The addresses represent the physical addresses assigned to

each IP block.

Table 2-1. Memory map

Start address End address Size

(KB) Region name

On-chip memory

0x0000_0000 0x0003_FFFF 256 Code Flash Array 0

0x0004_0000 0x001F_FFFF 1792 Reserved

0x0020_0000 0x0020_3FFF 16 Code Flash Array 0 Shadow Sector

0x0020_4000 0x003F_FFFF 2032 Reserved

0x0040_0000 0x0040_3FFF 16 Code Flash Array 0 Test Sector

0x0040_4000 0x007F_FFFF 4080 Reserved

0x0080_0000 0x0080_FFFF 64 Data Flash Array 0

0x0081_0000 0x00C0_1FFF 4040 Reserved

0x00C0_2000 0x00C0_3FFF 8 Data Flash Array 0 Test Sector

0x00C0_4000 0x00FF_FFFF 4080 Reserved

0x0100_0000 0x1FFF_FFFF 507904 Flash Emulation Mapping

0x2000_0000 0x3FFF_FFFF 524288 Reserved

0x4000_0000 0x4000_4FFF 20 SRAM

0x4000_5000 0xC3F8_0000 1048536 Reserved

On-chip peripherals

0xC3F8_0000 0xC3F8_7FFF 32 Reserved

0xC3F8_8000 0xC3F8_BFFF 16 Code Flash 0 Configuration (CFLASH_0)

0xC3F8_C000 0xC3F8_FFFF 16 Data Flash 0 Configuration (DFLASH_0)

0xC3F9_0000 0xC3F9_3FFF 16 System Integration Unit Lite (SIUL)

0xC3F9_4000 0xC3F9_7FFF 16 WakeUp Unit (WKUP)

0xC3F9_8000 0xC3FD_7FF

256 Reserved

0xC3FD_8000 0xC3FD_BFF

16 System Status and Configuration Module (SSCM)

0xC3FD_C00

0xC3FD_FFF

16 Mode Entry module (ME)

0xC3FE_0000 0xC3FE_3FFF 16 Clock Generation Module (CGM, XOSC, IRC, FMPLL_0, CMU0)

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0xC3FE_4000 0xC3FE_7FFF 16 Reset Generation Module (RGM)

0xC3FE_8000 0xC3FE_BFF

16 Power Control Unit (PCU)1

0xC3FE_C00

0xC3FE_FFF

16 Reserved

0xC3FF_0000 0xC3FF_3FFF 16 Periodic Interrupt Timer (PIT)

0xC3FF_4000 0xC3FF_FFFF 48 Reserved

0xFFE0_0000 0xFFE0_3FFF 16 Analog to Digital Converter 0 (ADC_0)

0xFFE0_4000 0xFFE0_BFFF 32 Reserved

0xFFE0_C000 0xFFE0_FFFF 16 CTU_0

0xFFE1_0000 0xFFE1_7FFF 32 Reserved

0xFFE1_8000 0xFFE1_BFFF 16 eTimer_0

0xFFE1_C000 0xFFE2_3FFF 32 Reserved

0xFFE2_4000 0xFFE2_7FFF 16 FlexPWM_0

0xFFE2_8000 0xFFE3_FFFF 96 Reserved

0xFFE4_0000 0xFFE4_3FFF 16 LINFlex_0

0xFFE4_4000 0xFFE4_7FFF 16 LINFlex_1

0xFFE5_0000 0xFFE6_7FFF 128 Reserved

0xFFE6_8000 0xFFE6_BFFF 16 Cyclic Redundancy Check (CRC)

0xFFE6_C000 0xFFE6_FFFF 16 Fault Collection Unit (FCU)

0xFFE7_0000 0xFFE7_FFFF 64 Reserved

0xFFE8_0000 0xFFEF_FFFF 512 Mirrored (range 0xC3F8_0000 – 0xC3FF_FFFF)

0xFFF0_0000 0xFFF3_7FFF 224 Reserved

0xFFF3_8000 0xFFF3_BFFF 16 Software Watchdog (SWT_0)

0xFFF3_C000 0xFFF3_FFFF 16 System Timer Module (STM_0)

0xFFF4_0000 0xFFF4_3FFF 16 Error Correction Status Module (ECSM)

0xFFF4_4000 0xFFF4_7FFF 16 Enhanced Direct Memory Access Controller (eDMA)

0xFFF4_8000 0xFFF4_BFFF 16 Interrupt Controller (INTC)

0xFFF4_C000 0xFFF8_FFFF 272 Reserved

0xFFF9_0000 0xFFF9_3FFF 16 DSPI_0

0xFFF9_4000 0xFFF9_7FFF 16 DSPI_1

0xFFF9_8000 0xFFF9_BFFF 16 DSPI_2

0xFFF9_C000 0xFFFB_FFFF 144 Reserved

Table 2-1. Memory map (continued)

Start address End address Size

(KB) Region name

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0xFFFC_0000 0xFFFC_3FFF 16 FlexCAN_0 (CAN0)

0xFFFC_4000 0xFFFD_BFF

96 Reserved

0xFFFD_C00

0xFFFD_FFF

16 DMA Multiplexer (DMA_MUX)

0xFFFE_0000 0xFFFE_7FFF 32 Reserved

0xFFFE_8000 0xFFFE_BFF

16 Safety Port (FlexCAN)

0xFFFE_C00

0xFFFF_BFFF 64 Reserved

0xFFFF_C000 0xFFFF_FFFF 16 Boot Assist Module (BAM)

1This address space contains also VREG registers. See Chapter 34, “Voltage Regulators and Power Supplies.”

Table 2-1. Memory map (continued)

Start address End address Size

(KB) Region name

Chapter 2 MPC5602P Memory Map

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62 Freescale Semiconductor

Chapter 3 Signal Description

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Freescale Semiconductor 63

Chapter 3

Signal Description

This chapter describes the signals of the MPC5602P. It includes a table of signal properties and detailed

descriptions of signals.

3.1 100-pin LQFP pinout

Figure 3-1 shows the pinout of the 100-pin LQFP.

Figure 3-1. 100-pin LQFP pinout (top view)

100

NMI

A[6]

D[1]

A[7]

C[4]

A[8]

C[5]

A[5]

C[7]

C[3]

N.C.

VDD_HV_IO1

VSS_HV_IO1

D[9]

VDD_HV_OSC

VSS_HV_OSC

XTAL

EXTAL

RESET

D[8]

D[5]

D[6]

VSS_LV_COR0

VDD_LV_COR0

A[4]

VPP_TEST

D[14]

C[14]

C[13]

D[12]

N.C.

D[13]

VSS_LV_COR1

VDD_LV_COR1

A[3]

VDD_HV_IO2

VSS_HV_IO2

TDO

TCK

TMS

TDI

A[2]

C[12]

C[11]

D[11]

D[10]

A[1]

A[0]

D[7]

E[1]

C[1]

B[7]

C[2]

B[8]

E[2]

N.C.

B[9]

B[10]

B[11]

B[12]

VDD_HV_ADC0

VSS_HV_ADC0

E[7]/D[15]

E[3]/B[13]

E[5]/B[15]

E[4]/B[14]

E[6]/C[0]

N.C.

BCTRL

N.C.

VDD_HV_REG

A[15]

A[14]

C[6]

D[2]

B[6]

A[13]

A[9]

VSS_LV_COR2

VDD_LV_COR2

C[8]

D[4]

D[3]

VSS_HV_IO3

VDD_HV_IO3

D[0]

C[15]

C[9]

A[12]

A[11]

A[10]

B[3]

B[2]

C[10]

B[1]

B[0]

100 LQFP

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64 Freescale Semiconductor

3.2 64-pin LQFP pinout

Figure 3-2. 64-pin LQFP pinout(top view)

3.3 Pin description

The following sections provide signal descriptions and related information about the functionality and

configuration of the MPC5602P devices.

3.3.1 Power supply and reference voltage pins

Table 3-1 lists the power supply and reference voltage for the MPC5602P devices.

NMI

A[6]

A[7]

A[8]

A[5]

VDD_HV_IO1

VSS_HV_IO1

D[9]

VDD_HV_OSC

VSS_HV_OSC

XTAL

EXTAL

RESET

D[8]

VSS_LV_COR0

VDD_LV_COR0

A[4]

VPP_TEST

D[14]]

D[12]

D[13

VSS_LV_COR1

VDD_LV_COR1

A[3]

VDD_HV_IO2

VSS_HV_IO2

TDO

TCK

TMS

TDI

C[12]

C[11]

D[7]

E[1]

C[1]

B[7]

C[2]

B[8]

E[2]

B[9]

B[10]

B[11]

B[12]

VDD_HV_ADC0

VSS_HV_ADC0

E[3]/B[13]

BCTRL

VDD_HV_REG

A[15]

A[14]

B[6]

A[13]

A[9]

VSS_LV_COR2

VDD_LV_COR2

C[8]

VSS_HV_IO3

VDD_HV_IO3

A[12]

A[11]

A[10]

B[2]

B[1]

B[0]

64 LQFP

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 65

Table 3-1. Supply pins

Supply Pin

Symbol Description 64-pin 100-pin

VREG control and power supply pins. Pins available on 64-pin and 100-pin packages

BCTRL Voltage regulator external NPN ballast base control pin 31 47

VDD_HV_REG

(3.3 V or 5.0 V)

Voltage regulator supply voltage 32 50

ADC_0 reference and supply voltage. Pins available on 64-pin and 100-pin packages

VDD_HV_ADC01

1Analog supply/ground and high/low reference lines are internally physically separate, but are shorted via a

double-bonding connection on VDD_HV_ADCx/VSS_HV_ADCx pins.

ADC_0 supply and high reference voltage 28 39

VSS_HV_ADC0 ADC_0 ground and low reference voltage 29 40

Power supply pins (3.3 V or 5.0 V). Pins available on 64-pin and 100-pin packages

VDD_HV_IO1 Input/output supply voltage 6 13

VSS_HV_IO1 Input/output ground 7 14

VDD_HV_IO2 Input/output supply voltage and data Flash memory supply voltage 40 63

VSS_HV_IO2 Input/output ground and Flash memory HV ground 39 62

VDD_HV_IO3 Input/output supply voltage and code Flash memory supply voltage 55 87

VSS_HV_IO3 Input/output ground and code Flash memory HV ground 56 88

VDD_HV_OSC Crystal oscillator amplifier supply voltage 9 16

VSS_HV_OSC Crystal oscillator amplifier ground 10 17

Power supply pins (1.2 V). Pins available on 64-pin and 100-pin packages

VDD_LV_COR0 1.2 V supply pins for core logic and PLL. Decoupling capacitor must be

connected between these pins and the nearest VSS_LV_COR pin.

16 25

VSS_LV_COR0 1.2 V supply pins for core logic and PLL. Decoupling capacitor must be

connected between these pins and the nearest VDD_LV_COR pin.

15 24

VDD_LV_COR1 1.2 V supply pins for core logic and data Flash. Decoupling capacitor

must be connected between these pins and the nearest VSS_LV_COR pin.

42 65

VSS_LV_COR1 1.2 V supply pins for core logic and data Flash. Decoupling capacitor

must be connected between these pins and the nearest VDD_LV_COR pin.

43 66

VDD_LV_COR2 1.2 V supply pins for core logic and code Flash. Decoupling capacitor

must be connected between these pins and the nearest VSS_LV_COR pin.

58 92

VSS_LV_COR2 1.2 V supply pins for core logic and code Flash. Decoupling capacitor

must be connected betwee.n these pins and the nearest VDD_LV_COR pin.

59 93

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

66 Freescale Semiconductor

3.3.2 System pins

Table 3-2 and Table 3-3 contain information on pin functions for the MPC5602P devices. The pins listed

in Table 3-2 are single-function pins. The pins shown in Table 3-3 are multi-function pins, programmable

via their respective pad configuration register (PCR) values.

3.3.3 Pin multiplexing

Table 3-3 defines the pin list and muxing for the MPC5602P devices.

Each row of Table 3-3 shows all the possible ways of configuring each pin, via alternate functions. The

default function assigned to each pin after reset is the ALT0 function.

MPC5602P devices provide three main I/O pad types, depending on the associated functions:

•Slow pads are the most common, providing a compromise between transition time and low

electromagnetic emission.

•Medium pads provide fast enough transition for serial communication channels with controlled

current to reduce electromagnetic emission.

•Fast pads provide maximum speed. They are used for improved NEXUS debugging capability.

Table 3-2. System pins

Symbol Description Direction

Pad speed1

1SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.

SRC = 0 SRC = 1 64-pin 100-pin

Dedicated pins

NMI Non-maskable Interrupt Input only Slow — 1 1

XTAL Analog output of the oscillator amplifier

circuit—needs to be grounded if oscillator is

used in bypass mode

———1118

EXTAL Analog input of the oscillator amplifier circuit,

when the oscillator is not in bypass mode

Analog input for the clock generator when the

oscillator is in bypass mode

———1219

TDI JTAG test data input Input only Slow — 35 58

TMS JTAG state machine control Input only Slow — 36 59

TCK JTAG clock Input only Slow — 37 60

TDO JTAG test data output Output only Slow Fast 38 61

Reset pin

RESET Bidirectional reset with Schmitt trigger

characteristics and noise filter

Bidirectional Medium — 13 20

Test pin

VPP_TEST Pin for testing purpose only. To be tied to ground

in normal operating mode.

———4774

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 67

Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of

reducing AC performance. For more information, see “Pad AC Specifications” in the device data sheet.

Table 3-3. Pin muxing

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Port A (16-bit)

A[0] PCR[0] ALT0

ALT1

ALT2

ALT3

—

GPIO[0]

ETC[0]

SCK

F[0]

EIRQ[0]

SIUL

eTimer_0

DSPI_2

FCU_0

SIUL

I/O

Slow Medium — 51

A[1] PCR[1] ALT0

ALT1

ALT2

ALT3

—

GPIO[1]

ETC[1]

SOUT

F[1]

EIRQ[1]

SIUL

eTimer_0

DSPI_2

FCU_0

SIUL

I/O

Slow Medium — 52

A[2] PCR[2] ALT0

ALT1

ALT2

ALT3

—

GPIO[2]

ETC[2]

—

A[3]

SIN

ABS[0]

EIRQ[2]

SIUL

eTimer_0

—

FlexPWM_0

DSPI_2

MC_RGM

SIUL

I/O

—

Slow Medium — 57

A[3] PCR[3] ALT0

ALT1

ALT2

ALT3

—

GPIO[3]

ETC[3]

CS0

B[3]

ABS[1]

EIRQ[3]

SIUL

eTimer_0

DSPI_2

FlexPWM_0

MC_RGM

SIUL

I/O

Slow Medium 41 64

A[4] PCR[4] ALT0

ALT1

ALT2

ALT3

—

GPIO[4]

—

CS1

ETC[4]

FAB

EIRQ[4]

SIUL

—

DSPI_2

eTimer_0

MC_RGM

SIUL

I/O

—

I/O

Slow Medium 48 75

A[5] PCR[5] ALT0

ALT1

ALT2

ALT3

—

GPIO[5]

CS0

—

CS7

EIRQ[5]

SIUL

DSPI_1

—

DSPI_0

SIUL

I/O

—

Slow Medium 5 8

A[6] PCR[6] ALT0

ALT1

ALT2

ALT3

—

GPIO[6]

SCK

—

EIRQ[6]

SIUL

DSPI_1

—

SIUL

I/O

—

Slow Medium 2 2

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

68 Freescale Semiconductor

A[7] PCR[7] ALT0

ALT1

ALT2

ALT3

—

GPIO[7]

SOUT

—

EIRQ[7]

SIUL

DSPI_1

—

SIUL

I/O

—

Slow Medium 3 4

A[8] PCR[8] ALT0

ALT1

ALT2

ALT3

—

GPIO[8]

—

SIN

EIRQ[8]

SIUL

—

DSPI_1

SIUL

I/O

—

Slow Medium 4 6

A[9] PCR[9] ALT0

ALT1

ALT2

ALT3

—

GPIO[9]

CS1

—

B[3]

FAULT[0]

SIUL

DSPI_2

—

FlexPWM_0

I/O

—

Slow Medium 60 94

A[10] PCR[10] ALT0

ALT1

ALT2

ALT3

—

GPIO[10]

CS0

B[0]

X[2]

EIRQ[9]

SIUL

DSPI_2

FlexPWM_0

SIUL

I/O

Slow Medium 52 81

A[11] PCR[11] ALT0

ALT1

ALT2

ALT3

—

GPIO[11]

SCK

A[0]

A[2]

EIRQ[10]

SIUL

DSPI_2

FlexPWM_0

SIUL

I/O

Slow Medium 53 82

A[12] PCR[12] ALT0

ALT1

ALT2

ALT3

—

GPIO[12]

SOUT

A[2]

B[2]

EIRQ[11]

SIUL

DSPI_2

FlexPWM_0

SIUL

I/O

Slow Medium 54 83

A[13] PCR[13] ALT0

ALT1

ALT2

ALT3

—

GPIO[13]

—

B[2]

—

SIN

FAULT[0]

EIRQ[12]

SIUL

—

FlexPWM_0

—

DSPI_2

FlexPWM_0

SIUL

I/O

—

Slow Medium 61 95

A[14] PCR[14] ALT0

ALT1

ALT2

ALT3

—

GPIO[14]

TXD

—

EIRQ[13]

SIUL

Safety Port_0

—

SIUL

I/O

—

Slow Medium 63 99

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 69

A[15] PCR[15] ALT0

ALT1

ALT2

ALT3

—

GPIO[15]

—

RXD

EIRQ[14]

SIUL

—

Safety Port_0

SIUL

I/O

—

Slow Medium 64 100

Port B (16-bit)

B[0] PCR[16] ALT0

ALT1

ALT2

ALT3

—

GPIO[16]

TXD

—

DEBUG[0]

EIRQ[15]

SIUL

FlexCAN_0

—

SSCM

SIUL

I/O

—

Slow Medium 49 76

B[1] PCR[17] ALT0

ALT1

ALT2

ALT3

—

GPIO[17]

—

DEBUG[1]

RXD

EIRQ[16]

SIUL

—

SSCM

FlexCAN_0

SIUL

I/O

—

Slow Medium 50 77

B[2] PCR[18] ALT0

ALT1

ALT2

ALT3

—

GPIO[18]

TXD

—

DEBUG[2]

EIRQ[17]

SIUL

LIN_0

—

SSCM

SIUL

I/O

—

Slow Medium 51 79

B[3] PCR[19] ALT0

ALT1

ALT2

ALT3

—

GPIO[19]

—

DEBUG[3]

RXD

SIUL

—

SSCM

LIN_0

I/O

—

Slow Medium — 80

B[6] PCR[22] ALT0

ALT1

ALT2

ALT3

—

GPIO[22]

CLKOUT

CS2

—

EIRQ[18]

SIUL

Control

DSPI_2

—

SIUL

I/O

—

Slow Medium 62 96

B[7] PCR[23] ALT0

ALT1

ALT2

ALT3

—

GPIO[23]

—

AN[0]

RXD

SIUL

—

ADC_0

LIN_0

Input only — — 20 29

B[8] PCR[24] ALT0

ALT1

ALT2

ALT3

—

GPIO[24]

—

AN[1]

ETC[5]

SIUL

—

ADC_0

eTimer_0

Input only — — 22 31

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

70 Freescale Semiconductor

B[9] PCR[25] ALT0

ALT1

ALT2

ALT3

—

GPIO[25]

—

AN[11]

SIUL

—

ADC_0

Input only — — 24 35

B[10] PCR[26] ALT0

ALT1

ALT2

ALT3

—

GPIO[26]

—

AN[12]

SIUL

—

ADC_0

Input only — — 25 36

B[11] PCR[27] ALT0

ALT1

ALT2

ALT3

—

GPIO[27]

—

AN[13]

SIUL

—

ADC_0

Input only — — 26 37

B[12] PCR[28] ALT0

ALT1

ALT2

ALT3

—

GPIO[28]

—

AN[14]

SIUL

—

ADC_0

Input only — — 27 38

B[13] PCR[29] ALT0

ALT1

ALT2

ALT3

—

GPIO[29]

—

AN[6]

emu. AN[0]

RXD

SIUL

—

ADC_0

emu. ADC_16

LIN_1

Input only — — 30 42

B[14] PCR[30] ALT0

ALT1

ALT2

ALT3

—

GPIO[30]

—

AN[7]

emu. AN[1]

ETC[4]

EIRQ[19]

SIUL

—

ADC_0

emu. ADC_16

eTimer_0

SIUL

Input only — — — 44

B[15] PCR[31] ALT0

ALT1

ALT2

ALT3

—

GPIO[31]

—

AN[8]

emu. AN[2]

EIRQ[20]

SIUL

—

ADC_0

emu. ADC_16

SIUL

Input only — — — 43

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 71

Port C (16-bit)

C[0] PCR[32] ALT0

ALT1

ALT2

ALT3

—

GPIO[32]

—

AN[9]

emu. AN[3]

SIUL

—

ADC_0

emu. ADC_16

Input only — — — 45

C[1] PCR[33] ALT0

ALT1

ALT2

ALT3

—

GPIO[33]

—

AN[2]

SIUL

—

ADC_0

Input only — — 19 28

C[2] PCR[34] ALT0

ALT1

ALT2

ALT3

—

GPIO[34]

—

AN[3]

SIUL

—

ADC_0

Input only — — 21 30

C[3] PCR[35] ALT0

ALT1

ALT2

ALT3

—

GPIO[35]

CS1

—

TXD

EIRQ[21]

SIUL

DSPI_0

—

LIN_1

SIUL

I/O

—

Slow Medium — 10

C[4] PCR[36] ALT0

ALT1

ALT2

ALT3

—

GPIO[36]

CS0

X[1]

DEBUG[4]

EIRQ[22]

SIUL

DSPI_0

FlexPWM_0

SSCM

SIUL

I/O

—

Slow Medium — 5

C[5] PCR[37] ALT0

ALT1

ALT2

ALT3

—

GPIO[37]

SCK

—

DEBUG[5]

EIRQ[23]

SIUL

DSPI_0

—

SSCM

SIUL

I/O

—

Slow Medium — 7

C[6] PCR[38] ALT0

ALT1

ALT2

ALT3

—

GPIO[38]

SOUT

B[1]

DEBUG[6]

EIRQ[24]

SIUL

DSPI_0

FlexPWM_0

SSCM

SIUL

I/O

—

Slow Medium — 98

C[7] PCR[39] ALT0

ALT1

ALT2

ALT3

—

GPIO[39]

—

A[1]

DEBUG[7]

SIN

SIUL

—

FlexPWM_0

SSCM

DSPI_0

I/O

—

Slow Medium — 9

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

72 Freescale Semiconductor

C[8] PCR[40] ALT0

ALT1

ALT2

ALT3

GPIO[40]

CS1

—

CS6

SIUL

DSPI_1

—

DSPI_0

I/O

—

Slow Medium 57 91

C[9] PCR[41] ALT0

ALT1

ALT2

ALT3

GPIO[41]

CS3

—

X[3]

SIUL

DSPI_2

—

FlexPWM_0

I/O

—

Slow Medium — 84

C[10

]

PCR[42] ALT0

ALT1

ALT2

ALT3

—

GPIO[42]

CS2

—

A[3]

FAULT[1]

SIUL

DSPI_2

—

FlexPWM_0

I/O

—

Slow Medium — 78

C[11

]

PCR[43] ALT0

ALT1

ALT2

ALT3

GPIO[43]

ETC[4]

CS2

—

SIUL

eTimer_0

DSPI_2

—

I/O

—

Slow Medium 33 55

C[12

]

PCR[44] ALT0

ALT1

ALT2

ALT3

GPIO[44]

ETC[5]

CS3

—

SIUL

eTimer_0

DSPI_2

—

I/O

—

Slow Medium 34 56

C[13

]

PCR[45] ALT0

ALT1

ALT2

ALT3

—

GPIO[45]

—

EXT_IN

EXT_SYNC

SIUL

—

CTU_0

FlexPWM_0

I/O

—

Slow Medium — 71

C[14

]

PCR[46] ALT0

ALT1

ALT2

ALT3

GPIO[46]

—

EXT_TGR

—

SIUL

—

CTU_0

—

I/O

—

Slow Medium — 72

C[15

]

PCR[47] ALT0

ALT1

ALT2

ALT3

—

GPIO[47]

—

A[1]

EXT_IN

EXT_SYNC

SIUL

—

FlexPWM_0

CTU_0

FlexPWM_0

I/O

—

Slow Medium — 85

Port D (16-bit)

D[0] PCR[48] ALT0

ALT1

ALT2

ALT3

GPIO[48]

—

B[1]

SIUL

—

FlexPWM_0

I/O

—

Slow Medium — 86

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 73

D[1] PCR[49] ALT0

ALT1

ALT2

ALT3

GPIO[49]

—

EXT_TRG

SIUL

—

CTU_0

I/O

—

Slow Medium — 3

D[2] PCR[50] ALT0

ALT1

ALT2

ALT3

GPIO[50]

—

X[3]

SIUL

—

FlexPWM_0

I/O

—

Slow Medium — 97

D[3] PCR[51] ALT0

ALT1

ALT2

ALT3

GPIO[51]

—

A[3]

SIUL

—

FlexPWM_0

I/O

—

Slow Medium — 89

D[4] PCR[52] ALT0

ALT1

ALT2

ALT3

GPIO[52]

—

B[3]

SIUL

—

FlexPWM_0

I/O

—

Slow Medium — 90

D[5] PCR[53] ALT0

ALT1

ALT2

ALT3

GPIO[53]

CS3

F[0]

—

SIUL

DSPI_0

FCU_0

—

I/O

—

Slow Medium — 22

D[6] PCR[54] ALT0

ALT1

ALT2

ALT3

—

GPIO[54]

CS2

—

FAULT[1]

SIUL

DSPI_0

—

FlexPWM_0

I/O

—

Slow Medium — 23

D[7] PCR[55] ALT0

ALT1

ALT2

ALT3

GPIO[55]

CS3

F[1]

CS4

SIUL

DSPI_1

FCU_0

DSPI_0

I/O

Slow Medium 17 26

D[8] PCR[56] ALT0

ALT1

ALT2

ALT3

GPIO[56]

CS2

—

CS5

SIUL

DSPI_1

—

DSPI_0

I/O

—

Slow Medium 14 21

D[9] PCR[57] ALT0

ALT1

ALT2

ALT3

GPIO[57]

X[0]

TXD

—

SIUL

FlexPWM_0

LIN_1

—

I/O

—

Slow Medium 8 15

D[10

]

PCR[58] ALT0

ALT1

ALT2

ALT3

GPIO[58]

A[0]

—

SIUL

FlexPWM_0

—

I/O

—

Slow Medium — 53

D[11

]

PCR[59] ALT0

ALT1

ALT2

ALT3

GPIO[59]

B[0]

—

SIUL

FlexPWM_0

—

I/O

—

Slow Medium — 54

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

74 Freescale Semiconductor

D[12

]

PCR[60] ALT0

ALT1

ALT2

ALT3

—

GPIO[60]

X[1]

—

RXD

SIUL

FlexPWM_0

—

LIN_1

I/O

—

Slow Medium 45 70

D[13

]

PCR[61] ALT0

ALT1

ALT2

ALT3

GPIO[61]

A[1]

—

SIUL

FlexPWM_0

—

I/O

—

Slow Medium 44 67

D[14

]

PCR[62] ALT0

ALT1

ALT2

ALT3

GPIO[62]

B[1]

—

SIUL

FlexPWM_0

—

I/O

—

Slow Medium 46 73

D[15

]

PCR[63] ALT0

ALT1

ALT2

ALT3

—

GPIO[63]

—

AN[10]

emu. AN[4]

SIUL

—

ADC_0

emu. ADC_16

Input only — — — 41

Port E (16-bit)

E[1] PCR[65] ALT0

ALT1

ALT2

ALT3

—

GPIO[65]

—

AN[4]

SIUL

—

ADC_0

Input only — — 18 27

E[2] PCR[66] ALT0

ALT1

ALT2

ALT3

—

GPIO[66]

—

AN[5]

SIUL

—

ADC_0

Input only — — 23 32

E[3] PCR[67] ALT0

ALT1

ALT2

ALT3

—

GPIO[67]

—

AN[6]

SIUL

—

ADC_0

Input only — — 30 42

E[4] PCR[68] ALT0

ALT1

ALT2

ALT3

—

GPIO[68]

—

AN[7]

SIUL

—

ADC_0

Input only — — — 44

E[5] PCR[69] ALT0

ALT1

ALT2

ALT3

—

GPIO[69]

—

AN[8]

SIUL

—

ADC_0

Input only — — — 43

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 75

3.4 CTU / ADC / FlexPWM / eTimer connections

Figure 3-3 shows the interconnections between the CTU, ADC, FlexPWM, and eTimer.

E[6] PCR[70] ALT0

ALT1

ALT2

ALT3

—

GPIO[70]

—

AN[9]

SIUL

—

ADC_0

Input only — — — 45

E[7] PCR[71] ALT0

ALT1

ALT2

ALT3

—

GPIO[71]

—

AN[10]

SIUL

—

ADC_0

Input only — — — 41

1ALT0 is the primary (default) function for each port after reset.

2Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIU module.

PCR.PA = 00 ALT0; PCR.PA = 01 ALT1; PCR.PA = 10 ALT2; PCR.PA = 11 ALT3. This is intended to

select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of

the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is

reported as “—”.

3Module included on the MCU.

4Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by

setting the values of the PSMIO.PADSELx bitfields inside the SIUL module.

5Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.

6ADC0.AN emulates ADC1.AN. This feature is used to provide software compatibility between MPC5602P and

MPC5604P. Refer to ADC chapter of reference manual for more details.

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

76 Freescale Semiconductor

Figure 3-3. CTU / ADC / FlexPWM / eTimer connections

Table 3-4. CTU / ADC / FlexPWM / eTimer connections

Source module

(Signal)

Target module

(Signal) Comment

PWM (Master Reload) CTU (PWM Reload) From PWM sub-module 0

PWM (OUT_TRIG0_0) CTU (PWM_ODD_0) OUT_TRIG0 sub-module 0

PWM (OUT_TRIG1_0) CTU (PWM_EVEN_0) OUT_TRIG1 sub-module 0

PWM (PWMX0) CTU (PWM_REAL_0) —

PWM (OUT_TRIG0_1) CTU (PWM_ODD_1) OUT_TRIG0 sub-module 1

PWM (OUT_TRIG1_1) CTU (PWM_EVEN_1) OUT_TRIG1 sub-module 1

PWM (PWMX1) CTU (PWM_REAL_1) —

PWM (OUT_TRIG0_2) CTU (PWM_ODD_2) OUT_TRIG0 sub-module 2

PWM (OUT_TRIG1_2) CTU (PWM_EVEN_2) OUT_TRIG1 sub-module 2

PWM (PWMX2) CTU (PWM_REAL_2) —

PWM (OUT_TRIG0_3) CTU (PWM_ODD_3) OUT_TRIG0 sub-module 3

PWM (OUT_TRIG1_3) CTU (PWM_EVEN_3) OUT_TRIG1 sub-module 3

PWM (PWMX3) CTU (PWM_REAL_3) —

External pins

PWMA0

PWMB0

PWMA1

PWMB1

PWMA2

PWMB2

PWMA3

PWMB3

Master reload

FAULT0

FAULT1

OUT_TRIG0_0

OUT_TRIG0_1

OUT_TRIG0_2

OUT_TRIG0_3

OUT_TRIG1_0

OUT_TRIG1_1

OUT_TRIG1_2

OUT_TRIG1_3

PWMX0

PWMX1

PWMX2

PWMX3

FlexPWM

EXT_FORCE

CLOCK

EXT_SYNC

PWM_REL

PWM_ODD_0

PWM_ODD_1

PWM_ODD_2

PWM_ODD_3

PWM_EVEN_0

PWM_EVEN_1

PWM_EVEN_2

TRIGGER_0

RPWM_0

RPWM_1

ADC_CMD_0

NEXT_CMD_0

FIFO_0

TRIGGER_1

ADC_CMD_1

NEXT_CMD_1

FIFO_1

EXT_IN

EXT_TRG

CTU

PWM_EVEN_3

RPWM_2

RPWM_3

ETMR0_IN

ETIMER0_TRG

ETIMER1_TRG

AUX_0

AUX_1

AUX_2

eTimer0 External pins

DSPI1

SCK

ADC0

(ipp_ind_injection_trg)

External pins

CTU/ADC

IP Interface

External pins

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 77

PWM (PWMA0) SIU lite —

PWM (PWMB0) SIU lite —

PWM (PWMX1) SIU lite —

PWM (PWMA1) SIU lite —

PWM (PWMB1) SIU lite —

PWM (PWMX2) SIU lite —

PWM (PWMA2) SIU lite —

PWM (PWMB2) SIU lite —

PWM (PWMX3) SIU lite —

PWM (PWMA3) SIU lite —

PWM (PWMB3) SIU lite —

PWM (PWMX3) SIU lite —

eTimer_0 (T1) PWM (EXT_FORCE) —

eTimer_0 (T2) CTU (ETMR0_IN) —

eTimer_0 (T5) ADC_0 ADC injected conversion request signal (for non CTU mode of

operation)

CTU (ETIMER0_TRG) eTimer_0 (AUX_0) —

CTU (ETIMER1_TRG) eTimer_0 (AUX_1) —

CTU (TRIGGER_0) ADC_0 (through

CTU/ADC IP Interface)

—

CTU (TRIGGER_1) Virtual ADC_1 (through

CTU/ADC IP Interface)

—

CTU (ADC_CMD_0) ADC_0 (through

CTU/ADC IP Interface)

16-bit signal

CTU (ADC_CMD_1) Virtual ADC_1 (through

CTU/ADC IP Interface)

16-bit signal

CTU (EXT_TGR) SIU lite —

ADC_0 (EOC) CTU (NEXT_CMD_0) End Of Conversion should be used as next command request

signal

Virtual ADC_1 (EOC) CTU (NEXT_CMD_1)

(through CTU/ADC IP

Interface)

End Of Conversion should be used as next command request

signal

ADC_0 CTU (FIFO_0) 18-bit signal

Virtual ADC_1 CTU (FIFO_1) (through

CTU/ADC IP Interface)

18-bit signal

SIU lite CTU (EXT_IN) The same GPIO pin as used for CTU (EXT_IN) and the PWM

(EXT_SYNC)

Table 3-4. CTU / ADC / FlexPWM / eTimer connections (continued)

Source module

(Signal)

Target module

(Signal) Comment

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

78 Freescale Semiconductor

SIU lite PWM (EXT_SYNC) The same GPIO pin as used for CTU (EXT_IN) and the PWM

(EXT_SYNC)

SIU lite PWM (FAULT0) —

SIU lite PWM (FAULT1) —

DSPI_1 (SCK) eTimer_0 (AUX_2) —

Table 3-4. CTU / ADC / FlexPWM / eTimer connections (continued)

Source module

(Signal)

Target module

(Signal) Comment

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 79

Chapter 4

Clock Description

This chapter describes the clock architectural implementation for MPC5602P.

The following clock related modules are implemented on the MPC5602P:

• Clock, Reset, and Mode Handling

— Clock Generation Module (CGM) (see Chapter 5, “Clock Generation Module (MC_CGM))

— Reset Generation Module (RGM) (see Chapter 8, “Reset Generation Module (MC_RGM))

— Mode Entry Module (ME) (see Chapter 7, “Mode Entry Module (MC_ME))

• High Frequency Oscillator (XOSC) (see Section 4.7, “XOSC external crystal oscillator)

• High Frequency RC Oscillator (IRC) (see Section 4.6, “IRC 16 MHz internal RC oscillator

(RC_CTL))

• FMPLL (FMPLL_0) (see Section 4.8, “Frequency Modulated Phase Locked Loop (FMPLL))

• CMU (CMU_0) (see Section 4.9, “Clock Monitor Unit (CMU))

• Periodic Interrupt Timer (PIT) (see Chapter 30, “Periodic Interrupt Timer (PIT))

• System Timer Module (STM_0) (see Chapter 31, “System Timer Module (STM))

• Software Watchdog Timer (SWT_0) (see Section 27.3, “Software Watchdog Timer (SWT))

4.1 Clock architecture

The system and peripheral clocks are generated from three sources:

• IRC—internal RC oscillator clock

• XOSC—oscillator clock

• FMPLL_0 clock output

The clock architecture is shown in Figure 4-1, Figure 4-2, and Figure 4-3.

The frequencies shown in Figure 4-1 represent only one possible setting.

NOTE

MC_PLL_CLK and SP_PLL_CLK are SYS_CLK.

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

80 Freescale Semiconductor

Figure 4-1. MPC5602P system clock generation

PHI_PCS

PHI

FMPLL_0

64 MHz

CMU_0

1, 2, 3, ... 16

Clock Out Divider

MC_PLL Divider

CMU_PLL Divider

SP_PLL Divider

[0]

[2]

[4]

[5]

[8]

AUX Clock Selector 0

AUX Clock Selector 1

[0]

[2]

[4]

[5]

[8]

System Clock Selector 0

RC Oscillator

(IRC)

Oscillator

(XOSC40)

N.C.

IRC_CLK

16 MHz

SYS_CLK

64 MHz—50%

IRC_CLK

16 MHz

XOSC_CLK

8 MHz—50%

Clockout

30/32 MHz

1, 2, 4, 8

Clock Out Selector

[0]

[1]

[2]

[3]

1, 2, 3, ... 16

[0]

[2]

[4]

[5]

[8]

AUX Clock Selector 2

XOSC_CLK

8 MHz—50%

FMPLL_0_PCS_CLK

FMPLL_0_CLK

NOTE: FlexRay protocol clock does not support IRC as a clock source.

FMPLL_0_CLK

XOSC_CLK

IRC_CLK

FMPLL_0_PCS_CLK—64 MHz, 50%

FMPLL_0_CLK—64 MHz, 50%

SYS_CLK = System Clock

N.C.

50%

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 81

Figure 4-2. MPC5602P system clock distribution Part A

SafetyPort

Protocol Clock

Module Clock

XOSC_CLK

SP_CLK

eTimer_0

FlexPWM

ADC_0

Module Clock

DMA Support

CTU

SYS_CLK

MC_CLK

DSPI_0

DSPI_1

DSPI_2

CTU Trigger Output

CTU Sync Event Input

Legend:

BIU

IPS @ SYS_CLK

BIU

MC_CLK

Module Clock

BIU

MC_CLK

Module Clock

BIU

MC_CLK

Protocol Clock

Module Clock

BIU

Module Clock

BIU

SYS_CLK

Module Clock

BIU

SYS_CLK

Module Clock

BIU

SYS_CLK

SP_CLK

IPS @ MC_CLK

IPS @ SP_CLK

NOTE: MC_CLK and SP_CLK are SYS_CLK

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

82 Freescale Semiconductor

Figure 4-3. MPC5602P system clock distribution Part B

4.2 Available clock domains

This section describes the various clock domains available on MPC5602P.

4.2.1 FMPLL input reference clock

The input reference clock for FMPLL_0 is always the external crystal oscillator clock (XOSC).

4.2.2 Clock selectors

4.2.2.1 System clock selector 0 for SYS_CLK

The system clock selector 0 selects the clock source for the system clock (SYS_CLK) from clock signals:

SYS_CLK

IRCOSC_CLK

SYS_CLK

IRCOSC_CLK

XOSC_CLK

SYS_CLK

IPS

SYS_CLK

IPS

SYS_CLK

LINFlex_0

Module clock

BIU

LINFlex_1

Module clock

BIU

DMA Mux

Module clock

BIU

eDMA2

Module clock

BIU

INTC

Module clock

BIU

SWT

Module clock

Protocol clock

BIU

FlexCAN

Module clock

Protocol clock

BIU

FCU

Module clock

Protocol clock

BIU

STM

Module clock

BIU

ECSM

Module clock

BIU

SIUL

Module clock

BIU

SSCM

Module clock

BIU

WKPU

Module clock

BIU

PIT/RTI

Module clock

BIU

Data Flash 0

Code Flash 0

MC Unit

Module clock

BIU

CGM

RGM

PCU

PMU

FMPLL_0

CQM_0

IRCOSC

XOSC

SYS_CLK

Platform Flash Controller

Module clock

BIU

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 83

• Internal RC oscillator clock (IRC)

• Progressive output clock of FMPLL_0

• Directly from the oscillator clock (XOSC)

Its behavior is configured via software through ME_x_MC register of the ME module.

When the standard boot from internal flash is selected via the boot configuration pins, the clock source for

the system clock (SYS_CLK) after reset (DRUN mode) is the internal RC oscillator (IRC).

4.2.3 Auxiliary Clock Selector 0

There is no Auxiliary Clock present on MPC5602P device, but to maintain the software compatibility,

corresponding register in MC_CGM (CGM_AC0_SC) has been implemented through which user can

select any clock source from the given auxiliary clock sources. As there is no auxiliary clock, all the

auxiliary clock sources have been tied to ‘0’.

4.2.4 Auxiliary Clock Selector 1

There is no Auxiliary Clock present on MPC5602P device, but to maintain the software compatibility,

corresponding register in MC_CGM (CGM_AC1_SC) has been implemented through which user can

select any clock source from the given auxiliary clock sources. As there is no auxiliary clock, all the

auxiliary clock sources have been tied to ‘0’.

4.2.5 Auxiliary Clock Selector 2

There is no Auxiliary Clock present on MPC5602P device, but to maintain the software compatibility,

corresponding register in MC_CGM (CGM_AC2_SC) has been implemented through which user can

select any clock source from the given auxiliary clock sources. As there is no auxiliary clock, all the

auxiliary clock sources have been tied to ‘0’.

4.2.6 Auxiliary clock dividers

As there is no auxiliary clock present on MPC5602P, there is no point in having the auxiliary clock

dividers. To maintain the software compatibility, one divider corresponding to every auxiliary clock has

been implemented. Corresponding registers have been implemented in MC_CGM which can be accessed

by user but have no impact in device. These registers are CGM_AC0_DC0, CGM_AC1_DC0, and

CGM_AC2_DC0

4.2.7 External clock divider

The output clock divider provides a nominal 50% duty cycle clock and allows the selected output clock

source to be divided with these divide options:

• ÷ 1, ÷ 2, ÷ 4, ÷ 8

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

84 Freescale Semiconductor

4.3 Alternate module clock domains

This section lists the different clock domains for each module. If not otherwise noted, all modules on the

MPC5602P device are clocked on the SYS_CLK.

4.3.1 FlexCAN clock domains

The FlexCAN modules have two distinct software controlled clock domains. One of the clock domains is

always derived from the system clock. This clock domain includes the message buffer logic. The source

for the second clock domain can be either the system clock (SYS_CLK) or a direct feed from the oscillator

pin XOSC_CLK. The logic in the second clock domain controls the CAN interface pins. The CLK_SRC

bit in the FlexCAN CTRL register selects between the system clock and the oscillator clock as the clock

source for the second domain. Selecting the oscillator as the clock source ensures very low jitter on the

CAN bus. System software can gate both clocks by writing to the MDIS bit in the FlexCAN MCR.

Figure 22-1 shows the two clock domains in the FlexCAN modules.

Refer to Chapter 22, “FlexCAN for more information on the FlexCAN modules.

4.3.2 SWT clock domains

The SWT module has two distinct clock domains. The first clock domain (Module Clock) is always

supplied from the SYS_CLK. This clock domain includes the register interface.

The source for the second clock domain (Protocol Clock) is always the IRC generated by the internal RC

oscillator.

4.3.3 Cross Triggering Unit (CTU) clock domains

The CTU module has two distinct clock domains. The first clock domain (Module Clock) is supplied from

the SYS_CLK. This clock domain includes the Command Buffer logic.

The source for the second clock domain (Protocol Clock) is the MC_PLL_CLK. The logic in the Protocol

Clock domain controls the CTU interface pins to the eTimer module and the ADC module.

4.3.4 Peripherals behind the IPS bus clock sync bridge

4.3.4.1 FlexPWM clock domain

The FlexPWM module has only one clock domain. The FlexPWM module is clocked from the

MC_PLL_CLK. Therefore, it is placed behind the IPS bus clock sync bridge.

4.3.4.2 eTimer_0 clock domain

The eTimer_0 module has only one clock domain. The eTimer_0 module is clocked from the

MC_PLL_CLK. Therefore, it is placed behind the IPS bus clock sync bridge.

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 85

4.3.4.3 ADC_0 clock domain

The ADC_0 module has only one clock domain. The ADC_0 module is clocked from the MC_PLL_CLK.

Therefore, it is placed behind the IPS bus clock sync bridge.

4.3.4.4 Safety Port clock domains

The Safety Port module has two distinct software-controlled clock domains. The first clock domain

(Module Clock) is always supplied from the SP_PLL_CLK. The source for the second clock domain

(Protocol Clock) can either be the SP_PLL_CLK or the XOSC_CLK.

The user must ensure that the frequency of the first clock domain (Module Clock) clocked from the

MC_PLL_CLK is always the same or greater than the clock selected for the second clock domain

(Protocol Clock).

4.4 Clock behavior in STOP and HALT mode

In this section the term “resume” is used to describe the transition from STOP and HALT mode back to a

RUN mode.

The MPC5602P supports the STOP and the HALT modes. These two modes allow to put the device into

a power saving mode with the configuration options defined in the ME module.

The following constraints are applied on MPC5602P to guarantee that in all modes of operation a resume

from STOP or HALT mode is always possible without the need to reset:

• STOP and HALT mode:

— SIUL clock is not gateable

— SIUL filter for external interrupt capable pins is always clocked with IRC

— Resume via interrupt that can be generated by any peripheral that clock is not gated

— Resume via NMI pin is always possible if once enabled after reset (no software configuration

that could block resume afterwards)

• STOP mode:

— IRC can NOT be switched off

— The System Clock Selector 0 is switched to the IRC and therefore the SYS_CLK is feed by the

IRC signal

— Resume via external interrupt pin is always possible (if not masked)

• HALT mode:

— The output of the System Clock Selector 0 can only be switched to a running clock input

— Resume via external interrupt pin is always possible (if not masked) and IRC is not switched off

4.5 System clock functional safety

This section shows the MPC5602P modules used to detect clock failures:

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

86 Freescale Semiconductor

• The Clock Monitoring Unit (CMU_0) monitors the clock frequency of the FMPLL_0 and the

XOSC signal against the IRC and provides clock out of range information about the monitored

clock signals.

• FMPLL_0 provides a signal that indicates a loss of lock. Each loss of lock signal is sent to the CGM

module.

Upon the detection of one of the above mentioned failures, the MPC5602P device either asserts a reset,

generates an interrupt, or sends the device into the SAFE state.

The reaction to each of the clock failures and system parameters (like active clocks and SYS_CLK clock

source) that become active in SAFE state are under software control and can be configured in the ME

module.

4.6 IRC 16 MHz internal RC oscillator (RC_CTL)

The IRC output frequency can be trimmed using RCTRIM bits. After a power-on reset, the IRC is trimmed

using a factory test value stored in test flash memory. However, after a power-on reset the test flash

memory value is not visible at RC_CTL[RCTRIM], and this field shows a value of zero. Therefore, be

aware that the RC_CTL[RCTRIM] field does not reflect the current trim value until you have written to

it. Pay particular attention to this feature when you initiate a read-modify-write operation on RC_CTL,

because a RCTRIM value of zero may be unintentionally written back and this may alter the IRC

frequency. In this case, you should calibrate the IRC using the CMU.

In this oscillator, two's complement trimming method is implemented. So the trimming code increases

from -32 to 31. As the trimming code increases, the internal time constant increases and frequency reduces.

Please refer to device datasheet for average frequency variation of the trimming step.

Address:

0xC3FE_0060

(Base + 0x0000)

Access: Supervisor read/write; User read-only

0123456789101112131415

R0000000000 RCTRIM[5:0]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000000000000000

Reset0000000000000000

Figure 4-4. RC Control register (RC_CTL)

Table 4-1. RC_CTL field descriptions

Field Description

RCTRIM[5:0] Main RC trimming bits

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 87

4.7 XOSC external crystal oscillator

The external crystal oscillator (XOSC) operates in the range of 4 MHz to 40 MHz. The XOSC digital

interface contains the control and status registers accessible for the external crystal oscillator.

Main features are:

• Oscillator clock available interrupt

• Oscillator bypass mode

4.7.1 Functional description

The crystal oscillator circuit includes an internal oscillator driver and an external crystal circuitry. The

XOSC provides an output clock to the PLL or it is used as a reference clock to specific modules depending

on system needs.

The crystal oscillator can be controlled by the ME:

• Control by ME module. The OSCON bit of the ME_xxx_MCRs controls the powerdown of

oscillator based on the current device mode while S_OSC of ME_GS register provides the

oscillator clock available status.

After system reset, the oscillator is put to power down state and software has to switch on when required.

Whenever the crystal oscillator is switched on from off state, OSCCNT counter starts and when it reaches

the value EOCV[7:0] × 512, oscillator clock is made available to the system. Also an interrupt pending bit

I_OSC of OSC_CTL register is set. An interrupt will be generated if the interrupt mask bit M_OSC is set.

The oscillator circuit can be bypassed by setting OSC_CTL[OSCBYP]. This bit can only be set by the

software. System reset is needed to reset this bit. In this bypass mode, the output clock has the same

polarity as external clock applied on EXTAL pin and the oscillator status is forced to ‘1’. The bypass

configuration is independent of the powerdown mode of the oscillator.

Table 4-2 shows the truth table of different configurations of oscillator.

Table 4-2. Crystal oscillator truth table

ENABLE BYP XTALIN EXTAL CK_OSCM XOSC Mode

0 0 No crystal,

High Z

No crystal,

High Z

0 Power down, IDDQ

x 1 x Ext clock EXTAL Bypass, XOSC disabled

1 0 Crystal Crystal EXTAL Normal, XOSC enabled

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

88 Freescale Semiconductor

4.7.2 Register description

Table 4-3. OSC_CTL memory map

Offset from

OSC_CTL_BASE

(0xC3FE_0000)

Access

Reset value Location

0x0000 OSC_CTL—Oscillator control register R/W 0x0080_0000 on page 88

0x0004–0x000F Reserved

Address:

0xC3FE_0000

(Base + 0x0000)

Access: Supervisor read/write; User read-only

0123456789101112131415

ROSC

BYP

0000000EOCV[7:0]

Reset0000000010000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RM_

OSC

0000000I_

OSC 0000000

Ww1c

Reset0000000000000000

Figure 4-5. Crystal Oscillator Control register (OSC_CTL)

Table 4-4. OSC_CTL field descriptions

Field Description

OSCBYP Crystal Oscillator bypass

This bit specifies whether the oscillator should be bypassed or not. Software can only set this bit.

System reset is needed to reset this bit.

0: Oscillator output is used as root clock.

1: EXTAL is used as root clock.

EOCV[7:0] End of Count Value

These bits specify the end of count value to be used for comparison by the oscillator stabilization

counter OSCCNT after reset or whenever it is switched on from the off state. This counting period

ensures that external oscillator clock signal is stable before it can be selected by the system. When

oscillator counter reaches the value EOCV[7:0]*512, oscillator available interrupt request is generated.

The reset value of this field depends on the device specification. The OSCCNT counter will be kept

under reset if oscillator bypass mode is selected.

M_OSC Crystal oscillator clock interrupt mask

0: Crystal oscillator clock interrupt masked

1: Crystal oscillator clock interrupt enabled

I_OSC Crystal oscillator clock interrupt

This bit is set by hardware when OSCCNT counter reaches the count value EOCV[7:0]*512. It is

cleared by software by writing 1.

0: No oscillator clock interrupt occurred

1: Oscillator clock interrupt pending

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 89

4.8 Frequency Modulated Phase Locked Loop (FMPLL)

4.8.1 Introduction

This section describes the features and functions of the FMPLL module implemented in MPC5602P.

4.8.2 Overview

The FMPLL enables the generation of high speed system clocks from a common 4–40 MHz input clock.

Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL

multiplication factor and output clock divider ratio are all software configurable.

The FMPLL block diagram is shown in Figure 4-6.

Figure 4-6. FMPLL block diagram

4.8.3 Features

The FMPLL has the following major features:

• Input clock frequency 4–40 MHz

• Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz

• Reduced frequency divider (RFD) for reduced frequency operation without forcing the FMPLL to

relock

• Frequency modulated PLL

— Modulation enabled/disabled through software

— Triangle wave modulation

• Programmable modulation depth

— ±0.25% to ±4% deviation from center spread frequency

— –0.5% to +8% deviation from down spread frequency

— Programmable modulation frequency dependent on reference frequency

• Self-clocked mode (SCM) operation

• 4 available modes

— Normal mode

— Progressive clock switching

BUFFER

Charge

Pump

Low Pass

Filter

VCO

IDF

DIV2

Loop

Division

Factor

XOSC

Output

PHI

(LDF)

CR[NDIV]

Division

Factor

(ODF)

CR[ODF]

DIV4

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

90 Freescale Semiconductor

— Normal Mode with SSCG

— Powerdown mode

4.8.4 Memory map

Table 4-5 shows the memory map locations. Addresses are given as offsets of the module base address.

4.8.5 Register description

The PLL operation is controlled by two registers. Those registers can only be written in supervisor mode.

4.8.5.1 Control Register (CR)

Table 4-5. FMPLL memory map

Offset from

ME_CGM_BASE

FMPLL_0: 0xC3FE_00A0

1FMPLL_x are mapped through the ME_CGM Register Slot

Access

Reset value Location

0x0000 CR—Control Register R/W 0x0080_0000 on page 90

0x0004 MR—Modulation register R/W 0x0080_0000 on page 92

0x0004–0x000F Reserved

Address:

Base + 0x0000

FMPLL_0 = 0xC3FE_00A0

Access: Supervisor read/write

User read-only

0123456789101112131415

R 0 0 IDF[3:0] ODF[1:0] 0NDIV[6:0]

Reset0000010101000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

0000000

en_pll

_sw

unlock

_once

0 i_lock

s_lock pll_fail

_mask

pll_fai

l_flag 1

Ww1c w1c

Reset0000000000000001

Figure 4-7. Control Register (CR)

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 91

Table 4-6. CR field descriptions

Field Description

IDF[3:0] Input Division Factor

The value of this field sets the PLL input division factor.

0000: Divide by 1

0001: Divide by 2

0010: Divide by 3

0011: Divide by 4

0100: Divide by 5

0101: Divide by 6

0110: Divide by 7

0111: Divide by 8

1000: Divide by 9

1001: Divide by 10

1010: Divide by 11

1011: Divide by 12

1100: Divide by 13

1101: Divide by 14

1110: Divide by 15

1111: Clock Inhibit

ODF[1:0] Output Division Factor

The value of this field sets the PLL output division factor.

00: Divide by 2

01: Divide by 4

10: Divide by 8

11: Divide by 16

NDIV[6:0] Loop Division Factor

The value of this field sets the PLL loop division factor.

0000000–0011111: Reserved

0100000: Divide by 32

0100001: Divide by 33

0100010: Divide by 34

...

1011111: Divide by 95

1100000: Divide by 96

1100001–1111111: Reserved

en_pll_sw This bit is used to enable progressive clock switching. After the PLL locks, the PLL output initially

is divided by 8, and then progressively decreases until it reaches divide-by-1.

Note: The PLL output should not be used if a non-changing clock is needed, such as for serial

communications, until the division has finished.

0: Progressive clock switching disabled

1: Progressive clock switching enabled

unlock_once This bit is a sticky indication of PLL loss of lock condition. Unlock_once is set when the PLL loses

lock. Whenever the PLL reacquires lock, unlock_once remains set. unlock_once is cleared after a

POR event.

i_lock This bit is set by hardware whenever there is a lock/unlock event.It is cleared by software, writing 1.

s_lock This bit indicates whether the PLL has acquired lock.

0: PLL unlocked

1: PLL locked

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

92 Freescale Semiconductor

4.8.5.2 Modulation Register (MR)

pll_fail_mask This bit masks the pll_fail output.

0: pll_fail not masked

1: pll_fail masked

pll_fail_flag This bit is asynchronously set by hardware whenever a loss of lock event occurs while PLL is

switched on. It is cleared by software, writing 1.

Address:

Base + 0x0004 Access: Supervisor read/write

User read-only

0123456789101112131415

STRB

_BYPA

0SPRD

_SEL

MOD_PERIOD

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RFM_

EN INC_STEP

Reset0000000000000000

Figure 4-8. Modulation Register (MR)

Table 4-7. MR field descriptions

Field Description

STRB_BYPASS Strobe bypass

The STRB_BYPASS signal bypasses the STRB signal used inside the PLL to latch the correct

values for control bits (INC_STEP, MOD_PERIOD and SPRD_SEL).

0: STRB latches the PLL modulation control bits.

1: STRB is bypassed. In this case, the control bits need to be static. The control bits must be

changed only when PLL is in power down mode.

SPRD_SEL Spread type selection

The SPRD_SEL bit selects the spread type in Frequency Modulation mode.

0: Center spread

1: Down spread

MOD_PERIOD Modulation period

The MOD_PERIOD field is the binary equivalent of the value modperiod derived from following

formula:

where:

fref: represents the frequency of the feedback divider

fmod: represents the modulation frequency

Table 4-6. CR field descriptions (continued)

Field Description

modperiod fref

mod



--------------------

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 93

4.8.6 Functional description

4.8.6.1 Normal mode

In Normal mode, the PLL inputs are driven by the Control Register (CR). This means that when the PLL

is locked, the PLL output clock (PHI) is derived from the reference clock (XOSC) through this

relationship:

Eqn. 4-1

where the value of idf (Input Division Factor), ldf (Loop Division Factor), and odf (Output Division Factor)

are set in the CR as shown in Table 4-6. idf and odf are specified in the IDF and ODF bitfields, respectively;

ldf is specified in the NDIV bitfield.

4.8.6.2 Progressive clock switching

Progressive clock switching allows to switch system clock to PLL output clock stepping through different

division factors. This means that the current consumption gradually increases and, in turn, voltage

regulator response is improved.

This feature can be enabled by programming bit en_pll_sw in the CR. Then, when the PLL is selected as

the system clock, the output clock progressively increases its frequency as shown in Table 4-8.

FM_EN Frequency modulation enable

The FM_EN bit enables the frequency modulation.

0: Frequency Modulation disabled

1: Frequency Modulation enabled

INC_STEP Increment step

The INC_STEP field is the binary equivalent of the value incstep derived from following formula:

where:

md: represents the peak modulation depth in percentage

(Center spread — pk-pk = ±md, Downspread — pk-pk = –2 × md)

MDF: represents the nominal value of loop divider (NDIV in PLL Control Register).

Table 4-8. Progressive clock switching on pll_select rising edge

Number of PLL output clock cycles ck_pll_div frequency (PLL output frequency)

8 (ck_pll_out frequency) 8

16 (ck_pll_out frequency) 4

32 (ck_pll_out frequency) 2

Table 4-7. MR field descriptions (continued)

Field Description

incstep round 215 1–mdMDF

100 5MODPERIOD

---------------------------------------------------------------





phi xosc ldf

idf odf

-----------------------

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

94 Freescale Semiconductor

Figure 4-9. Progressive clock switching scheme

4.8.6.3 Normal Mode with frequency modulation

The FMPLL default mode is without frequency modulation enabled. When frequency modulation is

enabled, however, two parameters must be set to generate the desired level of modulation: the PERIOD,

and the STEP. The modulation waveform is always a triangle wave and its shape is not programmable.

Frequency modulation is activated as follows:

1. Configure the FM modulation characteristics: MOD_PERIOD, INC_STEP.

2. Enable the FM modulation by programming bit SSCG_EN of the MR to ‘1’. FM modulated mode

can be enabled only when PLL is in lock state.

There are two ways to latch these values inside the FMPLL, depending on the value of bit STRB_BYPASS

in the MR.

If STRB_BYPASS is low, the modulation parameters are latched in the PLL only when the strobe signal

goes high. The strobe signal is automatically generated in the FMPLL when the modulation is enabled

(SSCG_EN goes high) if the PLL is locked (s_lock = 1) or when the modulation has been enabled

(SSCG_EN = 1) and PLL enters in lock state (s_lock goes high).

If STRB_BYPASS is high, the strobe signal is bypassed. In this case, control bits (MOD_PERIOD[12:0],

INC_STEP[14:0], SPREAD_CONTROL) must be changed only when the PLL is in power down mode.

The modulation depth in % is

Eqn. 4-2

NOTE

The user must ensure that the product of INCSTEP and MODPERIOD is

less than (215 –1).

The following values show the input setting for one possible configuration of the PLL:

• PLL input frequency: 4 MHz

• Loop divider (LDF): 64

• Input divider (IDF): 1

• VCO frequency = 4 MHz × 64 = 256 MHz

onward (ck_pll_out frequency)

Table 4-8. Progressive clock switching on pll_select rising edge (continued)

Number of PLL output clock cycles ck_pll_div frequency (PLL output frequency)

Division factors

ck_pll_out ck_pll_div

of 8, 4, 2, or 1

ModulationDepth 100 5INCSTEPxMODPERIOD

215 1–MDF

---------------------------------------------------------------------------------------------





Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 95

• PLL output frequency = 256 MHz/ODF

• Spread: Center spread (SPREAD_CONTROL = 0)

• Modulation frequency = 24 kHz

• Modulation depth = ±2.0% (4% pk-pk)

Using the formulae for MODPERIOD and INCSTEP:

MODPERIOD = Round [(4e06) / (4 × 24e03)] = Round [41.66] = 42 Eqn. 4-3

INCSTEP = Round [((215 – 1) × 2 × 64) / (100 × 5 × 42)] = Round [199.722] = 200 Eqn. 4-4

MODPERIOD × INCSTEP = 42 × 200 = 8400 (which is less than 215)Eqn. 4-5

md(quantized)% = ((42*200*100*5) / ((2^15-1)*64) = 2.00278% (peak) Eqn. 4-6

Error in modulation depth = 2.00278 - 2.0 = 0.00278% Eqn. 4-7

If we choose MODPERIOD = 41,

INCSTEP = Round [((215 – 1) × 2 × 64) / (100 × 5 × 41)] = Round [204.878] = 205 Eqn. 4-8

MODPERIOD × INCSTEP = 41 × 205 = 8405 (which is less than 215)Eqn. 4-9

md(quantized)% = ((41 × 205 × 100 × 5) / ((215 – 1) × 64) = 2.00397% (peak) Eqn. 4-10

Error in modulation depth = 2.00397 – 2.0 = 0.00397% Eqn. 4-11

The above calculations show that the quantization error in the modulation depth depends on the flooring

and rounding of MODPERIOD and INCSTEP. For this reason, the MODPERIOD and INCSTEP should

be judiciously rounded/floored to minimize the quantization error in the modulation depth.

Figure 4-10. Frequency modulation depth spreads

Time

Frequency

Center Spread

Down Spread

2× md

Tmod 2Tmod

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

96 Freescale Semiconductor

4.8.6.4 Powerdown mode

To reduce consumption, the FMPLL can be switched off when not required by programming the registers

ME_x_MC on the ME module.

4.8.7 Recommendations

To avoid any unpredictable behavior of the PLL clock, it is recommended to follow these guidelines:

• The PLL VCO frequency should reside in the range 256 MHz to 512 MHz. Care is required when

programming the multiplication and division factors to respect this requirement.

• The user must change the multiplication, division factors only when the PLL output clock is not

selected as system clock. MOD_PERIOD, INC_STEP, SPREAD_SEL bits should be modified

before activating the FM modulated mode. Then strobe has to be generated to enable the new

settings. If STRB_BYP is set to ‘1’ then MOD_PERIOD, INC_STEP and SPREAD_SEL can be

modified only when PLL is in power down mode.

• Use progressive clock switching.

4.9 Clock Monitor Unit (CMU)

4.9.1 Overview

The Clock Monitor Unit (CMU) serves three purposes:

• PLL clock monitoring: detects if PLL leaves an upper or lower frequency boundary

• XOSC clock monitoring: monitor the XOSC clock, which must be greater than the IRCOSC clock

divided by a division factor given by CMU_CSR[RCDIV]

• Frequency meter: measure the frequency of the IRCOSC clock versus the reference XOSC clock

frequency

When mismatch occurs in the CMU either with the PLL monitor or the XOSC monitor, the CMU notifies

the RGM, ME and the FCU (Fault Collection Unit) modules. The default behavior is such that a reset

occurs and a status bit is set in the RGM. The user also has the option to change the behavior of the action

by disabling the reset and selecting an alternate action. The alternate action can be either entering safe

mode or generating an interrupt.

Table 4-9. CMU module summary

Module Monitored clocks

CMU_0 • XOSC integrity supervisor

• FMPLL_0 integrity supervisor

• IRCOSC frequency meter

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 97

Figure 4-11. MPC5602PCMU

4.9.2 Main features

• RC oscillator frequency measurement

• External oscillator clock monitoring with respect to CK_IRC/n clock

• PLL clock frequency monitoring with respect to CK_IRC/4 clock

• Event generation for various failures detected inside monitoring unit

4.9.3 Functional description

The clock and frequency names referenced in this block are defined as follows:

• CK_XOSC: clock coming from the external crystal oscillator

• CK_IRC: clock coming from the low frequency internal RC oscillator

• CK_PLL: clock coming from the PLL

•f

XOSC: frequency of external crystal oscillator clock

•f

RC: frequency of low frequency internal RC oscillator

•f

PLL: frequency of FMPLL clock

4.9.3.1 Crystal clock monitor

If fXOSC is smaller than fRC divided by 2RCDIV bits of CMU_0_CSR and the CK_XOSC is ‘ON’ and stable

as signaled by the ME, then:

• An event pending bit OLRI in CMU_0_ISR is set

• A failure event OLR is signaled to the RGM and FCU, which in turn can generate either an

interrupt, a reset, or a SAFE mode request.

IRC_CLK

XOSC_CLK

FMPLL_0

16 MHz

4 to 40 MHz

64 MHz

CK 0 (reference)

CK XOSC

CK PLL

XOSC valid (on AND stable) / off

CMU_0

FLL

OLR

FMPLL_0 valid (on AND locked) / off

FCU

FMPLL_0 freq.

out of range

Loss of crystal

Clock

Control

Logic

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

98 Freescale Semiconductor

4.9.3.2 PLL clock monitor

The PLL clock CK_PLL frequency can be monitored by programming bit CME_0 of the CMU_0_CSR to

‘1’. The CK_PLL monitor starts as soon as bit CME_0 is set. This monitor can be disabled at any time by

writing bit CME_0 to ‘0’.

If the CK_PLL frequency (fPLL) is greater than a reference value determined by bits HFREF[11:0] of the

CMU_HFREFR and the CK_PLL is ‘ON’ and the PLL locked as signaled by the ME then:

• An event pending bit FHHI_0 in the CMU_0_ISR is set.

• A failure event FHH is signaled to the RGM and FCU, which in turn can generate either an

interrupt, a reset, or a SAFE mode request.

If fPLL is less than a reference clock frequency (fRC/4) and the CK_PLL is ‘ON’ and the PLL locked as

signaled by the ME, then:

• An event pending bit FLCI_0 in the CMU_0_ISR is set.

• A failure event FLC is signaled to the RGM and FCU, which in turn can generate either an

interrupt, a reset, or a SAFE mode request.

If fPLL is less than a reference value determined by bits LFREF[11:0] of the CMU_LFREFR and the

CK_PLL is ‘ON’ and the PLL locked as signaled by the ME, then:

• An event pending bit FLLI_0 in the CMU_0_ISR is set.

• A failure event FLL is signaled to the RGM and FCU, which in turn can generate either an

interrupt, a reset, or a SAFE mode request.

NOTE

It is possible for either the XOSC or PLL monitors to produce a false event

when the XOSC or PLL frequency is too close to RC/2RCDIV frequency due

to an accuracy limitation of the compare circuitry.

4.9.3.3 System clock monitor

The system clock is monitored by CMU_1. The FSYS_CLK frequency can be monitored by programming

CMU_1_CSR[CME] = 1. SYS_CLK monitoring starts as soon as CMU_1_CSR[CME] = 1. This

monitor can be disabled at any time by writing CME bit to 0.

If FSYS_CLK is greater than a reference value determined by the CMU_1_HFREFR_A[HFREF_A] bits and

the system clock is enabled, then:

• CMU_1_ISR[FHHI] is set

• A failure event is signaled to the MC_RGM and FCU, which in turn can generate a ‘functional'

reset, a SAFE mode request, or an interrupt

If FSYS_CLK is less than a reference clock frequency (FIRCOSC_CLK4) and the system clock is enabled,

then:

• CMU_1_ISR[FLCI] is set

• A failure event FLC is signaled to the MC_RGM and Fault Collection Unit, which in turn can

generate a ‘functional' reset, a SAFE mode request, or an interrupt

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 99

If FSYS_CLK is less than a reference value determined by the CMU_1_LFREFR_A[LFREF_A] bits and

the system clock is enabled, then:

• CMU_1_ISR[FLLI] is set

• A failure event is signaled to the MC_RGM and FCU, which in turn can generate a ‘functional’

reset, a SAFE mode request, or an interrupt

NOTE

The system clock monitor may produce a false event when FSYS_CLK is less

than 2FIRCOSC_CLK/2CMU_1_CSR[RCDIV] due to an accuracy limitation of

the compare circuitry.

4.9.3.4 Frequency meter

The frequency meter calibrates the internal RC oscillator (CK_IRC) using a known frequency.

NOTE

This value can then be stored into the flash so that application software can

reuse it later on.

The reference clock will be always the XOSC. A simple frequency meter returns a draft value of CK_IRC.

The measure starts when bit SFM (Start Frequency Measure) in the CMU_CSR is set to ‘1’. The

measurement duration is given by the CMU_MDR in numbers of IRC clock cycles with a width of 20 bits.

Bit SFM is reset to ‘0’ by hardware once the frequency measurement is done and the count is loaded in the

CMU_FDR. The frequency fRC can be derived from the value loaded in the CMU_FDR as follows:

fRC = (fOSC × MD) / n Eqn. 4-12

where n is the value in the CMU_FDR and MD is the value in the CMU_MDR.

4.9.4 Memory map and register description

Table 4-10 shows the memory map of the CMU.

Table 4-10. CMU memory map

Offset from

CMU_BASE

(0xC3FE_0100)

Access

Reset value Location

0x0000 Control Status Register (CMU_0_CSR) R/W 0x0000_0006 on page 100

0x0004 Frequency Display Register (CMU_0_FDISP) R 0x0000_0000 on page 101

0x0008 High Frequency Reference Register FMPLL_0

(CMU_0_HFREFR_A)

R/W 0x0000_0FFF on page 101

0x000C Low Frequency Reference Register FMPLL_0

(CMU_0_LFREFR_A)

R/W 0x0000_0000 on page 102

0x0010 Interrupt Status Register (CMU_0_ISR) R/W 0x0000_0000 on page 102

0x0014 Reserved

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

100 Freescale Semiconductor

4.9.4.1 Control Status Register (CMU_0_CSR)

0x0018 Measurement Duration Register (CMU_0_MDR) R/W 0x0000_0000 on page 103

0x001C–0x3FFF Reserved

Address:

Base + 0x0000 Access: User read/write

0123456789101112131415

R00000000SFM 0000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000000000000

RCDIV[1:0] CME

Reset0000000000000000

Figure 4-12. Control Status Register (CMU_0_CSR)

Table 4-11. CMU_0_CSR field descriptions

Field Description

SFM Start frequency measure

The software can only set this bit to start a clock frequency measure. It is reset by hardware when the

measure is ready in the CMU_FDR.

0: Frequency measurement completed or not yet started

1: Frequency measurement not completed

RCDIV[1:0] RC clock division factor

These bits specify the RC clock division factor. The output clock is CK_IRC divided by the factor 2RCDIV

This output clock is compared with CK_XOSC for crystal clock monitor feature.The clock division

coding is as follows.

00: Clock divided by 1 (no division)

01: Clock divided by 2

10: Clock divided by 4

11: Clock divided by 8

CME_0 FMPLL_0 clock monitor enable

0: FMPLL_0 monitor disabled

1: FMPLL_0 monitor enabled

Table 4-10. CMU memory map (continued)

Offset from

CMU_BASE

(0xC3FE_0100)

Access

Reset value Location

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 101

4.9.4.2 Frequency Display Register (CMU_0_FDR)

4.9.4.3 High Frequency Reference Register FMPLL_0 (CMU_0_HFREFR_A)

Address:

Base + 0x0004 Access: User read-only

0123456789101112131415

R000000000000 FD[19:16]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RFD[15:0]

Reset0000000000000000

Figure 4-13. Frequency Display Register (CMU_0_FDR)

Table 4-12. CMU_0_FDR field descriptions

Field Description

FD[19:0] Measured frequency bits

This register displays the measured frequency fRC with respect to fOSC. The measured value is given

by the following formula: fRC = (f

OSC × MD) / n, where n is the value in CMU_FDR.

Address:

Base + 0x0008 Access: User read/write

0123456789101112131415

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000 HFREF[11:0]

Reset0000111111111111

Figure 4-14. High Frequency Reference register FMPLL_0 (CMU_0_HFREFR_A)

Table 4-13. CMU_0_HFREFR_A field descriptions

Field Description

HFREF_A High Frequency reference value

These bits determine the high reference value for the FMPLL_0 clock. The reference value is given by:

(HFREF_A[11:0]/16) × (fRC/4).

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

102 Freescale Semiconductor

4.9.4.4 Low Frequency Reference Register FMPLL_0 (CMU_0_LFREFR_A)

4.9.4.5 Interrupt Status Register (CMU_0_ISR)

Address:

Base + 0x000C Access: User read/write

0123456789101112131415

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000 LFREF[11:0]

Reset0000000000000000

Figure 4-15. Low Frequency Reference Register FMPLL_0 (CMU_0_LFREFR_A)

Table 4-14. CMU_0_LFREFR_A fields descriptions

Field Description

LFREF_A Low Frequency reference value

These bits determine the low reference value for the FMPLL_0. The reference value is given by:

(LFREF_A[11:0]/16) * (fRC/4).

Address:

Base + 0x0010 Access: User read/write

0123456789101112131415

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R000000000000

FLCI

FHHI

FLLI

_0 OLRI

Ww1c w1c w1c w1c

Reset0000000000000000

Figure 4-16. Interrupt Status Register (CMU_0_ISR)

Table 4-15. CMU_0_ISR field descriptions

Field Description

FLCI_0 FMPLL_0 Clock frequency less than reference clock interrupt

This bit is set by hardware when CK_FMPLL_0 frequency becomes lower than reference clock

frequency (fRC/4) value and CK_FMPLL_0 is ‘ON’ and the PLL locked as signaled by the ME. It can be

cleared by software by writing 1.

0: No FLC event

1: FLC event pending

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 103

4.9.4.6 Measurement Duration Register (CMU_0_MDR)

FHHI_0 FMPLL_0 Clock frequency higher than high reference interrupt

This bit is set by hardware when CK_FMPLL_ 0 frequency becomes higher than HFREF_A value and

CK_FMPLL_0 is ‘ON’ and the PLL locked as signaled by the ME. It can be cleared by software by

writing 1.

0: No FHH event

1: FHH event pending

FLLI_0 FMPLL_0 Clock frequency less than low reference event

This bit is set by hardware when CK_FMPLL_0 frequency becomes lower than LFREF_A value and

CK_FMPLL_0 is ‘ON’ and the PLL locked as signaled by the ME. It can be cleared by software by

writing 1.

0: No FLL event

1: FLL event pending

OLRI Oscillator frequency less than RC frequency event

This bit is set by hardware when the frequency of CK_XOSC is less than CK_IRC/2RCDIV frequency and

CK_XOSC is ‘ON’ and stable as signaled by the ME. It can be cleared by software by writing 1.

0: No OLR event

1: OLR event pending

Address:

Base + 0x0018 Access: User read/write

0123456789101112131415

R000000000000 MD[19:16]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RMD[15:0]

Reset0000000000000000

Figure 4-17. Measurement Duration Register (CMU_0_MDR)

Table 4-16. CMU_0_MDR field descriptions

Field Description

MD[19:0] Measurement duration bits

This register displays the measured duration in term of IRC clock cycles. This value is loaded in the

frequency meter downcounter. When SFM bit is set to ‘1’, downcounter starts counting.

Table 4-15. CMU_0_ISR field descriptions (continued)

Field Description

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

104 Freescale Semiconductor

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 105

Chapter 5

Clock Generation Module (MC_CGM)

5.1 Overview

The clock generation module (MC_CGM) generates reference clocks for all the SoC blocks. The

MC_CGM selects one of the system clock sources to supply the system clock. The MC_ME controls the

system clock selection (see the MC_ME chapter for more details). Peripheral clock selection is controlled

by MC_CGM control registers. A set of MC_CGM registers controls the clock dividers which are used for

divided system and peripheral clock generation. The memory spaces of system and peripheral clock

sources which have addressable memory spaces are accessed through the MC_CGM memory space. The

MC_CGM also selects and generates an output clock.

Figure 5-1 depicts the MC_CGM Block Diagram.

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

106 Freescale Semiconductor

5.2 Features

The MC_CGM includes the following features:

• generates system and peripheral clocks

• selects and enables/disables the system clock supply from system clock sources according to

MC_ME control

• contains a set of registers to control clock dividers for divided clock generation

Output Clock

Selector/Divider

Registers

Platform Interface

core

MC_CGM

Figure 5-1. MC_CGMBlock Diagram

MC_ME

Auxiliary Clock

Selector/Divider

System Clock

Multiplexer/Divider

XOSC0

PLL0

16 MHz_IRC

Mapped Modules Interface

mapped

peripherals

PA D [ 2 2 ]

MC_RGM

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 107

• contains a set of registers to control peripheral clock selection

• supports multiple clock sources and maps their address spaces to its memory map

• generates an output clock

• guarantees glitch-less clock transitions when changing the system clock selection

• supports 8, 16 and 32-bit wide read/write accesses

5.3 External Signal Description

The MC_CGM delivers an output clock to the PAD[22] pin for off-chip use and/or observation.

5.4 Memory Map and Register Definition

NOTE

Any access to unused registers as well as write accesses to read-only

registers will not change register content, and cause a transfer error.

Table 5-1. MC_CGM Register Description

Address Name Description Size

Access

Location

User Supervisor Test

0xC3FE

_0370

CGM_OC_EN Output Clock Enable word read read/write read/write on page 112

0xC3FE

_0374

CGM_OCDS_SC Output Clock Division

Select

byte read read/write read/write on page 113

0xC3FE

_0378

CGM_SC_SS System Clock Select

Status

byte read read read on page 114

0xC3FE

_037C

CGM_SC_DC0 System Clock Divider

Configuration 0

byte read read/write read/write on page 114

0xC3FE

_0380

CGM_AC0_SC Aux Clock 0 Select

Control

word read read/write read/write on page 115

0xC3FE

_0384

CGM_AC0_DC0 Aux Clock 0 Divider

Configuration 0

byte read read/write read/write on page 116

0xC3FE

_0388

CGM_AC1_SC Aux Clock 1 Select

Control

word read read/write read/write on page 116

0xC3FE

_038C

CGM_AC1_DC0 Aux Clock 1 Divider

Configuration 0

byte read read/write read/write on page 117

0xC3FE

_0390

CGM_AC2_SC Aux Clock 2 Select

Control

word read read/write read/write on page 118

0xC3FE

_0394

CGM_AC2_DC0 Aux Clock 2 Divider

Configuration 0

byte read read/write read/write on page 119

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

108 Freescale Semiconductor

Table 5-2. MC_CGM Memory Map

0xC3FE

_0000

…

0xC3FE

_001C

XOSC registers

0xC3FE

_0020

…

0xC3FE

_003C

reserved

0xC3FE

_0040

…

0xC3FE

_005C

reserved

0xC3FE

_0060

…

0xC3FE

_007C

IRCOSC registers

0xC3FE

_0080

…

0xC3FE

_009C

reserved

0xC3FE

_00A0

…

0xC3FE

_00BC

PLL0 registers

0xC3FE

_00C0

…

0xC3FE

_00DC

reserved

0xC3FE

_00E0

…

0xC3FE

_00FC

reserved

0xC3FE

_0100

…

0xC3FE

_011C

CMU0 registers

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 109

0xC3FE

_0120

…

0xC3FE

_013C

reserved

0xC3FE

_0140

…

0xC3FE

_015C

reserved

0xC3FE

_0160

…

0xC3FE

_017C

reserved

0xC3FE

_0180

…

0xC3FE

_019C

reserved

0xC3FE

_01A0

…

0xC3FE

_01BC

reserved

0xC3FE

_01C0

…

0xC3FE

_01DC

reserved

0xC3FE

_01E0

…

0xC3FE

_01FC

reserved

0xC3FE

_0200

…

0xC3FE

_021C

reserved

0xC3FE

_0220

…

0xC3FE

_023C

reserved

Table 5-2. MC_CGM Memory Map (continued)

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

110 Freescale Semiconductor

0xC3FE

_0240

…

0xC3FE

_025C

reserved

0xC3FE

_0260

…

0xC3FD

_C27C

reserved

0xC3FE

_0280

…

0xC3FE

_029C

reserved

0xC3FE

_02A0

…

0xC3FE

_02BC

reserved

0xC3FE

_02C0

…

0xC3FE

_02DC

reserved

0xC3FE

_02E0

…

0xC3FE

_02FC

reserved

0xC3FE

_0300

…

0xC3FE

_031C

reserved

0xC3FE

_0320

…

0xC3FE

_033C

reserved

0xC3FE

_0340

…

0xC3FE

_035C

reserved

Table 5-2. MC_CGM Memory Map (continued)

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 111

0xC3FE

_0360

…

0xC3FE

_036C

reserved

0xC3FE

_0370

CGM_OC_ENR0000000000000000

R000000000000000

0xC3FE

_0374

CGM_OCDS_

R0 0

SELDIV SELCTL

00000000

R0000000000000000

0xC3FE

_0378

CGM_SC_SSR0000 SELSTAT 00000000

R0000000000000000

0xC3FE

_037C

CGM_SC_DC

DE0

000

DIV0

00000000

R0000000000000000

0xC3FE

_0380

CGM_AC0_S

R0000

SELCTL

00000000

R0000000000000000

0xC3FE

_0384

CGM_AC0_D

DE0

000

DIV0

00000000

R0000000000000000

0xC3FE

_0388

CGM_AC1_S

R0000

SELCTL

00000000

R0000000000000000

Table 5-2. MC_CGM Memory Map (continued)

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

112 Freescale Semiconductor

5.5 Register Descriptions

All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered

according to big endian. For example, the CGM_OC_EN register may be accessed as a word at address

0xC3FE_0370, as a half-word at address 0xC3FE_0372, or as a byte at address 0xC3FE_0373.

5.5.1 Output Clock Enable Register (CGM_OC_EN)

This register is used to enable and disable the output clock.

0xC3FE

_038C

CGM_AC1_D

DE0

000

DIV0

00000000

R0000000000000000

0xC3FE

_0390

CGM_AC2_S

R0000

SELCTL

00000000

R0000000000000000

0xC3FE

_0394

CGM_AC2_D

DE0

000

DIV0

00000000

R0000000000000000

0xC3FE

_0398

…

0xC3FE

_3FFC

reserved

Address 0xC3FE_0370 Access: User read, Supervisor read/write, Test read/write

R0000000000000000

Reset0000000000000000

R000000000000000

Reset0000000000000000

Figure 5-2. Output Clock Enable Register (CGM_OC_EN)

Table 5-2. MC_CGM Memory Map (continued)

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 113

5.5.2 Output Clock Division Select Register (CGM_OCDS_SC)

This register is used to select the current output clock source and by which factor it is divided before being

delivered at the output clock.

Table 5-3. Output Clock Enable Register (CGM_OC_EN) Field Descriptions

Field Description

EN Output Clock Enable control

0 Output Clock is disabled

1 Output Clock is enabled

Address 0xC3FE_0374 Access: User read, Supervisor read/write, Test read/write

R0 0 SELDIV SELCTL 00000000

Reset0000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-3. Output Clock Division Select Register (CGM_OCDS_SC)

Table 5-4. Output Clock Division Select Register (CGM_OCDS_SC) Field Descriptions

Field Description

SELDIV Output Clock Division Select

00 output selected Output Clock without division

01 output selected Output Clock divided by 2

10 output selected Output Clock divided by 4

11 output selected Output Clock divided by 8

SELCTL Output Clock Source Selection Control — This value selects the current source for the output clock.

0000 16 MHz int. RC osc.

0001 4 MHz crystal osc.

0010 system PLL

0011 reserved

0100 reserved

0101 reserved

0110 reserved

0111 reserved

1000 reserved

1001 reserved

1010 reserved

1011 reserved

1100 reserved

1101 reserved

1110 reserved

1111 reserved

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

114 Freescale Semiconductor

5.5.3 System Clock Select Status Register (CGM_SC_SS)

This register provides the current system clock source selection.

5.5.4 System Clock Divider Configuration Register (CGM_SC_DC0)

This register controls the system clock divider.

Address 0xC3FE_0378 Access: User read, Supervisor read, Test read

R0000 SELSTAT 00000000

Reset0000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-4. System Clock Select Status Register (CGM_SC_SS)

Table 5-5. System Clock Select Status Register (CGM_SC_SS) Field Descriptions

Field Description

SELSTAT System Clock Source Selection Status — This value indicates the current source for the system clock.

0000 16 MHz int. RC osc.

0001 reserved

0010 4 MHz crystal osc.

0011 reserved

0100 system PLL

0101 reserved

0110 reserved

0111 reserved

1000 reserved

1001 reserved

1010 reserved

1011 reserved

1100 reserved

1101 reserved

1110 reserved

1111 system clock is disabled

Address 0xC3FE_037C Access: User read, Supervisor read/write, Test read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RDE0 000 DIV0 00000000

Reset1000000000000000

1514131211109876543210

R0000000000000000

Reset0000000000000000

Figure 5-5. System Clock Divider Configuration Register (CGM_SC_DC0)

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 115

5.5.5 Auxiliary Clock 0 Select Control Register (CGM_AC0_SC)

This register is used to select the current clock source for the following clocks:

• undivided: (unused)

• divided by auxiliary clock 0 divider 0: (unused)

See Figure 5-15 for details.

Table 5-6. System Clock Divider Configuration Register (CGM_SC_DC0) Field Descriptions

Field Description

DE0 Divider 0 Enable

0 Disable system clock divider 0

1 Enable system clock divider 0

DIV0 Divider 0 Division Value — The resultant divided system clock 0 will have a period DIV0 + 1 times that

of the system clock. If the DE0 is set to ‘0’ (Divider 0 is disabled), any write access to the DIV0 field is

ignored and the divided system clock 0 remains disabled.

Address 0xC3FE_0380 Access: User read, Supervisor read/write, Test read/write

R0000 SELCTL 00000000

Reset0000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-6. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC)

Table 5-7. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) Field Descriptions

Field Description

SELCTL Auxiliary Clock 0 Source Selection Control — This value selects the current source for auxiliary clock

0000 (no clock)

0001 reserved

0010 (no clock)

0011 reserved

0100 (no clock)

0101 (no clock)

0110 reserved

0111 reserved

1000 (no clock)

1001 reserved

1010 reserved

1011 reserved

1100 reserved

1101 reserved

1110 reserved

1111 reserved

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

116 Freescale Semiconductor

5.5.6 Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0)

This register controls the auxiliary clock 0 divider.

5.5.7 Auxiliary Clock 1 Select Control Register (CGM_AC1_SC)

This register is used to select the current clock source for the following clocks:

• undivided: (unused)

• divided by auxiliary clock 1 divider 0: (unused)

Address 0xC3FE_0384 Access: User read, Supervisor read/write, Test read/write

RDE0 000 DIV0 00000000

Reset1000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-7. Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0)

Table 5-8. Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0) Field Descriptions

Field Description

DE0 Divider 0 Enable

0 Disable auxiliary clock 0 divider 0

1 Enable auxiliary clock 0 divider 0

DIV0 Divider 0 Division Value — The resultant (unused) will have a period DIV0 + 1 times that of auxiliary

clock 0. If the DE0 is set to 0 (Divider 0 is disabled), any write access to the DIV0 field is ignored and the

(unused) remains disabled.

Address 0xC3FE_0388 Access: User read, Supervisor read/write, Test read/write

R0000 SELCTL 00000000

Reset0000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-8. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC)

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 117

5.5.8 Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0)

This register controls the auxiliary clock 1 divider.

Table 5-9. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) Field Descriptions

Field Description

SELCTL Auxiliary Clock 1 Source Selection Control — This value selects the current source for auxiliary clock

0000 (no clock)

0001 reserved

0010 reserved

0011 reserved

0100 reserved

0101 reserved

0110 reserved

0111 reserved

1000 reserved

1001 reserved

1010 reserved

1011 reserved

1100 reserved

1101 reserved

1110 reserved

1111 reserved

Address 0xC3FE_038C Access: User read, Supervisor read/write, Test read/write

RDE0 000 DIV0 00000000

Reset1000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-9. Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0)

Table 5-10. Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0) Field Descriptions

Field Description

DE0 Divider 0 Enable

0 Disable auxiliary clock 1 divider 0

1 Enable auxiliary clock 1 divider 0

DIV0 Divider 0 Division Value — The resultant (unused) will have a period DIV0 + 1 times that of auxiliary

clock 1. If the DE0 is set to 0 (Divider 0 is disabled), any write access to the DIV0 field is ignored and the

(unused) remains disabled.

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

118 Freescale Semiconductor

5.5.9 Auxiliary Clock 2 Select Control Register (CGM_AC2_SC)

This register is used to select the current clock source for the following clocks:

• undivided: (unused)

• divided by auxiliary clock 2 divider 0: (unused)

See Figure 5-13 for details.

Address 0xC3FE_0390 Access: User read, Supervisor read/write, Test read/write

R0000 SELCTL 00000000

Reset0000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-10. Auxiliary Clock 2 Select Control Register (CGM_AC2_SC)

Table 5-11. Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) Field Descriptions

Field Description

SELCTL Auxiliary Clock 2 Source Selection Control — This value selects the current source for auxiliary clock

0000 (no clock)

0001 reserved

0010 (no clock)

0011 reserved

0100 (no clock)

0101 (no clock)

0110 reserved

0111 reserved

1000 (no clock)

1001 reserved

1010 reserved

1011 reserved

1100 reserved

1101 reserved

1110 reserved

1111 reserved

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 119

5.5.10 Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0)

This register controls the auxiliary clock 2 divider.

5.6 Functional Description

5.7 System Clock Generation

Figure 5-12 shows the block diagram of the system clock generation logic. The MC_ME provides the

system clock select and switch mask (see MC_ME chapter for more details), and the MC_RGM provides

the safe clock request (see MC_RGM chapter for more details). The safe clock request forces the selector

to select the 16 MHz int. RC osc. as the system clock and to ignore the system clock select.

Address 0xC3FE_0394 Access: User read, Supervisor read/write, Test read/write

RDE0 000 DIV0 00000000

Reset1000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-11. Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0)

Table 5-12. Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) Field Descriptions

Field Description

DE0 Divider 0 Enable

0 Disable auxiliary clock 2 divider 0

1 Enable auxiliary clock 2 divider 0

DIV0 Divider 0 Division Value — The resultant (unused) will have a period DIV0 + 1 times that of auxiliary

clock 2. If the DE0 is set to 0 (Divider 0 is disabled), any write access to the DIV0 field is ignored and the

(unused) remains disabled.

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

120 Freescale Semiconductor

Figure 5-12. MC_CGM System Clock Generation Overview

5.7.1 System Clock Source Selection

During normal operation, the system clock selection is controlled

• on a SAFE mode or reset event, by the MC_RGM

• otherwise, by the MC_ME

5.7.2 System Clock Disable

During the TEST mode, the system clock can be disabled by the MC_ME.

5.7.3 System Clock Dividers

The MC_CGM generates the divided system clock 0 - controlled by the CGM_SC_DC0 register.

5.8 Auxiliary Clock Generation

Figure 5-13 shows the block diagram of the auxiliary clock generation logic. See Section 5.5.5, “Auxiliary

Clock 0 Select Control Register (CGM_AC0_SC), Section 5.5.7, “Auxiliary Clock 1 Select Control

(CGM_AC2_SC) for auxiliary clock selection control.

4 MHz crystal osc. 2

system PLL 4

system clock

’0’

CGM_SC_SS Register

MC_RGM SAFE mode request

ME_<current mode>

_MC.SYSCLK

CGM_SC_DC0 Register

clock divider divided system clock 0

system clock is disabled if

ME_<current mode>_MC.SYSCLK = “1111”

“0000” 1

16 MHz int. RC osc. 0

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 121

Figure 5-13. MC_CGM Auxiliary Clock 0 Generation Overview

CGM_AC0_DC0 Register

clock divider (unused)

(unused)

(no clock) 2

(no clock) 4

(no clock) 5

(no clock) 8

CGM_AC0_SC Register

(no clock) 0

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

122 Freescale Semiconductor

Figure 5-14. MC_CGM Auxiliary Clock 1 Generation Overview

CGM_AC1_DC0 Register

clock divider (unused)

(unused)

CGM_AC1_SC Register

(no clock) 0

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 123

Figure 5-15. MC_CGM Auxiliary Clock 2 Generation Overview

5.8.1 Auxiliary Clock Source Selection

During normal operation, the auxiliary clock selection is done via the CGM_AC0…2_SC registers. If

software selects an ‘unavailable’ source, the old selection remains, and the register content does not

change.

5.8.2 Auxiliary Clock Dividers

The MC_CGM generates the following derived clocks:

• (unused) - controlled by the CGM_AC0_DC0 register

• (unused) - controlled by the CGM_AC1_DC0 register

• (unused) - controlled by the CGM_AC2_DC0 register

5.9 Dividers Functional Description

Dividers are used for the generation of divided system and peripheral clocks. The MC_CGM has the

following control registers for built-in dividers:

•Section 5.5.4, “System Clock Divider Configuration Register (CGM_SC_DC0)

•Section 5.5.6, “Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0)

•Section 5.5.8, “Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0)

•Section 5.5.10, “Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0)

CGM_AC2_DC0 Register

clock divider (unused)

(unused)

(no clock) 2

(no clock) 4

(no clock) 5

(no clock) 8

CGM_AC2_SC Register

(no clock) 0

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

124 Freescale Semiconductor

The reset value of all counters is ‘1’. If a divider has its DE bit in the respective configuration register set

to ‘0’ (the divider is disabled), any value in its DIVn field is ignored.

5.10 Output Clock Multiplexing

The MC_CGM contains a multiplexing function for a number of clock sources which can then be used as

output clock sources. The selection is done via the CGM_OCDS_SC register.

5.11 Output Clock Division Selection

Figure 5-16. MC_CGM Output Clock Multiplexer and PAD[22] Generation

The MC_CGM provides the following output signals for the output clock generation:

• PAD[22] (see Figure 5-16). This signal is generated by using one of the 3-stage ripple counter

outputs or the selected signal without division. The non-divided signal is not guaranteed to be 50%

duty cycle by the MC_CGM.

the MC_CGM also has an output clock enable register (see Section 5.5.1, “Output Clock Enable Register

(CGM_OC_EN)) which contains the output clock enable/disable control bit.

CGM_OCDS_SC.SELCTL CGM_OCDS_SC.SELDIV

16 MHz int. RC osc. 0

4 MHz crystal osc. 1

system PLL 2

reserved 3

PAD[22]

’0’

CGM_OC_EN Register

Chapter 6 Power Control Unit (MC_PCU)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 125

Chapter 6

Power Control Unit (MC_PCU)

6.1 Introduction

6.1.1 Overview

The power control unit (MC_PCU) acts as a bridge for mapping the PMU peripheral to the MC_PCU

address space.

Figure 6-1 depicts the MC_PCU block diagram.

Registers

Platform Interface

MC_PCU

Figure 6-1. MC_PCU Block Diagram

Mapped Module Interface

mapped

peripheral

core

Chapter 6 Power Control Unit (MC_PCU)

MPC5602P Microcontroller Reference Manual, Rev. 4

126 Freescale Semiconductor

6.1.2 Features

The MC_PCU includes the following features:

• maps the PMU registers to the MC_PCU address space

6.2 External Signal Description

The MC_PCU has no connections to any external pins.

6.3 Memory Map and Register Definition

6.3.1 Memory Map

NOTE

Any access to unused registers as well as write accesses to read-only

registers will:

• not change register content

• cause a transfer error

Table 6-1. MC_PCU Register Description

Address Name Description Size

Access

Location

User Supervisor Test

0xC3FE

_8040

PCU_PSTAT Power Domain Status

word read read read on page 127

Table 6-2. MC_PCU Memory Map

0xC3FE

_80004

…

0xC3FE

_803C

reserved

0xC3FE

_8040

PCU_PSTAT R0000000000000000

R000000000000000

PD0

0x044

…

0x07C

reserved

Chapter 6 Power Control Unit (MC_PCU)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 127

6.3.2 Register Descriptions

All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered

according to big endian. For example, the PD0 field of the PCU_PSTAT register may be accessed as a

word at address 0xC3FE_8040, as a half-word at address 0xC3FE_8042, or as a byte at address

0xC3FE_8043.

6.3.2.1 Power Domain Status Register (PCU_PSTAT)

This register reflects the power status of all available power domains.

0xC3FE

_8080

…

0xC3FE

_80FC

PMU registers

0xC3FE

_8100

…

0xC3FE

_BFFC

reserved

Address 0xC3FE_8040 Access: User read, Supervisor read, Test read

R0000000000000000

Reset0000000000000000

R000000000000000

PD0

Reset0000000000000001

Figure 6-2. Power Domain Status Register (PCU_PSTAT)

Table 6-3. Power Domain Status Register (PCU_PSTAT) Field Descriptions

Field Description

PDnPower status for power domain #n

0 Power domain is inoperable

1 Power domain is operable

Table 6-2. MC_PCU Memory Map (continued)

Chapter 6 Power Control Unit (MC_PCU)

MPC5602P Microcontroller Reference Manual, Rev. 4

128 Freescale Semiconductor

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 129

Chapter 7

Mode Entry Module (MC_ME)

7.1 Introduction

7.1.1 Overview

The MC_ME controls the SoC mode and mode transition sequences in all functional states. It also contains

configuration, control and status registers accessible for the application.

Figure 7-1 depicts the MC_ME Block Diagram.

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

130 Freescale Semiconductor

Registers

Platform Interface

core

MC_ME

Figure 7-1. MC_ME Block Diagram

MC_RGM

XOSC0

PLL0

16 MHz_IRC

MC_CGM

peripherals

Flashes

VREG

Device

Mode

State

Machine

WKPU

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 131

7.1.2 Features

The MC_ME includes the following features:

• control of the available modes by the ME_ME register

• definition of various device mode configurations by the ME_<mode>_MC registers

• control of the actual device mode by the ME_MCTL register

• capture of the current mode and various resource status within the contents of the ME_GS register

• optional generation of various mode transition interrupts

• status bits for each cause of invalid mode transitions

• peripheral clock gating control based on the ME_RUN_PC0…7, ME_LP_PC0…7, and

ME_PCTL0…143 registers

• capture of current peripheral clock gated/enabled status

7.1.3 Modes of Operation

The MC_ME is based on several device modes corresponding to different usage models of the device.

Each mode is configurable and can define a policy for energy and processing power management to fit

particular system requirements. An application can easily switch from one mode to another depending on

the current needs of the system. The operating modes controlled by the MC_ME are divided into system

and user modes. The system modes are modes such as RESET, DRUN, SAFE, and TEST. These modes

aim to ease the configuration and monitoring of the system. The user modes are modes such as RUN0…3,

HALT0, and STOP0 which can be configured to meet the application requirements in terms of energy

management and available processing power. The modes DRUN, SAFE, TEST, and RUN0…3 are the

device software running modes.

Table 7-1 describes the MC_ME modes.

Table 7-1. MC_ME Mode Descriptions

Name Description Entry Exit

RESET This is a chip-wide virtual mode during which the

application is not active. The system remains in this mode

until all resources are available for the embedded software

to take control of the device. It manages hardware

initialization of chip configuration, voltage regulators, clock

sources, and flash modules.

system reset

assertion from

MC_RGM

system reset

deassertion from

MC_RGM

DRUN This is the entry mode for the embedded software. It

provides full accessibility to the system and enables the

configuration of the system at startup. It provides the

unique gate to enter user modes. BAM when present is

executed in DRUN mode.

system reset

deassertion from

MC_RGM,

software request

from SAFE, TEST

and RUN0…3

system reset

assertion,

RUN0…3, TEST

via software, SAFE

via software or

hardware failure.

SAFE This is a chip-wide service mode which may be entered on

the detection of a recoverable error. It forces the system

into a pre-defined safe configuration from which the system

may try to recover.

hardware failure,

software request

from DRUN, TEST,

and RUN0…3

system reset

assertion, DRUN

via software

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

132 Freescale Semiconductor

7.2 External Signal Description

The MC_ME has no connections to any external pins.

7.3 Memory Map and Register Definition

The MC_ME contains registers for:

• mode selection and status reporting

• mode configuration

• mode transition interrupts status and mask control

• scalable number of peripheral sub-mode selection and status reporting

TEST This is a chip-wide service mode which is intended to

provide a control environment for device software teting.

software request

from DRUN

system reset

assertion, DRUN

via software

RUN0…3 These are software running modes where most processing

activity is done. These various run modes allow to enable

different clock & power configurations of the system with

respect to each other.

software request

from DRUN or

other RUN0…3,

interrupt event

from HALT0,

interrupt or wakeup

event from STOP0

system reset

assertion, SAFE

via software or

hardware failure,

other RUN0…3

modes, HALT0,

STOP0 via

software

HALT0 This is a reduced-activity low-power mode during which the

clock to the core is disabled. It can be configured to switch

off analog peripherals like clock sources, flash, main

regulator, etc. for efficient power management at the cost of

higher wakeup latency.

software request

from RUN0…3

system reset

assertion, SAFE

on hardware

failure, RUN0…3

on interrupt event

STOP0 This is an advanced low-power mode during which the

clock to the core is disabled. It may be configured to switch

off most of the peripherals including clock sources for

efficient power management at the cost of higher wakeup

latency.

software request

from RUN0…3

system reset

assertion, SAFE

on hardware

failure, RUN0…3

on interrupt event

or wakeup event

Table 7-1. MC_ME Mode Descriptions (continued)

Name Description Entry Exit

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 133

7.3.1 Memory Map

Table 7-2. MC_ME Register Description

Address Name Description Size

Access

Location

User Supervisor Test

0xC3FD

_C000

ME_GS Global Status word read read read on page 140

0xC3FD

_C004

ME_MCTL Mode Control word read read/write read/write on page 142

0xC3FD

_C008

ME_ME Mode Enable word read read/write read/write on page 143

0xC3FD

_C00C

ME_IS Interrupt Status word read read/write read/write on page 144

0xC3FD

_C010

ME_IM Interrupt Mask word read read/write read/write on page 145

0xC3FD

_C014

ME_IMTS Invalid Mode Transition

Status

word read read/write read/write on page 146

0xC3FD

_C018

ME_DMTS Debug Mode Transition

Status

word read read read on page 147

0xC3FD

_C020

ME_RESET_MC RESET Mode

Configuration

word read read read on page 150

0xC3FD

_C024

ME_TEST_MC TEST Mode

Configuration

word read read/write read/write on page 150

0xC3FD

_C028

ME_SAFE_MC SAFE Mode

Configuration

word read read/write read/write on page 151

0xC3FD

_C02C

ME_DRUN_MC DRUN Mode

Configuration

word read read/write read/write on page 151

0xC3FD

_C030

ME_RUN0_MC RUN0 Mode

Configuration

word read read/write read/write on page 152

0xC3FD

_C034

ME_RUN1_MC RUN1 Mode

Configuration

word read read/write read/write on page 152

0xC3FD

_C038

ME_RUN2_MC RUN2 Mode

Configuration

word read read/write read/write on page 152

0xC3FD

_C03C

ME_RUN3_MC RUN3 Mode

Configuration

word read read/write read/write on page 152

0xC3FD

_C040

ME_HALT0_MC HALT0 Mode

Configuration

word read read/write read/write on page 152

0xC3FD

_C048

ME_STOP0_MC STOP0 Mode

Configuration

word read read/write read/write on page 153

0xC3FD

_C060

ME_PS0 Peripheral Status 0 word read read read on page 155

0xC3FD

_C064

ME_PS1 Peripheral Status 1 word read read read on page 155

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

134 Freescale Semiconductor

0xC3FD

_C068

ME_PS2 Peripheral Status 2 word read read read on page 156

0xC3FD

_C080

ME_RUN_PC0 Run Peripheral

Configuration 0

word read read/write read/write on page 156

0xC3FD

_C084

ME_RUN_PC1 Run Peripheral

Configuration 1

word read read/write read/write on page 156

…

0xC3FD

_C09C

ME_RUN_PC7 Run Peripheral

Configuration 7

word read read/write read/write on page 156

0xC3FD

_C0A0

ME_LP_PC0 Low-Power Peripheral

Configuration 0

word read read/write read/write on page 157

0xC3FD

_C0A4

ME_LP_PC1 Low-Power Peripheral

Configuration 1

word read read/write read/write on page 157

…

0xC3FD

_C0BC

ME_LP_PC7 Low-Power Peripheral

Configuration 7

word read read/write read/write on page 157

0xC3FD

_C0C4

ME_PCTL4 DSPI_0 Control byte read read/write read/write on page 158

0xC3FD

_C0C5

ME_PCTL5 DSPI_1 Control byte read read/write read/write on page 158

0xC3FD

_C0C6

ME_PCTL6 DSPI_2 Control byte read read/write read/write on page 158

0xC3FD

_C0D0

ME_PCTL16 FlexCAN_0 Control byte read read/write read/write on page 158

0xC3FD

_C0DA

ME_PCTL26 SafetyPort Control byte read read/write read/write on page 158

0xC3FD

_C0E0

ME_PCTL32 ADC_0 Control byte read read/write read/write on page 158

0xC3FD

_C0E3

ME_PCTL35 CTU Control byte read read/write read/write on page 158

0xC3FD

_C0E6

ME_PCTL38 eTimer_0 Control byte read read/write read/write on page 158

0xC3FD

_C0E9

ME_PCTL41 FlexPWM_0 Control byte read read/write read/write on page 158

0xC3FD

_C0F0

ME_PCTL48 LIN_FLEX_0 Control byte read read/write read/write on page 158

Table 7-2. MC_ME Register Description (continued)

Address Name Description Size

Access

Location

User Supervisor Test

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 135

NOTE

Any access to unused registers as well as write accesses to read-only

registers will not change register content, and cause a transfer error.

0xC3FD

_C0F1

ME_PCTL49 LIN_FLEX_1 Control byte read read/write read/write on page 158

0xC3FD

_C11C

ME_PCTL92 PIT Control byte read read/write read/write on page 158

Table 7-3. MC_ME Memory Map

0xC3FD

_C000

ME_GS

R S_CURRENT_MODE

S_MTRANS

100

S_PDO

S_MVR

S_DFLA S_CFLA

R0 0 0 0 00000

S_PLL0

S_XOSC0

S_16 MHz_IRC

S_SYSCLK

0xC3FD

_C004

ME_MCTL R

TA R G E T _ M OD E

0000000 00000

R1 0 1 0 0101000 01111

W KEY

0xC3FD

_C008

ME_ME R0 0 0 0 0000000 00000

R0 0 0 0 0

STOP0

HALT0

RUN3

RUN2

RUN1

RUN0

DRUN

SAFE

TEST

RESET

0xC3FD

_C00C

ME_IS R0 0 0 0 0000000 00000

R0 0 0 0 0000000 0

I_ICONF

I_IMODE

I_SAFE

I_MTC

Ww1c w1c w1c w1c

Table 7-2. MC_ME Register Description (continued)

Address Name Description Size

Access

Location

User Supervisor Test

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

136 Freescale Semiconductor

0xC3FD

_C010

ME_IM R0 0 0 0 0000000 00000

R0 0 0 0 0000000 0

M_ICONF

M_IMODE

M_SAFE

M_MTC

0xC3FD

_C014

ME_IMTS R0 0 0 0 0000000 00000

R0 0 0 0 0000000

S_MTI

S_MRI

S_DMA

S_NMA

S_SEA

Ww1c w1c w1c w1c w1c

0xC3FD

_C018

ME_DMTS

RPREVIOUS_MODE 0000

MPH_BUSY

PMC_PROG

CORE_DBG

SMR

VREG_CSRC_SC

CSRC_CSRC_SC

16 MHz_IRC_SC

SCSRC_SC

SYSCLK_SW

DFLASH_SC

CFLASH_SC

CDP_PRPH_0_143

00 0 0

CDP_PRPH_64_95

CDP_PRPH_32_63

CDP_PRPH_0_31

0xC3FD

_C01C reserved

0xC3FD

_C020

ME_RESET_

MC R0 0 0 0 0000

PDO

MVRON

DFLAON CFLAON

R0 0 0 0 00000

PLL0ON

XOSC0ON

16 MHz_IRCON

SYSCLK

Table 7-3. MC_ME Memory Map (continued)

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 137

0xC3FD

_C024

ME_TEST_M

C R0 0 0 0 0000

PDO

MVRON

DFLAON CFLAON

R0 0 0 0 00000

PLL0ON

XOSC0ON

16 MHz_IRCON

SYSCLK

0xC3FD

_C028

ME_SAFE_M

C R0 0 0 0 0000

PDO

MVRON

DFLAON CFLAON

R0 0 0 0 00000

PLL0ON

XOSC0ON

16 MHz_IRCON

SYSCLK

0xC3FD

_C02C

ME_DRUN_M

C R0 0 0 0 0000

PDO

MVRON

DFLAON CFLAON

R0 0 0 0 00000

PLL0ON

XOSC0ON

16 MHz_IRCON

SYSCLK

0xC3FD

_C030

…

0xC3FD

_C03C

ME_RUN0…3

_MC R0 0 0 0 0000

PDO

MVRON

DFLAON CFLAON

R0 0 0 0 00000

PLL0ON

XOSC0ON

16 MHz_IRCON

SYSCLK

Table 7-3. MC_ME Memory Map (continued)

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

138 Freescale Semiconductor

0xC3FD

_C040

ME_HALT0_

MC R0 0 0 0 0000

PDO

MVRON

DFLAON CFLAON

R0 0 0 0 00000

PLL0ON

XOSC0ON

16 MHz_IRCON

SYSCLK

0xC3FD

_C044 reserved

0xC3FD

_C048

ME_STOP0_

MC R0 0 0 0 0000

PDO

MVRON

DFLAON CFLAON

R0 0 0 0 00000

PLL0ON

XOSC0ON

16 MHz_IRCON

SYSCLK

0xC3FD

_C04C

…

0xC3FD

_C05C

reserved

0xC3FD

_C060

ME_PS0

R0 0 0 0 0

S_SafetyPort

00000 0000

S_FlexCAN_0

R0 0 0 0 00000

S_DSPI_2

S_DSPI_1

S_DSPI_0

0000

Table 7-3. MC_ME Memory Map (continued)

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 139

0xC3FD

_C064

ME_PS1

R0 0 0 0 0000000 0 0 0

S_LIN_FLEX_1

S_LIN_FLEX_0

R0 0 0 0 00

S_FlexPWM_0

S_eTimer_0

S_CTU

S_ADC_0

0xC3FD

_C068

ME_PS2 R0 0 0

S_PIT

0000000 00000

R0 0 0 0 0000000 00000

0xC3FD

_C06C reserved

0xC3FD

_C070 reserved

0xC3FD

_C074

…

0xC3FD

_C07C

reserved

0xC3FD

_C080

…

0xC3FD

_C09C

ME_RUN_PC

0…7

R0 0 0 0 0000000 00000

R0 0 0 0 0000

RUN3

RUN2

RUN1

RUN0

DRUN

SAFE

TEST

RESET

0xC3FD

_C0A0

…

0xC3FD

_C0BC

ME_LP_PC0

…7

R0 0 0 0 0000000 00000

R0 0 0 0 0

STOP0

HALT0

00000000

Table 7-3. MC_ME Memory Map (continued)

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

140 Freescale Semiconductor

7.3.2 Register Description

Unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes.

The bytes are ordered according to big endian. For example, the ME_RUN_PC0 register may be accessed

as a word at address 0xC3FD_C080, as a half-word at address 0xC3FD_C082, or as a byte at address

0xC3FD_C083.

7.3.2.1 Global Status Register (ME_GS)

This register contains global mode status.

0xC3FD

_C0C0

…

0xC3FD

_C14C

ME_PCTL0…

143

DBG_F

LP_CFG RUN_CFG

DBG_F

LP_CFG RUN_CFG

DBG_F

LP_CFG RUN_CFG

DBG_F

LP_CFG RUN_CFG

0xC3FD

_C150

…

0xC3FD

_FFFC

reserved

Address 0xC3FD_C000 Access: User read, Supervisor read, Test read

S_CURRENT_MODE

S_MTRANS

100

S_PDO

S_MVR

S_DFLA S_CFLA

Reset0000110000011111

000000000

S_PLL0

S_XOSC0

S_16 MHz_IRC

S_SYSCLK

Reset0000000000010000

Figure 7-2. Global Status Register (ME_GS)

Table 7-3. MC_ME Memory Map (continued)

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 141

Table 7-4. Global Status Register (ME_GS) Field Descriptions

Field Description

S_CURREN

T_MODE

Current device mode status

0000 RESET

0001 TEST

0010 SAFE

0011 DRUN

0100 RUN0

0101 RUN1

0110 RUN2

0111 RUN3

1000 HALT0

1001 reserved

1010 STOP0

1011 reserved

1100 reserved

1101 reserved

1110 reserved

1111 reserved

S_MTRANS Mode transition status

0 Mode transition process is not active

1 Mode transition is ongoing

S_PDO Output power-down status — This bit specifies output power-down status of I/Os. This bit is

asserted whenever outputs of pads are forced to high impedance state or the pads power sequence

driver is switched off.

0 No automatic safe gating of I/Os used and pads power sequence driver is enabled

1 In SAFE/TEST modes, outputs of pads are forced to high impedance state and the pads power

sequence driver is disabled. The inputs are level unchanged. In STOP0 mode, only the pad power

sequence driver is disabled, but the state of the output remains functional.

S_MVR Main voltage regulator status

0 Main voltage regulator is not ready

1 Main voltage regulator is ready for use

S_DFLA Data flash availability status

00 Data flash is not available

01 Data flash is in power-down mode

10 Data flash is not available

11 Data flash is in normal mode and available for use

S_CFLA Code flash availability status

00 Code flash is not available

01 Code flash is in power-down mode

10 Code flash is in low-power mode

11 Code flash is in normal mode and available for use

S_PLL0 system PLL status

0 system PLL is not stable

1 system PLL is providing a stable clock

S_XOSC0 4 MHz crystal oscillator status

0 4 MHz crystal oscillator is not stable

1 4 MHz crystal oscillator is providing a stable clock

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

142 Freescale Semiconductor

7.3.2.2 Mode Control Register (ME_MCTL)

This register is used to trigger software-controlled mode changes. Depending on the modes as enabled by

ME_ME register bits, configurations corresponding to unavailable modes are reserved and access to

ME_<mode>_MC registers must respect this for successful mode requests.

NOTE

Byte and half-word write accesses are not allowed for this register as a

predefined key is required to change its value.

S_16

MHz_IRC

16 MHz internal RC oscillator status

0 16 MHz internal RC oscillator is not stable

1 16 MHz internal RC oscillator is providing a stable clock

S_SYSCLK System clock switch status — These bits specify the system clock currently used by the system.

0000 16 MHz int. RC osc.

0001 reserved

0010 4 MHz crystal osc.

0011 reserved

0100 system PLL

0101 reserved

0110 reserved

0111 reserved

1000 reserved

1001 reserved

1010 reserved

1011 reserved

1100 reserved

1101 reserved

1110 reserved

1111 system clock is disabled

Address 0xC3FD_C004 Access: User read, Supervisor read/write, Test read/write

TA R G E T _ M OD E

000000000000

Reset0011000000000000

R1010010100001111

W KEY

Reset1010010100001111

Figure 7-3. Mode Control Register (ME_MCTL)

Table 7-4. Global Status Register (ME_GS) Field Descriptions (continued)

Field Description

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 143

7.3.2.3 Mode Enable Register (ME_ME)

This register allows a way to disable the device modes which are not required for a given device. RESET,

SAFE, DRUN, and RUN0 modes are always enabled.

Table 7-5. Mode Control Register (ME_MCTL) Field Descriptions

Field Description

TA R G E T _ M

ODE

Target device mode — These bits provide the target device mode to be entered by software

programming. The mechanism to enter into any mode by software requires the write operation twice:

first time with key, and second time with inverted key. These bits are automatically updated by

hardware while entering SAFE on hardware request. Also, while exiting from the HALT0 and STOP0

modes on hardware exit events, these are updated with the appropriate RUN0…3 mode value.

0000 RESET

0001 TEST

0010 SAFE

0011 DRUN

0100 RUN0

0101 RUN1

0110 RUN2

0111 RUN3

1000 HALT0

1001 reserved

1010 STOP0

1011 reserved

1100 reserved

1101 reserved

1110 reserved

1111 reserved

KEY Control key — These bits enable write access to this register. Any write access to the register with

a value different from the keys is ignored. Read access will always return inverted key.

KEY:0101101011110000 (0x5AF0)

INVERTED KEY:1010010100001111 (0xA50F)

Address 0xC3FD_C008 Access: User read, Supervisor read/write, Test read/write

R0000000000000000

Reset0000000000000000

R00000

STOP0

HALT0

RUN3

RUN2

RUN1

RUN0

DRUN

SAFE

TEST

RESET

Reset0000000000011101

Figure 7-4. Mode Enable Register (ME_ME)

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

144 Freescale Semiconductor

7.3.2.4 Interrupt Status Register (ME_IS)

Table 7-6. Mode Enable Register (ME_ME) Field Descriptions

Field Description

STOP0 STOP0 mode enable

0 STOP0 mode is disabled

1 STOP0 mode is enabled

HALT0 HALT0 mode enable

0 HALT0 mode is disabled

1 HALT0 mode is enabled

RUN3 RUN3 mode enable

0 RUN3 mode is disabled

1 RUN3 mode is enabled

RUN2 RUN2 mode enable

0RUN2 mode is disabled

1RUN2 mode is enabled

RUN1 RUN1 mode enable

0 RUN1 mode is disabled

1RUN1 mode is enabled

RUN0 RUN0 mode enable

0 RUN0 mode is disabled

1 RUN0 mode is enabled

DRUN DRUN mode enable

0 DRUN mode is disabled

1 DRUN mode is enabled

SAFE SAFE mode enable

0 SAFE mode is disabled

1 SAFE mode is enabled

TEST TEST mode enable

0 TEST mode is disabled

1 TEST mode is enabled

RESET RESET mode enable

0 RESET mode is disabled

1 RESET mode is enabled

Address 0xC3FD_C00C Access: User read, Supervisor read/write, Test read/write

R0000000000000000

Reset0000000000000000

000000000000

I_ICONF

I_IMODE

I_SAFE

I_MTC

Ww1c w1c w1c w1c

Reset0000000000000000

Figure 7-5. Interrupt Status Register (ME_IS)

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 145

This register provides the current interrupt status.

7.3.2.5 Interrupt Mask Register (ME_IM)

This register controls whether an event generates an interrupt or not.

Table 7-7. Interrupt Status Register (ME_IS) Field Descriptions

Field Description

I_ICONF Invalid mode configuration interrupt — This bit is set whenever a write operation to

ME_<mode>_MC registers with invalid mode configuration is attempted. It is cleared by writing a ‘1’

to this bit.

0 No invalid mode configuration interrupt occurred

1 Invalid mode configuration interrupt is pending

I_IMODE Invalid mode interrupt — This bit is set whenever an invalid mode transition is requested. It is

cleared by writing a ‘1’ to this bit.

0 No invalid mode interrupt occurred

1 Invalid mode interrupt is pending

I_SAFE SAFE mode interrupt — This bit is set whenever the device enters SAFE mode on hardware

requests generated in the system. It is cleared by writing a ‘1’ to this bit.

0 No SAFE mode interrupt occurred

1 SAFE mode interrupt is pending

I_MTC Mode transition complete interrupt — This bit is set whenever the mode transition process

completes (S_MTRANS transits from 1 to 0). It is cleared by writing a ‘1’ to this bit. This mode

transition interrupt bit will not be set while entering low-power modes HALT0, or STOP0.

0 No mode transition complete interrupt occurred

1 Mode transition complete interrupt is pending

Address 0xC3FD_C010 Access: User read, Supervisor read/write, Test read/write

R0000000000000000

Reset0000000000000000

R000000000000

M_ICONF

M_IMODE

M_SAFE

M_MTC

Reset0000000000000000

Figure 7-6. Interrupt Mask Register (ME_IM)

Table 7-8. Interrupt Mask Register (ME_IM) Field Descriptions

Field Description

M_ICONF Invalid mode configuration interrupt mask

0 Invalid mode interrupt is masked

1 Invalid mode interrupt is enabled

M_IMODE Invalid mode interrupt mask

0 Invalid mode interrupt is masked

1 Invalid mode interrupt is enabled

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

146 Freescale Semiconductor

7.3.2.6 Invalid Mode Transition Status Register (ME_IMTS)

This register provides the status bits for the possible causes of an invalid mode interrupt.

M_SAFE SAFE mode interrupt mask

0 SAFE mode interrupt is masked

1 SAFE mode interrupt is enabled

M_MTC Mode transition complete interrupt mask

0 Mode transition complete interrupt is masked

1 Mode transition complete interrupt is enabled

Address 0xC3FD_C014 Access: User read, Supervisor read/write, Test read/write

R0000000000000000

Reset0000000000000000

R00000000000

S_MTI

S_MRI

S_DMA

S_NMA

S_SEA

Ww1c w1c w1c w1c w1c

Reset0000000000000000

Figure 7-7. Invalid Mode Transition Status Register (ME_IMTS)

Table 7-9. Invalid Mode Transition Status Register (ME_IMTS) Field Descriptions

Field Description

S_MTI Mode Transition Illegal status — This bit is set whenever a new mode is requested while some

other mode transition process is active (S_MTRANS is ‘1’). Please refer to Section 7.4.5, “Mode

Transition Interrupts for the exceptions to this behavior. It is cleared by writing a ‘1’ to this bit.

0 Mode transition requested is not illegal

1 Mode transition requested is illegal

S_MRI Mode Request Illegal status — This bit is set whenever the target mode requested is not a valid

mode with respect to current mode. It is cleared by writing a ‘1’ to this bit.

0 Target mode requested is not illegal with respect to current mode

1 Target mode requested is illegal with respect to current mode

S_DMA Disabled Mode Access status — This bit is set whenever the target mode requested is one of those

disabled modes determined by ME_ME register. It is cleared by writing a ‘1’ to this bit.

0 Target mode requested is not a disabled mode

1 Target mode requested is a disabled mode

Table 7-8. Interrupt Mask Register (ME_IM) Field Descriptions (continued)

Field Description

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 147

7.3.2.7 Debug Mode Transition Status Register (ME_DMTS)

This register provides the status of different factors which influence mode transitions. It is used to give an

indication of why a mode transition indicated by ME_GS.S_MTRANS may be taking longer than

expected.

NOTE

The ME_DMTS register does not indicate whether a mode transition is

ongoing. Therefore, some ME_DMTS bits may still be asserted after the

mode transition has completed.

S_NMA Non-existing Mode Access status — This bit is set whenever the target mode requested is one of

those non existing modes determined by ME_ME register. It is cleared by writing a ‘1’ to this bit.

0 Target mode requested is an existing mode

1 Target mode requested is a non-existing mode

S_SEA SAFE Event Active status — This bit is set whenever the device is in SAFE mode, SAFE event bit

is pending and a new mode requested other than RESET/SAFE modes. It is cleared by writing a ‘1’

to this bit.

0 No new mode requested other than RESET/SAFE while SAFE event is pending

1 New mode requested other than RESET/SAFE while SAFE event is pending

Address 0xC3FD_C018 Access: User read, Supervisor read/write, Test read/write

PREVIOUS_MODE 0 0 0 0

MPH_BUSY

PMC_PROG

CORE_DBG

SMR

Reset0000000000000000

VREG_CSRC_SC

CSRC_CSRC_SC

16 MHz_IRC_SC

SCSRC_SC

SYSCLK_SW

DFLASH_SC

CFLASH_SC

CDP_PRPH_0_143

0000

CDP_PRPH_64_95

CDP_PRPH_32_63

CDP_PRPH_0_31

Reset0000000000000000

Figure 7-8. Debug Mode Transition Status Register (ME_DMTS)

Table 7-9. Invalid Mode Transition Status Register (ME_IMTS) Field Descriptions (continued)

Field Description

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

148 Freescale Semiconductor

Table 7-10. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions

Field Description

PREVIOUS_

MODE

Previous device mode — These bits show the mode in which the device was prior to the latest

change to the current mode.

0000 RESET

0001 TEST

0010 SAFE

0011 DRUN

0100 RUN0

0101 RUN1

0110 RUN2

0111 RUN3

1000 HALT0

1001 reserved

1010 STOP0

1011 reserved

1100 reserved

1101 reserved

1110 reserved

1111 reserved

MPH_BUSY MC_ME/MC_PCU Handshake Busy indicator — This bit is set if the MC_ME has requested a mode

change from the MC_PCU and the MC_PCU has not yet responded. It is cleared when the MC_PCU

has responded.

0 Handshake is not busy

1 Handshake is busy

PMC_PROG MC_PCU Mode Change in Progress indicator — This bit is set if the MC_PCU is in the process of

powering up or down power domains. It is cleared when all power-up/down processes have

completed.

0 Power-up/down transition is not in progress

1 Power-up/down transition is in progress

CORE_DBG Processor is in Debug mode indicator — This bit is set while the processor is in debug mode.

0 The processor is not in debug mode

1 The processor is in debug mode

SMR SAFE mode request from MC_RGM is active indicator — This bit is set if a hardware SAFE mode

request has been triggered. It is cleared when the hardware SAFE mode request has been cleared.

0 A SAFE mode request is not active

1 A SAFE mode request is active

VREG_CSR

C_SC

Main VREG dependent Clock Source State Change during mode transition indicator — This bit is set

when a clock source which depends on the main voltage regulator to be powered-up is requested to

change its power up/down state. It is cleared when the clock source has completed its state change.

0 No state change is taking place

1 A state change is taking place

CSRC_CSR

C_SC

(Other) Clock Source dependent Clock Source State Change during mode transition indicator — This

bit is set when a clock source which depends on another clock source to be powered-up is requested

to change its power up/down state. It is cleared when the clock source has completed its state

change.

0 No state change is taking place

1 A state change is taking place

MHz_IRC_S

16 MHz_IRC State Change during mode transition indicator — This bit is set when the 16 MHz

internal RC oscillator is requested to change its power up/down state. It is cleared when the 16 MHz

internal RC oscillator has completed its state change.

0 No state change is taking place

1 A state change is taking place

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 149

SYSCLK_S

System Clock Switching pending status —

0 No system clock source switching is pending

1 A system clock source switching is pending

DFLASH_SC DFLASH State Change during mode transition indicator — This bit is set when the DFLASH is

requested to change its power up/down state. It is cleared when the DFLASH has completed its state

change.

0 No state change is taking place

1 A state change is taking place

CFLASH_SC CFLASH State Change during mode transition indicator — This bit is set when the CFLASH is

requested to change its power up/down state. It is cleared when the DFLASH has completed its state

change.

0 No state change is taking place

1 A state change is taking place

CDP_PRPH

_0_143

Clock Disable Process Pending status for Peripherals 0…143 — This bit is set when any peripheral

has been requested to have its clock disabled. It is cleared when all the peripherals which have been

requested to have their clocks disabled have entered the state in which their clocks may be disabled.

0 No peripheral clock disabling is pending

1 Clock disabling is pending for at least one peripheral

CDP_PRPH

_64_95

Clock Disable Process Pending status for Peripherals 64…95 — This bit is set when any peripheral

appearing in ME_PS2 has been requested to have its clock disabled. It is cleared when all these

peripherals which have been requested to have their clocks disabled have entered the state in which

their clocks may be disabled.

0 No peripheral clock disabling is pending

1 Clock disabling is pending for at least one peripheral

CDP_PRPH

_32_63

Clock Disable Process Pending status for Peripherals 32…63 — This bit is set when any peripheral

appearing in ME_PS1 has been requested to have its clock disabled. It is cleared when all these

peripherals which have been requested to have their clocks disabled have entered the state in which

their clocks may be disabled.

0 No peripheral clock disabling is pending

1 Clock disabling is pending for at least one peripheral

CDP_PRPH

_0_31

Clock Disable Process Pending status for Peripherals 0…31 — This bit is set when any peripheral

appearing in ME_PS0 has been requested to have its clock disabled. It is cleared when all these

peripherals which have been requested to have their clocks disabled have entered the state in which

their clocks may be disabled.

0 No peripheral clock disabling is pending

1 Clock disabling is pending for at least one peripheral

Table 7-10. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions (continued)

Field Description

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150 Freescale Semiconductor

7.3.2.8 RESET Mode Configuration Register (ME_RESET_MC)

This register configures system behavior during RESET mode. Please refer to Table 7-11 for details.

7.3.2.9 TEST Mode Configuration Register (ME_TEST_MC)

This register configures system behavior during TEST mode. Please refer to Table 7-11 for details.

NOTE

Byte write accesses are not allowed to this register.

Address 0xC3FD_C020 Access: User read, Supervisor read/write, Test read/write

00000000PDO00

MVRON

DFLAON CFLAON

Reset0000000000011111

000000000

PLL0ON

XOSC0ON

16 MHz_IRCON

SYSCLK

Reset0000000000010000

Figure 7-9. RESET Mode Configuration Register (ME_RESET_MC)

Address 0xC3FD_C024 Access: User read, Supervisor read/write, Test read/write

00000000

PDO

MVRON

DFLAON CFLAON

Reset0000000000011111

R000000000

PLL0ON

XOSC0ON

16 MHz_IRCON

SYSCLK

Reset0000000000010000

Figure 7-10. TEST Mode Configuration Register (ME_TEST_MC)

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 151

7.3.2.10 SAFE Mode Configuration Register (ME_SAFE_MC)

This register configures system behavior during SAFE mode. Please refer to Table 7-11 for details.

NOTE

Byte write accesses are not allowed to this register.

7.3.2.11 DRUN Mode Configuration Register (ME_DRUN_MC)

This register configures system behavior during DRUN mode. Please refer to Table 7-11 for details.

NOTE

Byte write accesses are not allowed to this register.

Address 0xC3FD_C028 Access: User read, Supervisor read/write, Test read/write

00000000

PDO

MVRON

DFLAON CFLAON

Reset0000000010011111

000000000

PLL0ON

XOSC0ON

16 MHz_IRCON

SYSCLK

Reset0000000000010000

Figure 7-11. SAFE Mode Configuration Register (ME_SAFE_MC)

Address 0xC3FD_C02C Access: User read, Supervisor read/write, Test read/write

00000000PDO00

MVRON

DFLAON CFLAON

Reset0000000000011111

000000000

PLL0ON

XOSC0ON

16 MHz_IRCON

SYSCLK

Reset0000000000010000

Figure 7-12. DRUN Mode Configuration Register (ME_DRUN_MC)

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152 Freescale Semiconductor

7.3.2.12 RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC)

This register configures system behavior during RUN0…3 modes. Please refer to Table 7-11 for details.

NOTE

Byte write accesses are not allowed to this register.

7.3.2.13 HALT0 Mode Configuration Register (ME_HALT0_MC)

This register configures system behavior during HALT0 mode. Please refer to Table 7-11 for details.

NOTE

Byte write accesses are not allowed to this register.

Address 0xC3FD_C030 - 0xC3FD_C03C Access: User read, Supervisor read/write, Test read/write

00000000PDO00

MVRON

DFLAON CFLAON

Reset0000000000011111

000000000

PLL0ON

XOSC0ON

16 MHz_IRCON

SYSCLK

Reset0000000000010000

Figure 7-13. RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC)

Address 0xC3FD_C040 Access: User read, Supervisor read/write, Test read/write

00000000PDO00

MVRON

DFLAON CFLAON

Reset0000000000011010

R000000000

PLL0ON

XOSC0ON

16 MHz_IRCON

SYSCLK

Reset0000000000010000

Figure 7-14. HALT0 Mode Configuration Register (ME_HALT0_MC)

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Freescale Semiconductor 153

NOTE

The reset value of the DFLAON field in the ME_HALT0_MC register is

“10”. This reset value is illegal for the data flash. Thus, the reset value for

the HALT0 mode configuration cannot be used as is and must be set to a

legal value before requesting the entry of the HALT0 mode.

7.3.2.14 STOP0 Mode Configuration Register (ME_STOP0_MC)

This register configures system behavior during STOP0 mode. Please refer to Table 7-11 for details.

NOTE

Byte write accesses are not allowed to this register.

Address 0xC3FD_C048 Access: User read, Supervisor read/write, Test read/write

00000000

PDO

MVRON

DFLAON CFLAON

Reset0000000000010101

000000000

PLL0ON

XOSC0ON

16 MHz_IRCON

SYSCLK

Reset0000000000010000

Figure 7-15. STOP0 Mode Configuration Register (ME_STOP0_MC)

Table 7-11. Mode Configuration Registers (ME_<mode>_MC) Field Descriptions

Field Description

PDO I/O output power-down control — This bit controls the output power-down of I/Os.

0 No automatic safe gating of I/Os used and pads power sequence driver is enabled

1 In SAFE/TEST modes, outputs of pads are forced to high impedance state and pads power

sequence driver is disabled. The inputs are level unchanged. In STOP0 mode, only the pad power

sequence driver is disabled, but the state of the output remains functional.

MVRON Main voltage regulator control — This bit specifies whether main voltage regulator is switched off

or not while entering this mode.

1 Main voltage regulator is switched on

DFLAON Data flash power-down control — This bit specifies the operating mode of the data flash after

entering this mode.

00 reserved

01 Data flash is in power-down mode

10 reserved

11 Data flash is in normal mode

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MPC5602P Microcontroller Reference Manual, Rev. 4

154 Freescale Semiconductor

CFLAON Code flash power-down control — This bit specifies the operating mode of the code flash after

entering this mode.

00 reserved

01 Code flash is in power-down mode

10 Code flash is in low-power mode

11 Code flash is in normal mode

PLL0ON system PLL control

0 system PLL is switched off

1 system PLL is switched on

XOSC0ON 4 MHz crystal oscillator control

0 4 MHz crystal oscillator is switched off

1 4 MHz crystal oscillator is switched on

MHz_IRCON

16 MHz internal RC oscillator control

0 16 MHz internal RC oscillator is switched off

1 16 MHz internal RC oscillator is switched on

SYSCLK System clock switch control — These bits specify the system clock to be used by the system.

0000 16 MHz int. RC osc.

0001 reserved

0010 4 MHz crystal osc.

0011 reserved

0100 system PLL

0101 reserved

0110 reserved

0111 reserved

1000 reserved

1001 reserved

1010 reserved

1011 reserved

1100 reserved

1101 reserved

1110 reserved

1111 system clock is disabled in TEST mode, reserved in all other modes

Table 7-11. Mode Configuration Registers (ME_<mode>_MC) Field Descriptions (continued)

Field Description

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 155

7.3.2.15 Peripheral Status Register 0 (ME_PS0)

This register provides the status of the peripherals. Please refer to Table 7-12 for details.

7.3.2.16 Peripheral Status Register 1 (ME_PS1)

This register provides the status of the peripherals. Please refer to Table 7-12 for details.

Address 0xC3FD_C060 Access: User read, Supervisor read, Test read

00000

S_SafetyPort

000000000

S_FlexCAN_0

Reset0000000000000000

000000000

S_DSPI_2

S_DSPI_1

S_DSPI_0

0000

Reset0000000000000000

Figure 7-16. Peripheral Status Register 0 (ME_PS0)

Address 0xC3FD_C064 Access: User read, Supervisor read, Test read

00000000000000

S_LIN_FLEX_1

S_LIN_FLEX_0

Reset0000000000000000

00000

S_FlexPWM_0

S_eTimer_0

S_CTU

S_ADC_0

Reset0000000000000000

Figure 7-17. Peripheral Status Register 1 (ME_PS1)

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156 Freescale Semiconductor

7.3.2.17 Peripheral Status Register 2 (ME_PS2)

This register provides the status of the peripherals. Please refer to Table 7-12 for details.

7.3.2.18 Run Peripheral Configuration Registers (ME_RUN_PC0…7)

These registers configure eight different types of peripheral behavior during run modes.

Address 0xC3FD_C068 Access: User read, Supervisor read, Test read

R000

S_PIT

000000000000

Reset0000000000000000

R0000000000000000

Reset0000000000000000

Figure 7-18. Peripheral Status Register 2 (ME_PS2)

Table 7-12. Peripheral Status Registers 0…4 (ME_PS0…4) Field Descriptions

Field Description

S_<periph> Peripheral status — These bits specify the current status of the peripherals in the system. If no

peripheral is mapped on a particular position (i.e., the corresponding MODS bit is ‘0’), the

corresponding bit is always read as ‘0’.

0 Peripheral is frozen

1 Peripheral is active

Address 0xC3FD_C080 - 0xC3FD_C09C Access: User read, Supervisor read/write, Test read/write

R0000000000000000

Reset0000000000000000

R00000000

RUN3

RUN2

RUN1

RUN0

DRUN

SAFE

TEST

RESET

Reset0000000000000000

Figure 7-19. Run Peripheral Configuration Registers (ME_RUN_PC0…7)

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Freescale Semiconductor 157

7.3.2.19 Low-Power Peripheral Configuration Registers (ME_LP_PC0…7)

These registers configure eight different types of peripheral behavior during non-run modes.

Table 7-13. Run Peripheral Configuration Registers (ME_RUN_PC0…7) Field Descriptions

Field Description

RUN3 Peripheral control during RUN3

0 Peripheral is frozen with clock gated

1 Peripheral is active

RUN2 Peripheral control during RUN2

0 Peripheral is frozen with clock gated

1 Peripheral is active

RUN1 Peripheral control during RUN1

0 Peripheral is frozen with clock gated

1 Peripheral is active

RUN0 Peripheral control during RUN0

0 Peripheral is frozen with clock gated

1 Peripheral is active

DRUN Peripheral control during DRUN

0 Peripheral is frozen with clock gated

1 Peripheral is active

SAFE Peripheral control during SAFE

0 Peripheral is frozen with clock gated

1 Peripheral is active

TEST Peripheral control during TEST

0 Peripheral is frozen with clock gated

1 Peripheral is active

RESET Peripheral control during RESET

0 Peripheral is frozen with clock gated

1 Peripheral is active

Address 0xC3FD_C0A0 - 0xC3FD_C0BC Access: User read, Supervisor read/write, Test read/write

R0000000000000000

Reset0000000000000000

R00000

STOP0

HALT0

00000000

Reset0000000000000000

Figure 7-20. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7)

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158 Freescale Semiconductor

7.3.2.20 Peripheral Control Registers (ME_PCTL0…143)

These registers select the configurations during run and non-run modes for each peripheral.

Table 7-14. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) Field Descriptions

Field Description

STOP0 Peripheral control during STOP0

0 Peripheral is frozen with clock gated

1 Peripheral is active

HALT0 Peripheral control during HALT0

0 Peripheral is frozen with clock gated

1 Peripheral is active

Address 0xC3FD_C0C0 - 0xC3FD_C14F Access: User read, Supervisor read/write, Test read/write

DBG_F LP_CFG RUN_CFG

Reset00000000

Figure 7-21. Peripheral Control Registers (ME_PCTL0…143)

Table 7-15. Peripheral Control Registers (ME_PCTL0…143) Field Descriptions

Field Description

DBG_F Peripheral control in debug mode — This bit controls the state of the peripheral in debug mode

0 Peripheral state depends on RUN_CFG/LP_CFG bits and the device mode

1 Peripheral is frozen if not already frozen in device modes.

NOTE

This feature is useful to freeze the peripheral state

while entering debug. For example, this may be used

to prevent a reference timer from running while

making a debug accesses.

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Freescale Semiconductor 159

7.4 Functional Description

7.4.1 Mode Transition Request

The transition from one mode to another mode is normally handled by software by accessing the mode

control register ME_MCTL. But the in case of special events, the mode transition can be automatically

managed by hardware. In order to switch from one mode to another, the application should access the

ME_MCTL register twice by writing

• the first time with the value of the key (0x5AF0) into the KEY bit field and the required target mode

into the TARGET_MODE bit field,

• and the second time with the inverted value of the key (0xA50F) into the KEY bit field and the

required target mode into the TARGET_MODE bit field.

Once a valid mode transition request is detected, the target mode configuration information is loaded from

the corresponding ME_<mode>_MC register. The mode transition request may require a number of cycles

depending on the programmed configuration, and software should check the S_CURRENT_MODE bit

field and the S_MTRANS bit of the global status register ME_GS to verify when the mode has been

correctly entered and the transition process has completed. For a description of valid mode requests, please

refer to Section 7.4.5, “Mode Transition Interrupts“.

Any modification of the mode configuration register of the currently selected mode will not be taken into

account immediately but on the next request to enter this mode. This means that transition requests such

as RUN0…3 Æ RUN0…3, DRUN Æ DRUN, SAFE Æ SAFE, and TEST Æ TEST are considered valid

mode transition requests. As soon as the mode request is accepted as valid, the S_MTRANS bit is set till

LP_CFG Peripheral configuration select for non-run modes — These bits associate a configuration as

defined in the ME_LP_PC0…7 registers to the peripheral.

000 Selects ME_LP_PC0 configuration

001 Selects ME_LP_PC1 configuration

010 Selects ME_LP_PC2 configuration

011 Selects ME_LP_PC3 configuration

100 Selects ME_LP_PC4 configuration

101 Selects ME_LP_PC5 configuration

110 Selects ME_LP_PC6 configuration

111 Selects ME_LP_PC7 configuration

RUN_CFG Peripheral configuration select for run modes — These bits associate a configuration as defined

in the ME_RUN_PC0…7 registers to the peripheral.

000 Selects ME_RUN_PC0 configuration

001 Selects ME_RUN_PC1 configuration

010 Selects ME_RUN_PC2 configuration

011 Selects ME_RUN_PC3 configuration

100 Selects ME_RUN_PC4 configuration

101 Selects ME_RUN_PC5 configuration

110 Selects ME_RUN_PC6 configuration

111 Selects ME_RUN_PC7 configuration

Table 7-15. Peripheral Control Registers (ME_PCTL0…143) Field Descriptions (continued)

Field Description

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the status in the ME_GS register matches the configuration programmed in the respective

ME_<mode>_MC register.

NOTE

It is recommended that software poll the S_MTRANS bit in the ME_GS

7.4.2 Modes Details

7.4.2.1 RESET Mode

The device enters this mode on the following events:

• from SAFE, DRUN, RUN0…3, or TEST mode when the TARGET_MODE bit field of the

ME_MCTL register is written with “0000”

• from any mode due to a system reset by the MC_RGM because of some non-recoverable hardware

failure in the system (see the MC_RGM chapter for details)

Transition to this mode is instantaneous, and the system remains in this mode until the reset sequence is

finished. The mode configuration information for this mode is provided by the ME_RESET_MC register.

This mode has a pre-defined configuration, and the 16 MHz int. RC osc. is selected as the system clock.

SAFE

DRUN

TEST

RESET

RUN0

RUN1

HALT0

STOP0

SYSTEM MODES USER MODES

software

request

non-recoverable

failure

RUN2

RUN3

recoverable

hardware failure

Figure 7-22. MC_ME Mode Diagram

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Freescale Semiconductor 161

7.4.2.2 DRUN Mode

The device enters this mode on the following events:

• automatically from RESET mode after completion of the reset sequence

• from RUN0…3, SAFE, or TEST mode when the TARGET_MODE bit field of the ME_MCTL

As soon as any of the above events has occurred, a DRUN mode transition request is generated. The mode

configuration information for this mode is provided by the ME_DRUN_MC register. In this mode, the

flashes, all clock sources, and the system clock configuration can be controlled by software as required.

After system reset, the software execution starts with the default configuration selecting the 16 MHz int.

RC osc. as the system clock.

This mode is intended to be used by software

• to initialize all registers as per the system needs

NOTE

Software must ensure that the code executes from RAM before changing to

this mode if the flashes are configured to be in the low-power or

power-down state in this mode.

7.4.2.3 SAFE Mode

The device enters this mode on the following events:

• from DRUN, RUN0…3, or TEST mode when the TARGET_MODE bit field of the ME_MCTL

• from any mode except RESET due to a SAFE mode request generated by the MC_RGM because

of some potentially recoverable hardware failure in the system (see the MC_RGM chapter for

details)

As soon as any of the above events has occurred, a SAFE mode transition request is generated. The mode

configuration information for this mode is provided by the ME_SAFE_MC register. This mode has a

pre-defined configuration, and the 16 MHz int. RC osc. is selected as the system clock.

If the SAFE mode is requested by software while some other mode transition process is ongoing, the new

target mode becomes the SAFE mode regardless of other pending requests or new requests during the

mode transition. No new mode request made during a transition to the SAFE mode will cause an invalid

mode interrupt.

NOTE

If software requests to change to the SAFE mode and then requests to

change back to the parent mode before the mode transition is completed, the

device’s final mode after mode transition will be the SAFE mode.

As long as a SAFE event is active, the system remains in the SAFE mode, and any software mode request

during this time is ignored and lost.

This mode is intended to be used by software

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• to assess the severity of the cause of failure and then to either

— re-initialize the device via the DRUN mode, or

— completely reset the device via the RESET mode.

If the outputs of the system I/Os need to be forced to a high impedance state upon entering this mode, the

PDO bit of the ME_SAFE_MC register should be set. The input levels remain unchanged.

7.4.2.4 TEST Mode

The device enters this mode on the following events:

• from the DRUN mode when the TARGET_MODE bit field of the ME_MCTL register is written

with “0001”

As soon as any of the above events has occurred, a TEST mode transition request is generated. The mode

configuration information for this mode is provided by the ME_TEST_MC register. Except for the main

voltage regulator, all resources of the system are configurable in this mode. The system clock to the whole

system can be stopped by programming the SYSCLK bit field to “1111”, and in this case, the only way to

exit this mode is via a device reset.

This mode is intended to be used by software

• to execute software test routines

NOTE

Software must ensure that the code executes from RAM before changing to

this mode if the flashes are configured to be in the low-power or

power-down state in this mode.

7.4.2.5 RUN0…3 Modes

The device enters one of these modes on the following events:

• from the DRUN, SAFE, or another RUN0…3 mode when the TARGET_MODE bit field of the

ME_MCTL register is written with “0100…0111”

• from the HALT0 mode due to an interrupt event

• from the STOP0 mode due to an interrupt or wakeup event

As soon as any of the above events has occurred, a RUN0…3 mode transition request is generated. The

mode configuration information for these modes is provided by the ME_RUN0…3_MC registers. In these

modes, the flashes, all clock sources, and the system clock configuration can be controlled by software as

required.

These modes are intended to be used by software

• to execute application routines

NOTE

Software must ensure that the code executes from RAM before changing to

this mode if the flashes are configured to be in the low-power or

power-down state in this mode.

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Freescale Semiconductor 163

7.4.2.6 HALT0 Mode

The device enters this mode on the following events:

• from one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register

is written with “1000”.

As soon as any of the above events has occurred, a HALT0 mode transition request is generated. The mode

configuration information for this mode is provided by ME_HALT0_MC register. This mode is quite

configurable, and the ME_HALT0_MC register should be programmed according to the system needs.

The flashes can be put in low-power or power-down mode as needed. If there is a HALT0 mode request

while an interrupt request is active, the transition to HALT0 is aborted with the resultant mode being the

current mode, SAFE (on SAFE mode request), or DRUN (on reset), and an invalid mode interrupt is not

generated.

This mode is intended as a first-level low-power mode with

• the core clock frozen

• only a few peripherals running

and to be used by software

• to wait until it is required to do something and then to react quickly (i.e., within a few system clock

cycles of an interrupt event)

7.4.2.7 STOP0 Mode

The device enters this mode on the following events:

• from one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register

is written with “1010”.

As soon as any of the above events has occurred, a STOP0 mode transition request is generated. The mode

configuration information for this mode is provided by the ME_STOP0_MC register. This mode is fully

configurable, and the ME_STOP0_MC register should be programmed according to the system needs. The

following clock sources are switched off in this mode:

• the system PLL

The flashes can be put in power-down mode as needed. If there is a STOP0 mode request while any

interrupt or wakeup event is active, the transition to STOP0 is aborted with the resultant mode being the

current mode, SAFE (on SAFE mode request), or DRUN (on reset), and an invalid mode interrupt is not

generated.

This can be used as an advanced low-power mode with the core clock frozen and almost all peripherals

stopped.

This mode is intended as an advanced low-power mode with

• the core clock frozen

• almost all peripherals stopped

and to be used by software

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• to wait until it is required to do something with no need to react quickly (e.g., allow for system

clock source to be re-started)

This mode can be used to stop all clock sources and thus preserve the device status. When exiting the

STOP0 mode, the 16 MHz internal RC oscillator clock is selected as the system clock until the target clock

is available.

7.4.3 Mode Transition Process

The process of mode transition follows the following steps in a pre-defined manner depending on the

current device mode and the requested target mode. In many cases of mode transition, not all steps need

to be executed based on the mode control information, and some steps may not be applicable according to

the mode definition itself.

7.4.3.1 Target Mode Request

The target mode is requested by accessing the ME_MCTL register with the required keys. This mode

transition request by software must be a valid request satisfying a set of pre-defined rules to initiate the

process. If the request fails to satisfy these rules, it is ignored, and the TARGET_MODE bit field is not

updated. An optional interrupt can be generated for invalid mode requests. Refer to Section 7.4.5, “Mode

Transition Interrupts for details.

In the case of mode transitions occurring because of hardware events such as a reset, a SAFE mode request,

or interrupt requests and wakeup events to exit from low-power modes, the TARGET_MODE bit field of

the ME_MCTL register is automatically updated with the appropriate target mode. The mode change

process start is indicated by the setting of the mode transition status bit S_MTRANS of the ME_GS

A RESET mode requested via the ME_MCTL register is passed to the MC_RGM, which generates a

global system reset and initiates the reset sequence. The RESET mode request has the highest priority, and

the MC_ME is kept in the RESET mode during the entire reset sequence.

The SAFE mode request has the next highest priority after reset. It can be generated either by software via

the ME_MCTL register from all software running modes including DRUN, RUN0…3, and TEST or by

the MC_RGM after the detection of system hardware failures, which may occur in any mode.

7.4.3.2 Target Mode Configuration Loading

On completion of the Target Mode Request step, the target mode configuration from the

ME_<target mode>_MC register is loaded to start the resources (voltage sources, clock sources, flashes,

pads, etc.) control process.

An overview of resource control possibilities for each mode is shown in . A ‘’ indicates that a given

resource is configurable for a given mode.

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Freescale Semiconductor 165

7.4.3.3 Peripheral Clocks Disable

On completion of the Target Mode Request step, the MC_ME requests each peripheral to enter its stop

mode when:

• the peripheral is configured to be disabled via the target mode, the peripheral configuration

registers ME_RUN_PC0…7 and ME_LP_PC0…7, and the peripheral control registers

ME_PCTL0…143

WARNING

The MC_ME does not automatically request peripherals to enter their stop

modes if the power domains in which they are residing are to be turned off

due to a mode change. Therefore, it is software’s responsibility to ensure

that those peripherals that are to be powered down are configured in the

MC_ME to be frozen.

Each peripheral acknowledges its stop mode request after closing its internal activity. The MC_ME then

disables the corresponding clock(s) to this peripheral.

In the case of a SAFE mode transition request, the MC_ME does not wait for the peripherals to

acknowledge the stop requests. The SAFE mode clock gating configuration is applied immediately

regardless of the status of the peripherals’ stop acknowledges.

Table 7-16. MC_ME Resource Control Overview

Resource

Mode

RESET TEST SAFE DRUN RUN0…3 HALT0 STOP0

MHz_IRC



on on on on on on on

XOSC0 

off off offoffoffoffoff

PLL0 

off off offoffoffoffoff

CFLASH 

normal normal normal normal normal low-power power-

down

DFLASH 

normal normal normal normal normal low-power power-

down

MVREG 

on on on on on on on

PDO  

off off on off off off off

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166 Freescale Semiconductor

Please refer to Section 7.4.6, “Peripheral Clock Gating“ for more details.

Each peripheral that may block or disrupt a communication bus to which it is connected ensures that these

outputs are forced to a safe or recessive state when the device enters the SAFE mode.

7.4.3.4 Processor Low-Power Mode Entry

If, on completion of the Peripheral Clocks Disable step, the mode transition is to the HALT0 mode, the

MC_ME requests the processor to enter its halted state. The processor acknowledges its halt state request

after completing all outstanding bus transactions.

If, on completion of the Peripheral Clocks Disable step, the mode transition is to the STOP0 mode, the

MC_ME requests the processor to enter its stopped state. The processor acknowledges its stop state request

after completing all outstanding bus transactions.

7.4.3.5 Processor and System Memory Clock Disable

If, on completion of the Processor Low-Power Mode Entry step, the mode transition is to the HALT0 or

STOP0 mode and the processor is in its appropriate halted or stopped state, the MC_ME disables the

processor and system memory clocks to achieve further power saving.

The clocks to the processor and system memory are unaffected while transitioning between software

running modes such as DRUN, RUN0…3, and SAFE.

WARNING

Clocks to the whole device including the processor and system memory can

be disabled in TEST mode.

7.4.3.6 Clock Sources Switch-On

On completion of the Processor Low-Power Mode Entry step, the MC_ME switches on all clock sources

based on the <clock source>ON bits of the ME_<current mode>_MC and ME_<target mode>_MC

registers. The following clock sources are switched on at this step:

• the 16 MHz internal RC oscillator

• the 4 MHz crystal oscillator

• the system PLL

The clock sources that are required by the target mode are switched on. The duration required for the

output clocks to be stable depends on the type of source, and all further steps of mode transition depending

on one or more of these clocks waits for the stable status of the respective clocks. The availability status

of these clocks is updated in the S_<clock source> bits of ME_GS register.

The clock sources which need to be switched off are unaffected during this process in order to not disturb

the system clock which might require one of these clocks before switching to a different target clock.

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 167

7.4.3.7 Flash Modules Switch-On

On completion of the step, if one or more of the flashes needs to be switched to normal mode from its

low-power or power-down mode based on the CFLAON and DFLAON bit fields of the

ME_<current mode>_MC and ME_<target mode>_MC registers, the MC_ME requests the flash to exit

from its low-power/power-down mode. When the flashes are available for access, the S_CFLA and

S_DFLA bit fields of the ME_GS register are updated to “11” by hardware.

WAR N IN G

It is illegal to switch the flashes from low-power mode to power-down mode

and from power-down mode to low-power mode. The MC_ME, however,

does not prevent this nor does it flag it.

7.4.3.8 Pad Outputs-On

On completion of the step, if the PDO bit of the ME_<target mode>_MC register is cleared, then

• all pad outputs are enabled to return to their previous state

• the I/O pads power sequence driver is switched on

7.4.3.9 Peripheral Clocks Enable

Based on the current and target device modes, the peripheral configuration registers ME_RUN_PC0…7,

ME_LP_PC0…7, and the peripheral control registers ME_PCTL0…143, the MC_ME enables the clocks

for selected modules as required. This step is executed only after the process is completed.

7.4.3.10 Processor and Memory Clock Enable

If the mode transition is from any of the low-power modes HALT0 or STOP0 to RUN0…3, the clocks to

the processor and system memory are enabled. The process of enabling these clocks is executed only after

the Flash Modules Switch-On process is completed.

7.4.3.11 Processor Low-Power Mode Exit

If the mode transition is from any of the low-power modes HALT0 orSTOP0 to RUN0…3, the MC_ME

requests the processor to exit from its halted or stopped state. This step is executed only after the Processor

and Memory Clock Enable process is completed.

7.4.3.12 System Clock Switching

Based on the SYSCLK bit field of the ME_<current mode>_MC and ME_<target mode>_MC registers,

if the target and current system clock configurations differ, the following method is implemented for clock

switching.

• The target clock configuration for the 16 MHz int. RC osc. takes effect only after the S_16

MHz_IRC bit of the ME_GS register is set by hardware (i.e., the 16 MHz internal RC oscillator

has stabilized).

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

168 Freescale Semiconductor

• The target clock configuration for the 4 MHz crystal osc. takes effect only after the S_XOSC0 bit

of the ME_GS register is set by hardware (i.e the 4 MHz crystal oscillator has stabilized).

• The target clock configuration for the system PLL takes effect only after the S_PLL0 bit of the

ME_GS register is set by hardware (i.e., the system PLL has stabilized).

• If the clock is to be disabled, the SYSCLK bit field should be programmed with “1111”. This is

possible only in theTEST mode.

The current system clock configuration can be observed by reading the S_SYSCLK bit field of the ME_GS

uses the previous clock configuration.

System clock switching starts only after

• the Clock Sources Switch-On process has completed if the target system clock source is one of the

following:

— the 16 MHz internal RC oscillator

— the system PLL

• the Peripheral Clocks Disable process has completed in order not to change the system clock

frequency before peripherals close their internal activities

An overview of system clock source selection possibilities for each mode is shown in Table 7-17. A ‘’

indicates that a given clock source is selectable for a given mode.

7.4.3.13 Pad Switch-Off

If the PDO bit of the ME_<target mode>_MC register is ‘1’ then

• the outputs of the pads are forced to the high impedance state if the target mode is SAFE or TEST

This step is executed only after the Peripheral Clocks Disable process has completed.

Table 7-17. MC_ME System Clock Selection Overview

System

Clock

Source

Mode

RESET TEST SAFE DRUN RUN0…3 HALT0 STOP0

16 MHz

int. RC

osc.



(default)



(default)



(default)



(default)



(default)



(default)



(default)

4 MHz

crystal

osc.



system

PLL



system

clock is

disabled



1disabling the system clock during TEST mode will require a reset in order to exit TEST mode

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 169

7.4.3.14 Clock Sources (with no Dependencies) Switch-Off

Based on the device mode and the <clock source>ON bits of the ME_<mode>_MC registers, if a given

clock source is to be switched off and no other clock source needs it to be on, the MC_ME requests the

clock source to power down and updates its availability status bit S_<clock source> of the ME_GS register

to ‘0’. The following clock sources switched off at this step:

• the 4 MHz crystal oscillator

• the system PLL

This step is executed only after the System Clock Switching process has completed.

7.4.3.15 Clock Sources (with Dependencies) Switch-Off

Based on the device mode and the <clock source>ON bits of the ME_<mode>_MC registers, if a given

clock source is to be switched off and all clock sources which need this clock source to be on have been

switched off, the MC_ME requests the clock source to power down and updates its availability status bit

S_<clock source> of the ME_GS register to ‘0’. The following clock sources switched off at this step:

• the 16 MHz internal RC oscillator

This step is executed only after

• the System Clock Switching process has completed in order not to lose the current system clock

during mode transition

• the Clock Sources (with no Dependencies) Switch-Off process has completed in order to, for

example, prevent unwanted lock transitions

7.4.3.16 Flash Switch-Off

Based on the CFLAON and DFLAON bit fields of the ME_<current mode>_MC and

ME_<target mode>_MC registers, if any of the flashes is to be put in its low-power or power-down mode,

the MC_ME requests the flash to enter the corresponding power mode and waits for the flash to

acknowledge. The exact power mode status of the flashes is updated in the S_CFLA and S_DFLA bit

fields of the ME_GS register. This step is executed only when the Processor and System Memory Clock

Disable process has completed.

7.4.3.17 Current Mode Update

The current mode status bit field S_CURRENT_MODE of the ME_GS register is updated with the target

mode bit field TARGET_MODE of the ME_MCTL register when:

• all the updated status bits in the ME_GS register match the configuration specified in the

ME_<target mode>_MC register

• power sequences are done

• clock disable/enable process is finished

• processor low-power mode (halt/stop) entry and exit processes are finished

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

170 Freescale Semiconductor

Software can monitor the mode transition status by reading the S_MTRANS bit of the ME_GS register.

The mode transition latency can differ from one mode to another depending on the resources’ availability

before the new mode request and the target mode’s requirements.

If a mode transition is taking longer to complete than is expected, the ME_DMTS register can indicate

which process is still in progress.

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 171

End

Target Mode Request

Write ME_MCTL register

SAFE mode request

interrupt/wakeup event

Peripheral Clocks

Disable

Clock Sources

Switch-On

System Clock

Switching

FLASH

Switch-On

Pad

Processor

Low-Power

Processor &

PAD

Peripheral Clocks

Enable

FLASH

Switch-Off

S_MTRANS = ‘1’

ANALOG ON

DIGITAL CONTROLANALOG OFF

Current Mode Update

Start

S_MTRANS = ‘0’

Outputs On

Outputs Off

Entry

Processor

Low-Power

Exit

Clock Disable

Memory

Processor &

Clock Enable

Memory

Figure 7-23. MC_ME Transition Diagram

Clock Sources Without

Dependencies Switch-Off

Clock Sources With

Dependencies Switch-Off

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

172 Freescale Semiconductor

7.4.4 Protection of Mode Configuration Registers

While programming the mode configuration registers ME_<mode>_MC, the following rules must be

respected. Otherwise, the write operation is ignored and an invalid mode configuration interrupt may be

generated.

• If the 16 MHz int. RC osc. is selected as the system clock, 16 MHz_IRC must be on.

• If the 4 MHz crystal osc. clock is selected as the system clock, OSC must be on.

• If the system PLL clock is selected as the system clock, PLL must be on.

• The 4 MHz crystal oscillator must be on if the system PLL is on. Therefore, when writing a ‘1’ to

PLL0ON, a ‘1’ must also be written to XOSC0ON.

NOTE

Software must ensure that clock sources with dependencies other than those

mentioned above are swithced on as needed. There is no automatic

protection mechanism to check this in the MC_ME.

• Configuration “00” for the CFLAON and DFLAON bit fields is reserved.

• Configuration “10” for the DFLAON bit field is reserved.

• If the DFLAON bit field is set to “11”, the CFLAON field must also be set to “11”.

• System clock configurations marked as ‘reserved’ may not be selected.

• Configuration “1111” for the SYSCLK bit field is allowed only for theTEST mode, and only in this

case may all system clock sources be turned off.

WARNING

If the system clock is stopped during TEST mode, the device can exit only

via a system reset.

7.4.5 Mode Transition Interrupts

The MC_ME provides interrupts for incorrectly configuring a mode, requesting an invalid mode

transition, indicating a SAFE mode transition not due to a software request, and indicating when a mode

transition has completed.

7.4.5.1 Invalid Mode Configuration Interrupt

Whenever a write operation is attempted to the ME_<mode>_MC registers violating the protection rules

mentioned in the Section 7.4.4, “Protection of Mode Configuration Registers, the interrupt pending bit

I_ICONF of the ME_IS register is set and an interrupt request is generated if the mask bit M_ICONF of

ME_IM register is ‘1’.

7.4.5.2 Invalid Mode Transition Interrupt

The mode transition request is considered invalid under the following conditions:

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 173

• If the system is in the SAFE mode and the SAFE mode request from MC_RGM is active, and if

the target mode requested is other than RESET or SAFE, then this new mode request is considered

to be invalid, and the S_SEA bit of the ME_IMTS register is set.

• If the TARGET_MODE bit field of the ME_MCTL register is written with a value different from

the specified mode values (i.e., a non-existing mode), an invalid mode transition event is generated.

When such a non existing mode is requested, the S_NMA bit of the ME_IMTS register is set. This

condition is detected regardless of whether the proper key mechanism is followed while writing

the ME_MCTL register.

• If some of the device modes are disabled as programmed in the ME_ME register, their respective

configurations are considered reserved, and any access to the ME_MCTL register with those

values results in an invalid mode transition request. When such a disabled mode is requested, the

S_DMA bit of the ME_IMTS register is set. This condition is detected regardless of whether the

proper key mechanism is followed while writing the ME_MCTL register.

• If the target mode is not a valid mode with respect to the current mode, the mode request illegal

status bit S_MRI of the ME_IMTS register is set. This condition is detected only when the proper

key mechanism is followed while writing the ME_MCTL register. Otherwise, the write operation

is ignored.

• If further new mode requests occur while a mode transition is in progress (the S_MTRANS bit of

the ME_GS register is ‘1’), the mode transition illegal status bit S_MTI of the ME_IMTS register

is set. This condition is detected only when the proper key mechanism is followed while writing

the ME_MCTL register. Otherwise, the write operation is ignored.

NOTE

As the causes of invalid mode transitions may overlap at the same time, the

priority implemented for invalid mode transition status bits of the

ME_IMTS register in the order from highest to lowest is S_SEA, S_NMA,

S_DMA, S_MRI, and S_MTI.

As an exception, the mode transition request is not considered as invalid under the following conditions:

• A new request is allowed to enter the RESET or SAFE mode irrespective of the mode transition

status.

• As the exit of HALT0 and STOP0 modes depends on the interrupts of the system which can occur

at any instant, these requests to return to RUN0…3 modes are always valid.

• In order to avoid any unwanted lockup of the device modes, software can abort a mode transition

by requesting the parent mode if, for example, the mode transition has not completed after a

software determined ‘reasonable’ amount of time for whatever reason. The parent mode is the

device mode before a valid mode request was made.

• Self-transition requests (e.g., RUN0 Æ RUN0) are not considered as invalid even when the mode

transition process is active (i.e., S_MTRANS is ‘1’). During the low-power mode exit process, if

the system is not able to enter the respective RUN0…3 mode properly (i.e., all status bits of the

ME_GS register match with configuration bits in the ME_<mode>_MC register), then software

can only request the SAFE or RESET mode. It is not possible to request any other mode or to go

back to the low-power mode again.

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

174 Freescale Semiconductor

Whenever an invalid mode request is detected, the interrupt pending bit I_IMODE of the ME_IS register

is set, and an interrupt request is generated if the mask bit M_IMODE of the ME_IM register is ‘1’.

7.4.5.3 SAFE Mode Transition Interrupt

Whenever the system enters the SAFE mode as a result of a SAFE mode request from the MC_RGM due

to a hardware failure, the interrupt pending bit I_SAFE of the ME_IS register is set, and an interrupt is

generated if the mask bit M_SAFE of ME_IM register is ‘1’.

The SAFE mode interrupt pending bit can be cleared only when the SAFE mode request is deasserted by

the MC_RGM (see the MC_RGM chapter for details on how to clear a SAFE mode request). If the system

is already in SAFE mode, any new SAFE mode request by the MC_RGM also sets the interrupt pending

bit I_SAFE. However, the SAFE mode interrupt pending bit is not set when the SAFE mode is entered by

a software request (i.e., programming of ME_MCTL register).

7.4.5.4 Mode Transition Complete Interrupt

Whenever the system fully completes a mode transition (i.e., the S_MTRANS bit of ME_GS register

transits from ‘1’ to ‘0’), the interrupt pending bit I_MTC of the ME_IS register is set, and an interrupt

request is generated if the mask bit M_MTC of the ME_IM register is ‘1’. The interrupt bit I_MTC is not

set when entering low-power modes HALT0 and STOP0 in order to avoid the same event requesting the

immediate exit of these low-power modes.

7.4.6 Peripheral Clock Gating

During all device modes, each peripheral can be associated with a particular clock gating policy

determined by two groups of peripheral configuration registers.

The run peripheral configuration registers ME_RUN_PC0…7 are chosen only during the software running

modes DRUN, TEST, SAFE, and RUN0…3. All configurations are programmable by software according

to the needs of the application. Each configuration register contains a mode bit which determines whether

or not a peripheral clock is to be gated. Run configuration selection for each peripheral is done by the

RUN_CFG bit field of the ME_PCTL0…143 registers.

The low-power peripheral configuration registers ME_LP_PC0…7 are chosen only during the low-power

modes HALT0 and STOP0. All configurations are programmable by software according to the needs of

the application. Each configuration register contains a mode bit which determines whether or not a

peripheral clock is to be gated. Low-power configuration selection for each peripheral is done by the

LP_CFG bit field of the ME_PCTL0…143 registers.

Any modifications to the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers do not

affect the clock gating behavior until a new mode transition request is generated.

Whenever the processor enters a debug session during any mode, the following occurs for each peripheral:

• The clock is gated if the DBG_F bit of the associated ME_PCTL0…143 register is set. Otherwise,

the peripheral clock gating status depends on the RUN_CFG and LP_CFG bits. Any further

modifications of the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers

during a debug session will take affect immediately without requiring any new mode request.

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 175

7.4.7 Application Example

Figure 7-24 shows an example application flow for requesting a mode change and then waiting until the

mode transition has completed.

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

176 Freescale Semiconductor

Figure 7-24. MC_ME Application Example Flow Diagram

START of mode change

config

for target mode

okay?

write ME_<target mode>_MC,

ME_RUN_PC0…7, ME_LP_PC0…7,

and ME_PCTL0…143 registers

write ME_MCTL with target mode

and key

write ME_MCTL with target mode

and inverted key

start timer

S_MTRANS

cleared?

timer

expired?

write ME_MCTL with current or

SAFE mode and key

write ME_MCTL with current or

SAFE mode and inverted key

stop timer

mode change DONE

Chapter 8 Reset Generation Module (MC_RGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 177

Chapter 8

Reset Generation Module (MC_RGM)

8.1 Introduction

8.1.1 Overview

The reset generation module (MC_RGM) centralizes the different reset sources and manages the reset

sequence of the device. It provides a register interface and the reset sequencer. Various registers are

available to monitor and control the device reset sequence. The reset sequencer is a state machine which

controls the different phases (PHASE0, PHASE1, PHASE2, PHASE3, and IDLE) of the reset sequence

and controls the reset signals generated in the system.

Figure 8-1 depicts the MC_RGM block diagram.

Chapter 8 Reset Generation Module (MC_RGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

178 Freescale Semiconductor

8.1.2 Features

The MC_RGM contains the functionality for the following features:

• ‘destructive’ resets management

• ‘functional’ resets management

• signalling of reset events after each reset sequence (reset status flags)

• conversion of reset events to SAFE mode or interrupt request events

• short reset sequence configuration

PAD[4:2]

RESET_B

Registers

Platform Interface

core

MC_RGM

Figure 8-1. MC_RGM Block Diagram

MC_ME

power-on

1.2V low-voltage detected

software watchdog timer

2.7V low-voltage detected

(VREG)

2.7V low-voltage detected

(flash)

2.7V low-voltage detected (I/O)

JTAG initiated reset

core reset

software reset

checkstop reset

PLL0 fail

oscillator frequency lower than

reference

CMU0 clock frequency

higher/lower than reference

4.5V low-voltage detected

code or data flash fatal error

PLL1 fail

Functional

Reset Filter

Boot Mode

Capture

Destructive

Reset Filter

Reset

State

Machine

SSCM

peripherals

MC_CGM

Chapter 8 Reset Generation Module (MC_RGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 179

• bidirectional reset behavior configuration

• boot mode capture on RESET_B deassertion

8.1.3 Reset Sources

The different reset sources are organized into two families: ‘destructive’ and ‘functional’.

• A ‘destructive’ reset source is associated with an event related to a critical - usually hardware -

error or dysfunction. When a ‘destructive’ reset event occurs, the full reset sequence is applied to

the device starting from PHASE0. This resets the full device ensuring a safe start-up state for both

digital and analog modules. ‘Destructive’ resets are

— power-on reset

— 1.2V low-voltage detected

— software watchdog timer

— 2.7V low-voltage detected (VREG)

— 2.7V low-voltage detected (flash)

— 2.7V low-voltage detected (I/O)

— comparator error

• A ‘functional’ reset source is associated with an event related to a less-critical - usually

non-hardware - error or dysfunction. When a ‘functional’ reset event occurs, a partial reset

sequence is applied to the device starting from PHASE1. In this case, most digital modules are reset

normally, while analog modules or specific digital modules’ (e.g., debug modules, flash modules)

state is preserved. ‘Functional’ resets are

— external reset

— JTAG initiated reset

— core reset

— software reset

— checkstop reset

— PLL0 fail

— oscillator frequency lower than reference

— CMU0 clock frequency higher/lower than reference

— 4.5V low-voltage detected

— code or data flash fatal error

— PLL1 fail

When a reset is triggered, the MC_RGM state machine is activated and proceeds through the different

phases (i.e., PHASEn states). Each phase is associated with a particular device reset being provided to the

system. A phase is completed when all corresponding phase completion gates from either the system or

internal to the MC_RGM are acknowledged. The device reset associated with the phase is then released,

and the state machine proceeds to the next phase up to entering the IDLE phase. During this entire process,

the MC_ME state machine is held in RESET mode. Only at the end of the reset sequence, when the IDLE

phase is reached, does the MC_ME enter the DRUN mode.

Chapter 8 Reset Generation Module (MC_RGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

180 Freescale Semiconductor

Alternatively, it is possible for software to configure some reset source events to be converted from a reset

to either a SAFE mode request issued to the MC_ME or to an interrupt issued to the core (see

Section 8.3.1.3, “Functional Event Reset Disable Register (RGM_FERD) and Section 8.3.1.5, “Functional

Event Alternate Request Register (RGM_FEAR) for ‘functional’ resets).

8.2 External Signal Description

The MC_RGM interfaces to the bidirectional reset pin RESET_B and the boot mode pins PAD[4:2].

8.3 Memory Map and Register Definition

NOTE

Any access to unused registers as well as write accesses to read-only

registers will not change register content, and cause a transfer error.

Table 8-1. MC_RGM Register Description

Address Name Description Size

Access

Location

User Supervisor Test

0xC3FE

_4000

RGM_FES Functional Event Status half-word read read/write1read/write1on page 182

0xC3FE

_4002

RGM_DES Destructive Event Status half-word read read/write1

1individual bits cleared on writing ‘1’

read/write1on page 184

0xC3FE

_4004

RGM_FERD Functional Event Reset

Disable

half-word read read/write2

2write once: ‘0’ = enable, ‘1’ = disable.

read/write2on page 185

0xC3FE

_4006

RGM_DERD Destructive Event Reset

Disable

half-word read read read on page 186

0xC3FE

_4010

RGM_FEAR Functional Event Alternate

Request

half-word read read/write read/write on page 187

0xC3FE

_4018

RGM_FESS Functional Event Short

Sequence

half-word read read/write read/write on page 188

0xC3FE

_401C

RGM_FBRE Functional Bidirectional

Reset Enable

half-word read read/write read/write on page 190

Chapter 8 Reset Generation Module (MC_RGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 181

Table 8-2. MC_RGM Memory Map

0xC3FE

_4000

RGM_

FES /

RGM_

DES

F_EXR

00000

F_PLL1

F_FLASH

F_LVD45

F_CMU0_FHL

F_CMU0_OLR

F_PLL0

F_CHKSTOP

F_SOFT

F_CORE

F_JTAG

Ww1c

F_POR

00000000

F_LVD27_IO

F_LVD27_FLASH

F_LVD27_VREG

F_SWT

F_LVD12

Ww1c

0xC3FE

_4004

RGM_

FERD /

RGM_

DERD R

D_EXR

00000

D_PLL1

D_FLASH

D_LVD45

D_CMU0_FHL

D_CMU0_OLR

D_PLL0

D_CHKSTOP

D_SOFT

D_CORE

D_JTAG

R000000000

D_LVD27_IO

D_LVD27_FLASH

D_LVD27_VREG

D_SWT

D_LVD12

0xC3FE

_4008

…

0xC3FE

_400C

reserved

0xC3FE

_4010

RGM_

FEAR

R000000

AR_PLL1

AR_LVD45

AR_CMU0_FHL

AR_CMU0_OLR

AR_PLL0

AR_CORE

AR_JTAG

R0000000000000000

0xC3FE

_4014 reserved

w1c

Chapter 8 Reset Generation Module (MC_RGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

182 Freescale Semiconductor

8.3.1 Register Descriptions

Unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes.

The bytes are ordered according to big endian. For example, the RGM_DES[:] register bits may be

accessed as a word at address 0xC3FE_4000, as a half-word at address 0xC3FE_4002, or as a byte at

address 0xC3FE_4004.

8.3.1.1 Functional Event Status Register (RGM_FES)

0xC3FE

_4018

RGM_

FESS

SS_EXR

00000

SS_PLL1

SS_FLASH

SS_LVD45

SS_CMU0_FHL

SS_CMU0_OLR

SS_PLL0

SS_CHKSTOP

SS_SOFT

SS_CORE

SS_JTAG

R0000000000000000

0xC3FE

_401C

RGM_

FBRE

BE_EXR

00000

BE_PLL1

BE_FLASH

BE_LVD45

BE_CMU0_FHL

BE_CMU0_OLR

BE_PLL0

BE_CHKSTOP

BE_SOFT

BE_CORE

BE_JTAG

R0000000000000000

0xC3FE

_4020

…

0xC3FE

_7FFC

reserved

Address 0xC3FE_4000 Access: User read, Supervisor read/write, Test read/write

F_EXR

00000

F_PLL1

F_FLASH

F_LVD45

F_CMU0_FHL

F_CMU0_OLR

F_PLL0

F_CHKSTOP

F_SOFT

F_CORE

F_JTAG

Ww1c

POR0000000000000000

Figure 8-2. Functional Event Status Register (RGM_FES)

Table 8-2. MC_RGM Memory Map (continued)

w1c

Chapter 8 Reset Generation Module (MC_RGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 183

This register contains the status of the last asserted functional reset sources. It can be accessed in read/write

on either supervisor mode or test mode. Register bits are cleared on write ‘1’.

Table 8-3. Functional Event Status Register (RGM_FES) Field Descriptions

Field Description

F_EXR Flag for External Reset

0 No external reset event has occurred since either the last clear or the last destructive reset

assertion

1 An external reset event has occurred

F_PLL1 Flag for PLL1 fail

0 No PLL1 fail event has occurred since either the last clear or the last destructive reset assertion

1 A PLL1 fail event has occurred

F_FLASH Flag for code or data flash fatal error

0 No code or data flash fatal error event has occurred since either the last clear or the last

destructive reset assertion

1 A code or data flash fatal error event has occurred

F_LVD45 Flag for 4.5V low-voltage detected

0 No 4.5V low-voltage detected event has occurred since either the last clear or the last destructive

reset assertion

1 A 4.5V low-voltage detected event has occurred

F_CMU0_FHL Flag for CMU0 clock frequency higher/lower than reference

0 No CMU0 clock frequency higher/lower than reference event has occurred since either the last

clear or the last destructive reset assertion

1 A CMU0 clock frequency higher/lower than reference event has occurred

F_CMU0_OLR Flag for oscillator frequency lower than reference

0 No oscillator frequency lower than reference event has occurred since either the last clear or the

last destructive reset assertion

1 A oscillator frequency lower than reference event has occurred

F_PLL0 Flag for PLL0 fail

0 No PLL0 fail event has occurred since either the last clear or the last destructive reset assertion

1 A PLL0 fail event has occurred

F_CHKSTOP Flag for checkstop reset

0 No checkstop reset event has occurred since either the last clear or the last destructive reset

assertion

1 A checkstop reset event has occurred

F_SOFT Flag for software reset

0 No software reset event has occurred since either the last clear or the last destructive reset

assertion

1 A software reset event has occurred

F_CORE Flag for core reset

0 No core reset event has occurred since either the last clear or the last destructive reset assertion

1 A core reset event has occurred

F_JTAG Flag for JTAG initiated reset

0 No JTAG initiated reset event has occurred since either the last clear or the last destructive reset

assertion

1 A JTAG initiated reset event has occurred

Chapter 8 Reset Generation Module (MC_RGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

184 Freescale Semiconductor

8.3.1.2 Destructive Event Status Register (RGM_DES)

This register contains the status of the last asserted destructive reset sources. It can be accessed in

read/write on either supervisor mode or test mode. Register bits are cleared on write ‘1’.

Address 0xC3FE_4002 Access: User read, Supervisor read/write, Test read/write

F_POR

00000000

F_LVD27_IO

F_LVD27_FLASH

F_LVD27_VREG

F_SWT

F_LVD12

Ww1c

POR1000000000000000

Figure 8-3. Destructive Event Status Register (RGM_DES)

Table 8-4. Destructive Event Status Register (RGM_DES) Field Descriptions

Field Description

F_POR Flag for Power-On reset

0 No power-on event has occurred since the last clear

1 A power-on event has occurred

F_LVD27_IO Flag for 2.7V low-voltage detected (I/O)

0 No 2.7V low-voltage detected (I/O) event has occurred since either the last clear or the last

power-on reset assertion

1 A 2.7V low-voltage detected (I/O) event has occurred

F_LVD27_FLASH Flag for 2.7V low-voltage detected (flash)

0 No 2.7V low-voltage detected (flash) event has occurred since either the last clear or the last

power-on reset assertion

1 A 2.7V low-voltage detected (flash) event has occurred

F_LVD27_VREG Flag for 2.7V low-voltage detected (VREG)

0 No 2.7V low-voltage detected (VREG) event has occurred since either the last clear or the last

power-on reset assertion

1 A 2.7V low-voltage detected (VREG) event has occurred

F_SWT Flag for software watchdog timer

0 No software watchdog timer event has occurred since either the last clear or the last power-on

reset assertion

1 A software watchdog timer event has occurred

F_LVD12 Flag for 1.2V low-voltage detected

0 No 1.2V low-voltage detected event has occurred since either the last clear or the last

power-on reset assertion

1 A 1.2V low-voltage detected event has occurred

w1c

Chapter 8 Reset Generation Module (MC_RGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 185

NOTE

The F_POR flag is automatically cleared on a 1.2 V low-voltage detected or

a 2.7 V low-voltage detected. This means that if the power-up sequence is

not monotonic (i.e., the voltage rises and then drops enough to trigger a

low-voltage detection), the F_POR flag may not be set but instead the

F_LVD12 or F_LVD27_VREG flag is set on exiting the reset sequence.

Therefore, if the F_POR, F_LVD12 or F_LVD27_VREG flags are set on

reset exit, software should interpret the reset cause as power-on.

8.3.1.3 Functional Event Reset Disable Register (RGM_FERD)

This register provides dedicated bits to disable functional reset sources.When a functional reset source is

disabled, the associated functional event will trigger either a SAFE mode request or an interrupt request

(see Section 8.3.1.5, “Functional Event Alternate Request Register (RGM_FEAR)). It can be accessed in

read/write in either supervisor mode or test mode. It can be accessed in read only in user mode. Each byte

can be written only once after power-on reset.

Address 0xC3FE_4004 Access: User read, Supervisor read/write, Test read/write

D_EXR

00000

D_PLL1

D_FLASH

D_LVD45

D_CMU0_FHL

D_CMU0_OLR

D_PLL0

D_CHKSTOP

D_SOFT

D_CORE

D_JTAG

POR0000000000000000

Figure 8-4. Functional Event Reset Disable Register (RGM_FERD)

Table 8-5. Functional Event Reset Disable Register (RGM_FERD) Field Descriptions

Field Description

D_EXR Disable External Reset

0 An external reset event triggers a reset sequence

D_PLL1 Disable PLL1 fail

0 A PLL1 fail event triggers a reset sequence

1 A PLL1 fail event generates either a SAFE mode or an interrupt request depending on the value

of RGM_FEAR.AR_PLL1

D_FLASH Disable code or data flash fatal error

0 A code or data flash fatal error event triggers a reset sequence

D_LVD45 Disable 4.5V low-voltage detected

0 A 4.5V low-voltage detected event triggers a reset sequence

1 A 4.5V low-voltage detected event generates either a SAFE mode or an interrupt request

depending on the value of RGM_FEAR.AR_LVD45

D_CMU0_FHL Disable CMU0 clock frequency higher/lower than reference

0 A CMU0 clock frequency higher/lower than reference event triggers a reset sequence

1 A CMU0 clock frequency higher/lower than reference event generates either a SAFE mode or

an interrupt request depending on the value of RGM_FEAR.AR_CMU0_FHL

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MPC5602P Microcontroller Reference Manual, Rev. 4

186 Freescale Semiconductor

8.3.1.4 Destructive Event Reset Disable Register (RGM_DERD)

This register provides dedicated bits to disable particular destructive reset sources. It can be accessed in

read-only in supervisor mode, test mode, and user mode.

D_CMU0_OLR Disable oscillator frequency lower than reference

0 A oscillator frequency lower than reference event triggers a reset sequence

1 A oscillator frequency lower than reference event generates either a SAFE mode or an interrupt

request depending on the value of RGM_FEAR.AR_CMU0_OLR

D_PLL0 Disable PLL0 fail

0 A PLL0 fail event triggers a reset sequence

1 A PLL0 fail event generates either a SAFE mode or an interrupt request depending on the value

of RGM_FEAR.AR_PLL0

D_CHKSTOP Disable checkstop resetl

0 A checkstop reset event triggers a reset sequence

D_SOFT Disable software reset

0 A software reset event triggers a reset sequence

D_CORE Disable core reset

0 A core reset event triggers a reset sequence

1 A core reset event generates either a SAFE mode or an interrupt request depending on the

value of RGM_FEAR.AR_CORE

D_JTAG Disable JTAG initiated reset

0 A JTAG initiated reset event triggers a reset sequence

1 A JTAG initiated reset event generates either a SAFE mode or an interrupt request depending

on the value of RGM_FEAR.AR_JTAG

Address 0xC3FE_4006 Access: User read, Supervisor read, Test read

000000000

D_LVD27_IO

D_LVD27_FLASH

D_LVD27_VREG

D_SWT

D_LVD12

POR0000000000000000

Figure 8-5. Destructive Event Reset Disable Register (RGM_DERD)

Table 8-5. Functional Event Reset Disable Register (RGM_FERD) Field Descriptions (continued)

Field Description

Chapter 8 Reset Generation Module (MC_RGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 187

8.3.1.5 Functional Event Alternate Request Register (RGM_FEAR)

This register defines an alternate request to be generated when a reset on a functional event has been

disabled. The alternate request can be either a SAFE mode request to MC_ME or an interrupt request to

the system. It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in

read only in user mode.

Table 8-6. Destructive Event Reset Disable Register (RGM_DERD) Field Descriptions

Field Description

D_LVD27_IO Disable 2.7V low-voltage detected (I/O)

0 A 2.7V low-voltage detected (I/O) event triggers a reset sequence

D_LVD27_FLASH Disable 2.7V low-voltage detected (flash)

0 A 2.7V low-voltage detected (flash) event triggers a reset sequence

D_LVD27_VREG Disable 2.7V low-voltage detected (VREG)

0 A 2.7V low-voltage detected (VREG) event triggers a reset sequence

D_SWT Disable software watchdog timer

0 A software watchdog timer event triggers a reset sequence

D_LVD12 Disable 1.2V low-voltage detected

0 A 1.2V low-voltage detected event triggers a reset sequence

Address 0xC3FE_4010 Access: User read, Supervisor read/write, Test read/write

000000

AR_PLL1

AR_LVD45

AR_CMU0_FHL

AR_CMU0_OLR

AR_PLL0

AR_CORE

AR_JTAG

POR0000000000000000

Figure 8-6. Functional Event Alternate Request Register (RGM_FEAR)

Table 8-7. Functional Event Alternate Request Register (RGM_FEAR) Field Descriptions

Field Description

AR_PLL1 Alternate Request for PLL1 fail

0 Generate a SAFE mode request on a PLL1 fail event if the reset is disabled

1 Generate an interrupt request on a PLL1 fail event if the reset is disabled

AR_LVD45 Alternate Request for 4.5V low-voltage detected

0 Generate a SAFE mode request on a 4.5V low-voltage detected event if the reset is disabled

1 Generate an interrupt request on a 4.5V low-voltage detected event if the reset is disabled

AR_CMU0_FHL Alternate Request for CMU0 clock frequency higher/lower than reference

0 Generate a SAFE mode request on a CMU0 clock frequency higher/lower than reference

event if the reset is disabled

1 Generate an interrupt request on a CMU0 clock frequency higher/lower than reference event

if the reset is disabled

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188 Freescale Semiconductor

8.3.1.6 Functional Event Short Sequence Register (RGM_FESS)

This register defines which reset sequence will be done when a functional reset sequence is triggered. The

functional reset sequence can either start from PHASE1 or from PHASE3, skipping PHASE1 and

PHASE2.

NOTE

This could be useful for fast reset sequence, for example to skip flash reset.

It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read in user

mode.

AR_CMU0_OLR Alternate Request for oscillator frequency lower than reference

0 Generate a SAFE mode request on a oscillator frequency lower than reference event if the

reset is disabled

1 Generate an interrupt request on a oscillator frequency lower than reference event if the reset

is disabled

AR_PLL0 Alternate Request for PLL0 fail

0 Generate a SAFE mode request on a PLL0 fail event if the reset is disabled

1 Generate an interrupt request on a PLL0 fail event if the reset is disabled

AR_CORE Alternate Request for core reset

0 Generate a SAFE mode request on a core reset event if the reset is disabled

1 Generate an interrupt request on a core reset event if the reset is disabled

AR_JTAG Alternate Request for JTAG initiated reset

0 Generate a SAFE mode request on a JTAG initiated reset event if the reset is disabled

1 Generate an interrupt request on a JTAG initiated reset event if the reset is disabled

Address 0xC3FE_4018 Access: User read, Supervisor read/write, Test read/write

SS_EXR

00000

SS_PLL1

SS_FLASH

SS_LVD45

SS_CMU0_FHL

SS_CMU0_OLR

SS_PLL0

SS_CHKSTOP

SS_SOFT

SS_CORE

SS_JTAG

POR0000000000000000

Figure 8-7. Functional Event Short Sequence Register (RGM_FESS)

Table 8-7. Functional Event Alternate Request Register (RGM_FEAR) Field Descriptions (continued)

Field Description

Chapter 8 Reset Generation Module (MC_RGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 189

NOTE

This register is reset on any enabled ‘destructive’ or ‘functional’ reset event.

Table 8-8. Functional Event Short Sequence Register (RGM_FESS) Field Descriptions

Field Description

SS_EXR Short Sequence for External Reset

0 The reset sequence triggered by an external reset event will start from PHASE1

SS_PLL1 Short Sequence for PLL1 fail

0 The reset sequence triggered by a PLL1 fail event will start from PHASE1

1 The reset sequence triggered by a PLL1 fail event will start from PHASE3, skipping PHASE1

and PHASE2

SS_FLASH Short Sequence for code or data flash fatal error

0 The reset sequence triggered by a code or data flash fatal error event will start from PHASE1

SS_LVD45 Short Sequence for 4.5V low-voltage detected

0 The reset sequence triggered by a 4.5V low-voltage detected event will start from PHASE1

1 The reset sequence triggered by a 4.5V low-voltage detected event will start from PHASE3,

skipping PHASE1 and PHASE2

SS_CMU0_FHL Short Sequence for CMU0 clock frequency higher/lower than reference

0 The reset sequence triggered by a CMU0 clock frequency higher/lower than reference event

will start from PHASE1

1 The reset sequence triggered by a CMU0 clock frequency higher/lower than reference event

will start from PHASE3, skipping PHASE1 and PHASE2

SS_CMU0_OLR Short Sequence for oscillator frequency lower than reference

0 The reset sequence triggered by a oscillator frequency lower than reference event will start

from PHASE1

1 The reset sequence triggered by a oscillator frequency lower than reference event will start

from PHASE3, skipping PHASE1 and PHASE2

SS_PLL0 Short Sequence for PLL0 fail

0 The reset sequence triggered by a PLL0 fail event will start from PHASE1

1 The reset sequence triggered by a PLL0 fail event will start from PHASE3, skipping PHASE1

and PHASE2

SS_CHKSTOP Short Sequence for checkstop reset

0 The reset sequence triggered by a checkstop reset event will start from PHASE1

SS_SOFT Short Sequence for software reset

0 The reset sequence triggered by a software reset event will start from PHASE1

SS_CORE Short Sequence for core reset

0 The reset sequence triggered by a core reset event will start from PHASE1

1 The reset sequence triggered by a core reset event will start from PHASE3, skipping PHASE1

and PHASE2

SS_JTAG Short Sequence for JTAG initiated reset

0 The reset sequence triggered by a JTAG initiated reset event will start from PHASE1

1 The reset sequence triggered by a JTAG initiated reset event will start from PHASE3, skipping

PHASE1 and PHASE2

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MPC5602P Microcontroller Reference Manual, Rev. 4

190 Freescale Semiconductor

8.3.1.7 Functional Bidirectional Reset Enable Register (RGM_FBRE)

This register enables the generation of an external reset on functional reset. It can be accessed in read/write

in either supervisor mode or test mode. It can be accessed in read in user mode.

Address 0xC3FE_401C Access: User read, Supervisor read/write, Test read/write

BE_EXR

00000

BE_PLL1

BE_FLASH

BE_LVD45

BE_CMU0_FHL

BE_CMU0_OLR

BE_PLL0

BE_CHKSTOP

BE_SOFT

BE_CORE

BE_JTAG

POR0000000000000000

Figure 8-8. Functional Bidirectional Reset Enable Register (RGM_FBRE)

Table 8-9. Functional Bidirectional Reset Enable Register (RGM_FBRE) Field Descriptions

Field Description

BE_EXR Bidirectional Reset Enable for External Reset

0 RESET_B is asserted on an external reset event if the reset is enabled

1 RESET_B is not asserted on an external reset event

BE_PLL1 Bidirectional Reset Enable for PLL1 fail

0 RESET_B is asserted on a PLL1 fail event if the reset is enabled

1 RESET_B is not asserted on a PLL1 fail event

BE_FLASH Bidirectional Reset Enable for code or data flash fatal error

0 RESET_B is asserted on a code or data flash fatal error event if the reset is enabled

1 RESET_B is not asserted on a code or data flash fatal error event

BE_LVD45 Bidirectional Reset Enable for 4.5V low-voltage detected

0 RESET_B is asserted on a 4.5V low-voltage detected event if the reset is enabled

1 RESET_B is not asserted on a 4.5V low-voltage detected event

BE_CMU0_FHL Bidirectional Reset Enable for CMU0 clock frequency higher/lower than reference

0 RESET_B is asserted on a CMU0 clock frequency higher/lower than reference event if the

reset is enabled

1 RESET_B is not asserted on a CMU0 clock frequency higher/lower than reference event

BE_CMU0_OLR Bidirectional Reset Enable for oscillator frequency lower than reference

0 RESET_B is asserted on a oscillator frequency lower than reference event if the reset is

enabled

1 RESET_B is not asserted on a oscillator frequency lower than reference event

BE_PLL0 Bidirectional Reset Enable for PLL0 fail

0 RESET_B is asserted on a PLL0 fail event if the reset is enabled

1 RESET_B is not asserted on a PLL0 fail event

BE_CHKSTOP Bidirectional Reset Enable for checkstop reset

0 RESET_B is asserted on a checkstop reset event if the reset is enabled

1 RESET_B is not asserted on a checkstop reset event

BE_SOFT Bidirectional Reset Enable for software reset

0 RESET_B is asserted on a software reset event if the reset is enabled

1 RESET_B is not asserted on a software reset event

Chapter 8 Reset Generation Module (MC_RGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 191

8.4 Functional Description

8.4.1 Reset State Machine

The main role of MC_RGM is the generation of the reset sequence which ensures that the correct parts of

the device are reset based on the reset source event. This is summarized in Table 8-10.

NOTE

JTAG logic has its own independent reset control and is not controlled by

the MC_RGM in any way.

The reset sequence is comprised of five phases managed by a state machine, which ensures that all phases

are correctly processed through waiting for a minimum duration and until all processes that need to occur

during that phase have been completed before proceeding to the next phase.

The state machine used to produce the reset sequence is shown in Figure 8-9.

BE_CORE Bidirectional Reset Enable for core reset

0 RESET_B is asserted on a core reset event if the reset is enabled

1 RESET_B is not asserted on a core reset event

BE_JTAG Bidirectional Reset Enable for JTAG initiated reset

0 RESET_B is asserted on a JTAG initiated reset event if the reset is enabled

1 RESET_B is not asserted on a JTAG initiated reset event

Table 8-10. MC_RGM Reset Implications

Source What Gets Reset External Reset

Assertion1

1‘external reset assertion’ means that the RESET_B pin is asserted by the MC_RGM until the end of reset PHASE3

Boot Mode

Capture

power-on reset all yes yes

‘destructive’ resets all except some clock/reset management yes yes

external reset all except some clock/reset management and

debug

programmable2

2the assertion of the external reset is controlled via the RGM_FBRE register

yes

‘functional’ resets all except some clock/reset management and

debug

programmable2programmable3

3the boot mode is captured if the external reset is asserted

shortened ‘functional’ resets4

4the short sequence is enabled via the RGM_FESS register

flip-flops except some clock/reset management programmable2programmable3

Table 8-9. Functional Bidirectional Reset Enable Register (RGM_FBRE) Field Descriptions (continued)

Field Description

Chapter 8 Reset Generation Module (MC_RGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

192 Freescale Semiconductor

8.4.1.1 PHASE0 Phase

This phase is entered immediately from any phase on a power-on or enabled ‘destructive’ reset event. The

reset state machine exits PHASE0 and enters PHASE1 on verification of the following:

• all enabled ‘destructive’ resets have been processed

• all processes that need to be done in PHASE0 are completed

Figure 8-9. MC_RGM State Machine

PHASE0

PHASE1

PHASE2

PHASE3

IDLE

duration  3 16 MHz internal RC oscillator clock cycles

16 MHz IRC stable, VREG voltage okay done

duration  350 16 MHz internal RC oscillator clock cycles

duration 16 MHz internal RC oscillator clock cycles

code and data flash initialization done

duration 4016 MHz internal RC oscillator clock cycles

power-on

or enabled

‘destructive’

reset

enabled

non-shortened

external or

‘functional’

reset1

enabled

shortened

external or

‘functional’

reset

code and data flash initialization done

RESET_B released

Chapter 8 Reset Generation Module (MC_RGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 193

— 16 MHz IRC stable, VREG voltage okay

• a minimum of 3 16 MHz internal RC oscillator clock cycles have elapsed since power-up

completion and the last enabled ‘destructive’ reset event

8.4.1.2 PHASE1 Phase

This phase is entered either on exit from PHASE0 or immediately from PHASE2, PHASE3, or IDLE on

a non-masked external or ‘functional’ reset event if it has not been configured to trigger a ‘short’ sequence.

The reset state machine exits PHASE1 and enters PHASE2 on verification of the following:

• all enabled, non-shortened ‘functional’ resets have been processed

• a minimum of 350 16 MHz internal RC oscillator clock cycles have elapsed since the last enabled

external or non-shortened ‘functional’ reset event

8.4.1.3 PHASE2 Phase

This phase is entered on exit from PHASE1. The reset state machine exits PHASE2 and enters PHASE3

on verification of the following:

• all processes that need to be done in PHASE2 are completed

— code and data flash initialization

• a minimum of 8 16 MHz internal RC oscillator clock cycles have elapsed since entering PHASE2

8.4.1.4 PHASE3 Phase

This phase is a entered either on exit from PHASE2 or immediately from IDLE on an enabled, shortened

‘functional’ reset event. The reset state machine exits PHASE3 and enters IDLE on verification of the

following:

• all processes that need to be done in PHASE3 are completed

— code and data flash initialization

• a minimum of 40 16 MHz internal RC oscillator clock cycles have elapsed since the last enabled,

shortened ‘functional’ reset event

8.4.1.5 IDLE Phase

This is the final phase and is entered on exit from PHASE3. When this phase is reached, the MC_RGM

releases control of the system to the platform and waits for new reset events that can trigger a reset

sequence.

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194 Freescale Semiconductor

8.4.2 Destructive Resets

A ‘destructive’ reset indicates that an event has occurred after which critical register or memory content

can no longer be guaranteed.

The status flag associated with a given ‘destructive’ reset event (RGM_DES.F_<destructive reset> bit) is

set when the ‘destructive’ reset is asserted and the power-on reset is not asserted. It is possible for multiple

status bits to be set simultaneously, and it is software’s responsibility to determine which reset source is

the most critical for the application.

The device’s low-voltage detector threshold ensures that, when 1.2V low-voltage detected is enabled, the

supply is sufficient to have the destructive event correctly propagated through the digital logic. Therefore,

if a given ‘destructive’ reset is enabled, the MC_RGM ensures that the associated reset event will be

correctly triggered to the full system. However, if the given ‘destructive’ reset is disabled and the voltage

goes below the digital functional threshold, functionality can no longer be ensured, and the reset may or

may not be asserted.

An enabled destructive reset will trigger a reset sequence starting from the beginning of PHASE0.

8.4.3 External Reset

The MC_RGM manages the external reset coming from RESET_B. The detection of a falling edge on

RESET_B will start the reset sequence from the beginning of PHASE1.

The status flag associated with the external reset falling edge event (RGM_FES.F_EXR bit) is set when

the external reset is asserted and the power-on reset is not asserted.

The external reset can optionally be disabled by writing bit RGM_FERD.D_EXR.

NOTE

The RGM_FERD register can be written only once between two power-on

reset events.

An enabled external reset will normally trigger a reset sequence starting from the beginning of PHASE1.

Nevertheless, the RGM_FESS register enables the further configuring of the reset sequence triggered by

the external reset. When RGM_FESS.SS_EXR is set, the external reset will trigger a reset sequence

starting directly from the beginning of PHASE3, skipping PHASE1 and PHASE2. This can be useful

especially when an external reset should not reset the flash.

The MC_RGM may also assert the external reset if the reset sequence was triggered by one of the

following:

• a power-on reset

• a ‘destructive’ reset event

• an external reset event

• a ‘functional’ reset event configured via the RGM_FBRE register to assert the external reset

In this case, the external reset is asserted until the end of PHASE3.

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 195

8.4.4 Functional Resets

A ‘functional’ reset indicates that an event has occurred after which it can be guaranteed that critical

The status flag associated with a given ‘functional’ reset event (RGM_FES.F_<functional reset> bit) is set

when the ‘functional’ reset is asserted and the power-on reset is not asserted. It is possible for multiple

status bits to be set simultaneously, and it is software’s responsibility to determine which reset source is

the most critical for the application.

The ‘functional’ reset can be optionally disabled by software writing bit

RGM_FERD.D_<functional reset>.

NOTE

The RGM_FERD register can be written only once between two power-on

reset events.

An enabled functional reset will normally trigger a reset sequence starting from the beginning of PHASE1.

Nevertheless, the RGM_FESS register enables the further configuring of the reset sequence triggered by

a functional reset. When RGM_FESS.SS_<functional reset> is set, the associated ‘functional’ reset will

trigger a reset sequence starting directly from the beginning of PHASE3, skipping PHASE1 and PHASE2.

This can be useful especially in case a functional reset should not reset the flash module.

See the MC_ME chapter for details on the STANDBY0 and DRUN modes.

8.4.5 Alternate Event Generation

The MC_RGM provides alternative events to be generated on reset source assertion. When a reset source

is asserted, the MC_RGM normally enters the reset sequence. Alternatively, it is possible for some reset

source events to be converted from a reset to either a SAFE mode request issued to the MC_ME or to an

interrupt request issued to the core.

Alternate event selection for a given reset source is made via the RGM_FERD and RGM_FEAR registers

as shown in Table 8-11.

The alternate event is cleared by deasserting the source of the request (i.e., at the reset source that caused

the alternate request) and also clearing the appropriate RGM_FES status bit.

NOTE

Alternate requests (SAFE mode as well as interrupt requests) are generated

regardless of whether the system clock is running.

Table 8-11. MC_RGM Alternate Event Selection

RGM_FERD

Bit Value

RGM_FEAR

Bit Value Generated Event

0 X reset

1 0 SAFE mode request

1 1 interrupt request

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196 Freescale Semiconductor

NOTE

If a masked ‘functional’ reset event which is configured to generate a SAFE

mode/interrupt request occurs during PHASE1, it is ignored, and the

MC_RGM will not send any safe mode/interrupt request to the MC_ME.

8.4.6 Boot Mode Capturing

The MC_RGM provides sampling of the boot mode PAD[4:2] for use by the system. This sampling is done

five 16 MHz internal RC oscillator clock cycles before the rising edge of RESET_B. The result of the

sampling is then provided to the system. For each bit, a value of ‘1’ is produced only if each of the oldest

three of the five samples have the value ‘1’, otherwise a value of ‘0’ is produced.

NOTE

In order to ensure that the boot mode is correctly captured, the application

needs to apply the valid boot mode value to the device at least five 16 MHz

internal RC oscillator clock periods before the external reset deassertion

crosses the VIH threshold.

NOTE

RESET_B can be low as a consequence of the internal reset generation. This

will force re-sampling of the boot mode pins. (See Table 8-10 for details.)

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 197

Chapter 9

Interrupt Controller (INTC)

9.1 Introduction

The INTC provides priority-based preemptive scheduling of interrupt service requests (ISRs). This

scheduling scheme is suitable for statically scheduled hard real-time systems. The INTC supports 128

interrupt requests. It is targeted to work with Power Architecture technology and automotive applications

where the ISRs nest to multiple levels, but it also can be used with other processors and applications.For

high-priority interrupt requests in these target applications, the time from the assertion of the peripheral’s

interrupt request to when the processor is performing useful work to service the interrupt request needs to

be minimized. The INTC supports this goal by providing a unique vector for each interrupt request source.

It also provides 16 priorities so that lower priority ISRs do not delay the execution of higher priority ISRs.

Because each individual application will have different priorities for each source of interrupt request, the

priority of each interrupt request is configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC

supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the

priority can be raised temporarily so that tasks sharing the resource will not preempt each other.

Multiple processors can assert interrupt requests to each other through software configurable interrupt

requests. These software configurable interrupt requests can also be used to separate the work involved in

servicing an interrupt request into a high-priority portion and a low-priority portion. The high-priority

portion is initiated by a peripheral interrupt request, but then the ISR can assert a software configurable

interrupt request to finish the servicing in a lower priority ISR. Therefore these software configurable

interrupt requests can be used instead of the peripheral ISR scheduling a task through the RTOS.

9.2 Features

• Supports 120 peripheral interrupt and 8 software-configurable interrupt request sources

• Unique 9-bit vector per interrupt source

• Each interrupt source programmable to one of 16 priorities

• Preemption

— Preemptive prioritized interrupt requests to processor

— ISR at a higher priority preempts ISRs or tasks at lower priorities

— Automatic pushing or popping of preempted priority to or from a LIFO

— Ability to modify the ISR or task priority; modifying the priority can be used to implement the

priority ceiling protocol for accessing shared resources.

• Low latency—3 clock cycles from receipt of interrupt request from peripheral to interrupt request

to processor

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

198 Freescale Semiconductor

Table 9-1. Interrupt sources available

Interrupt sources (128) Number available

Software 8

ECSM 3

eDMA2x 17

SWT 1

STM 4

SIUL 4

MC_ME 4

MC_RGM 1

XOSC 1

PIT 4

ADC 3

FlexCAN 8

eTimer 8

FlexPWM 10

CTU 15

Safety Port 8

DSPI 15

LINFlex 6

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 199

9.3 Block diagram

Figure 9-1 shows a block diagram of the interrupt controller (INTC).

Figure 9-1. INTC block diagram

9.4 Modes of operation

9.4.1 Normal mode

In normal mode, the INTC has two handshaking modes with the processor: software vector mode and

hardware vector mode.

NOTE

To correctly configure the interrupts in both software and hardware vector

mode, the user must also configure the IVPR. The core register IVPR

contains the base address for the interrupt handlers. Please refer to the core

reference manual for more information.

9.4.1.1 Software vector mode

In software vector mode, the interrupt exception handler software must read a register in the INTC to

obtain the vector associated with the interrupt request to the processor. The INTC will use software vector

Peripheral

Hardware

Vector Enable

Software

Set/Clear

Interrupt

Registers

Flag Bits

Peripheral

Interrupt

Requests

Module

Configuration

Highest Priority

Priority

Comparator

Slave

Interface

for Reads

& Writes

Push/Update/Acknowledge

Update Interrupt Vector

Interrupt

Request to

Processor

Memory Mapped Registers

Non-Memory Mapped Logic

End of

Interrupt

Request

Selector

Priority

Arbitrator

Highest

Priority

Interrupt

Requests

n1n1Vector

Encoder

Interrupt

Vector

Processor 0

Interrupt

Acknowledge

Interrupt

Vector

n1 x

4-bits

New

Priority

Current

Priority

Processor 0

Current

Priority

Processor 0

Priority

LIFO

Pop

Lowest

Vector

Interrupt

Request

Vector Table

Entry Size

Pushed

Priority

Popped

Priority

Interrupt Acknowledge

1The total number of interrupt sources is 128, which includes 16 reserved sources and 8 software sources.

Priority

Select

Registers

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

200 Freescale Semiconductor

mode for a given processor when its associated HVEN bit in INTC_MCR is negated. The hardware vector

enable signal to processor 0 or processor 1 is driven as negated when its associated HVEN bit is negated.

The vector is read from INC_IACKR. Reading the INTC_IACKR negates the interrupt request to the

associated processor. Even if a higher priority interrupt request arrived while waiting for this interrupt

acknowledge, the interrupt request to the processor will negate for at least one clock. The reading also

pushes the PRI value in INTC_CPR onto the associated LIFO and updates PRI in the associated

INTC_CPR with the new priority.

Furthermore, the interrupt vector to the processor is driven as all 0s. The interrupt acknowledge signal

from the associated processor is ignored.

9.4.1.2 Hardware vector mode

In hardware vector mode, the hardware signals the interrupt vector from the INTC in conjunction with a

processor that can use that vector. This hardware causes the first instruction to be executed in handling the

interrupt request to the processor to be specific to that vector. Therefore, the interrupt exception handler is

specific to a peripheral or software configurable interrupt request rather than being common to all of them.

The INTC uses hardware vector mode for a given processor when the associated HVEN bit in the

INTC_MCR is asserted. The hardware vector enable signal to the associated processor is driven as

asserted. When the interrupt request to the associated processor asserts, the interrupt vector signal is

updated. The value of that interrupt vector is the unique vector associated with the preempting peripheral

or software configurable interrupt request. The vector value matches the value of the INTVEC field in the

INTC_IACKR field in the INTC_IACKR, depending on which processor was assigned to handle a given

interrupt source.

The processor negates the interrupt request to the processor driven by the INTC by asserting the interrupt

acknowledge signal for one clock. Even if a higher priority interrupt request arrived while waiting for the

interrupt acknowledge, the interrupt request to the processor will negate for at least one clock.

The assertion of the interrupt acknowledge signal for a given processor pushes the associated PRI value in

the associated INTC_CPR register onto the associated LIFO and updates the associated PRI in the

associated INTC_CPR register with the new priority. This pushing of the PRI value onto the associated

LIFO and updating PRI in the associated INTC_CPR does not occur when the associated interrupt

acknowledge signal asserts and INTC_SSCIR0_3–INTC_SSCIR4_7 is written at a time such that the PRI

value in the associated INTC_CPR register would need to be pushed and the previously last pushed PRI

value would need to be popped simultaneously. In this case, PRI in the associated INTC_CPR is updated

with the new priority, and the associated LIFO is neither pushed or popped.

9.4.1.3 Debug mode

The INTC operation in debug mode is identical to its operation in normal mode.

9.4.1.4 Stop mode

The INTC supports stop mode. The INTC can have its clock input disabled at any time by the clock driver

on the device. While its clocks are disabled, the INTC registers are not accessible.

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 201

The INTC requires clocking in order for a peripheral interrupt request to generate an interrupt request to

the processor.

9.5 Memory map and registers description

9.5.1 Module memory map

Table 9-2 shows the INTC memory map.

9.5.2 Registers description

With exception of the INTC_SSCIn and INTC_PSRn, all registers are 32 bits in width. Any combination

of accessing the four bytes of a register with a single access is supported, provided that the access does not

cross a register boundary. These supported accesses include types and sizes of 8 bits, aligned 16 bits,

misaligned 16 bits to the middle 2 bytes, and aligned 32 bits.

Although INTC_SSCIn and INTC_PSRn are 8 bits wide, they can be accessed with a single 16-bit or

32-bit access, provided that the access does not cross a 32-bit boundary.

In software vector mode, the side effects of a read of INTC_IACKR are the same regardless of the size of

the read. In either software or hardware vector mode, the size of a write to either

INTC_SSCIR0_3–INTC_SSCIR4_7 or INTC_EOIR does not affect the operation of the write.

Table 9-2. INTC memory map

Offset from

INTC_BASE

0xFFF4_8000

0x0000 INTC Module Configuration Register (INTC_MCR) on page 202

0x0004 Reserved

0x0008 INTC Current Priority Register (INTC_CPR) on page 203

0x000C Reserved

0x0010 INTC Interrupt Acknowledge Register(INTC_IACKR) on page 204

0x0014 Reserved

0x0018 INTC End-of-Interrupt Register (INTC_EOIR) on page 205

0x001C Reserved

0x0020–0x0027 INTC Software Set/Clear Interrupt Registers

(INTC_SSCIR0_3–INTC_SSCIR4_7)

on page 205

0x0028– 0x003C Reserved

0x0040–0x011C INTC Priority Select Registers

(INTC_PSR0_3–INTC_PSR220_221)1

1The PRI fields are “reserved” for peripheral interrupt requests whose vectors are labeled as

Reserved in Tab l e 9 -9.

on page 206

0x0120–0x3FFF

Reserved

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

202 Freescale Semiconductor

INTC registers are accessible only when the core is in supervisor mode (see Section 15.4.3,

“ECSM_reg_protection).

9.5.2.1 INTC Module Configuration Register (INTC_MCR)

The module configuration register configures options of the INTC.

Address:

Base + 0x0000 Access: User read/write

0123456789101112131415

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R00000000 0 0

VTES

0 0 0 0

HVEN

Reset0000000000000000

Figure 9-2. INTC Module Configuration Register (INTC_MCR)

Table 9-3. INTC_MCR field descriptions

Field Description

VTES

Vector table entry size

Controls the number of 0s to the right of INTVEC in Section 9.5.2.3, “INTC Interrupt Acknowledge

table as in software vector mode, then the number of right most 0s will determine the size of each

vector table entry. VTES impacts software vector mode operation but also affects

INTC_IACKR[INTVEC] position in both hardware vector mode and software vector mode.

0 4 bytes

1 8 bytes

HVEN

Hardware vector enable

Controls whether the INTC is in hardware vector mode or software vector mode. Refer to Section 9.4,

“Modes of operation, for the details of the handshaking with the processor in each mode.

0 Software vector mode

1 Hardware vector mode

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 203

9.5.2.2 INTC Current Priority Register (INTC_CPR)

The INTC_CPR masks any peripheral or software settable interrupt request set at the same or lower

priority as the current value of the INTC_CPR[PRI] field from generating an interrupt request to the

processor. When the INTC interrupt acknowledge register (INTC_IACKR) is read in software vector

mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode, the

value of PRI is pushed onto the LIFO, and PRI is updated with the priority of the preempting interrupt

request. When the INTC end-of-interrupt register (INTC_EOIR) is written, the LIFO is popped into the

INTC_CPR’s PRI field.

The masking priority can be raised or lowered by writing to the PRI field, supporting the PCP. Refer to

Section 9.7.5, “Priority ceiling protocol.

Address:

Base + 0x0008 Access: User read/write

0123456789101112131415

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R 0 00000000000 PRI

Reset0000000000001111

Figure 9-3. INTC Current Priority Register (INTC_CPR)

Table 9-4. INTC_CPR field descriptions

Field Description

28–31

PRI[0:3]

Priority

PRI is the priority of the currently executing ISR according to the following:

1111 Priority 15—highest priority

1110 Priority 14

1101 Priority 13

1100 Priority 12

1011 Priority 11

1010 Priority 10

1001 Priority 9

1000 Priority 8

0111 Priority 7

0110 Priority 6

0101 Priority 5

0100 Priority 4

0011 Priority 3

0010 Priority 2

0001 Priority 1

0000 Priority 0—lowest priority

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

204 Freescale Semiconductor

NOTE

A store to modify the PRI field that closely precedes or follows an access to

a shared resource can result in a non-coherent access to the resource. Refer

to Section 9.7.5.2, “Ensuring coherency, for example code to ensure

coherency.

9.5.2.3 INTC Interrupt Acknowledge Register(INTC_IACKR)

The interrupt acknowledge register provides a value that can be used to load the address of an ISR from a

vector table. The vector table can be composed of addresses of the ISRs specific to their respective

interrupt vectors.

In software vector mode, the INTC_IACKR has side effects from reads. Therefore, it must not be

speculatively read while in this mode. The side effects are the same regardless of the size of the read.

Reading the INTC_IACKR does not have side effects in hardware vector mode.

Address Base + 0x0010 Access: User read/write

0123456789101112131415

RVTBA (most significant 16 bits)

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RVTBA

(least significant 5 bits)

INTVEC10 0

Reset0000000000000000

1When the VTES bit in INTC_MCR is asserted, INTVEC is shifted to the left one bit. Bit 29 is read as a

‘0’. VTBA is narrowed to 20 bits in width.

Figure 9-4. INTC Interrupt Acknowledge Register (INTC_IACKR)

Table 9-5. INTC_IACKR field descriptions

Field Description

0–20

0–19

VTBA

Vector Table Base Address

Can be the base address of a vector table of addresses of ISRs. The VTBA only uses the leftmost

20 bits when the VTES bit in INTC_MCR is asserted.

21–29

20–28

INTVEC

Interrupt Vector

It is the vector of the peripheral or software configurable interrupt request that caused the interrupt

request to the processor. When the interrupt request to the processor asserts, the INTVEC is

updated, whether the INTC is in software or hardware vector mode.

Note: If INTC_MCR[VTES] = 1, then the INTVEC field is shifted left one position to bits 20–28.

VTBA is then shortened by one bit to bits 0–19.

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 205

9.5.2.4 INTC End-of-Interrupt Register (INTC_EOIR)

Writing to the end-of-interrupt register signals the end of the servicing of the interrupt request. When the

INTC_EOIR is written, the priority last pushed on the LIFO is popped into INTC_CPR. An exception to

this behavior is described in Section 9.4.1.2, “Hardware vector mode. The values and size of data written

to the INTC_EOIR are ignored. The values and sizes written to this register neither update the

INTC_EOIR contents or affect whether the LIFO pops. For possible future compatibility, write four bytes

of all 0s to the INTC_EOIR.

Reading the INTC_EOIR has no effect on the LIFO.

9.5.2.5 INTC Software Set/Clear Interrupt Registers

(INTC_SSCIR0_3–INTC_SSCIR4_7)

Address Base + 0x0018 Access: Write-only

0123456789101112131415

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reset0000000000000000

Figure 9-5. INTC End-of-Interrupt Register (INTC_EOIR)

Address Base + 0x0020

Access: User read/write

0123456789101112131415

R0000000CLR

0000000CLR

SET0

SET1

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000000CLR

0000000CLR

SET2

SET3

Reset0000000000000000

Figure 9-6. INTC Software Set/Clear Interrupt Register 0–3 (INTC_SSCIR[0:3])

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

206 Freescale Semiconductor

The software set/clear interrupt registers support the setting or clearing of software configurable interrupt

request. These registers contain eight independent sets of bits to set and clear a corresponding flag bit by

software. Excepting being set by software, this flag bit behaves the same as a flag bit set within a

peripheral. This flag bit generates an interrupt request within the INTC like a peripheral interrupt request.

Writing a ‘1’ to SETx will leave SETx unchanged at 0 but sets CLRx. Writing a ‘0’ to SETx has no effect.

CLRx is the flag bit. Writing a ‘1’ to CLRx clears it. Writing a ‘0’ to CLRx has no effect. If a ‘1’ is written

simultaneously to a pair of SETx and CLRx bits, CLRx will be asserted, regardless of whether CLRx was

asserted before the write.

9.5.2.6 INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR220_221)

Address Base + 0x0024 Access: User read/write

0123456789101112131415

R0000000CLR

0000000CLR

SET4

SET5

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000000CLR

0000000CLR

SET6

SET7

Reset0000000000000000

Figure 9-7. INTC Software Set/Clear Interrupt Register 4–7 (INTC_SSCIR[4:7])

Table 9-6. INTC_SSCIR[0:7] field descriptions

Field Description

6, 14, 22, 30

SET[0:7]

Set Flag Bits

Writing a ‘1’ sets the corresponding CLRx bit. Writing a ‘0’ has no effect. Each SETx always will

be read as a ‘0’.

7, 15, 23, 31

CLR[0:7]

Clear Flag Bits

CLRx is the flag bit. Writing a ‘1’ to CLRx clears it provided that a ‘1’ is not written simultaneously

to its corresponding SETx bit. Writing a ‘0’ to CLRx has no effect.

0 Interrupt request not pending within INTC

1 Interrupt request pending within INTC

Address Base + 0x0040 Access: User read/write

0123456789101112131415

R0000 PRI0 0000 PRI1

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000 PRI2 0000 PRI3

Reset0000000000000000

Figure 9-8. INTC Priority Select Register 0–3 (INTC_PSR[0:3])

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 207

Address Base +

0x011C

Access: User read/write

0123456789101112131415

R0000 PRI220 0000 PRI221

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R 0 000000000000000

Reset0000000000000000

Figure 9-9. INTC Priority Select Register 220–221 (INTC_PSR[220:221])

Table 9-7. INTC_PSR0_3–INTC_PSR220–221 field descriptions

Field Description

4–7, 12–15,

20–23, 28–31

PRI[0:3]–

PRI220:221

Priority Select

PRIx selects the priority for interrupt requests. Refer to Section 9.6, “Functional description.

Table 9-8. INTC Priority Select Register address offsets

INTC_PSRx_xOffset Address INTC_PSRx_xOffset Address

INTC_PSR0_3 0x0040 INTC_PSR112_115 0x00B0

INTC_PSR4_7 0x0044 INTC_PSR116_119 0x00B4

INTC_PSR8_11 0x0048 INTC_PSR120_123 0x00B8

INTC_PSR12_15 0x004C INTC_PSR124_127 0x00BC

INTC_PSR16_19 0x0050 INTC_PSR128_131 0x00C0

INTC_PSR20_23 0x0054 INTC_PSR132_135 0x00C4

INTC_PSR24_27 0x0058 INTC_PSR136_139 0x00C8

INTC_PSR28_31 0x005C INTC_PSR140_143 0x00CC

INTC_PSR32_35 0x0060 INTC_PSR144_147 0x00D0

INTC_PSR36_39 0x0064 INTC_PSR148_151 0x00D4

INTC_PSR40_43 0x0068 INTC_PSR152_155 0x00D8

INTC_PSR44_47 0x006C INTC_PSR156_159 0x00DC

INTC_PSR48_51 0x0070 INTC_PSR160_163 0x00E0

INTC_PSR52_55 0x0074 INTC_PSR164_167 0x00E4

INTC_PSR56_59 0x0078 INTC_PSR168_171 0x00E8

F60_63 0x007C INTC_PSR172_175 0x00EC

INTC_PSR64_67 0x0080 INTC_PSR176_179 0x00F0

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

208 Freescale Semiconductor

INTC_PSR68_71 0x0084 INTC_PSR180_183 0x00F4

INTC_PSR72_75 0x0088 INTC_PSR184_187 0x00F8

INTC_PSR76_79 0x008C INTC_PSR188_191 0x00FC

INTC_PSR80_83 0x0090 INTC_PSR192_195 0x0100

INTC_PSR84_87 0x0094 INTC_PSR196_199 0x0104

INTC_PSR88_91 0x0098 INTC_PSR200_203 0x0108

INTC_PSR92_95 0x009C INTC_PSR204_207 0x010C

INTC_PSR96_99 0x00A0 INTC_PSR208_211 0x0110

INTC_PSR100_103 0x00A4 INTC_PSR212_215 0x0114

INTC_PSR104_107 0x00A8 INTC_PSR216_219 0x0118

INTC_PSR108_111 0x00AC INTC_PSR220_221 0x011C

Table 9-8. INTC Priority Select Register address offsets (continued)

INTC_PSRx_xOffset Address INTC_PSRx_xOffset Address

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 209

9.6 Functional description

The functional description involves the areas of interrupt request sources, priority management, and

handshaking with the processor.

NOTE

The INTC has no spurious vector support. Therefore, if an asserted

peripheral or software settable interrupt request, whose PRIn value in

INTC_PSR0–INTC_PSR221 is higher than the PRI value in INTC_CPR,

negates before the interrupt request to the processor for that peripheral or

software settable interrupt request is acknowledged, the interrupt request to

the processor still can assert or will remain asserted for that peripheral or

software settable interrupt request. In this case, the interrupt vector will

correspond to that peripheral or software settable interrupt request. Also, the

PRI value in the INTC_CPR will be updated with the corresponding PRIn

value in INTC_PSRn. Furthermore, clearing the peripheral interrupt

request’s enable bit in the peripheral or, alternatively, setting its mask bit has

the same consequences as clearing its flag bit. Setting its enable bit or

clearing its mask bit while its flag bit is asserted has the same effect on the

INTC as an interrupt event setting the flag bit.

Table 9-9. Interrupt vector table

IRQ # Offset Interrupt Module

On-Platform Peripherals

Software Interrupts

0 0x0800 Software configurable flag 0 Software

1 0x0804 Software configurable flag 1 Software

2 0x0808 Software configurable flag 2 Software

3 0x080C Software configurable flag 3 Software

4 0x0810 Software configurable flag 4 Software

5 0x0814 Software configurable flag 5 Software

6 0x0818 Software configurable flag 6 Software

7 0x081C Software configurable flag 7 Software

80x0820 Reserved

ECSM

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

210 Freescale Semiconductor

9 0x0824 Platform Flash Bank 0 Abort |

Platform Flash Bank 0 Stall |

Platform Flash Bank 1 Abort |

Platform Flash Bank 1 Stall |

Platform Flash Bank 2 Abort |

Platform Flash Bank 2 Stall |

Platform Flash Bank 3 Abort |

Platform Flash Bank 3 Stall

ECSM

DMA2x

10 0x0828 Combined Error DMA2x

11 0x082C Channel 0 DMA2x

12 0x0830 Channel 1 DMA2x

13 0x0834 Channel 2 DMA2x

14 0x0838 Channel 3 DMA2x

15 0x083C Channel 4 DMA2x

16 0x0840 Channel 5 DMA2x

17 0x0844 Channel 6 DMA2x

18 0x0848 Channel 7 DMA2x

19 0x084C Channel 8 DMA2x

20 0x0850 Channel 9 DMA2x

21 0x0854 Channel 10 DMA2x

22 0x0858 Channel 11 DMA2x

23 0x085C Channel 12 DMA2x

24 0x0860 Channel 13 DMA2x

25 0x0864 Channel 14 DMA2x

26 0x0868 Channel 15 DMA2x

27 0x086C Reserved

SWT

28 0x0870 Timeout Software Watchdog (SWT)

29 0x0874 Reserved

STM

30 0x0878 Match on channel 0 STM

31 0x087C Match on channel 1 STM

32 0x0880 Match on channel 2 STM

33 0x0884 Match on channel 3 STM

Table 9-9. Interrupt vector table (continued)

IRQ # Offset Interrupt Module

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 211

34 0x0888 Reserved

ECSM

35 0x088C ECC_DBD_PlatformFlash |

ECC_DBD_PlatformRAM

ECSM

36 0x0890 ECC_SBC_PlatformFlash |

ECC_SBC_PlatformRAM

ECSM

37 0x0894 Reserved

38 0x0898 Reserved

39 0x089C Reserved

40 0x08A0 Reserved

SIUL

41 0x08A4 SIU External IRQ_0 SIUL

42 0x08A8 SIU External IRQ_1 SIUL

43 0x08AC SIU External IRQ_2 SIUL

44 0x08B0 SIU External IRQ_3 SIUL

45 0x08B4 Reserved

46 0x08B8 Reserved

47 0x08BC Reserved

48 0x08C0 Reserved

49 0x08C4 Reserved

50 0x08C8 Reserved

MC_ME

51 0x08CC Safe Mode Interrupt Mode Entry module (MC_ME)

52 0x08D0 Mode Transition Interrupt Mode Entry module (MC_ME)

53 0x08D4 Invalid Mode Interrupt Mode Entry module (MC_ME)

54 0x08D8 Invalid Mode Configuration Mode Entry module (MC_ME)

55 0x08DC Reserved

MC_RGM

56 0x08E0 Functional and destructive reset alternate

event interrupt

Reset Generation Module (MC_RGM)

XOSC

57 0x08E4 XOSC counter expired XOSC

PIT

Table 9-9. Interrupt vector table (continued)

IRQ # Offset Interrupt Module

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

212 Freescale Semiconductor

58 0x08E8 Reserved

59 0x08EC PITimer Channel 0 PIT

60 0x08F0 PITimer Channel 1 PIT

61 0x08F4 PITimer Channel 2 PIT

ADC0

62 0x08F8 ADC_EOC ADC_0

63 0x08FC ADC_ER ADC_0

64 0x0900 ADC_WD ADC_0

FlexCAN0

65 0x0904 FLEXCAN_ESR[ERR_INT] FlexCAN_0

66 0x0908 FLEXCAN_ESR_BOFF |

FLEXCAN_Transmit_Warning |

FLEXCAN_Receive_Warning

FlexCAN_0

67 0x090C FLEXCAN_ESR_WAK FlexCAN_0

68 0x0910 FLEXCAN_BUF_00_03 FlexCAN_0

69 0x0914 FLEXCAN_BUF_04_07 FlexCAN_0

70 0x0918 FLEXCAN_BUF_08_11 FlexCAN_0

71 0x091C FLEXCAN_BUF_12_15 FlexCAN_0

72 0x0920 FLEXCAN_BUF_16_31 FlexCAN_0

73 0x0924 Reserved

DSPI0

74 0x0928 DSPI_SR[TFUF]

DSPI_SR[RFOF]

DSPI_0

75 0x092C DSPI_SR[EOQF] DSPI_0

76 0x0930 DSPI_SR[TFFF] DSPI_0

77 0x0934 DSPI_SR[TCF] DSPI_0

78 0x0938 DSPI_SR[RFDF] DSPI_0

LINFlex0

79 0x093C LINFlex_RXI LINFlex_0

80 0x0940 LINFlex_TXI LINFlex_0

81 0x0944 LINFlex_ERR LINFlex_0

82 0x0948 Reserved

83 0x094C Reserved

Table 9-9. Interrupt vector table (continued)

IRQ # Offset Interrupt Module

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 213

84 0x0950 Reserved

FlexCAN1

85 0x0954 FLEXCAN_ESR[ERR_INT] FlexCAN_1

86 0x0958 FLEXCAN_ESR_BOFF |

FLEXCAN_Transmit_Warning |

FLEXCAN_Receive_Warning

FlexCAN_1

87 0x095C FLEXCAN_ESR_WAK FlexCAN_1

88 0x0960 FLEXCAN_BUF_00_03 FlexCAN_1

89 0x0964 FLEXCAN_BUF_04_07 FlexCAN_1

90 0x0968 FLEXCAN_BUF_08_11 FlexCAN_1

91 0x096C FLEXCAN_BUF_12_15 FlexCAN_1

92 0x0970 FLEXCAN_BUF_16_31 FlexCAN_1

93 0x0974 Reserved

DSPI1

94 0x0978 DSPI_SR[TFUF]

DSPI_SR[RFOF]

DSPI_1

95 0x097C DSPI_SR[EOQF] DSPI_1

96 0x0980 DSPI_SR[TFFF] DSPI_1

97 0x0984 DSPI_SR[TCF] DSPI_1

98 0x0988 DSPI_SR[RFDF] DSPI_1

LINFlex1

99 0x098C LINFlex_RXI LINFlex_1

100 0x0990 LINFlex_TXI LINFlex_1

101 0x0994 LINFlex_ERR LINFlex_1

102 0x0998 Reserved

103 0x099C Reserved

104 0x09A0 Reserved

105 0x09A4 Reserved

106 0x09A8 Reserved

107 0x09AC Reserved

108 0x09B0 Reserved

109 0x09B4 Reserved

110 0x09B8 Reserved

Table 9-9. Interrupt vector table (continued)

IRQ # Offset Interrupt Module

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111 0x09BC Reserved

112 0x09C0 Reserved

113 0x09C4 Reserved

DSPI2

114 0x09C8 DSPI_SR[TFUF]

DSPI_SR[RFOF]

DSPI_2

115 0x09CC DSPI_SR[EOQF] DSPI_2

116 0x09D0 DSPI_SR[TFFF] DSPI_2

117 0x09D4 DSPI_SR[TCF] DSPI_2

118 0x09D8 DSPI_SR[RFDF] DSPI_2

119 0x09DC Reserved

120 0x09E0 Reserved

121 0x09E4 Reserved

122 0x09E8 Reserved

123 0x09EC Reserved

124 0x09F0 Reserved

125 0x09F4 Reserved

126 0x09F8 Reserved

PIT

127 0x09FC PITimer Channel 3 PIT

128 0x0A00 Reserved

129 0x0A04 Reserved

130 0x0A08 Reserved

131 0x0A0C Reserved

132 0x0A10 Reserved

133 0x0A14 Reserved

134 0x0A18 Reserved

135 0x0A1C Reserved

136 0x0A20 Reserved

137 0x0A24 Reserved

138 0x0A28 Reserved

139 0x0A2C Reserved

140 0x0A30 Reserved

Table 9-9. Interrupt vector table (continued)

IRQ # Offset Interrupt Module

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141 0x0A34 Reserved

142 0x0A38 Reserved

143 0x0A3C Reserved

144 0x0A40 Reserved

145 0x0A44 Reserved

146 0x0A48 Reserved

147 0x0A4C Reserved

148 0x0A50 Reserved

149 0x0A54 Reserved

150 0x0A58 Reserved

151 0x0A5C Reserved

152 0x0A60 Reserved

153 0x0A64 Reserved

154 0x0A68 Reserved

155 0x0A6C Reserved

156 0x0A70 Reserved

eTimer

157 0x0A74 TC0IR eTimer_0

158 0x0A78 TC1IR eTimer_0

159 0x0A7C TC2IR eTimer_0

160 0x0A80 TC3IR eTimer_0

161 0x0A84 TC4IR eTimer_0

162 0x0A88 TC5IR eTimer_0

163 0x0A8C Reserved

164 0x0A90 Reserved

165 0x0A94 WTIF eTimer_0

166 0x0A98 Reserved

167 0x0A9C RCF eTimer_0

168 0x0AA0 Reserved

169 0x0AA4 Reserved

170 0x0AA8 Reserved

171 0x0AAC Reserved

Table 9-9. Interrupt vector table (continued)

IRQ # Offset Interrupt Module

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172 0x0AB0 Reserved

173 0x0AB4 Reserved

174 0x0AB8 Reserved

175 0x0ABC Reserved

176 0x0AC0 Reserved

177 0x0AC4 Reserved

178 0x0AC8 Reserved

FlexPWM

179 0x0ACC RF0 FlexPWM_0

180 0x0AD0 COF0 FlexPWM_0

181 0x0AD4 Reserved

182 0x0AD8 RF1 FlexPWM_0

183 0x0ADC COF1 FlexPWM_0

184 0x0AE0 Reserved

185 0x0AE4 RF2 FlexPWM_0

186 0x0AE8 COF2 FlexPWM_0

187 0x0AEC Reserved

188 0x0AF0 RF3 FlexPWM_0

189 0x0AF4 COF3 FlexPWM_0

190 0x0AF8 Reserved

191 0x0AFC FFLAG FlexPWM_0

192 0x0B00 REF FlexPWM_0

CTU

193 0x0B04 MRS_I CTU_0

194 0x0B08 T0_I CTU_0

195 0x0B0C T1_I CTU_0

196 0x0B10 T2_I CTU_0

197 0x0B14 T3_I CTU_0

198 0x0B18 T4_I CTU_0

199 0x0B1C T5_I CTU_0

200 0x0B20 T6_I CTU_0

201 0x0B24 T7_I CTU_0

Table 9-9. Interrupt vector table (continued)

IRQ # Offset Interrupt Module

Chapter 9 Interrupt Controller (INTC)

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9.6.1 Interrupt request sources

The INTC has two types of interrupt requests, peripheral and software configurable. These interrupt

requests can assert on any clock cycle.

9.6.1.1 Peripheral interrupt requests

An interrupt event in a peripheral’s hardware sets a flag bit that resides in the peripheral. The interrupt

request from the peripheral is driven by that flag bit.

The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the time

that the INTC starts to drive the interrupt request to the processor is three clocks.

External interrupts are handled by the SIU (see Section 11.6.4, “External interrupts).

202 0x0B28 FIFO1_I CTU_0

203 0x0B2C FIFO2_I CTU_0

204 0x0B30 FIFO3_I CTU_0

205 0x0B34 FIFO4_I CTU_0

206 0x0B38 ADC_I CTU_0

207 0x0B3C ERR_I CTU_0

SafetyPort

208 0x0B40 FLEXCAN_ESR[ERR_INT] SafetyPort (FlexCAN)

209 0x0B44 FLEXCAN_ESR_BOFF |

FLEXCAN_Transmit_Warning |

FLEXCAN_Receive_Warning

SafetyPort (FlexCAN)

210 0x0B48 FLEXCAN_ESR_WAK SafetyPort (FlexCAN)

211 0x0B4C FLEXCAN_BUF_0_3 SafetyPort (FlexCAN)

212 0x0B50 FLEXCAN_BUF_4_7 SafetyPort (FlexCAN)

213 0x0B54 FLEXCAN_BUF_8_11 SafetyPort (FlexCAN)

214 0x0B58 FLEXCAN_BUF_12_15 SafetyPort (FlexCAN)

215 0x0B5C FLEXCAN_BUF_16_31 SafetyPort (FlexCAN)

216 0x0B60 Reserved

217 0x0B64 Reserved

218 0x0B68 Reserved

219 0x0B6C Reserved

220 0x0B70 Reserved

221 0x0B74 Reserved

Table 9-9. Interrupt vector table (continued)

IRQ # Offset Interrupt Module

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9.6.1.2 Software configurable interrupt requests

An interrupt request is triggered by software by writing a ‘1’ to a SETx bit in

INTC_SSCIR0_3–INTC_SSCIR4_7. This write sets the corresponding flag bit, CLRx, resulting in the

interrupt request. The interrupt request is cleared by writing a ‘1’ to the CLRx bit.

The time from the write to the SETx bit to the time that the INTC starts to drive the interrupt request to the

processor is four clocks.

9.6.1.3 Unique vector for each interrupt request source

Each peripheral and software configurable interrupt request is assigned a hardwired unique 9-bit vector.

Software configurable interrupts 0–7 are assigned vectors 0–7 respectively. The peripheral interrupt

requests are assigned vectors 8 to as high as needed to include all the peripheral interrupt requests. The

peripheral interrupt request input ports at the boundary of the INTC block are assigned specific hardwired

vectors within the INTC (see Table 9-1).

9.6.2 Priority management

The asserted interrupt requests are compared to each other based on their PRIx values set in INTC Priority

Select Registers (INTC_PSR0_3–INTC_PSR220_221). The result is compared to PRI in the associated

INTC_CPR. The results of those comparisons manage the priority of the ISR executed by the associated

processor. The associated LIFO also assists in managing that priority.

9.6.2.1 Current priority and preemption

The priority arbitrator, selector, encoder, and comparator subblocks shown in Figure 9-1 compare the priority of the asserted

interrupt requests to the current priority. If the priority of any asserted peripheral or software configurable interrupt request is

higher than the current priority for a given processor, then the interrupt request to the processor is asserted. Also, a unique vector

for the preempting peripheral or software settable interrupt request is generated for INTC interrupt acknowledge register

(INTC_IACKR), and if in hardware vector mode, for the interrupt vector provided to the processor.

9.6.2.1.1 Priority arbitrator subblock

The priority arbitrator subblock for each processor compares all the priorities of all of the asserted interrupt

requests assigned to that processor, both peripheral and software configurable. The output of the priority

arbitrator subblock is the highest of those priorities assigned to a given processor. Also, any interrupt

requests that have this highest priority are output as asserted interrupt requests to the associated request

selector subblock.

9.6.2.1.2 Request selector subblock

If only one interrupt request from the associated priority arbitrator subblock is asserted, then it is passed

as asserted to the associated vector encoder subblock. If multiple interrupt requests from the associated

priority arbitrator subblock are asserted, only the one with the lowest vector passes as asserted to the

associated vector encoder subblock. The lower vector is chosen regardless of the time order of the

assertions of the peripheral or software configurable interrupt requests.

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Freescale Semiconductor 219

9.6.2.1.3 Vector encoder subblock

The vector encoder subblock generates the unique 9-bit vector for the asserted interrupt request from the

request selector subblock for the associated processor.

9.6.2.1.4 Priority comparator subblock

The priority comparator submodule compares the highest priority output from the priority arbitrator submodule with PRI in

INTC_CPR. If the priority comparator submodule detects that this highest priority is higher than the current priority, then it asserts

the interrupt request to the processor. This interrupt request to the processor asserts whether this highest priority is raised above

the value of PRI in INTC_CPR or the PRI value in INTC_CPR is lowered below this highest priority. This highest priority then

becomes the new priority that will be written to PRI in INTC_CPR when the interrupt request to the processor is acknowledged.

Interrupt requests whose PRIn in INTC_PSRn are zero will not cause a preemption because their PRIn will not be higher than

PRI in INTC_CPR.

9.6.2.2 Last-in first-out (LIFO)

The LIFO stores the preempted PRI values from the INTC_CPR. Therefore, because these priorities are

stacked within the INTC, if interrupts need to be enabled during the ISR, at the beginning of the interrupt

exception handler the PRI value in the INTC_CPR does not need to be loaded from the INTC_CPR and

stored onto the context stack. Likewise at the end of the interrupt exception handler, the priority does not

need to be loaded from the context stack and stored into the INTC_CPR.

The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in software

vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode.

The priority is popped into PRI in the INTC_CPR whenever the INTC_EOIR is written.

Although the INTC supports 16 priorities, an ISR executing with PRI in the INTC_CPR equal to 15 will

not be preempted. Therefore, the LIFO supports the stacking of 15 priorities. However, the LIFO is only

14 entries deep. An entry for a priority of 0 is not needed because of how pushing onto a full LIFO and

popping an empty LIFO are treated. If the LIFO is pushed 15 or more times than it is popped, the priorities

first pushed are overwritten. A priority of 0 would be an overwritten priority. However, the LIFO will pop

0s if it is popped more times than it is pushed. Therefore, although a priority of 0 was overwritten, it is

regenerated with the popping of an empty LIFO.

The LIFO is not memory mapped.

9.6.3 Handshaking with processor

9.6.3.1 Software vector mode handshaking

This section describes handshaking in software vector mode.

9.6.3.1.1 Acknowledging interrupt request to processor

A timing diagram of the interrupt request and acknowledge handshaking in software vector mode and the

handshake near the end of the interrupt exception handler, is shown in Figure 9-10. The INTC examines

the peripheral and software configurable interrupt requests. When it finds an asserted peripheral or

software configurable interrupt request with a higher priority than PRI in the associated INTC_CPR, it

asserts the interrupt request to the processor. The INTVEC field in the associated INTC_IACKR is

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updated with the preempting interrupt request’s vector when the interrupt request to the processor is

asserted. The INTVEC field retains that value until the next time the interrupt request to the processor is

asserted. The rest of handshaking process is described in Section 9.4.1.1, “Software vector mode.

”

9.6.3.1.2 End of interrupt exception handler

Before the interrupt exception handling completes, INTC end-of-interrupt register (INTC_EOIR) must be written.When written,

the associated LIFO is popped so the preempted priority is restored into PRI of the INTC_CPR. Before it is written, the peripheral

or software configurable flag bit must be cleared so that the peripheral or software configurable interrupt request is negated.

NOTE

To ensure proper operation across all eSys MCUs, execute an MBAR or

MSYNC instruction between the access to clear the flag bit and the write to

the INTC_EOIR.

When returning from the preemption, the INTC does not search for the peripheral or software settable

interrupt request whose ISR was preempted. Depending on how much the ISR progressed, that interrupt

request may no longer even be asserted. When PRI in INTC_CPR is lowered to the priority of the

preempted ISR, the interrupt request for the preempted ISR or any other asserted peripheral or software

settable interrupt request at or below that priority will not cause a preemption. Instead, after the restoration

of the preempted context, the processor will return to the instruction address that it was to next execute

before it was preempted. This next instruction is part of the preempted ISR or the interrupt exception

handler’s prolog or epilog.

Figure 9-10. Software vector mode handshaking timing diagram

010

Clock

Interrupt request to processor

Hardware vector enable

Interrupt vector

Interrupt acknowledge

Read INTC_IACKR

Write INTC_EOIR

INTVEC in INTC_IACKR

PRI in INTC_CPR

Peripheral interrupt request 100

0108

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9.6.3.2 Hardware vector mode handshaking

A timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode, along

with the handshaking near the end of the interrupt exception handler, is shown in Figure 9-11. As in

software vector mode, the INTC examines the peripheral and software settable interrupt requests, and

when it finds an asserted one with a higher priority than PRI in INTC_CPR, it asserts the interrupt request

to the processor. The INTVEC field in the INTC_IACKR is updated with the preempting peripheral or

software settable interrupt request’s vector when the interrupt request to the processor is asserted. The

INTVEC field retains that value until the next time the interrupt request to the processor is asserted. In

addition, the value of the interrupt vector to the processor matches the value of the INTVEC field in the

INTC_IACKR. The rest of the handshaking is described in” Section 9.4.1.2, “Hardware vector mode.

The handshaking near the end of the interrupt exception handler, that is the writing to the INTC_EOIR, is

the same as in software vector mode. Refer to Section 9.6.3.1.2, “End of interrupt exception handler.

Figure 9-11. Hardware vector mode handshaking timing diagram

9.7 Initialization/application information

9.7.1 Initialization flow

After exiting reset, all of the PRIn fields in INTC Priority Select Registers

(INTC_PSR0_3–INTC_PSR220_221) will be zero, and PRI in INTC current priority register

(INTC_CPR) will be 15. These reset values will prevent the INTC from asserting the interrupt request to

the processor. The enable or mask bits in the peripherals are reset such that the peripheral interrupt requests

0108

010

Clock

Interrupt request to processor

Hardware vector enable

Interrupt vector

Interrupt acknowledge

Read INTC_IACKR

Write INTC_EOIR

INTVEC in INTC_IACKR

PRI in INTC_CPR

Peripheral interrupt request 100

0108

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are negated. An initialization sequence for allowing the peripheral and software settable interrupt requests

to cause an interrupt request to the processor is: interrupt_request_initialization:

interrupt_request_initialization:

configure VTES and HVEN in INTC_MCR

configure VTBA in INTC_IACKR

raise the PRIn fields in INTC_PSRn

set the enable bits or clear the mask bits for the peripheral interrupt requests

lower PRI in INTC_CPR to zero

enable processor recognition of interrupts

9.7.2 Interrupt exception handler

These example interrupt exception handlers use Power Architecture assembly code.

9.7.2.1 Software vector mode

interrupt_exception_handler:

code to create stack frame, save working register, and save SRR0 and SRR1

lis r3,INTC_IACKR@ha # form adjusted upper half of INTC_IACKR address

lwz r3,INTC_IACKR@l(r3) # load INTC_IACKR, which clears request to processor

lwz r3,0x0(r3) # load address of ISR from vector table

wrteei 1 # enable processor recognition of interrupts

code to save rest of context required by e500 EABI

mtlr r3 # move INTC_IACKR contents into link register

blrl # branch to ISR; link register updated with epilog

# address

epilog:

code to restore most of context required by e500 EABI

# Popping the LIFO after the restoration of most of the context and the disabling of processor

# recognition of interrupts eases the calculation of the maximum stack depth at the cost of

# postponing the servicing of the next interrupt request.

mbar # ensure store to clear flag bit has completed

lis r3,INTC_EOIR@ha # form adjusted upper half of INTC_EOIR address

li r4,0x0 # form 0 to write to INTC_EOIR

wrteei 0 # disable processor recognition of interrupts

stw r4,INTC_EOIR@l(r3) # store to INTC_EOIR, informing INTC to lower priority

code to restore SRR0 and SRR1, restore working registers, and delete stack frame

rfi

vector_table_base_address:

address of ISR for interrupt with vector 0

address of ISR for interrupt with vector 1

address of ISR for interrupt with vector 510

address of ISR for interrupt with vector 511

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ISRx:

code to service the interrupt event

code to clear flag bit that drives interrupt request to INTC

blr # return to epilog

9.7.2.2 Hardware vector mode

This interrupt exception handler is useful with processor and system bus implementations that support a

hardware vector. This example assumes that each interrupt_exception_handlerx only has space for four

instructions, and therefore a branch to interrupt_exception_handler_continuedx is needed.

interrupt_exception_handlerx:

b interrupt_exception_handler_continuedx# 4 instructions available, branch to continue

interrupt_exception_handler_continuedx:

code to create stack frame, save working register, and save SRR0 and SRR1

wrteei 1 # enable processor recognition of interrupts

code to save rest of context required by e500 EABI

bl ISRx # branch to ISR for interrupt with vector x

epilog:

code to restore most of context required by e500 EABI

# Popping the LIFO after the restoration of most of the context and the disabling of processor

# recognition of interrupts eases the calculation of the maximum stack depth at the cost of

# postponing the servicing of the next interrupt request.

mbar # ensure store to clear flag bit has completed

lis r3,INTC_EOIR@ha # form adjusted upper half of INTC_EOIR address

li r4,0x0 # form 0 to write to INTC_EOIR

wrteei 0 # disable processor recognition of interrupts

stw r4,INTC_EOIR@l(r3) # store to INTC_EOIR, informing INTC to lower priority

code to restore SRR0 and SRR1, restore working registers, and delete stack frame

rfi

ISRx:

code to service the interrupt event

code to clear flag bit that drives interrupt request to INTC

blr # branch to epilog

9.7.3 ISR, RTOS, and task hierarchy

The RTOS and all of the tasks under its control typically execute with PRI in INTC current priority register

(INTC_CPR) having a value of 0. The RTOS will execute the tasks according to whatever priority scheme

that it may have, but that priority scheme is independent and has a lower priority of execution than the

priority scheme of the INTC. In other words, the ISRs execute above INTC_CPR priority 0 and outside

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the control of the RTOS, the RTOS executes at INTC_CPR priority 0, and while the tasks execute at

different priorities under the control of the RTOS, they also execute at INTC_CPR priority 0.

If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then the

task’s priority can be elevated in the INTC_CPR while the shared resource is being accessed.

An ISR whose PRIn in INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR220_221) has a value

of 0 will not cause an interrupt request to the processor, even if its peripheral or software settable interrupt

request is asserted. For a peripheral interrupt request, not setting its enable bit or disabling the mask bit

will cause it to remain negated, which consequently also will not cause an interrupt request to the

processor. Since the ISRs are outside the control of the RTOS, this ISR will not run unless called by another

ISR or the interrupt exception handler, perhaps after executing another ISR.

9.7.4 Order of execution

An ISR with a higher priority can preempt an ISR with a lower priority, regardless of the unique vectors

associated with each of their peripheral or software configurable interrupt requests. However, if multiple

peripheral or software configurable interrupt requests are asserted, more than one has the highest priority,

and that priority is high enough to cause preemption, the INTC selects the one with the lowest unique

vector regardless of the order in time that they asserted. However, the ability to meet deadlines with this

scheduling scheme is no less than if the ISRs execute in the time order that their peripheral or software

configurable interrupt requests asserted.

The example in Table 9-10 shows the order of execution of both ISRs with different priorities and the same

priority

Table 9-10. Order of ISR execution example

Step

#Step Description

Code Executing at End of Step PRI in

INTC_CPR

at End of

Step

RTOS ISR108

ISR20

ISR30

ISR40

Interrupt

Exception

Handler

1 RTOS at priority 0 is executing. X 0

2 Peripheral interrupt request 100 at

priority 1 asserts. Interrupt taken.

3 Peripheral interrupt request 400 at

priority 4 is asserts. Interrupt taken.

4 Peripheral interrupt request 300 at

priority 3 is asserts.

5 Peripheral interrupt request 200 at

priority 3 is asserts.

6 ISR408 completes. Interrupt

exception handler writes to

INTC_EOIR.

7 Interrupt taken. ISR208 starts to

execute, even though peripheral

interrupt request 300 asserted first.

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9.7.5 Priority ceiling protocol

9.7.5.1 Elevating priority

The PRI field in INTC_CPR is elevated in the OSEK PCP to the ceiling of all of the priorities of the ISRs

that share a resource. This protocol allows coherent accesses of the ISRs to that shared resource.

For example, ISR1 has a priority of 1, ISR2 has a priority of 2, and ISR3 has a priority of 3. They share

the same resource. Before ISR1 or ISR2 can access that resource, they must raise the PRI value in

INTC_CPR to 3, the ceiling of all of the ISR priorities. After they release the resource, the PRI value in

INTC_CPR can be lowered. If they do not raise their priority, ISR2 can preempt ISR1, and ISR3 can

preempt ISR1 or ISR2, possibly corrupting the shared resource. Another possible failure mechanism is

deadlock if the higher priority ISR needs the lower priority ISR to release the resource before it can

continue, but the lower priority ISR cannot release the resource until the higher priority ISR completes and

execution returns to the lower priority ISR.

Using the PCP instead of disabling processor recognition of all interrupts eliminates the time when

accessing a shared resource that all higher priority interrupts are blocked. For example, while ISR3 cannot

preempt ISR1 while it is accessing the shared resource, all of the ISRs with a priority higher than 3 can

preempt ISR1.

9.7.5.2 Ensuring coherency

A scenario can cause non-coherent accesses to the shared resource. For example, ISR1 and ISR2 are both

running on the same core and both share a resource. ISR1 has a lower priority than ISR2. ISR1 is executing

8 ISR208 completes. Interrupt

exception handler writes to

INTC_EOIR.

9 Interrupt taken. ISR308 starts to

execute.

10 ISR308 completes. Interrupt

exception handler writes to

INTC_EOIR.

11 ISR108 completes. Interrupt

exception handler writes to

INTC_EOIR.

12 RTOS continues execution. X 0

1ISR108 executes for peripheral interrupt request 100 because the first eight ISRs are for software configurable

interrupt requests.

Table 9-10. Order of ISR execution example (continued)

Step

#Step Description

Code Executing at End of Step PRI in

INTC_CPR

at End of

Step

RTOS ISR108

ISR20

ISR30

ISR40

Interrupt

Exception

Handler

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and writes to the INTC_CPR. The instruction following this store is a store to a value in a shared coherent

data block. Either immediately before or at the same time as the first store, the INTC asserts the interrupt

request to the processor because the peripheral interrupt request for ISR2 has asserted. As the processor is

responding to the interrupt request from the INTC, and as it is aborting transactions and flushing its

pipeline, it is possible that both stores will be executed. ISR2 thereby thinks that it can access the data

block coherently, but the data block has been corrupted.

OSEK uses the GetResource and ReleaseResource system services to manage access to a shared resource.

To prevent corruption of a coherent data block, modifications to PRI in INTC_CPR can be made by those

system services with the code sequence:

disable processor recognition of interrupts

PRI modification

enable processor recognition of interrupts

9.7.6 Selecting priorities according to request rates and deadlines

The selection of the priorities for the ISRs can be made using rate monotonic scheduling (RMS) or a

superset of it, deadline monotonic scheduling (DMS). In RMS, the ISRs that have higher request rates have

higher priorities. In DMS, if the deadline is before the next time the ISR is requested, then the ISR is

assigned a priority according to the time from the request for the ISR to the deadline, not from the time of

the request for the ISR to the next request for it.

For example, ISR1 executes every 100 µs, ISR2 executes every 200 µs, and ISR3 executes every 300 µs.

ISR1 has a higher priority than ISR2, which has a higher priority than ISR3; however, if ISR3 has a

deadline of 150 µs, then it has a higher priority than ISR2.

The INTC has 16 priorities, which may be less than the number of ISRs. In this case, the ISRs should be

grouped with other ISRs that have similar deadlines. For example, a priority could be allocated for every

time the request rate doubles. ISRs with request rates around 1 ms would share a priority, ISRs with request

rates around 500 µs would share a priority, ISRs with request rates around 250 µs would share a priority,

etc. With this approach, a range of ISR request rates of 216 could be included, regardless of the number of

ISRs.

Reducing the number of priorities reduces the processor’s ability to meet its deadlines. However, reducing

the number of priorities can reduce the size and latency through the interrupt controller. It also allows

easier management of ISRs with similar deadlines that share a resource. They do not need to use the PCP

to access the shared resource.

9.7.7 Software configurable interrupt requests

The software configurable interrupt requests can be used in two ways. They can be used to schedule a

lower priority portion of an ISR and they may also be used by processors to interrupt other processors in

a multiple processor system.

9.7.7.1 Scheduling a lower priority portion of an ISR

A portion of an ISR needs to be executed at the PRIx value in INTC Priority Select Registers

(INTC_PSR0_3–INTC_PSR220_221), which becomes the PRI value in INTC_CPR with the interrupt

Chapter 9 Interrupt Controller (INTC)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 227

acknowledge. The ISR, however, can have a portion that does not need to be executed at this higher

priority. Therefore, executing the later portion that does not need to be executed at this higher priority can

prevent the execution of ISRs that do not have a higher priority than the earlier portion of the ISR but do

have a higher priority than what the later portion of the ISR needs. This preemptive scheduling inefficiency

reduces the processor’s ability to meet its deadlines.

One option is for the ISR to complete the earlier higher priority portion, but then schedule through the

RTOS a task to execute the later lower priority portion. However, some RTOSs can require a large amount

of time for an ISR to schedule a task. Therefore, a second option is for the ISR, after completing the higher

priority portion, to set a SETx bit in INTC_SSCIR0_3–INTC_SSCIR4_7. Writing a ‘1’ to SETx causes a

software configurable interrupt request. This software configurable interrupt request will usually have a

lower PRIx value in the INTC_PSRx_x and will not cause preemptive scheduling inefficiencies. After

generating a software settable interrupt request, the higher priority ISR completes. The lower priority ISR

is scheduled according to its priority. Execution of the higher priority ISR is not resumed after the

completion of the lower priority ISR.

9.7.7.2 Scheduling an ISR on another processor

Because the SETx bits in the INTC_SSCIRx_x are memory mapped, processors in multiple-processor

systems can schedule ISRs on the other processors. One application is that one processor wants to

command another processor to perform a piece of work and the initiating processor does not need to use

the results of that work. If the initiating processor is concerned that the processor executing the software

configurable ISR has not completed the work before asking it to again execute the ISR, it can check if the

corresponding CLRx bit in INTC_SSCIRx_x is asserted before again writing a ‘1’ to the SETx bit.

Another application is the sharing of a block of data. For example, a first processor has completed

accessing a block of data and wants a second processor to then access it. Furthermore, after the second

processor has completed accessing the block of data, the first processor again wants to access it. The

accesses to the block of data must be done coherently. To do this, the first processor writes a ‘1’ to a SETx

bit on the second processor. After accessing the block of data, the second processor clears the

corresponding CLRx bit and then writes 1 to a SETx bit on the first processor, informing it that it can now

access the block of data.

9.7.8 Lowering priority within an ISR

A common method for avoiding preemptive scheduling inefficiencies with an ISR whose work spans

multiple priorities (see Section 9.7.7.1, “Scheduling a lower priority portion of an ISR) is to lower the

current priority. However, the INTC has a LIFO whose depth is determined by the number of priorities.

NOTE

Lowering the PRI value in INTC_CPR within an ISR to below the ISR’s

corresponding PRI value in INTC Priority Select Registers

(INTC_PSR0_3–INTC_PSR220_221) allows more preemptions than the

LIFO depth can support.

Therefore, the INTC does not support lowering the current priority within an ISR as a way to avoid

preemptive scheduling inefficiencies.

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228 Freescale Semiconductor

9.7.9 Negating an interrupt request outside of its ISR

9.7.9.1 Negating an interrupt request as a side effect of an ISR

Some peripherals have flag bits that can be cleared as a side effect of servicing a peripheral interrupt

request. For example, reading a specific register can clear the flag bits and their corresponding interrupt

requests. This clearing as a side effect of servicing a peripheral interrupt request can cause the negation of

other peripheral interrupt requests besides the peripheral interrupt request whose ISR presently is

executing. This negating of a peripheral interrupt request outside of its ISR can be a desired effect.

9.7.9.2 Negating multiple interrupt requests in one ISR

An ISR can clear other flag bits besides its own. One reason that an ISR clears multiple flag bits is because

it serviced those flag bits, and therefore the ISRs for these flag bits do not need to be executed.

9.7.9.3 Proper setting of interrupt request priority

Whether an interrupt request negates outside its own ISR due to the side effect of an ISR execution or the

intentional clearing a flag bit, the priorities of the peripheral or software configurable interrupt requests for

these other flag bits must be selected properly. Their PRIx values in INTC Priority Select Registers

(INTC_PSR0_3–INTC_PSR220_221) must be selected to be at or lower than the priority of the ISR that

cleared their flag bits. Otherwise, those flag bits can cause the interrupt request to the processor to assert.

Furthermore, the clearing of these other flag bits also has the same timing relationship to the writing to

INTC_SSCIR0_3–INTC_SSCIR4_7 as the clearing of the flag bit that caused the present ISR to be

executed (see Section 9.6.3.1.2, “End of interrupt exception handler).

A flag bit whose enable bit or mask bit negates its peripheral interrupt request can be cleared at any time,

regardless of the peripheral interrupt request’s PRIx value in INTC_PSRx_x.

9.7.10 Examining LIFO contents

In normal mode, the user does not need to know the contents of the LIFO. He may not even know how

deeply the LIFO is nested. However, if he wants to read the contents, such as in debug mode, they are not

memory mapped. The contents can be read by popping the LIFO and reading the PRI field in either

INTC_CPR. The code sequence is:

pop_lifo:

store to INTC_EOIR

load INTC_CPR, examine PRI, and store onto stack

if PRI is not zero or value when interrupts were enabled, branch to pop_lifo

When the examination is complete, the LIFO can be restored using this code sequence:

push_lifo:

load stacked PRI value and store to INTC_CPR

load INTC_IACKR

if stacked PRI values are not depleted, branch to push_lifo

Chapter 10 System Status and Configuration Module (SSCM)

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Freescale Semiconductor 229

Chapter 10

System Status and Configuration Module (SSCM)

10.1 Introduction

10.1.1 Overview

The System Status and Configuration Module (SSCM), pictured in Figure 10-1, provides central device

functionality.

Figure 10-1. SSCM block diagram

10.1.2 Features

The SSCM includes these features:

• System configuration and status

— Memory sizes/status

— Device mode and security status

— Determine boot vector

— Search Code Flash for bootable sector

— DMA status

• Debug status port enable and selection

Bus

System Status and Configuration Module

Interface

Password

Comparator

RevID

Hardmacro

Core

Logic

System

Status

Peripheral

Interface

Bus

Debug

Port

Chapter 10 System Status and Configuration Module (SSCM)

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230 Freescale Semiconductor

• Bus and peripheral abort enable/disable

10.1.3 Modes of operation

The SSCM operates identically in all system modes.

10.2 Memory map and register description

This section provides a detailed description of all memory-mapped registers in the SSCM.

10.2.1 Memory map

Table 10-1 shows the memory map for the SSCM. Note that all addresses are offsets; the absolute address

may be calculated by adding the specified offset to the base address of the SSCM.

All registers are accessible via 8, 16 or 32-bit accesses. However, 16-bit accesses must be aligned to 16-bit

boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, the MEMCONFIG

Base + 0x0003 is illegal.

10.2.2 Register description

Each description includes a standard register diagram. Details of register bit and field function follow the

numbering of the internal fields is LSB = 0, for example, register SSCM_STATUS[8] = BMODE[2].

Table 10-1. SSCM memory map

Offset from

SSCM_BASE

(0xC3FD_8000)

0x0000 STATUS—System Status register on page 231

0x0002 MEMCONFIG—System Memory Configuration register on page 232

0x0004 Reserved (Reads/Writes have no effect)

0x0006 ERROR—Error Configuration register on page 233

0x0008 DEBUGPORT—Debug Status Port register on page 233

0x000A Reserved (Reads/Writes have no effect)

0x000C

PWCMPH—Password Comparison High Word register

on page 236

0x0010

PWCMPL—Password Comparison Low Word register

on page 236

0x0014–0x3FFF Reserved

Chapter 10 System Status and Configuration Module (SSCM)

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Freescale Semiconductor 231

Figure 10-2. Key to register fields

10.2.2.1 System Status register (STATUS)

The system status register is a read-only register that reflects the current state of the system.

Always

1Always

0R/W

bit

BIT Read-

only bit

BIT Write-

only bit

Write 1

to clear

BIT Self-

clear

bit

0N/A

BIT w1

BIT

Address:

Base + 0x0000 Access: Read-only

0123456789101112131415

R0 0 0 0

NXEN

PUB SEC 0 BMODE[2:0] 0 ABD 0 0 0

RESET: 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0

Figure 10-3. Status (STATUS) register

Table 10-2. STATUS allowed register accesses

Access type

Access width

8-bit 16-bit 32-bit1

1All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8, or 0xC).

Read Allowed Allowed Allowed

Write Not allowed Not allowed Not allowed

Table 10-3. STATUS field descriptions

Field Description

NXEN Nexus enabled

PUB Public Serial Access Status

This bit indicates whether serial boot mode with public password is allowed.

1: Serial boot mode with public password allowed

0: Serial boot mode with private Flash password allowed, provided the key has not been swallowed

SEC Security Status

This bit reflects the current security state of the Flash.

1: Flash secured

0: Flash not secured

BMODE

[2:0]

Device Boot Mode

000: TestFlash

001: CAN Serial Boot Loader

010: SCI Serial Boot Loader

011: Single Chip

100–111: Reserved

This field is updated only during reset.

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10.2.2.2 System Memory Configuration register (MEMCONFIG)

The system memory configuration register is a read-only register that reflects the memory configuration

of the system.

ABD Autobaud

Indicates that autobaud detection is active when in SCI or CAN serial boot loader mode. No meaning in

other modes.

Address:

Base + 0x0002 Access: Read-only

0123456789101112131415

R0000000000IVLD0000

DVLD

Reset0000000000000000

Figure 10-4. System memory configuration (MEMCONFIG) register

Table 10-4. MEMCONFIG field descriptions

Field Description

IVLD

CFlash Valid

This bit identifies whether or not the on-chip CFlash is accessible in the system memory map. The Flash

may not be accessible due to security limitations.

1: CFlash accessible

0: CFlash not accessible

Note: This is a status bit only and writing to this bit does not enable the CFlash if it has been disabled due

to specific mode of operation.

DVLD DFlash Valid

This bit identifies whether or not the on-chip DFlash is visible in the system memory map. The Flash may

not be accessible due to security limitations.

1: DFlash visible

0: DFlash not visible

Note: This is a status bit only and writing to this bit does not enable the CFlash if it has been disabled due

to specific mode of operation.

Table 10-5. MEMCONFIG allowed register accesses

Access type

Access width

8-bit 16-bit 32-bit

Read Allowed Allowed Allowed

(also reads STATUS

Write Not allowed Not allowed Not allowed

Table 10-3. STATUS field descriptions (continued)

Field Description

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 233

10.2.2.3 Error Configuration (ERROR) register

The Error Configuration register is a read-write register that controls the error handling of the system.

NOTE

Transfers to Peripheral Bus resources may be aborted even before they

reach the Peripheral Bus (i.e., at the PRIDGE level). In this case, the PAE

and RAE register bits will have no effect on the abort.

10.2.2.4 Debug Status Port (DEBUGPORT) register

The Debug Status Port register provides debug data on a set of pins.

Address:

Base + 0x0006 Access: User read/write

0123456789101112131415

R00000000000000

PA E R A E

Reset0000000000000000

Figure 10-5. Error Configuration (ERROR) register

Table 10-6. ERROR field descriptions

Field Description

PAE Peripheral Bus Abort Enable

This bit enables bus aborts on any access to a peripheral slot that is not used on the device. This feature

is intended to aid in debugging when developing application code.

1: Illegal accesses to non-existing peripherals produce a Prefetch or Data Abort exception.

0: Illegal accesses to non-existing peripherals do not produce a Prefetch or Data Abort exception.

RAE Register Bus Abort Enable

This bit enables bus aborts on illegal accesses to off-platform peripherals. Illegal accesses are defined

as reads or writes to reserved addresses within the address space for a particular peripheral. This feature

is intended to aid in debugging when developing application code.

1: Illegal accesses to peripherals produce a Prefetch or Data Abort exception.

0: Illegal accesses to peripherals do not produce a Prefetch or Data Abort exception.

Table 10-7. ERROR allowed register accesses

Access type

Access width

8-bit 16-bit 32-bit

Read Allowed Allowed Allowed

Write Allowed Allowed Not allowed

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Address:

Base + 0x0008 Access: User read/write

0123456789101112131415

R0000000000000

DEBUG_MODE

[2:0]

Reset0000000000000000

Figure 10-6. Debug Status Port (DEBUGPORT) register

Table 10-8. DEBUGPORT field descriptions

Field Description

13-15

DEBUG_MODE[2:0]

Debug Status Port Mode

This field selects the alternate debug functionality for the Debug Status Port.

000: No alternate functionality selected

001: Mode 1 selected

010: Mode 2 selected

011: Mode 3 selected

100: Mode 4 selected

101: Mode 5 selected

110: Mode 6 selected

111: Mode 7 selected

Table 10-9 describes the functionality of the Debug Status Port in each mode.

Table 10-9. Debug Status Port modes

1All signals are active high, unless otherwise noted

Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

0 STATUS[0] STATUS[8] MEMCONFIG[0

]

MEMCONFIG[8] Reserved Reserved Reserved

1 STATUS[1] STATUS[9] MEMCONFIG[1

]

MEMCONFIG[9] Reserved Reserved Reserved

2 STATUS[2] STATUS[10] MEMCONFIG[2

]

MEMCONFIG[10

]

Reserved Reserved Reserved

3 STATUS[3] STATUS[11] MEMCONFIG[3

]

MEMCONFIG[11

]

Reserved Reserved Reserved

4 STATUS[4] STATUS[12] MEMCONFIG[4

]

MEMCONFIG[12

]

Reserved Reserved Reserved

5 STATUS[5] STATUS[13] MEMCONFIG[5

]

MEMCONFIG[13

]

Reserved Reserved Reserved

6 STATUS[6] STATUS[14] MEMCONFIG[6

]

MEMCONFIG[14

]

Reserved Reserved Reserved

7 STATUS[7] STATUS[15] MEMCONFIG[7

]

MEMCONFIG[15

]

Reserved Reserved Reserved

Chapter 10 System Status and Configuration Module (SSCM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 235

Table 10-10. DEBUGPORT allowed register accesses

Access type

Access width

8-bit 16-bit 32-bit1

1All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC).

Read Allowed Allowed Not allowed

Write Allowed Allowed Not allowed

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236 Freescale Semiconductor

10.2.2.5 Password comparison registers

These registers allow to unsecure the device, if the correct password is known.

Address:

Base + 0x000C Access: User read/write

0123456789101112131415

R0000000000000000

W PWD_HI[31:16]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000000000000000

W PWD_HI[15:0]

Reset0000000000000000

Figure 10-7. Password Comparison Register High Word (PWCMPH) register

Address:

Base + 0x0010 Access: User read/write

0123456789101112131415

R0000000000000000

W PWD_LO[31:16]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000000000000000

W PWD_LO[15:0]

Reset0000000000000000

Figure 10-8. Password Comparison Register Low Word (PWCMPL) register

Table 10-11. PWCMPH/L field descriptions

Field Description

PWD_HI[31:0] Upper 32 bits of the password

PWD_LO[31:0] Lower 32 bits of the password

Table 10-12. PWCMPH/L allowed register accesses

Access type

Access width

8-bit 16-bit 32-bit1

1All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC).

Read Allowed Allowed Allowed

Write Not allowed Not allowed Allowed

Chapter 10 System Status and Configuration Module (SSCM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 237

10.3 Functional description

The primary purpose of the SSCM is to provide information about the current state and configuration of

the system that may be useful for configuring application software and for debug of the system.

10.4 Initialization/application information

10.4.1 Reset

The reset state of each individual bit is shown in Section 10.2.2, “Register description.

Chapter 10 System Status and Configuration Module (SSCM)

MPC5602P Microcontroller Reference Manual, Rev. 4

238 Freescale Semiconductor

Chapter 11 System Integration Unit Lite (SIUL)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 239

Chapter 11

System Integration Unit Lite (SIUL)

11.1 Introduction

This chapter describes the System Integration Unit Lite (SIUL), which is used for the management of the

pads and their configuration. It controls the multiplexing of the alternate functions used on all pads and is

responsible for managing the external interrupts to the device.

11.2 Overview

The System Integration Unit Lite (SIUL) controls the MCU pad configuration, ports, general-purpose

input and output (GPIO) signals and external interrupts with trigger event configuration. Figure 11-1 is a

block diagram of the SIUL and its interfaces to other system components.

The module provides dedicated general-purpose pads that can be configured as either inputs or outputs.

When configured as an output, you can write to an internal register to control the state driven on the

associated output pad. When configured as an input, you can detect the state of the associated pad by

reading the value from an internal register. When configured as an input and output, the pad value can be

read back, which can be used a method of checking if the written value appeared on the pad.

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240 Freescale Semiconductor

Figure 11-1. System Integration Unit Lite block diagram

11.3 Features

The System Integration Unit Lite provides these features:

•GPIO

— GPIO function on up to 64 I/O pins

— Dedicated input and output registers for each GPIO pin

• External interrupts

— 4 system interrupt vectors for up to 25 interrupt sources

— 25 programmable digital glitch filters

— Independent interrupt mask

— Edge detection

IPS

BUS

Data

Pad Input

Interrupt

Controller

IPS

Master

– Configuration

– Glitch Filter

Pad Configuration (IOMUXC)

Pad Config (PCRs)

GPIO Functionality

MUX Pads

SIUL Module

Interrupt Functionality

Chapter 11 System Integration Unit Lite (SIUL)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 241

• System configuration

— Pad configuration control

11.3.1 Register protection

Most of the configuration registers of the System Integration Unit Lite are protected from accidental

writes, see Appendix A, “Registers Under Protection.

11.4 External signal description

The pad configuration allows flexible, centralized control of the pin electrical characteristics of the MCU

with the GPIO control providing centralized general purpose I/O for an MCU that multiplexes GPIO with

other signals at the I/O pads. These other signals, or alternate functions, will normally be the peripherals

functions. The internal multiplexing allows user selection of the input to chip-level signal multiplexers.

Each GPIO port communicates via 16 I/O channels. In order to use the pad as a GPIO, the corresponding

Pad Configuration Registers (PCR[0:71]) for all pads used in the port must be configured as GPIO rather

than as the alternate pad function.

Table 11-1 lists the external pins used by the SIUL.

(

11.4.1 Detailed signal descriptions

11.4.1.1 General-purpose I/O pins (GPIO[0:66])

The GPIO pins provide general-purpose input and output function. The GPIO pins are generally

multiplexed with other I/O pin functions. Each GPIO input and output is separately controlled by an input

(GPDIn_n) or output (GPDOn_n) register.

See Section 11.5.2.10, “GPIO Pad Data Output registers 0_3–68_71 (GPDO[0_3:68_71]) and

Section 11.5.2.11, “GPIO Pad Data Input registers 0_3–68_71 (GPDI[0_3:68_71]).

11.4.1.2 External interrupt request input pins (EIRQ[0:24])

The EIRQ[0:24] are connected to the SIUL inputs. Rising or falling edge events are enabled by setting the

corresponding bits in the “n” SIUL_IREER or the SIUL_IFEER register. See Section 11.5.2.5, “Interrupt

Table 11-1. SIUL signal properties

GPIO category Name I/O direction Function

System configuration GPIO[0:19],

GPIO[22],

GPIO[35:62]

Input/Output General-purpose input/output

GPIO[23:34],

GPIO[63],

GPIO[65:66]

Input Analog precise channel pins

External interrupt EIRQ[0:24] Input Pins with External Interrupt Request functionality.

Please refer to the signal description chapter of this

reference manual for details.

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242 Freescale Semiconductor

Rising-Edge Event Enable Register (IREER) and Section 11.5.2.6, “Interrupt Falling-Edge Event Enable

11.5 Memory map and register description

This section provides a detailed description of all registers accessible in the SIUL module.

11.5.1 SIUL memory map

Table 11-2 lists the SIUL registers.

Table 11-2. SIUL memory map

Offset from

SIUL_BASE

(0xC3F9_0000)

0x0000–0x0003 Reserved

0x0004 MCU ID Register #1 (MIDR1) on page 243

0x0008 MCU ID Register #2 (MIDR2) on page 245

0x000C–0x0013 Reserved

0x0014 Interrupt Status Flag Register (ISR) on page 246

0x0018 Interrupt Request Enable Register (IRER) on page 246

0x001C–0x0027 Reserved

0x0028 Interrupt Rising-Edge Event Enable Register (IREER) on page 247

0x002C Interrupt Falling-Edge Event Enable Register (IFEER) on page 247

0x0030 Interrupt Filter Enable Register (IFER) on page 248

0x0034–0x003F Reserved

0x0040–0x00CE Pad Configuration Registers (PCR[0:71]) on page 248

0x00D0–0x04FF Reserved

0x0500–0x0520 Pad Selection for Multiplexed Inputs registers (PSMI[0_3:32_35]) on page 250

0x0524–0x05FF Reserved

0x0600–0x0644 GPIO Pad Data Output registers 0_3–68_71 (GPDO[0_3:68_71]) on page 254

0648

–0x07FF Reserved

0x0800–0x

0844

GPIO Pad Data Input registers 0_3–68_71 (GPDI[0_3:68_71]) on page 254

0x0848–0x0BFF

Reserved

0x0C00–0x0C0C

Parallel GPIO Pad Data Out register 0–3 (PGPDO[0:3]) on page 255

0x0C10–0x0C3F

Reserved

0x0C40–0x0C4C

Parallel GPIO Pad Data In register 0–3 (PGPDI[0:3]) on page 255

0x0C50–0x0C7F Reserved

0x0C80–0x0C98

Masked Parallel GPIO Pad Data Out register 0–6 (MPGPDO[0:6]) on page 256

Chapter 11 System Integration Unit Lite (SIUL)

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Freescale Semiconductor 243

NOTE

A transfer error will be issued when trying to access completely reserved

11.5.2 Register description

This section describes in address order all the SIUL registers. Each description includes a standard register

diagram. Details of register bit and field function follow the register diagrams, in bit order. The numbering

convention of register is MSB = 0, however the numbering of internal field is LSB = 0, for example

PARTNUM[5] = MIDR1[10].

Figure 11-2. Key to register fields

11.5.2.1 MCU ID Register #1 (MIDR1)

This register contains the part number and the package ID of the device.

0x0C9C–

0x0FFF Reserved

0x1000–0x

1060

Interrupt Filter Maximum Counter registers 0–24 (IFMC[0:24]) on page 257

0x1064–0x107C Reserved

0x1080 Interrupt Filter Clock Prescaler Register (IFCPR) on page 257

0x1084–0x3FFF Reserved

Always

1Always

R/W bit BIT

Read-

only bit

BIT Write-

only bit

Write 1

to clear

BIT Self-

clear bit

0N/A

BIT w1c BIT

Address:

Base + 0x0004 Access: User read-only

0123456789101112131415

R PARTNUM[15:0]

Reset0101011000000010

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R CSP PKG[4:0] 0 0 MAJOR_MASK[3:0]1

1See Ta bl e 1 1- 3 .

MINOR_MASK[3:0]1

Reset0010010000000000

Figure 11-3. MCU ID Register #1 (MIDR1)

Table 11-2. SIUL memory map (continued)

Offset from

SIUL_BASE

(0xC3F9_0000)

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244 Freescale Semiconductor

Table 11-3. MIDR1 field descriptions

Field Description

PARTNUM[15:0] MCU Part Number

Device part number of the MCU.

0101_0110_0000_0001: 192 KB

0101_0110_0000_0010: 256 KB

0101_0110_0000_0011:384 KB

For the full part number this field needs to be combined with MIDR2.PARTNUM[23:16]

CSP Always reads back 0

PKG[4:0] Package Settings

Can by read by software to determine the package type that is used for the particular device:

00001: 64-pin LQFP

01001: 100-pin LQFP

MAJOR_MASK[3:0] Major Mask Revision

Counter starting at 0x0. Incremented each time a resynthesis is done.

MINOR_MASK[3:0] Minor Mask Revision

Counter starting at 0x0. Incremented each time a mask change is done.

Chapter 11 System Integration Unit Lite (SIUL)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 245

11.5.2.2 MCU ID Register #2 (MIDR2)

This register contains additional configuration information about the device.

Address:

Base + 0x0008 Access: User read-only

0123456789101112131415

R SF FLASH_SIZE_1[3:0] FLASH_SIZE_2[3:0] 0 0 0 0000

Reset0010000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R PARTNUM[23:16] 0 00EE000FR

Reset01010000000x

1The reset value of this bit depends on the device sales type.

0000

Figure 11-4. MCU ID Register #2 (MIDR2)

Table 11-4. MIDR2 field descriptions

Field Description

SF Manufacturer

0: Freescale

1: Reserved

FLASH_SIZE_1[3:0] Coarse granularity for Flash memory size

Needs to be combined with FLASH_SIZE_2 to calculate the actual memory size.

0011: 128 KB

0100: 256 KB

Other values are reserved.

FLASH_SIZE_2[3:0] Fine granularity for Flash memory size

Needs to be combined with FLASH_SIZE_1 to calculate the actual memory size.

0000: 0 x (FLASH_SIZE_1 / 8)

0010: 2 x (FLASH_SIZE_1 / 8)

0100: 4 x (FLASH_SIZE_1 / 8)

Other values are reserved.

PARTNUM[23:16] ASCII character in MCU Part Number

0x50: P family (Steering)

EE Data Flash present

0: No Data Flash present

1: Data Flash present

FR FlexRay present

0: No FlexRay present

1: FlexRay present

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11.5.2.3 Interrupt Status Flag Register (ISR)

This register holds the interrupt flags.

11.5.2.4 Interrupt Request Enable Register (IRER)

This register enables the interrupt messaging to the interrupt controller.

Address:

Base + 0x0014 Access: User read/write

0123456789101112131415

REIF[24:16]

Ww1c

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R EIF[15:0]

Ww1c

Reset0000000000000000

Figure 11-5. Interrupt Status Flag Register (ISR)

Table 11-5. ISR field descriptions

Field Description

EIFnExternal Interrupt Status Flag n

This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (IRERn), EIFn

causes an interrupt request.

0: No interrupt event has occurred on the pad.

1: An interrupt event as defined by IREERn and IFEERn has occurred.

Address:

Base + 0x0018 Access: User read/write

0123456789101112131415

RIRE[24:16]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RIRE[15:0]

Reset0000000000000000

Figure 11-6. Interrupt Request Enable Register (IRER)

Table 11-6. IRER field descriptions

Field Description

IREnExternal Interrupt Request Enable n

0: Interrupt requests from the corresponding EIFn bit are disabled.

1: A set EIFn bit causes an interrupt request.

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11.5.2.5 Interrupt Rising-Edge Event Enable Register (IREER)

This register allows rising-edge triggered events to be enabled on the corresponding interrupt pads.

11.5.2.6 Interrupt Falling-Edge Event Enable Register (IFEER)

This register allows falling-edge triggered events to be enabled on the corresponding interrupt pads.

Address:

Base + 0x0028 Access: User read/write

0123456789101112131415

RIREE[24:16]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RIREE[15:0]

Reset0000000000000000

Figure 11-7. Interrupt Rising-Edge Event Enable Register (IREER)

Table 11-7. IREER field descriptions

Field Description

IREEnEnable rising-edge events to cause the EIFn bit to be set.

0: Rising-edge event disabled

1: Rising-edge event enabled

Address:

Base + 0x002C Access: User read/write

0123456789101112131415

RIFEE[24:16]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RIFEE[15:0]

Reset0000000000000000

Figure 11-8. Interrupt Falling-Edge Event Enable Register (IFEER)

Table 11-8. IFEER field descriptions

Field Description

IFEEnEnable falling-edge events to cause the EIFn bit to be set.

0: Falling-edge event disabled

1: Falling-edge event enabled

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NOTE

If both the IREER.IREE and IFEER.IFEE bits are cleared for the same

interrupt source, the interrupt status flag for the corresponding external

interrupt will never be set.

11.5.2.7 Interrupt Filter Enable Register (IFER)

This register enables a digital filter counter on the corresponding interrupt pads to filter out glitches on the

inputs.

11.5.2.8 Pad Configuration Registers (PCR[0:71])

The Pad Configuration Registers allow configuration of the static electrical and functional characteristics

associated with I/O pads. Each PCR controls the characteristics of a single pad.

NOTE

16/32-bit access is supported for the PCR[0:71] registers.

Address:

Base + 0x0030 Access: User read/write

0123456789101112131415

RIFE[24:16]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RIFE[15:0]

Reset0000000000000000

Figure 11-9. Interrupt Filter Enable Register (IFER)

Table 11-9. IFER field descriptions

Field Description

IFEnEnable digital glitch filter on the interrupt pad input.

0: Filter disabled

1: Filter enabled

Address:

Base + 0x0040 (PCR0)

...

Base + 0x00CE (PCR71) 72 registers

Access: User read/write

0123456789101112131415

R0 SMC APC 0PA[1:0] OBE IBE 00

ODE 00

SRC WPE WPS

Reset1

1See Table 11-11.

0000000000000000

Figure 11-10. Pad Configuration Registers 0–71 (PCR[0:71])

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Table 11-10. PCR[0:71] field descriptions

Field Description

SMC Safe Mode Control

This bit supports the overriding of the automatic deactivation of the output buffer of the associated

pad upon entering Safe mode of the device.

0: In Safe mode, output buffer of the pad disabled

1: In Safe mode, output buffer remains functional

APC Analog Pad Control

This bit enables the usage of the pad as analog input.

0: Analog input path from the pad is gated and cannot be used.

1: Analog input path switch can be enabled by the ADC.

PA[1:0] Pad Output Assignment

This field selects the function that is allowed to drive the output of a multiplexed pad.The PA field

size can vary from 0 to 2 bits, depending on the number of output functions associated with this

pad.

00: Alternative mode 0: GPIO

01: Alternative mode 1 (see Chapter 3, “Signal Description)

10: Alternative mode 2 (see Chapter 3, “Signal Description)

11: Alternative mode 3 (see Chapter 3, “Signal Description)

Note: The number of bits in the PA bitfield depends of the number of actual alternate functions

provided for each pad. Please see the MPC5602P Datasheet (MPC5602P).

OBE Output Buffer Enable

This bit enables the output buffer of the pad in case the pad is in GPIO mode.

0: Output buffer of the pad disabled when PA = 00

1: Output buffer of the pad enabled when PA = 00

IBE Input Buffer Enable

This bit enables the input buffer of the pad.

0: Input buffer of the pad disabled

1: Input buffer of the pad enabled

ODE Open Drain Output Enable

This bit controls output driver configuration for the pads connected to this signal. Either open drain

or push/pull driver configurations can be selected. This feature applies to output pads only.

0: Open drain enable signal negated for the pad

1: Open drain enable signal asserted for the pad

SRC Slew Rate Control

0: Slowest configuration

1: Fastest configuration

WPE Weak Pull Up/Down Enable

This bit controls whether the weak pull up/down devices are enabled/disabled for the pad

connected to this signal.

0: Weak pull device enable signal negated for the pad

1: Weak pull device enable signal asserted for the pad

WPS Weak Pull Up/Down Select

This bit controls whether weak pull up or weak pull down devices are used for the pads connected

to this signal when weak pull up/down devices are enabled.

0: Pull down enabled

1: Pull up enabled

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In addition to the bit map above, the following Table 11-12 [PCR bit implementation by pad type]

describes the PCR depending on the pad type (refer to Section 11.7, “Pin muxing for pad types

description). The bits in shaded fields are not implemented for the particular I/O type. The PA field

selecting the number of alternate functions may or may not be present depending on the number of

alternate functions actually mapped on the pad.

11.5.2.9 Pad Selection for Multiplexed Inputs registers (PSMI[0_3:32_35])

The purpose of the PSMI[0_3:32_35] registers is to allow connecting a single input pad to one of several

peripheral inputs. Thus, it is possible to define different pads to be possible inputs for a certain peripheral

function.

Table 11-11. PCR[n] reset value exceptions

Field Description

PCR[2]

PCR[3]

PCR[4]

These registers correspond to the ABS[0], ABS[1], and FAB boot pins, respectively. Their default

state is input, pull enabled. Their reset value is 0x0102.

PCR[20] This register corresponds to the TDO pin. Its default state is ALT1, slew rate = 1. Its reset value is

0x0604.

PCR[21] This register corresponds to the TDI pin. Its default state is input, pull enabled, pull selected, slew

enabled. So its reset value is 0x0107.

PCR[n] For other PCR[n] registers, the reset value is 0x0000.

Table 11-12. PCR bit implementation by pad type

Pad type

PCR bit No.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

S, M, F (Pad

with GPIO

and digital

alternate

functionality)

SMC APC PA [1:0] OBE IBE ODE SRC WPE WPS

I (Pad with

GPIO and

analog

functionality)

SMC APC PA [1:0] OBE IBE ODE SRC WPE WPS

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Address:

Base + 0x0500 (PSMI0_3)

Base + 0x0504 (PSMI4_7)

Base + 0x0508 (PSMI8_11)

Base + 0x050C (PSMI12_15)

Base + 0x0510 (PSMI16_19)

Base + 0x0514 (PSMI20_23)

Base + 0x0518 (PSMI024_27)

Base + 0x051C (PSMI28_31)

Base + 0x0520 (PSMI32_35)

Access: User read/write

0123456789101112131415

R0000 PADSEL0[3:0] 0000 PADSEL1[3:0]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000 PADSEL2[3:0] 0000 PADSEL3[3:0]

Reset0000000000000000

Figure 11-11. Pad Selection for Multiplexed Inputs registers (PSMI[0_3:32_35])

Table 11-13. PSMI[0_3:32_35] field descriptions

Field Description

PADSEL0–3

...

PADSEL32–35

Pad Selection Bits

Each PADSEL field selects the pad currently used for a certain input function. See Table 11-14

Pad selection.

Table 11-14. Pad selection

value1Port name

LQFP pin

64-pin 100-pin

PSMI0_32PADSEL0 ctu0 EXT_IN 0000 C[13] — 71

0001 C[15] — 85

PADSEL1 dspi2 SCK 0000 A[0] — 51

0001 A[11] 53 82

PADSEL2 dspi2 SIN 0000 A[2] — 57

0001 A[13] 61 95

PADSEL3 dspi2 CS0 0000 A[3] 41 64

0001 A[10] 52 81

PSMI4_73PADSEL0 — — — — — —

PADSEL1 — — — — — —

PADSEL2 — — — — — —

PADSEL3 eTimer0 ETC[4] 0000 A[4] 48 75

0001 C[11] 33 55

0010 B[14] — 44

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PSMI8_112PADSEL0 eTimer0 ETC[5] 0000 C[12] 34 56

0001 B[8] 22 31

PADSEL1 — — — — — —

PADSEL2 — — — — — —

PADSEL3 — — — — — —

PSMI12_152PADSEL0 — — — — — —

PADSEL1 — — — — — —

PADSEL2 — — — — — —

PADSEL3 flexpwm0 EXT_SYNC 0000 C[13] — 71

0001 C[15] — 85

PSMI16_193PADSEL0 flexpwm0 FAULT0 0000 A[9] 60 94

0001 A[13] 61 95

PADSEL1 flexpwm0 FAULT1 0000 C[10] — 78

0001 D[6] — 23

PADSEL2 — — — — — —

PADSEL3 — — — — — —

PSMI20_23 PADSEL0 — — — — — —

PADSEL1 — — — — — —

PADSEL2 — — — — — —

PADSEL3 — — — — — —

PSMI24_27 PADSEL0 — — — — — —

PADSEL1 — — — — — —

PADSEL2 — — — — — —

PADSEL3 — — — — — —

PSMI28_312PADSEL0 — — — — — —

PADSEL1 — — — — — —

PADSEL2 — — — — — —

PADSEL3 LINflex0 RXD—Receive

Data Input Line

0000 B[3] — 80

0001 B[7] 20 29

PSMI32_353PADSEL0 LINflex1 RXD—Receive

Data Input Line

0000 B[13] 30 42

0001 D[12] 45 70

Table 11-14. Pad selection (continued)

value1Port name

LQFP pin

64-pin 100-pin

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1Values not listed are reserved.

2Writing to PADSELx[3:1] has no effect—a write to these three bits will return ‘0’.

3Writing to PADSELx[3:2] has no effect—a write to these two bits will return ‘0’.

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11.5.2.10 GPIO Pad Data Output registers 0_3–68_71 (GPDO[0_3:68_71])

These registers can be used to set or clear a single GPIO pad with a byte access.

11.5.2.11 GPIO Pad Data Input registers 0_3–68_71 (GPDI[0_3:68_71])

These registers can be used to read the GPIO pad data with a byte access.

Address: Base + 0x0600 (GPDO0_3)

...

Base + 0x0644 (GPDO68_71) 18 registers

Access: User read/write

0123456789101112131415

R000000 0 PDO

[0]

0000000

PDO

[1]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R 0 000000

PDO

[2]

0000000

PDO

[3]

Reset0000000000000000

Figure 11-12. Port GPIO Pad Data Output registers 0_3–68_71 (GPDO[0_3:68_71])

Table 11-15. GPDO[0_3:68_71] field descriptions

Field Description

PDO[n] Pad Data Out

This bit stores the data to be driven out on the external GPIO pad controlled by this register.

0: Logic low value is driven on the corresponding GPIO pad when the pad is configured as an

output.

1: Logic high value is driven on the corresponding GPIO pad when the pad is configured as an

output.

Address: Base + 0x0800 (GPDI0_3)

...

Base + 0x0844 (GPDI68_71) 18 registers

Access: User read-only

0123456789101112131415

R000000 0 PDI

[0] 0000000

PDI

[1]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000000

PDI

[2] 0000000

PDI

[3]

Reset0000000000000000

Figure 11-13. GPIO Pad Data Input registers 0_3–68_71 (GPDI[0_3:68_71])

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11.5.2.12 Parallel GPIO Pad Data Out register 0–3 (PGPDO[0:3])

These registers set or clear the respective pads of the device.

NOTE

The PGPDO registers access the same physical resource as the PDO and

MPGPDO address locations. Some examples of the mapping:

PPDO[0][0] = PDO[0]

PPDO[2][0] = PDO[32]

11.5.2.13 Parallel GPIO Pad Data In register 0–3 (PGPDI[0:3])

These registers hold the synchronized input value from the pads.

Table 11-16. GPDI[0_3:68_71] field descriptions

Field Description

PDI[x] Pad Data In

This bit stores the value of the external GPIO pad associated with this register.

0: The value of the data in signal for the corresponding GPIO pad is logic low.

1: The value of the data in signal for the corresponding GPIO pad is logic high.

Address: Base + 0x0C00 (PGPDO0)

Base + 0x0C04 (PGPDO1)

Base + 0x0C05 (PGPDO2)

Base + 0x0C0C (PGPDO3)

Access: User read/write

0123456789101112131415

RPPDO[x][15:0]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RPPDO[x+ 1][15:0]

Reset0000000000000000

Figure 11-14. Parallel GPIO Pad Data Out register 0–3(PGPDO[0:3])

Table 11-17. PGPDO0_3 field descriptions

Field Description

PPDO[x] Parallel Pad Data Out

Write or read the data register that stores the value to be driven on the pad in output mode.

Accesses to this register location are coherent with accesses to the bit-wise GPIO Pad Data

Output registers 0_3–68_71 (GPDO[0_3:68_71]).

The x and bit index define which PPDO register bit is equivalent to which PDO register bit

according to the following equation:

PPDO[x][y]=PDO[(x*16)+y]

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11.5.2.14 Masked Parallel GPIO Pad Data Out register 0–6 (MPGPDO[0:6])

This register can be used to selectively modify the pad values associated to PPDO[x][15:0]. The

MPGPDO[x] register may only be accessed with 32-bit writes. 8-bit or 16-bit writes will not modify any

bits in the register and cause a transfer error response by the module. Read accesses will return 0.

Address: Base + 0x0C40 (PGPDI0)

Base + 0x0C44 (PGPDI1)

Base + 0x0C45 (PGPDI2)

Base + 0x0C4C (PGPDI3)

Access: User read-only

0123456789101112131415

R PPDI[x][15:0]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RPPDI[x+ 1][15:0]

Reset0000000000000000

Figure 11-15. Parallel GPIO Pad Data In register 0–3 (PGPDI[0:3])

Table 11-18. PGPDI[0:3] field descriptions

Field Description

PPDI[x] Parallel Pad Data In

Read the current pad value. Accesses to this register location are coherent with accesses to the

bit-wise GPIO Pad Data Input registers 0_3–68_71 (GPDI[0_3:68_71]).

The x and bit index define which PPDI register bit is equivalent to which PDI register bit according

to the following equation:

PPDI[x][y]=PDI[(x*16)+y]

Address: Base + 0x0C80 (MPGPDO0)

Base + 0x0C84 (MPGPDO1)

Base + 0x0C88 (MPGPDO2)

Base + 0x0C8C (MPGPDO3)

Base + 0x0C80 (MPGPDO4)

Base + 0x0C84 (MPGPDO5)

Base + 0x0C98 (MPGPDO6)

Access: User write-only

0123456789101112131415

R0000000000000000

W MASK[x][15:0]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R 0 000000000000000

WMPPDO[x][15:0]

Reset0000000000000000

Figure 11-16. Masked Parallel GPIO Pad Data Out register 0–6 (MPGPDO[0:6])

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11.5.2.15 Interrupt Filter Maximum Counter registers 0–24 (IFMC[0:24])

These registers configure the filter counter associated with each digital glitch filter.

11.5.2.16 Interrupt Filter Clock Prescaler Register (IFCPR)

This register configures a clock prescaler that selects the clock for all digital filter counters in the SIUL.

Table 11-19. MPGPDO[0:6] field descriptions

Field Description

MASK[x]

[15:0]

Mask Field

Each bit corresponds to one data bit in the MPPDO[x] field at the same bit location.

0: The associated bit value in the MPPDO[x] field is ignored.

1: The associated bit value in the MPPDO[x] field is written.

MPPDO[x]

[15:0]

Masked Parallel Pad Data Out

Write the data register that stores the value to be driven on the pad in output mode.

Accesses to this register location are coherent with accesses to the bit-wise GPIO Pad Data

Output registers 0_3–68_71 (GPDO[0_3:68_71]).

The x and bit index define which MPPDO register bit is equivalent to which PDO register bit

according to the following equation:

MPPDO[x][y] = PDO[(x*16)+y]

Address: Base + 0x1000 (IFMC0)

...

Base + 0x

1060

(IFMC24) 25 registers

Access: User read/write

0123456789101112131415

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R 0 00000000000 MAXCNTx[3:0]

Reset0000000000000000

Figure 11-17. Interrupt Filter Maximum Counter registers 0–24 (IFMC[0:24])

Table 11-20. IFMC[0:24] field descriptions

Field Description

MAXCNTx

[3:0]

Maximum Interrupt Filter Counter setting.

Filter Period = (TCK × MAXCNTx) +(n×T

CK)

Where n can be –2 to 3

MAXCNTx can be 0 to 15

TCK: Prescaled Filter Clock Period, which is IRC clock prescaled to IFCP value

TIRC: Basic Filter Clock Period: 62.5 ns (fIRC =16MHz)

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Address: Base + 0x1080 Access: User read/write

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R 0 00000000000 IFCP[3:0]

Reset0000000000000000

Figure 11-18. Interrupt Filter Clock Prescaler Register (IFCPR)

Table 11-21. IFCPR field descriptions

Field Description

IFCP

[3:0]

Interrupt Filter Clock Prescaler setting

Prescaled Filter Clock Period = TIRC ×(IFCP+1)

TIRC is the internal oscillator period.

IFCP can be 0 to 15.

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11.6 Functional description

11.6.1 General

This section provides a functional description of the System Integration Unit Lite.

11.6.2 Pad control

The SIUL controls the configuration and electrical characteristic of the device pads. It provides a

consistent interface for all pads, both on a by-port and a by-bit basis. The SIUL allows each pad to be

configured as either a General Purpose Input Output pad (GPIO), and as one or more alternate functions

(input or output). The pad configuration registers (PCRn, see Section 11.5.2.8, “Pad Configuration

Registers (PCR[0:71])) allow software control of the static electrical characteristics of external pins with

a single write. These configure the following pad features:

• Open drain output enable

• Slew rate control

• Pull control

• Pad assignment

• Control of analog path switches

• Safe mode behavior configuration

11.6.3 General purpose input and output pads (GPIO)

The SIUL allows each pad to be configured as either a General Purpose Input Output pad (GPIO), and as

one or more alternate functions (input or output), the function of which is normally determined by the

peripheral that uses the pad.

The SIUL manages up to 64 GPIO pads organized as ports that can be accessed for data reads and writes

as 32-bit, 16-bit or 8-bit.

As shown in Figure 11-19, all port accesses are identical with each read or write being performed only at

a different location to access a different port width.

Figure 11-19. Data port example arrangement showing configuration for different port width accesses

This implementation requires that the registers are arranged in such a way as to support this range of port

widths without having to split reads or writes into multiple accesses.

31 23 15 7 0

SIUL Base + 15 7 0

SIUL Base +

15 7 0

SIUL Base + 70

0x0003

SIUL Base + 70

0x0002

SIUL Base + 70

0x0001

SIUL Base + 70

0x0000

0x0002 0x0000

32-bit Port

16-bit Port 16-bit Port

8-bit Port 8-bit Port 8-bit Port 8-bit Port

SIUL Base + 0x0000

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The SIUL has separate data input (GPDIn_n, see Section 11.5.2.11, “GPIO Pad Data Input registers

0_3–68_71 (GPDI[0_3:68_71])) and data output (GPDOn_n, see Section 11.5.2.10, “GPIO Pad Data

Output registers 0_3–68_71 (GPDO[0_3:68_71])) registers for all pads, allowing the possibility of reading

back an input or output value of a pad directly. This supports the ability to validate what is present on the

pad rather than merely confirming the value that was written to the data register by accessing the data input

registers.

The data output registers support both read and write operations to be performed.

The data input registers support read access only.

When the pad is configured to use one of its alternate functions, the data input value reflect the respective

value of the pad. If a write operation is performed to the data output register for a pad configured as an

alternate function (non GPIO), this write will not be reflected by the pad value until reconfigured to GPIO.

The allocation of what input function is connected to the pin is defined by the PSMI registers (see

Section 11.5.2.9, “Pad Selection for Multiplexed Inputs registers (PSMI[0_3:32_35])).

11.6.4 External interrupts

The SIUL supports 25 external interrupts, EIRQ[0:24]. The signal description chapter of this reference

manual provides a map of the external interrupts.

The SIUL supports four interrupt vectors to the interrupt controller. Each vector interrupt has eight external

interrupts combined together with the presence of flag generating an interrupt for that vector if enabled.

All of the external interrupt pads within a single group have equal priority.

Refer to Figure 11-20 for an overview of the external interrupt implementation.

Figure 11-20. External interrupt pad diagram

Interrupt

Controller

Interrupt

Vectors

EIF[24] EIF[23:16] EIF[15:8] EIF[7:0]

IRE[24:0]

Pads

IREE[24:0]

Interrupt Edge Enable

IFEE[24:0]

Falling

Rising

Edge Detection

Glitch Filter

IFE[24:0]

MAXCOUNT[x]

IRQ Glitch Filter enable

Glitch filter Counter_n

IFCP[3:0]

Glitch filter Prescaler

Interrupt enable

OR OR OR OR

IRQ_24 IRQ_23_16 IRQ_15_08 IRQ_07_00

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11.6.4.1 External interrupt management

Each interrupt can be enabled or disabled independently. This can be performed using the IRER (see

Section 11.5.2.4, “Interrupt Request Enable Register (IRER)). A pad defined as an external interrupt can

be configured to recognize interrupts with an active rising edge, an active falling edge or both edges being

active. A setting of having both edge events disabled is reserved and should not be configured.

The active EIRQ edge is controlled through the configuration of the registers IREER and IFEER.

Each external interrupt supports an individual flag that is held in the ISR (see Section 11.5.2.3, “Interrupt

Status Flag Register (ISR)). This register is a write-1-to-clear register type, preventing inadvertent

overwriting of other flags in the same register.

11.7 Pin muxing

For pin muxing, please refer to Chapter 3, “Signal Description of this reference manual.

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Chapter 12 e200z0 and e200z0h Core

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Chapter 12

e200z0 and e200z0h Core

12.1 Overview

The MPC5602P microcontroller implements the e200z0h core.

The e200 processor family is a set of CPU cores built on the Power Architecture technology. e200

processors are designed for deeply embedded control applications that require low cost solutions rather

than maximum performance.

The e200z0 and e200z0h processors integrate an integer execution unit, branch control unit, instruction

fetch and load/store units, and a multi-ported register file capable of sustaining three read and two write

operations per clock. Most integer instructions execute in a single clock cycle. Branch target prefetching

is performed by the branch unit to allow single-cycle branches in some cases.

The e200z0 core is a single-issue, 32-bit Power Architecture technology VLE-only design with 32-bit

general purpose registers (GPRs). Implementing only the VLE (variable-length encoding) APU provides

improved code density. All arithmetic instructions that execute in the core operate on data in the GPRs.

12.2 Features

The following is a list of some of the key features of the e200z0 and e200z0h cores:

• 32-bit Power Architecture technology VLE-only programmer’s model

• Single issue, 32-bit CPU

• Implements the VLE APU for reduced code footprint

• In-order execution and retirement

• Precise exception handling

• Branch processing unit

— Dedicated branch address calculation adder

— Branch acceleration using Branch Target Buffer (e200z0h only)

• Supports independent instruction and data accesses to different memory subsystems, such as

SRAM and Flash memory via independent Instruction and Data bus interface units (BIUs)

(e200z0h only)

• Supports instruction and data access via a unified 32-bit Instruction/Data BIU (e200z0 only)

• Load/store unit

— 1 cycle load latency

— Fully pipelined

— Big-endian support only

— Misaligned access support

— Zero load-to-use pipeline bubbles for aligned transfers

• Power management

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— Low power design

— Dynamic power management of execution units

• Testability

— Synthesizeable, full MuxD scan design

— ABIST/MBIST for optional memory arrays

12.2.1 Microarchitecture summary

The e200z0 processor utilizes a four stage pipeline for instruction execution. The Instruction Fetch (stage

1), Instruction Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory

Access (stage 3), and Register Writeback (stage 4) stages operate in an overlapped fashion, allowing single

clock instruction execution for most instructions.

The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel

shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a

Count-Leading-Zeros unit (CLZ), an 8 × 32 Hardware Multiplier array, result feed-forward hardware, and

a hardware divider.

Arithmetic and logical operations are executed in a single cycle with the exception of the divide and

multiply instructions. A Count-Leading-Zeros unit operates in a single clock cycle.

The Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to minimize delays

during change of flow operations. Sequential prefetching is performed to ensure a supply of instructions

into the execution pipeline. Branch target prefetching from the BTB is performed to accelerate certain

taken branches in the e200z0. Prefetched instructions are placed into an instruction buffer with 4 entries

(2 entries in e200z0), each capable of holding a single 32-bit instruction or a pair of 16-bit instructions.

Conditional branches that are not taken execute in a single clock. Branches with successful target

prefetching have an effective execution time of one clock on e200z0h. All other taken branches have an

execution time of two clocks.

Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic

zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These

instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word

instructions allow low overhead context save and restore operations. The load/store unit contains a

dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use

dependency does not incur any pipeline bubbles for most cases.

The Condition Register unit supports the condition register (CR) and condition register operations defined

by the Power Architecture architecture. The condition register consists of eight 4-bit fields that reflect the

results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical

instructions, and provide a mechanism for testing and branching.

Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to

allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead.

12.2.1.1 Block diagram

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 265

Figure 12-1. e200z0 block diagram

CPU

CONTROL LOGIC

INSTRUCTION UNIT

BRANCH

UNIT

INSTRUCTION BUFFER

GPR

SPR

MULTIPLY

UNIT

OnCE/NEXUS

CONTROL LOGIC

INTERFACE

CONTROL

DATA

(MTSPR/MFSPR)

INTEGER

EXECUTION

UNIT

EXTERNAL

SPR

CTR

XER

DATA ADDRESS

BUS INTERFACE UNIT

CONTROL

3232

LOAD/STORE

UNIT

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266 Freescale Semiconductor

Figure 12-2. e200z0h block diagram

12.2.1.2 Instruction unit features

The features of the e200 Instruction unit are:

• 32-bit instruction fetch path supports fetching of one 32-bit instruction per clock, or as many as

two 16-bit VLE instructions per clock

• Instruction buffer with 4 entries in e200z0h, each holding a single 32-bit instruction, or a pair of

16-bit instructions

CPU

CONTROL LOGIC

DATA

NEXUS

DEBUG

UNIT

ADDRESS

LOAD/STORE

UNIT

INSTRUCTION UNIT

BRANCH

UNIT

INSTRUCTION BUFFER

GPR

SPR

MULTIPLY

UNIT

DATA BUS INTERFACE UNIT

CONTROL

32 32 N

OnCE/NEXUS

CONTROL LOGIC

INTERFACE

CONTROL

DATA

(MTSPR/MFSPR)

INTEGER

EXECUTION

UNIT

EXTERNAL

SPR

CTR

XER

INSTRUCTION BUS INTERFACE UNIT

DATA ADDRESS

CONTROL

3232

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 267

• Instruction buffer with 2 entries in e200z0, each holding a single 32-bit instruction, or a pair of

16-bit instructions

• Dedicated PC incrementer supporting instruction prefetches

• Branch unit with dedicated branch address adder supporting single cycle of execution of certain

branches, two cycles for all others

12.2.1.3 Integer unit features

The e200 integer unit supports single cycle execution of most integer instructions:

• 32-bit AU for arithmetic and comparison operations

• 32-bit LU for logical operations

• 32-bit priority encoder for count leading zero’s function

• 32-bit single cycle barrel shifter for shifts and rotates

• 32-bit mask unit for data masking and insertion

• Divider logic for signed and unsigned divide in 5 to 34 clocks with minimized execution timing

• 8 × 32 hardware multiplier array supports 1 to 4 cycle 32 × 32 32 multiply (early out)

12.2.1.4 Load/Store unit features

The e200 load/store unit supports load, store, and the load multiple / store multiple instructions:

• 32-bit effective address adder for data memory address calculations

• Pipelined operation supports throughput of one load or store operation per cycle

• 32-bit interface to memory (dedicated memory interface on e200z0h)

12.2.1.5 e200z0h system bus features

The features of the e200z0h System Bus interface are as follows:

• Independent Instruction and Data Buses

• AMBA AHB Lite Rev 2.0 Specification with support for ARM v6 AMBA Extensions

— Exclusive Access Monitor

— Byte Lane Strobes

— Cache Allocate Support

• 32-bit address bus plus attributes and control on each bus

• 32-bit read data bus for Instruction Interface

• Separate uni-directional 32-bit read data bus and 32-bit write data bus for Data Interface

• Overlapped, in-order accesses

12.2.1.6 Nexus features

The Nexus 1 module is compliant with Class 1 of the IEEE-ISTO 5001-2003 standard. The following

features are implemented:

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• Program Trace via Branch Trace Messaging (BTM). Branch trace messaging displays program

flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool

to interpolate what transpires between the discontinuities. Thus, static code may be traced.

• Ownership Trace via Ownership Trace Messaging (OTM). OTM facilitates ownership trace by

providing visibility of which process ID or operating system task is activated. An Ownership Trace

Message is transmitted when a new process/task is activated, allowing the development tool to

trace ownership flow.

• Run-time access to the processor memory map via the JTAG port. This allows for enhanced

download/upload capabilities.

• Watchpoint Messaging

• Watchpoint Trigger enable of Program Trace Messaging

• Registers for Program Trace, Ownership Trace and Watchpoint Trigger control

• All features controllable and configurable via the JTAG port

12.3 Core registers and programmer’s model

This section describes the registers implemented in the e200z0 and e200z0h cores. It includes an overview

of registers defined by the Power Architecture technology, highlighting differences in how these registers

are implemented in the e200 core, and provides a detailed description of e200-specific registers. Full

descriptions of the architecture-defined register set are provided in Power Architecture Specification.

The Power Architecture defines register-to-register operations for all computational instructions. Source

data for these instructions are accessed from the on-chip registers or are provided as immediate values

embedded in the opcode. The three-register instruction format allows specification of a target register

distinct from the two source registers, thus preserving the original data for use by other instructions. Data

is transferred between memory and registers with explicit load and store instructions only.

Figure 12-3 and Figure 12-5 show the e200 register set, including the registers that are accessible while in

supervisor mode and the registers that are accessible in user mode. The number to the right of the

special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register

(for example, the integer exception register (XER) is SPR 1).

NOTE

e200z0 and e200z0h is a 32-bit implementation of the Power Architecture

specification.

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Figure 12-3. e200z0 Supervisor mode programmer’s model

SPR General

Exception Handling/Control Registers

Save and Restore

Machine State

MSR

PVR

Processor Control Registers

SPRG0

SPRG1

SPR 272

SPR 273

SRR0

SRR1

CSRR0

CSRR1

DSRR0

DSRR1

SPR 26

SPR 27

SPR 58

SPR 59

SPR 574

SPR 575

Processor ID

PIR SPR 286

Interrupt Vector Prefix

IVPR SPR 63

Debug Registers2

Debug Control

DBCR0

DBCR1

DBCR2

SPR 308

SPR 309

SPR 310

Instruction Address

Compare

IAC1

IAC2

IAC3

IAC4

SPR 312

SPR 313

SPR 314

SPR 315

Data Address Compare

DAC1

DAC2

SPR 316

SPR 317

1 - These e200-specific registers may not be supported

by other Power Architecture processors

2 - Optional registers defined by the Power Architecture

technology

Processor Version

Hardware Implementation

Dependent1

HID0

HID1

SPR 1008

SPR 1009

SPR 9

General-Purpose

Registers

Count Register

CTR

SPR 8

Link Register

Condition Register

GPR0

GPR1

GPR31

SPR 1

XER

General Registers

SPR 287

Debug Status

DBSR SPR 304

System Version1

SVR SPR 1023

ESR SPR 62

Exception Syndrome

Data Exception Address

DEAR SPR 61

Machine Check

Syndrome Register

MCSR SPR 572

Memory Management Registers

Process ID

PID0 SPR 48

Configuration (Read-only

MMUCFG SPR 1015

Cache Registers

SPR 515

Cache Configuration

(Read-only)

L1CFG0

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270 Freescale Semiconductor

Figure 12-4. e200z0h Supervisor mode programmer’s model

SPR General

Exception Handling/Control Registers

Save and Restore

Machine State

MSR

PVR

Processor Control Registers

SPRG0

SPRG1

SPR 272

SPR 273

SRR0

SRR1

CSRR0

CSRR1

DSRR0

DSRR1

SPR 26

SPR 27

SPR 58

SPR 59

SPR 574

SPR 575

Processor ID

PIR SPR 286

Interrupt Vector Prefix

IVPR SPR 63

Debug Registers2

Debug Control

DBCR0

DBCR1

DBCR2

SPR 308

SPR 309

SPR 310

Instruction Address

Compare

IAC1

IAC2

IAC3

IAC4

SPR 312

SPR 313

SPR 314

SPR 315

Data Address Compare

DAC1

DAC2

SPR 316

SPR 317

1 - These e200-specific registers may not be supported

by other Power Architecture processors

2 - Optional registers defined by the Power Architecture

technology

Processor Version

Hardware Implementation

Dependent1

HID0

HID1

SPR 1008

SPR 1009

SPR 9

General-Purpose

Registers

Count Register

CTR

SPR 8

Link Register

Condition Register

GPR0

GPR1

GPR31

SPR 1

XER

General Registers

SPR 287

Debug Status

DBSR SPR 304

System Version1

SVR SPR 1023

ESR SPR 62

Exception Syndrome

Data Exception Address

DEAR SPR 61

Machine Check

Syndrome Register

MCSR SPR 572

Memory Management Registers

Process ID

PID0 SPR 48

Configuration (Read-only

MMUCFG SPR 1015

Cache Registers

SPR 515

Cache Configuration

(Read-only)

L1CFG0

BTB Registers

SPR 1013

BTB Control1

BUCSR

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Figure 12-5. e200 User mode program model

12.3.1 Unimplemented SPRs and read-only SPRs

e200 fully decodes the SPR field of the mfspr and mtspr instructions. If the SPR specified is undefined

and not privileged, an illegal instruction exception is generated. If the SPR specified is undefined and

privileged and the CPU is in user mode (MSR[PR=1]), a privileged instruction exception is generated. If

the SPR specified is undefined and privileged and the core is in supervisor mode (MSR[PR=0]), an illegal

instruction exception is generated.

For the mtspr instruction, if the SPR specified is read-only and not privileged, an illegal instruction

exception is generated. If the SPR specified is read-only and privileged and the core is in user mode

(MSR[PR=1]), a privileged instruction exception is generated. If the SPR specified is read-only and

privileged and the core is in supervisor mode (MSR[PR=0]), an illegal instruction exception is generated.

12.4 Instruction summary

The e200z0 core supports Power Architecture technology VLE instructions..

USER Mode Programmer Model

SPR 9

General-Purpose

Registers

Count Register

CTR

SPR 8

Link Register

Condition Register

GPR0

GPR1

GPR31

SPR 1

XER

General Registers

Cache Registers

SPR 515

Cache Configuration

(Read-only)

L1CFG0

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Chapter 13 Peripheral Bridge (PBRIDGE)

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Chapter 13

Peripheral Bridge (PBRIDGE)

13.1 Introduction

The Peripheral Bridge (PBRIDGE) is the interface between the system bus and on-chip peripherals.

The Peripheral Bridge of MPC5602P is the same as the one of all other PPC55xx and PPC56xx products

except that it cannot be configured by software and that it has a hard-wired configuration.

13.1.1 Block diagram

Figure 13-1. PBRIDGE interface

13.1.2 Overview

The PBRIDGE acts as interface between the system bus and lower bandwidth peripherals. Accesses that

fall within the address space of the PBRIDGE are decoded to provide individual module selects for

peripheral devices on the slave bus interface.

As shown in Figure 13-1, the asynchronous bridge is a dedicated module that resynchronizes signals

synchronous to the system clock (SYS_CLK) to the ones synchronous to the motor control clock

(MC_PLL_CLK).

The PBRIDGE has the following key features:

• Supports the slave interface signals. This interface is only meant for slave peripherals.

• Supports 32-bit slave peripherals (byte, halfword, and word reads and writes are supported to each)

• Provides configurable per-master access protections

Peripheral

Bridge

System Bus

System Bus Crossbar Switch (XBAR)

Asynchronous

Bridge

eTimer_0

Other peripherals

FlexPWM

ADC_0

Safety_Port

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13.1.3 Modes of operation

The PBRIDGE has only one operating mode.

13.2 Functional description

The PBRIDGE serves as an interface between a system bus and the peripheral (slave) bus. It functions as

a protocol translator. Accesses that fall within the address space of the PBRIDGE are decoded to provide

individual module selects for peripheral devices on the slave bus interface.

13.2.1 Access support

Aligned 32-bit word accesses, halfword accesses, and byte accesses are supported for the peripherals.

Peripheral registers must not be misaligned, although no explicit checking is performed by the PBRIDGE.

NOTE

Data accesses that cross a 32-bit boundary are not supported.

13.2.1.1 Peripheral Write Buffering

Buffered writes are not supported by the device PBRIDGE.

13.2.1.2 Read cycles

Two-clock read accesses are possible with the Peripheral Bridge when the requested access size is 32-bits

or smaller, and is not misaligned across a 32-bit boundary.

13.2.1.3 Write cycles

Three clock write accesses are possible with the Peripheral Bridge when the requested access size is

32-bits or smaller. Misaligned writes that cross a 32-bit boundary are not supported.

13.2.2 General operation

Slave peripherals are modules that contain readable/writable control and status registers. The system bus

master reads and writes these registers through the PBRIDGE. The PBRIDGE generates module enables,

the module address, transfer attributes, byte enables, and write data as inputs to the slave peripherals. The

PBRIDGE captures read data from the slave interface and drives it on the system bus.

The PBRIDGE occupies a 64 MB portion of the address space. The register maps of the slave peripherals

are located on 16-KB boundaries. Each slave peripheral is allocated one 16-KB block of the memory map,

and is activated by one of the module enables from the PBRIDGE.

The PBRIDGE is responsible for indicating to slave peripherals if an access is in supervisor or user mode.

All eDMA transfers are done in supervisor mode.

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Chapter 14

Crossbar Switch (XBAR)

14.1 Introduction

This chapter describes the multi-port crossbar switch (XBAR), which supports simultaneous connections

between three master ports and three slave ports. XBAR supports a 32-bit address bus width and a 32-bit

data bus width at all master and slave ports.

The crossbar of MPC5602P is the same as the one of all other PPC55xx and PPC56xx products except that

it cannot be configured by software and that it has a hard-wired configuration.

14.2 Block diagram

Figure 14-1 shows a block diagram of the crossbar switch.

Figure 14-1. XBAR block diagram

Table 14-1 gives the crossbar switch port for each master and slave, the assigned and fixed ID number for

each master and shows the master ID numbers as they relate to the master port numbers.

Table 14-1. Device XBAR switch ports

Module

Port

Physical master ID

Type Logical

number

e200z0 core—CPU instructions Master 0 0

e200z0 core—Data Master 0 1

eDMA Master 2 2

Flash Controller Slave 0 —

Master

Crossbar Switch

Slave

Master modules

Slave modules

Master Master

Slave Slave

. . . .

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14.3 Overview

The XBAR allows for concurrent transactions to occur from any master port to any slave port. It is possible

for all master ports and slave ports to be in use at the same time as a result of independent master requests.

If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher

priority master and grants it ownership of the slave port. All other masters requesting that slave port are

stalled until the higher priority master completes its transactions.

Requesting masters are granted access based on a fixed priority.

14.4 Features

• 3 Master ports

— e200z0 core complex Instruction port

— e200z0 core complex Load/Store Data port

—eDMA

• 3 Slave ports

— Flash memory (code and data)

— Internal SRAM

— Peripheral bridge

• 32-bit internal address, 32-bit internal data paths

• Fully concurrent transfers between independent master and slave ports

• Fixed priority scheme and fixed parking strategy

14.5 Modes of operation

14.5.1 Normal mode

In normal mode, the XBAR provides the register interface and logic that controls crossbar switch

configuration.

14.5.2 Debug mode

The XBAR operation in debug mode is identical to operation in normal mode.

Internal SRAM Controller Slave 2 —

Peripheral bridge Slave 7 —

Table 14-1. Device XBAR switch ports (continued)

Module

Port

Physical master ID

Type Logical

number

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14.6 Functional description

This section describes the functionality of the XBAR in more detail.

14.6.1 Overview

The main goal of the XBAR is to increase overall system performance by allowing multiple masters to

communicate concurrently with multiple slaves. To maximize data throughput, it is essential to keep

arbitration delays to a minimum.

This section examines data throughput from the point of view of masters and slaves, detailing when the

XBAR stalls masters, or inserts bubbles on the slave side.

14.6.2 General operation

When a master makes an access to the XBAR from an idle master state, the access is taken immediately

by the XBAR. If the targeted slave port of the access is available (that is, the requesting master is currently

granted ownership of the slave port), the access is immediately presented on the slave port. It is possible

to make single clock (zero wait state) accesses through the XBAR by a granted master. If the targeted slave

port of the access is busy or parked on a different master port, the requesting master receives wait states

until the targeted slave port can service the master request. The latency in servicing the request depends

on each master’s priority level and the responding slave’s access time.

Because the XBAR appears to be just another slave to the master device, the master device has no

indication that it owns the slave port it is targeting. While the master does not have control of the slave port

it is targeting, it is wait-stated.

A master is given control of a targeted slave port only after a previous access to a different slave port has

completed, regardless of its priority on the newly targeted slave port. This prevents deadlock from

occurring when a master has the following conditions:

• Outstanding request to slave port A that has a long response time

• Pending access to a different slave port B

• Lower priority master also makes a request to the different slave port B.

In this case, the lower priority master is granted bus ownership of slave port B after a cycle of arbitration,

assuming the higher priority master slave port A access is not terminated.

After a master has control of the slave port it is targeting, the master remains in control of that slave port

until it gives up the slave port by running an IDLE cycle, leaves that slave port for its next access, or loses

control of the slave port to a higher priority master with a request to the same slave port. However, because

all masters run a fixed-length burst transfer to a slave port, it retains control of the slave port until that

transfer sequence is completed.

When a slave bus is idled by the XBAR, it is parked on the master that did the last transfer.

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14.6.3 Master ports

A master access is taken if the slave port to which the access decodes is either currently servicing the

master or is parked on the master. In this case, the XBAR is completely transparent and the master access

is immediately transmitted on the slave bus and no arbitration delays are incurred. A master access stall if

the access decodes to a slave port that is busy serving another master, parked on another master.

If the slave port is currently parked on another master, and no other master is requesting access to the slave

port, then only one clock of arbitration is incurred. If the slave port is currently serving another master of

a lower priority and the master has a higher priority than all other requesting masters, then the master gains

control over the slave port as soon as the data phase of the current access is completed. If the slave port is

currently servicing another master of a higher priority, then the master gains control of the slave port after

the other master releases control of the slave port if no other higher priority master is also waiting for the

slave port.

A master access is responded to with an error if the access decodes to a location not occupied by a slave

port. This is the only time the XBAR directly responds with an error response. All other error responses

received by the master are the result of error responses on the slave ports being passed through the XBAR.

14.6.4 Slave ports

The goal of the XBAR with respect to the slave ports is to keep them 100% saturated when masters are

actively making requests. To do this the XBAR must not insert any bubbles onto the slave bus unless

absolutely necessary.

There is only one instance when the XBAR forces a bubble onto the slave bus when a master is actively

making a request. This occurs when a handoff of bus ownership occurs and there are no wait states from

the slave port. A requesting master that does not own the slave port is granted access after a one clock

delay.

14.6.5 Priority assignment

Each master port is assigned a fixed 3-bit priority level (hard-wired priority). Table 14-2 shows the priority

levels assigned to each master (the lowest has highest priority).

14.6.6 Arbitration

XBAR supports only a fixed-priority comparison algorithm.

Table 14-2. Hardwired bus master priorities

Module

Port

Priority level

Type Number

e200z0 core–CPU instructions Master 0 7

e200z0 core—Data Master 1 6

eDMA Master 2 5

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14.6.6.1 Fixed priority operation

When operating in fixed-priority arbitration mode, each master is assigned a unique priority level in the

XBAR_MPR. If two masters both request access to a slave port, the master with the highest priority in the

selected priority register gains control over the slave port.

Any time a master makes a request to a slave port, the slave port checks to see if the new requesting

master’s priority level is higher than that of the master that currently has control over the slave port (if any).

The slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has

control of the slave port.

If the new requesting master’s priority level is higher than that of the master that currently has control of

the slave port, the higher priority master is granted control at the termination of any currently pending

access, assuming the pending transfer is not part of a burst transfer.

A new requesting master must wait until the end of the fixed-length burst transfer, before it is granted

control of the slave port. But if the new requesting master’s priority level is lower than that of the master

that currently has control of the slave port, the new requesting master is forced to wait until the master that

currently has control of the slave port is finished accessing the current slave port.

14.6.6.1.1 Parking

If no master is currently requesting the slave port, the slave port is parked. The slave port parks always to

the most recently requesting master (park-on-last). When parked on the last master, the slave port is

passing that master’s signals through to the slave bus. When the master accesses the slave port again, no

other arbitration penalties are incurred except that a one clock arbitration penalty is incurred for each

access request to the slave port made by another master port. All other masters pay a one clock penalty.

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Chapter 15 Error Correction Status Module (ECSM)

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Chapter 15

Error Correction Status Module (ECSM)

15.1 Introduction

The Error Correction Status Module (ECSM) provides control functions for the device Standard Product

Platform (SPP) including program-visible information about the platform configuration and revision

levels, a reset status register, a software watchdog timer, and wakeup control for exiting sleep modes, and

optional features such as an address map for the device’s crossbar switch, information on memory errors

reported by error-correcting codes and/or generic access error information for certain processor cores. It

also provides with register access protection for the following slave modules: INTC, ECSM, STM, and

SWT.

15.2 Overview

The Error Correction Status Module is mapped into the IPS space and supports a number of control

functions for the platform device.

15.3 Features

The ECSM includes these features:

• Program-visible information on the platform device configuration and revision

• Reset status register (MRSR)

• Registers for capturing information on platform memory errors if error-correcting codes (ECC) are

implemented

• Registers to specify the generation of single- and double-bit memory data inversions for test

purposes if error-correcting codes are implemented

• Access address information for faulted memory accesses for certain processor core

micro-architectures

• XBAR priority functions, including forcing round robin and high priority enabling

• Capability to restrict register access to supervisor mode to selected on-platform slave devices:

INTC, ECSM, STM, and SWT

15.4 Memory map and registers description

This section details the programming model for the ECSM. This is an on-platform 128-byte space mapped

to the region serviced by an IPS bus controller. Some of the control registers have a 64-bit width. These

64-bit registers are implemented as two 32-bit registers, and include an “H” and “L” suffixes, indicating

the “high” and “low” portions of the control function.

The Error Correction Status Module does not include any logic that provides access control. Rather, this

function is supported using the standard access control logic provided by the IPS controller.

Chapter 15 Error Correction Status Module (ECSM)

MPC5602P Microcontroller Reference Manual, Rev. 4

282 Freescale Semiconductor

ECSM registers are accessible only when the core is in supervisor mode (see Section 15.4.3,

“ECSM_reg_protection).

15.4.1 Memory map

Table 15-1 lists the registers in the ECSM.

Table 15-1. ECSM registers

Offset from

ECSM_BASE

0xFFF4_0000

0x0000 PCT—Processor Core Type register on page 283 16

0x0002 REV—Revision register on page 283 16

0x0004 PLAMC — Platform XBAR Master Configuration on page 284 16

0x0006 PLASC — Platform XBAR Sleave Configuration on page 284 16

0x0008 IMC—IPS Module Configuration register on page 285 16

0x000C–0x000E Reserved

0x000F MRSR—Miscellaneous Reset Status register on page 285 8

0x0010–0x001E Reserved

0x001F MIR—Miscellaneous Interrupt register on page 286 8

0x0020–0x0023 Reserved

0x0024 MUDCR—Miscellaneous User-Defined Control Register on page 287 32

0x0028–0x0042 Reserved

0x0043 ECR—ECC Configuration register on page 288 8

0x0044–0x0046 Reserved

0x0047 ESR—ECC Status register on page 289 8

0x0048–0x0049 Reserved

0x004A EEGR—ECC Error Generation register on page 290 16

0x004C–0x004F Reserved

0x0050 FEAR—Flash ECC Address register on page 292 32

0x0054–0x0055 Reserved

0x0056 FEMR—Flash ECC Master Number Register on page 293 8

0x0057 FEAT—Flash ECC Attributes register on page 293 8

0x0058–0x005B Reserved

0x005C FEDR—Flash ECC Data register on page 294 32

0x0060 REAR—RAM ECC Address register on page 295 32

0x0064 Reserved

0x0065 RESR—RAM ECC Syndrome register on page 296 8

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 283

15.4.2 Registers description

Attempted accesses to reserved addresses result in an error termination, while attempted writes to

read-only registers are ignored and do not terminate with an error. Unless noted otherwise, writes to the

programming model must match the size of the register, e.g., an n-bit register only supports n-bit writes,

etc. Attempted writes of a different size than the register width produce an error termination of the bus

cycle and no change to the targeted register.

15.4.2.1 Processor core type (PCT) register

The PCT is a 16-bit read-only register that specifies the architecture of the processor core in the device.

The state of this register is defined by a module input signal; it can only be read from the IPS programming

model. Any attempted write is ignored.

15.4.2.2 Revision (REV) register

The REV is a 16-bit read-only register specifying a revision number. The state of this register is defined

by an input signal; it can only be read from the IPS programming model. Any attempted write is ignored.

0x0066 REMR—RAM ECC Master register on page 298 8

0x0067 REAT—RAM ECC Attributes register on page 298 8

0x0068–0x006B Reserved

0x006C REDR—RAM ECC Data register on page 299 32

0x0070–0x3FFF Reserved

Address:

Base + 0x0000 Access: User read-only

0123456789101112131415

R PCT[15:0]

Reset1110000000010010

Figure 15-1. Processor core type (PCT) register

Table 15-2. PCT field descriptions

Name Description

0-15

PCT[15:0]

Processor Core Type

0xE012 identifies the z0H Power Architecture.

Table 15-1. ECSM registers (continued)

Offset from

ECSM_BASE

0xFFF4_0000

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284 Freescale Semiconductor

15.4.2.3 Platform XBAR Master Configuration (PLAMC)

The PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to

the device’s AMBA-AHB Crossbar Switch (XBAR). The state of this register is defined by a module input

signal; it can only be read from the IPS programming model. Any attempted write is ignored.

15.4.2.4 Platform XBAR Slave Configuration (PLASC)

The PLASC is a 16-bit read-only register identifying the presence/absence of bus slave connections to the

device’s AMBA-AHB Crossbar Switch (XBAR), plus a 1-bit flag defining the internal platform datapath

width (DP64). The state of this register is defined by a module input signal; it can only be read from the

IPS programming model. Any attempted write is ignored.

Address:

Base + 0x0002 Access: User read-only

0123456789101112131415

R REV[15:0]

Reset0000000000000000

Figure 15-2. Revision (REV) register

Table 15-3. REV field descriptions

Name Description

0-15

REV[15:0]

Revision

The REV[15:0] field is specified by an input signal to define a software-visible revision number.

Address Base + 0x0004 Access: User read/-only

0123456789101112131415

R00000000 AMC[7:0]

Reset00000000 AMC[7:0]

Figure 15-3. Platform XBAR Master Configuration (PLAMC) register

Table 15-4. PLAMC field descriptions

Field Description

AMC[7:0] XBAR Master Configuration

0 Bus master connection to XBAR input port n is not present.

1 Bus master connection to XBAR input port n is present.

Address Base + 0x0006 Access: User read-only

0123456789101112131415

DP64

000000 0 ASC[7:0]

Reset00000000 ASC[7:0]

Figure 15-4. Platform XBAR Slave Configuration (PLASC) register

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 285

15.4.2.5 IPS Module Configuration (IMC) register

The IMC is a 32-bit read-only register identifying the presence/absence of the 32 low-order IPS peripheral

modules connected to the primary slave bus controller. The state of this register is defined by a module

input signal; it can only be read from the IPS programming model. Any attempted write is ignored.

15.4.2.6 Miscellaneous Reset Status Register (MRSR)

The MRSR contains a bit for each of the reset sources to the device. An asserted bit indicates the last type

of reset that occurred. Only one bit is set at any time in the MRSR, reflecting the cause of the most recent

reset as signaled by device reset input signals. The MRSR can only be read from the IPS programming

model. Any attempted write is ignored.

Table 15-5. ASC field descriptions

Field Description

DP64 64-bit Datapath

0 Datapath width is 32 bits.

1 Datapath width is 64 bits.

ASC[7:0] XBAR Slave Configuration

0 Bus slave connection to XBAR output port n is not present.

1 Bus slave connection to XBAR output port n is present.

Address Base + 0x0008 Access: User read-only

0123456789101112131415

R MC[31:16]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R MC[15:0]

Reset1110000000000000

Figure 15-5. IPS Module Configuration (IMC) register

Table 15-6. IMC field descriptions

Field Description

0-31

MC[31:0]

IPS Module Configuration

0 IPS module connection to decoded slot n not present

1 IPS module connection to decoded slot n present

Address:

Base + 0x000F Access: User read-only

01234567

RPOR DIR 000000

Resetxx000000

Figure 15-6. Miscellaneous Reset Status Register (MRSR)

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MPC5602P Microcontroller Reference Manual, Rev. 4

286 Freescale Semiconductor

15.4.2.7 Miscellaneous Interrupt Register (MIR)

All interrupt requests associated with ECSM are collected in the MIR register. This includes the processor

core system bus fault interrupt.

During the appropriate interrupt service routine handling these requests, the interrupt source contained in

the ECSMIR must be explicitly cleared.

Table 15-7. MRSR field descriptions

Field Description

POR

Power-On Reset

0 Last recorded event was not caused by a power-on reset (based on a device input signal).

1 Last recorded event was caused by a power-on reset (based on a device input signal).

DIR

Device Input Reset

0 Last recorded event was not caused by a device input reset.

1 Last recorded event was a reset caused by a device input reset.

Address:

Base + 0x001F Access: User read/write

01234567

RFB0AIFB0SIFB1AIFB1SI0000

W1111xxxx

Reset00000000

Figure 15-7. Miscellaneous Interrupt Register (MIR)

Table 15-8. MIR field descriptions

Field Description

FB0AI

Flash Bank 0 Abort Interrupt

0 A flash bank 0 abort has not occurred.

1 A flash bank 0 abort has occurred. The interrupt request is negated by writing a 1 to this bit. Writing

a 0 has no effect.

FB0SI

Flash Bank 0 Stall Interrupt

0 A flash bank 0 stall has not occurred.

1 A flash bank 0 stall has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a

0 has no effect.

FB1AI

Flash Bank 1 Abort Interrupt

0 A flash bank 1 abort has not occurred.

1 A flash bank 1 abort has occurred. The interrupt request is negated by writing a 1 to this bit. Writing

a 0 has no effect.

FB1SI

Flash Bank 1 Stall Interrupt

0 A flash bank 1 stall has not occurred.

1 A flash bank 1 stall has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a

0 has no effect.

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 287

15.4.2.8 Miscellaneous User-Defined Control Register (MUDCR)

The MUDCR provides a program-visible register for user-defined control functions. It provides

configuration control for assorted modules on the device. The contents of this register is output from the

ECSM to other modules where these user-defined control functions are implemented.

15.4.2.9 ECC registers

There are a number of program-visible registers for the sole purpose of reporting and logging of memory

failures. These registers include the following:

• ECC Configuration Register (ECR)

• ECC Status Register (ESR)

• ECC Error Generation Register (EEGR)

• Flash ECC Address Register (FEAR)

• Flash ECC Master Number Register (FEMR)

• Flash ECC Attributes Register (FEAT)

• Flash ECC Data Register (FEDR)

• RAM ECC Address Register (REAR)

• RAM ECC Syndrome Register (RESR)

• RAM ECC Master Number Register (REMR)

• RAM ECC Attributes Register (REAT)

• RAM ECC Data Register (REDR)

Address Base + 0x0024 Access: User read/write

0123456789101112131415

MUDC

R[31]

000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000000000000000

Reset0000000000000000

Figure 15-8. Miscellaneous User-Defined Control register (MUDCR)

Table 15-9. MUDCR field descriptions

Name Description

MUDCR[31]

XBAR force_round_robin bit

This bit is used to drive the force_round_robin bit of the XBAR. This forces the slaves into round robin

mode of arbitration rather than fixed mode (unless a master is using priority elevation, which forces

the design back into fixed mode regardless of this bit). By setting the hardware definition to

ENABLE_ROUND_ROBIN_RESET, this bit resets to 1.

0 XBAR is in fixed priority mode.

1 XBAR is in round robin mode.

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MPC5602P Microcontroller Reference Manual, Rev. 4

288 Freescale Semiconductor

The details on the ECC registers are provided in the subsequent sections. If the design does not include

ECC on the memories, these addresses are reserved locations within the ECSM’s programming model.

15.4.2.10 ECC Configuration Register (ECR)

The ECC Configuration Register is an 8-bit control register for specifying which types of memory errors

are reported. In all systems with ECC, the occurrence of a non-correctable error causes the current access

to be terminated with an error condition. In many cases, this error termination is reported directly by the

initiating bus master. However, there are certain situations where the occurrence of this type of

non-correctable error is not reported by the master. Examples include speculative instruction fetches,

which are discarded due to a change-of-flow operation, and buffered operand writes. The ECC reporting

logic in the ECSM provides an optional error interrupt mechanism to signal all non-correctable memory

errors. In addition to the interrupt generation, the ECSM captures specific information (memory address,

attributes and data, bus master number, etc.) that may be useful for subsequent failure analysis.

The reporting of single-bit memory corrections can only be enabled via an SoC-configurable module input

signal. This signal is tied to 1 at SoC level and hence reporting of single-bit memory corrections is always

enabled. While not directly accessible to a user, this capability is viewed as important for error logging and

failure analysis.

Address:

Base + 0x0043 Access: User read/write

01234567

R0 0 ER1BR EF1BR 00

ERNCR EFNCR

Reset00000000

Figure 15-9. ECC Configuration register (ECR)

Table 15-10. ECR field descriptions

Field Description

ER1BR

Enable RAM 1-bit Reporting

This bit can only be set if the input enable signal is asserted. This signal is tied to 1 at SoC level and

hence reporting of single-bit memory corrections is always enabled. The occurrence of a single-bit RAM

correction generates a ECSM ECC interrupt request as signaled by the assertion of ESR[R1BC]. The

address, attributes and data are also captured in the REAR, RESR, REMR, REAT and REDR registers.

0 Reporting of single-bit RAM corrections disabled

1 Reporting of single-bit RAM corrections enabled

EF1BR

Enable Flash 1-bit Reporting

This bit can only be set if the input enable signal is asserted. This signal is tied to 1 at SoC level and

hence reporting of single-bit memory corrections is always enabled. The occurrence of a single-bit flash

correction generates a ECSM ECC interrupt request as signaled by the assertion of ESR[F1BC]. The

address, attributes and data are also captured in the FEAR, FEMR, FEAT and FEDR registers.

0 Reporting of single-bit flash corrections disabled

1 Reporting of single-bit flash corrections enabled

ERNCR

Enable RAM Non-Correctable Reporting

The occurrence of a non-correctable multi-bit RAM error generates a ECSM ECC interrupt request as

signaled by the assertion of ESR[RNCE]. The faulting address, attributes and data are also captured in

the REAR, RESR, REMR, REAT and REDR registers.

0 Reporting of non-correctable RAM errors disabled

1 Reporting of non-correctable RAM errors enabled

Chapter 15 Error Correction Status Module (ECSM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 289

15.4.2.11 ECC Status Register (ESR)

The ECC Status Register is an 8-bit control register for signaling which types of properly enabled ECC

events have been detected. The ESR signals the last properly enabled memory event to be detected. ECC

interrupt generation is separated into single-bit error detection/correction, uncorrectable error detection,

and the combination of the two as defined by the following boolean equations:

ECSM_ECC1BIT_IRQ

= ECR[ER1BR] & ESR[R1BC] // ram, 1-bit correction

| ECR[EF1BR] & ESR[F1BC] // flash, 1-bit correction

ECSM_ECCRNCR_IRQ

= ECR[ERNCR] & ESR[RNCE] // ram, noncorrectable error

ECSM_ECCFNCR_IRQ

= ECR[EFNCR] & ESR[FNCE] // flash, noncorrectable error

ECSM_ECC2BIT_IRQ

= ECSM_ECCRNCR_IRQ // ram, noncorrectable error

| ECSM_ECCFNCR_IRQ // flash, noncorrectable error

ECSM_ECC_IRQ

= ECSM_ECC1BIT_IRQ // 1-bit correction

| ECSM_ECC2BIT_IRQ // noncorrectable error

where the combination of a properly enabled category in the ECR and the detection of the corresponding

condition in the ESR produces the interrupt request.

The ECSM allows a maximum of one bit of the ESR to be asserted at any given time. This preserves the

association between the ESR and the corresponding address and attribute registers, which are loaded on

each occurrence of an properly enabled ECC event. If there is a pending ECC interrupt and another

properly enabled ECC event occurs, the ECSM hardware automatically handles the ESR reporting,

clearing the previous data and loading the new state and thus guaranteeing that only a single flag is

asserted.

To maintain the coherent software view of the reported event, the following sequence in the ECSM error

interrupt service routine is suggested:

1. Read the ESR and save it.

2. Read and save all the address and attribute reporting registers.

3. Re-read the ESR and verify the current contents matches the original contents. If the two values

are different, go back to step 1 and repeat.

4. When the values are identical, write a 1 to the asserted ESR flag to negate the interrupt request.

EFNCR

Enable Flash Non-Correctable Reporting

The occurrence of a non-correctable multi-bit flash error generates a ECSM ECC interrupt request as

signaled by the assertion of ESR[FNCE]. The faulting address, attributes and data are also captured in

the FEAR, FEMR, FEAT and FEDR registers.

0 Reporting of non-correctable flash errors disabled

1 Reporting of non-correctable flash errors enabled

Table 15-10. ECR field descriptions (continued)

Field Description

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MPC5602P Microcontroller Reference Manual, Rev. 4

290 Freescale Semiconductor

In the event that multiple status flags are signaled simultaneously, ECSM records the event with the R1BC

as highest priority, then F1BC, then RNCE, and finally FNCE.

15.4.2.12 ECC Error Generation Register (EEGR)

The ECC error generation register is a 16-bit control register used to force the generation of single- and

double-bit data inversions in the memories with ECC, most notably the RAM. This capability is provided

for two purposes:

• It provides a software-controlled mechanism for injecting errors into the memories during data

writes to verify the integrity of the ECC logic.

• It provides a mechanism to allow testing of the software service routines associated with memory

error logging.

Address:

Base + 0x0047 Access: User read/write

01234567

R0 0 R1BC F1BC 00

RNCE FNCE

Reset00000000

Figure 15-10. ECC Status register (ESR)

Table 15-11. ESR field descriptions

Field Description

R1BC

RAM 1-bit Correction

This bit can only be set if ECR[ER1BR] is asserted. The occurrence of a properly enabled single-bit

RAM correction generates a ECSM ECC interrupt request. The address, attributes and data are also

captured in the REAR, RESR, REMR, REAT and REDR registers. To clear this interrupt flag, write a 1

to this bit. Writing a 0 has no effect.

0 No reportable single-bit RAM correction detected

1 Reportable single-bit RAM correction detected

F1BC

Flash 1-bit Correction

This bit can only be set if ECR[EF1BR] is asserted. The occurrence of a properly enabled single-bit flash

correction generates a ECSM ECC interrupt request. The address, attributes and data are also

captured in the FEAR, FEMR, FEAT and FEDR registers. To clear this interrupt flag, write a 1 to this bit.

Writing a 0 has no effect.

0 No reportable single-bit flash correction detected

1 Reportable single-bit flash correction detected

RNCE

RAM Non-Correctable Error

The occurrence of a properly enabled non-correctable RAM error generates a ECSM ECC interrupt

request. The faulting address, attributes and data are also captured in the REAR, RESR, REMR, REAT

and REDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect. This bit

can only be set if ECR[ERNCR] is asserted.

0 No reportable non-correctable RAM error detected

1 Reportable non-correctable RAM error detected

FNCE

Flash Non-Correctable Error

The occurrence of a properly enabled non-correctable flash error generates a ECSM ECC interrupt

request. The faulting address, attributes and data are also captured in the FEAR, FEMR, FEAT and

FEDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect. This bit can

only be set if ECR[ERNCR] is asserted.

0 No reportable non-correctable flash error detected

1 Reportable non-correctable flash error detected

Chapter 15 Error Correction Status Module (ECSM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 291

It should be noted that while the EEGR is associated with the RAM, similar capabilities exist for the flash,

that is, the ability to program the non-volatile memory with single- or double-bit errors is supported for

the same two reasons previously identified.

For both types of memories (RAM and flash), the intent is to generate errors during data write cycles, such

that subsequent reads of the corrupted address locations generate ECC events, either single-bit corrections

or double-bit non-correctable errors that are terminated with an error response.

The enabling of these error generation modes requires the same input enable signal (as that used to enable

single-bit correction reporting) be asserted. This signal is tied to 1 at SoC level and hence reporting of

single-bit memory corrections is always enabled.

Address Base + 0x004A Access: User read/write

0123456789101112131415

R0 0 FRC

1BI

FR11

FRC

NCI

FR1

NCI

0ERRBIT[6:0]

Reset0000000000000000

Figure 15-11. ECC Error Generation register (EEGR)

Table 15-12. EEGR field descriptions

Field Description

FRC1BI

Force RAM Continuous 1-Bit Data Inversions

0 No RAM continuous 1-bit data inversions generated

1 1-bit data inversions in the RAM continuously generated

The assertion of this bit forces the RAM controller to create 1-bit data inversions, as defined by the bit

position specified in ERRBIT[6:0], continuously on every write operation.

The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position

defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.

After this bit has been enabled to generate another continuous 1-bit data inversion, it must be cleared

before being set again to properly re-enable the error generation logic.

This bit can only be set if the same input enable signal (as that used to enable single-bit correction

reporting) is asserted. This signal is tied to 1 at SoC level and hence reporting of single-bit memory

corrections is always enabled.

FR11BI

Force RAM One 1-bit Data Inversion

0 No RAM single 1-bit data inversion generated

1 One 1-bit data inversion in the RAM generated

The assertion of this bit forces the RAM controller to create one 1-bit data inversion, as defined by the bit

position specified in ERRBIT[6:0], on the first write operation after this bit is set.

The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position

defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.

After this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being

set again to properly re-enable the error generation logic.

This bit can only be set if the same input enable signal (as that used to enable single-bit correction

reporting) is asserted. This signal is tied to 1 at SoC level and hence reporting of single-bit memory

corrections is always enabled.

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MPC5602P Microcontroller Reference Manual, Rev. 4

292 Freescale Semiconductor

If an attempt to force a non-correctable inversion (by asserting EEGR[FRCNCI] or EEGR[FRC1NCI])

and EEGR[ERRBIT] equals 64, then no data inversion will be generated.

The only allowable values for the 4 control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are

{0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in undefined behavior.

15.4.2.13 Flash ECC Address Register (FEAR)

The FEAR is a 32-bit register for capturing the address of the last properly enabled ECC event in the flash

memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash causes the

address, attributes and data associated with the access to be loaded into the FEAR, FEMR, FEAT and

FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be asserted.

FRCNCI

Force RAM Continuous Non-Correctable Data Inversions

0 No RAM continuous 2-bit data inversions generated

1 2-bit data inversions in the RAM continuously generated

The assertion of this bit forces the RAM controller to create 2-bit data inversions, as defined by the bit

position specified in ERRBIT[6:0] and the overall odd parity bit, continuously on every write operation.

After this bit has been enabled to generate another continuous non-correctable data inversion, it must be

cleared before being set again to properly re-enable the error generation logic.

The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position

defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.

FR1NCI

Force RAM One Non-Correctable Data Inversions

0 No RAM single 2-bit data inversions generated

1 One 2-bit data inversion in the RAM generated

The assertion of this bit forces the RAM controller to create one 2-bit data inversion, as defined by the bit

position specified in ERRBIT[6:0] and the overall odd parity bit, on the first write operation after this bit is

set.

The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position

defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.

After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again

to properly re-enable the error generation logic.

9-15

ERRBIT

[6:0]

Error Bit Position

The vector defines the bit position that is complemented to create the data inversion on the write

operation. For the creation of 2-bit data inversions, the bit specified by this field plus the odd parity bit of

the ECC code are inverted.

The RAM controller follows a vector bit ordering scheme where LSB=0. Errors in the ECC syndrome bits

can be generated by setting this field to a value greater than the RAM width. For example, consider a

32-bit RAM implementation.

The 32-bit ECC approach requires 7 code bits for a 32-bit word. For PRAM data width of 32 bits, the actual

SRAM (32 bits data + 7 bits for ECC) = 39 bits. The following association between the ERRBIT field and

the corrupted memory bit is defined:

if ERRBIT = 0, then RAM[0] of the odd bank is inverted.

if ERRBIT = 1, then RAM[1] of the odd bank is inverted.

...

if ERRBIT = 31, then RAM[31] of the odd bank is inverted.

if ERRBIT = 64, then ECC Parity[0] of the odd bank is inverted.

if ERRBIT = 65, then ECC Parity[1] of the odd bank is inverted.

...

if ERRBIT = 70, then ECC Parity[6] of the odd bank is inverted.

For ERRBIT values of 32 to 63 and greater than 70, no bit position is inverted.

Table 15-12. EEGR field descriptions (continued)

Field Description

Chapter 15 Error Correction Status Module (ECSM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 293

This register can only be read from the IPS programming model; any attempted write is ignored.

15.4.2.14 Flash ECC Master Number Register (FEMR)

The FEMR is a 4-bit register for capturing the XBAR bus master number of the last properly enabled ECC

event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in

the flash causes the address, attributes and data associated with the access to be loaded into the FEAR,

FEMR, FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register

to be asserted.

This register can only be read from the IPS programming model; any attempted write is ignored.

15.4.2.15 Flash ECC Attributes (FEAT) register

The FEAT is an 8-bit register for capturing the XBAR bus master attributes of the last properly enabled

ECC event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event

Address Base + 0x0050 Access: User read-only

0123456789101112131415

R FEAR[31:16]

Reset————————————————

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R FEAR[15:0]

Reset————————————————

Figure 15-12. Flash ECC Address register (FEAR)

Table 15-13. FEAR field descriptions

Field Description

0-31

FEAR[31:0]

Flash ECC Address Register

This 32-bit register contains the faulting access address of the last properly enabled flash ECC

event.

Address: Base + 0x0056 Access: User read-only

01234567

R 0 0 0 0 FEMR[3:0]

Reset0000––––

Figure 15-13. Flash ECC Master Number Register (FEMR)

Table 15-14. FEMR field descriptions

Name Description

4-7

FEMR[3:0]

Flash ECC Master Number Register

This 4-bit register contains the XBAR bus master number of the faulting access of the last properly

enabled flash ECC event.

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in the flash causes the address, attributes and data associated with the access to be loaded into the FEAR,

FEMR, FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register

to be asserted.

This register can only be read from the IPS programming model; any attempted write is ignored.

15.4.2.16 Flash ECC Data Register (FEDR)

The FEDR is a 32-bit register for capturing the data associated with the last properly enabled ECC event

in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash

causes the address, attributes and data associated with the access to be loaded into the FEAR, FEMR,

FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be

asserted.

The data captured on a multi-bit non-correctable ECC error is undefined.

This register can only be read from the IPS programming model; any attempted write is ignored.

Address: Base + 0x0057 Access: User read-only

01234567

R WRITE SIZE[2:0] PROTECTION[3:0]

Reset0000––––

Figure 15-14. Flash ECC Attributes (FEAT) Register

Table 15-15. FEAT field descriptions

Name Description

WRITE

AMBA-AHB HWRITE

0 AMBA-AHB read access

1 AMBA-AHB write access

1-3

SIZE[2:0]

AMBA-AHB HSIZE[2:0]

000 8-bit AMBA-AHB access

001 16-bit AMBA-AHB access

010 32-bit AMBA-AHB access

1xx Reserved

PROTECTION[3]

AMBA-AHB HPROT[3]

Protection[0]: Type

0I-Fetch

1 Data

PROTECTION[2]

AMBA-AHB HPROT[2]

Protection[1]: Mode

0 User mode

1 Supervisor mode

PROTECTION[1]

AMBA-AHB HPROT[1]

Protection[2]: Bufferable

0 Non-bufferable

1Bufferable

PROTECTION[0]

AMBA-AHB HPROT[0]

Protection[3]: Cacheable

0 Non-cacheable

1 Cacheable

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15.4.2.17 RAM ECC Address Register (REAR)

The REAR is a 32-bit register for capturing the address of the last properly enabled ECC event in the RAM

memory. Depending on the state of the ECC Configuration Register, an ECC event in the RAM causes the

address, attributes and data associated with the access to be loaded into the REAR, RESR, REMR, REAT

and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register to be asserted.

This register can only be read from the IPS programming model; any attempted write is ignored.

Address: Base + 0x005C Access: User read-only

0123456789101112131415

R FEDR[31:16]

Reset:————————————————

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R FEDR[15:0]

Reset:————————————————

Figure 15-15. Flash ECC Data register (FEDR)

Table 15-16. FEDR field descriptions

Name Description

0-31

FEDR[31:0]

Flash ECC Data Register

This 32-bit register contains the data associated with the faulting access of the last properly enabled

flash ECC event. The register contains the data value taken directly from the data bus.

Address:

Base + 0x0060 Access: User read-only

0123456789101112131415

R REAR[31:16]

Reset————————————————

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R REAR[15:0]

Reset————————————————

Figure 15-16. RAM ECC Address register (REAR)

Table 15-17. REAR field descriptions

Name Description

0-31

REAR[31:0]

RAM ECC Address Register

This 32-bit register contains the faulting access address of the last properly enabled RAM ECC event.

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15.4.2.18 RAM ECC Syndrome Register (RESR)

The RESR is an 8-bit register for capturing the error syndrome of the last properly enabled ECC event in

the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the RAM

causes the address, attributes and data associated with the access to be loaded into the REAR, RESR,

REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register

to be asserted.

This register can only be read from the IPS programming model; any attempted write is ignored.

Note: Ta b l e 1 5 - 1 9 associates the upper 7 bits of the ECC syndrome with the exact data bit in error for single-bit correctable

codewords. This table follows the bit vectoring notation where the LSB=0. Note that the syndrome value of 0x0001 implies

no error condition but this value is not readable when the PRESR is read for the no error case.

Address: Base + 0x0065 Access: User read-only

01234567

R RESR[7:0]

Reset————————

Figure 15-17. RAM ECC Syndrome Register (RESR)

Table 15-18. RESR field descriptions

Name Description

0-7

RESR[7:0]

RAM ECC Syndrome Register

This 8-bit syndrome field includes 6 bits of Hamming decoded parity plus an odd-parity bit for the

entire 39-bit (32-bit data + 7 ECC) code word. The upper 7 bits of the syndrome specify the exact bit

position in error for single-bit correctable codewords, and the combination of a non-zero 7-bit

syndrome plus overall incorrect parity bit signal a multi-bit, non-correctable error.

For correctable single-bit errors, the mapping shown in Table 15-19 associates the upper 7 bits of the

syndrome with the data bit in error.

Table 15-19. RAM syndrome mapping for single-bit correctable errors

RESR[7:0] Data Bit in Error

0x00 ECC ODD[0]

0x01 No Error

0x02 ECC ODD[1]

0x04 ECC ODD[2]

0x06 DATA ODD BANK[31]

0x08 ECC ODD[3]

0x0A DATA ODD BANK[30]

0x0C DATA ODD BANK[29]

0x0E DATA ODD BANK[28]

0x10 ECC ODD[4]

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0x12 DATA ODD BANK[27]

0x14 DATA ODD BANK[26]

0x16 DATA ODD BANK[25]

0x18 DATA ODD BANK[24]

0x1A DATA ODD BANK[23]

0x1C DATA ODD BANK[22]

0x50 DATA ODD BANK[21]

0x20 ECC ODD[5]

0x22 DATA ODD BANK[20]

0x24 DATA ODD BANK[19]

0x26 DATA ODD BANK[18]

0x28 DATA ODD BANK[17]

0x2A DATA ODD BANK[16]

0x2C DATA ODD BANK[15]

0x58 DATA ODD BANK[14]

0x30 DATA ODD BANK[13]

0x32 DATA ODD BANK[12]

0x34 DATA ODD BANK[11]

0x64 DATA ODD BANK[10]

0x38 DATA ODD BANK[9]

0x62 DATA ODD BANK[8]

0x70 DATA ODD BANK[7]

0x60 DATA ODD BANK[6]

0x40 ECC ODD[6]

0x42 DATA ODD BANK[5]

0x44 DATA ODD BANK[4]

0x46 DATA ODD BANK[3]

0x48 DATA ODD BANK[2]

0x4A DATA ODD BANK[1]

0x4C DATA ODD BANK[0]

0x03,0x05........0x4D Multiple bit error

> 0x4D Multiple bit error

Table 15-19. RAM syndrome mapping for single-bit correctable errors (continued)

RESR[7:0] Data Bit in Error

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15.4.2.19 RAM ECC Master Number Register (REMR)

The REMR is an 8-bit register in which the 4-bit field REMR[0:3] is used for capturing the XBAR bus

master number of the last properly enabled ECC event in the RAM memory. Depending on the state of the

ECC Configuration Register, an ECC event in the RAM causes the address, attributes and data associated

with the access to be loaded into the REAR, RESR, REMR, REAT and REDR registers, and the

appropriate flag (R1BC or RNCE) in the ECC Status Register to be asserted.

This register can only be read from the IPS programming model; any attempted write is ignored.

15.4.2.20 RAM ECC Attributes (REAT) register

The REAT is an 8-bit register for capturing the XBAR bus master attributes of the last properly enabled

ECC event in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event

in the RAM causes the address, attributes and data associated with the access to be loaded into the REAR,

RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status

This register can only be read from the IPS programming model; any attempted write is ignored.

Address: Base + 0x0066 Access: User read-only

01234567

R0 0 0 0 REMR[3:0]

Reset 0 0 0 0 — — — —

Figure 15-18. RAM ECC Master Number register (REMR)

Table 15-20. REMR field descriptions

Name Description

4-7

REMR[3:0]

RAM ECC Master Number Register

This 4-bit field contains the XBAR bus master number of the faulting access of the last properly

enabled RAM ECC event.

Address: Base + 0x0067 Access: User read/write

01234567

R WRITE SIZE[2:0] PROTECTION[3:0]

Reset————————

Figure 15-19. RAM ECC Attributes (REAT) register

Table 15-21. REAT field descriptions

Name Description

WRITE

AMBA-AHB HWRITE

0 AMBA-AHB read access

1 AMBA-AHB write access

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15.4.2.21 RAM ECC Data Register (REDR)

The REDR is a -bit register for capturing the data associated with the last properly enabled ECC event in

the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the RAM

causes the address, attributes and data associated with the access to be loaded into the REAR, RESR,

REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register

to be asserted.

The data captured on a multi-bit non-correctable ECC error is undefined.

This register can only be read from the IPS programming model; any attempted write is ignored.

1-3

SIZE[2:0]

AMBA-AHB HSIZE[2:0]

000 8-bit AMBA-AHB access

001 16-bit AMBA-AHB access

010 32-bit AMBA-AHB access

1xx Reserved

PROTECTION[3]

AMBA-AHB HPROT[3]

Protection[0]: Type

0 I-Fetch

1 Data

PROTECTION[2]

AMBA-AHB HPROT[2]

Protection[1]: Mode

0 User mode

1 Supervisor mode

PROTECTION[1]

AMBA-AHB HPROT[1]

Protection[2]: Bufferable

0Non-bufferable

1Bufferable

PROTECTION[0]

AMBA-AHB HPROT[0]

Protection[3]: Cacheable

0 Non-cacheable

1 Cacheable

Address:

Base + 0x006C Access: User read-only

0123456789101112131415

R REDR[31:16]

Reset————————————————

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R REDR[15:0]

Reset————————————————

Figure 15-20. Platform RAM ECC Data register (PREDR)

Table 15-21. REAT field descriptions

Name Description

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15.4.3 ECSM_reg_protection

The ECSM_reg_protection logic provides hardware enforcement of supervisor mode access protection for

four on-platform IPS modules: INTC, ECSM, STM, and SWT. This logic resides between the on-platform

bus sourced by the PBRIDGE bus controller and the individual slave modules. It monitors the bus access

type (supervisor or user) and if a user access is attempted, the transfer is terminated with an error and

inhibited from reaching the slave module. Identical logic is replicated for each of the five, targeted slave

modules. A block diagram of the ECSM_reg_protection module is shown in Figure 15-21.

Figure 15-21. Spp_Ips_Reg_Protection block diagram

Attempted accesses to reserved addresses result in an error termination, while attempted writes to

read-only registers are ignored and do not terminate with an error. Unless noted otherwise, writes to the

programming model must match the size of the register; for example, an n-bit register only supports n-bit

Table 15-22. REDR field descriptions

Name Description

0-31

REDR[31:0]

RAM ECC Data Register

This 32-bit register contains the data associated with the faulting access of the last properly

enabled RAM ECC event. The register contains the data value taken directly from the data bus.

PBRIDGE

INTC

ips_supervisor_access

ECSM_REG_PROTECTION

ECSM

STM

SWT

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writes, etc. Attempted writes of a different size than the register width produce an error termination of the

bus cycle and no change to the targeted register.

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Chapter 16 Internal Static RAM (SRAM)

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Chapter 16

Internal Static RAM (SRAM)

16.1 Introduction

The general-purpose SRAM has a size of 20 KB.

The SRAM provides the following features:

• SRAM can be read/written from any bus master

• Byte, halfword, word and doubleword addressable

• Single-bit correction and double-bit error detection

16.2 SRAM operating mode

The SRAM has only one operating mode. No standby mode is available.

16.3 Module memory map

The SRAM occupies up to 20 KB of address space.

Table 16-2 shows the SRAM memory map.

16.4 Register descriptions

The SRAM has no registers. Registers associated with the ECC are located in the ECSM. See

Section 15.4.2.9, “ECC registers.

16.5 SRAM ECC mechanism

The SRAM ECC detects the following conditions and produces the following results:

• Detects and corrects all 1-bit errors

• Detects and flags all 2-bit errors as non-correctable errors

• Detects 39-bit reads (32-bit data bus plus the 7-bit ECC) that return all zeros or all ones, asserts an

error indicator on the bus cycle, and sets the error flag

SRAM does not detect all errors greater than 2 bits.

Table 16-1. SRAM operating modes

Mode Configuration

Normal (functional) Allows reads and writes of SRAM

Table 16-2. SRAM memory map

Address Use

0x4000_0000 (Base) 20 KB RAM

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Internal SRAM write operations are performed on the following byte boundaries:

• 1 byte (0:7 bits)

• 2 bytes (0:15 bits)

• 4 bytes or 1 word (0:31 bits)

If the entire 32 data bits are written to SRAM, no read operation is performed and the ECC is calculated

across the 32-bit data bus. The 8-bit ECC is appended to the data segment and written to SRAM.

If the write operation is less than the entire 32-bit data width (1 or 2-byte segment), the following occurs:

1. The ECC mechanism checks the entire 32-bit data bus for errors, detecting and either correcting or

flagging errors.

2. The write data bytes (1 or 2-byte segment) are merged with the corrected 32 bits on the data bus.

3. The ECC is then calculated on the resulting 32 bits formed in the previous step.

4. The 7-bit ECC result is appended to the 32 bits from the data bus, and the 39-bit value is then

written to SRAM.

16.5.1 Access timing

The system bus is a two-stage pipelined bus that makes the timing of any access dependent on the access

during the previous clock. Table 16-3 lists the various combinations of read and write operations to SRAM

and the number of wait states used for the each operation. The table columns contain the following

information:

• Current operation—Lists the type of SRAM operation currently executing

• Previous operation—Lists the valid types of SRAM operations that can precede the current SRAM

operation (valid operation during the preceding clock)

• Wait states—Lists the number of wait states (bus clocks) the operation requires, which depends on

the combination of the current and previous operation

Table 16-3. Number of wait states required for SRAM operations

Operation type Current operation Previous operation Number of wait states required

Read Read Idle 1

Pipelined read

8 , 16 or 32-bit write 0

(read from the same address)

(read from a different address)

Pipelined read Read 0

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16.5.2 Reset effects on SRAM accesses

Asynchronous reset will possibly corrupt RAM if it asserts during a read or write operation to SRAM. The

completion of that access depends on the cycle at which the reset occurs. If no access is occurring when

reset occurs, RAM corruption does not happen.

Instead synchronous reset (SW reset) should be used in controlled function (without RAM accesses) in

case initialization procedure is needed without RAM initialization.

16.6 Functional description

ECC checks are performed during the read portion of an SRAM ECC read/write (R/W) operation, and

ECC calculations are performed during the write portion of a R/W operation. Because the ECC bits can

contain random data after the device is powered on, the SRAM must be initialized by executing 32-bit

write operations prior any read accesses. This is also true for implicit read accesses caused by any write

accesses smaller than 32 bits as discussed in Section 16.5, “SRAM ECC mechanism.

16.7 Initialization and application information

To use the SRAM, the ECC must check all bits that require initialization after power on. All writes must

specify an even number of registers performed on 32-bit word-aligned boundaries. If the write is not the

entire 32-bits (8 or 16 bits), a read/modify/write operation is generated that checks the ECC value upon

the read. Refer to Section 16.5, “SRAM ECC mechanism.

NOTE

You must initialize SRAM, even if the application does not use ECC

reporting.

Write 8 or 16-bit write Idle 1

Read

Pipelined 8- or 16-bit write 2

32-bit write

8 or 16-bit write 0

(write to the same address)

Pipelined 8, 16 or 32-bit write 8 , 16 or 32-bit write 0

32-bit write Idle 0

32-bit write

Read

Table 16-3. Number of wait states required for SRAM operations (continued)

Operation type Current operation Previous operation Number of wait states required

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Chapter 17 Flash Memory

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Chapter 17

Flash Memory

17.1 Introduction

The Flash memory comprises a platform Flash controller interface and two Flash memory arrays: one

array of 256 KB for code (code Flash) and one array of 64 KB for data (data Flash). The Flash architecture

of the MPC5602P device is illustrated in Figure 17-1.

Figure 17-1. MPC5602P Flash memory architecture

17.2 Platform Flash controller

17.2.1 Introduction

This section provides an introduction of the platform Flash controller, which acts as the interface between

the system bus and as many as two banks of Flash memory arrays (program and data). It intelligently

converts the protocols between the system bus and the dedicated Flash array interfaces. Several important

terms are used to describe the platform Flash controller module and its connections. These terms are

defined here.

•Port—This term describes the AMBA-AHB connection(s) into the platform Flash controller.

From an architectural and programming model viewpoint, the definition supports as many as two

AHB ports, even though this specific controller only supports a single AHB connection.

•Bank—This term describes the attached Flash memories. From the platform Flash controller’s

perspective, there may be one or two attached banks of Flash memory. The code Flash bank is

AHB CROSSBAR SWITCH

Bank0 (code Flash) Bank1 (data Flash)

AHB ports 32

64 KB

Array 0Array 0

1x128 Page Buffer4x128 Page Buffer

PFlash Controller

Data Flash Code Flash

256 KB

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required and always attached to bank0. Additionally, there is a data Flash attached to bank1. The

platform Flash controller interface supports two separate connections, one to each memory bank.

On the MPC5602P device, bank0 and bank1 are internal to the device.

•Array—Each memory bank has one Flash array instantiation.

•Page—This value defines the number of bits read from the Flash array in a single access. For this

controller and memory, the page size is 128 bits (16 bytes).

The nomenclature “page buffers” and “line buffers” are used interchangeably.

17.2.1.1 Overview

The platform Flash controller supports a 32-bit data bus width at the AHB port and connections to 128-bit

read data interfaces from two memory banks, where each bank contains one instantiation of the Flash

memory array. One Flash bank is connected to the code Flash memory and the other bank is connected to

the data Flash memory. The memory controller capabilities vary between the two banks with each bank’s

functionality optimized with the typical use cases associated with the attached Flash memory. As an

example, the platform Flash controller logic associated with the code Flash bank contains a four-entry

“page” buffer, each entry containing 128 bits of data (1 Flash page) plus an associated controller that

prefetches sequential lines of data from the Flash array into the buffer, while the controller logic associated

with the data Flash bank only supports a 128-bit register that serves as a temporary page holding register

and does not support any prefetching. Prefetch buffer hits from the code Flash bank support 0-wait AHB

data phase responses. AHB read requests that miss the buffers generate the needed Flash array access and

are forwarded to the AHB upon completion, typically incurring two wait states at an operating frequency

of 60 to 64 MHz.

This memory controller is optimized for applications where a cacheless processor core, for example the

Power e200z0h, is connected through the platform to on-chip memories, for example Flash and RAM,

where the processor and platform operate at the same frequency. For these applications, the 2-stage

pipeline AMBA-AHB system bus is effectively mapped directly into stages of the processor’s pipeline and

0 wait state responses for most memory accesses are critical for providing the required level of system

performance.

17.2.1.2 Features

The following list summarizes the key features of the platform Flash controller:

• Single AHB port interface supports a 32-bit data bus. All AHB aligned and unaligned reads within

the 32-bit container are supported. Only aligned word writes are supported.

• Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank.

• Interface with code Flash (bank0) provides configurable read buffering and page prefetch support.

Four page read buffers (each 128 bits wide) and a prefetch controller support single-cycle read

responses (0 AHB data phase wait states) for hits in the buffers. The buffers implement a

least-recently-used replacement algorithm to maximize performance.

• Interface with data Flash (bank1) includes a 128-bit register to temporarily hold a single Flash

page. This logic supports single-cycle read responses (0 AHB data phase wait states) for accesses

that hit in the holding register. There is no support for prefetching associated with bank1.

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• Programmable response for read-while-write sequences including support for stall-while-write,

optional stall notification interrupt, optional Flash operation termination, and optional termination

notification interrupt

• Separate and independent configurable access timing (on a per bank basis) to support use across a

wide range of platforms and frequencies

• Support of address-based read access timing for emulation of other memory types

• Support for reporting of single- and multi-bit Flash ECC events

• Typical operating configuration loaded into programming model by system reset

17.2.2 Modes of operation

The platform Flash controller module does not support any special modes of operation. Its operation is

driven from the AMBA-AHB memory references it receives from the platform’s bus masters. Its

configuration is defined by the setting of the programming model registers, physically located as part of

the Flash array modules.

17.2.3 External signal descriptions

The platform Flash controller does not directly interface with any external signals. Its primary internal

interfaces include a connection to an AMBA-AHB crossbar (or memory protection unit) slave port and

connections with as many as two banks (code and data) of Flash memory, each containing one instantiation

of the Flash array. Additionally, the operating configuration for the platform Flash controller is defined by

the contents of certain code Flash array0 registers that are inputs to the module.

17.2.4 Memory map and registers description

Two memory maps are associated with the platform Flash controller: one for the Flash memory space and

another for the program-visible control and configuration registers. The Flash memory space is accessed

via the AMBA-AHB port. The program-visible registers are accessed via the slave peripheral bus. Details

on both memory spaces are provided in Section 17.2.4.1, “Memory map.

There are no program-visible registers that physically reside inside the platform Flash controller. Rather,

the platform Flash controller receives control and configuration information from the Flash array

controller(s) to determine the operating configuration. These are part of the Flash array’s configuration

registers mapped into its slave peripheral (IPS) address space but are described here.

NOTE

Updating the configuration fields that control the platform flash controller

behavior should only occur while the flash controller is idle. Changing

configuration settings while a flash access is in progress can lead to

non-deterministic behavior.

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17.2.4.1 Memory map

First, consider the Flash memory space accessed via transactions from the platform Flash controller’s AHB

port. To support the two separate Flash memory banks, the platform Flash controller uses address bit 23

(haddr[23]) to steer the access to the appropriate memory bank. In addition to the actual Flash memory

regions, there are shadow and test sectors included in the system memory map. The program-visible

control and configuration registers associated with each memory array are included in the slave peripheral

address region. The system memory map defines one code Flash array and one data Flash array. See

Table 17-1.

CAUTION

Software executing from flash memory must not write to registers that

control flash behavior (such as wait state settings or prefetch

enable/disable). Doing so can cause data corruption. On this chip, these

registers include PFCR0 and PFAPR.

NOTE

Flash memory configuration registers should be written only with 32-bit

write operations to avoid any issues associated with register incoherency

caused by bit fields spanning smaller size (8-, 16-bit) boundaries.

For additional information on the address-based read access timing for emulation of other memory types,

see Section 17.2.17, “Wait state emulation.

Table 17-1. Flash-related regions in the system memory map

Start address End address Size

(KB) Region

0x0000_0000 0x0007_FFFF 512 Code Flash array 0

0x0008_0000 0x001F_FFFF 1536 Reserved

0x0020_0000 0x0020_3FFF 16 Code Flash array 0: shadow sector

0x0020_4000 0x003F_FFFF 2032 Reserved

0x0040_0000 0x0040_3FFF 16 Code Flash array 0: test sector

0x0040_4000 0x007F_FFFF 4080 Reserved

0x0080_0000 0x0080_FFFF 64 Data Flash array 0

0x0081_0000 0x00C0_1FFF 4040 Reserved

0x00C0_2000 0x00C0_3FFF 8 Data Flash array 0: test sector

0x00C0_4000 0x00FF_FFFF 4080 Reserved

0x0100_0000 0x1FFF_FFFF 507904 Emulation Mapping

0xFFE8_8000 0xFFE8_BFFF 16 Code Flash array 0 configuration1

1This region is also aliased to address 0xC3F8_nnnn.

0xFFE8_C000 0xFFE8_FFFF 16 Data Flash array 0 configuration1

0xFFEB_0000 0xFFEB_BFFF 48 Reserved

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Next, consider the memory map associated with the control and configuration registers.

There are multiple registers that control operation of the platform Flash controller. Note the first two Flash

array registers (PFCR0, PFCR1) are reset to a device-defined value, while the remaining register (PFAPR)

is loaded at reset from specific locations in the array’s shadow region.

Regardless of the number of populated banks or the number of Flash arrays included in a given bank, the

configuration of the platform Flash controller is wholly specified by the platform Flash controller control

registers associated with code Flash array0. The code array0 register settings define the operating behavior

of both Flash banks. It is recommended to set the platform Flash controller control registers for both arrays

to the array0 values.

NOTE

To perform program and erase operations, the control registers in the actual

referenced Flash array must both be programmed, but the configuration of

the platform Flash controller module is defined by the platform Flash

controller control registers of code array0.

The 32-bit memory map for the platform Flash controller control registers is shown in Table 17-2.

17.2.5 Functional description

The platform Flash controller interfaces between the AHB-Lite 2.v6 system bus and the Flash memory

arrays.

The platform Flash controller generates read and write enables, the Flash array address, write size, and

write data as inputs to the Flash array. The platform Flash controller captures read data from the Flash array

interface and drives it onto the AHB. As much as four pages of data (128-bit width) from bank0 are

buffered by the platform Flash controller. Lines may be prefetched in advance of being requested by the

AHB interface, allowing single-cycle (0 AHB wait states) read data responses on buffer hits.

Several prefetch control algorithms are available for controlling page read buffer fills. Prefetch triggering

may be restricted to instruction accesses only, data accesses only, or may be unrestricted. Prefetch

triggering may also be controlled on a per-master basis.

Buffers may also be selectively enabled or disabled for allocation by instruction and data prefetch.

Access protections may be applied on a per-master basis for both reads and writes to support security and

privilege mechanisms.

Table 17-2. Platform Flash controller 32-bit memory map

Offset from

PFlash_BASE

(0xFFE8_8000)

0x001C Platform Flash Configuration Register 0 (PFCR0) on page 351

0x0020 Platform Flash Configuration Register 1 (PFCR1) on page 354

0x0024 Platform Flash Access Protection Register (PFAPR) on page 356

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Throughout this discussion, bkn_ is used as a prefix to refer to two signals, each for each bank: bk0_ and

bk1_. Also, the nomenclature Bx_Py_RegName is used to reference a program-visible register field

associated with bank “x” and port “y”.

17.2.6 Basic interface protocol

The platform Flash controller interfaces to the Flash array by driving addresses (bkn_fl_addr[23:0]) and

read or write enable signals (bkn_fl_rd_en, bkn_fl_wr_en).

The read or write enable signal (bkn_fl_rd_en, bkn_fl_wr_en) is asserted in conjunction with the reference

address for a single rising clock when a new access request is made.

Addresses are driven to the Flash array in a flow-through fashion to minimize array access time. When no

outstanding access is in progress, the platform Flash controller drives addresses and asserts bkn_fl_rd_en

or bkn_fl_wr_en and then may change to the next outstanding address in the next cycle.

Accesses are terminated under control of the appropriate read/write wait state control setting. Thus, the

access time of the operation is determined by the settings of the wait state control fields. Access timing

can be varied to account for the operating conditions of the device (frequency, voltage, temperature) by

appropriately setting the fields in the programming model for either bank.

The platform Flash controller also has the capability of extending the normal AHB access time by inserting

additional wait states for reads and writes. This capability is provided to allow emulation of other

memories that have different access time characteristics. The added wait state specifications are provided

by bit 28 to bit 24 of Flash address (haddr[28:24], see Table 17-4 and Table 17-5). These wait states are

applied in addition to the normal wait states incurred for Flash accesses. Refer to Section 17.2.17, “Wait

state emulation for more details.

Prefetching of next sequential page is blocked when haddr[28:24] is non-zero. Buffer hits are also blocked

as well, regardless of whether the access corresponds to valid data in one of the page read buffers. These

steps are taken to ensure that timing emulation is correct and that excessive prefetching is avoided. In

addition, to prevent erroneous operation in certain rare cases, the buffers are invalidated on any

non-sequential AHB access with a non-zero value on haddr[28:24].

17.2.7 Access protections

The platform Flash controller provides programmable configurable access protections for both read and

write cycles from masters via the Platform Flash Access Protection Register (PFAPR). It allows restriction

of read and write requests on a per-master basis. This functionality is described in Section 17.3.7.7.3,

“Platform Flash Access Protection Register (PFAPR). Detection of a protection violation results in an error

response from the platform Flash controller on the AHB transfer.

17.2.8 Read cycles — buffer miss

Read cycles from the Flash array are initiated by driving a valid access address on bkn_fl_addr[23:0] and

asserting bkn_fl_rd_en for the required setup (and hold) time before (and after) the rising edge of hclk.

The platform Flash controller then waits for the programmed number of read wait states before sampling

the read data on bkn_fl_rdata[127:0]. This data is normally stored in the least-recently updated page read

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buffer for bank0 in parallel with the requested data being forwarded to the AHB. For bank1, the data is

captured in the page-wide temporary holding register as the requested data is forwarded to the AHB bus.

Timing diagrams of basic read accesses from the Flash array are shown in Figure 17-2 through

Figure 17-5.

If the Flash access was the direct result of an AHB transaction, the page buffer is marked as

most-recently-used as it is being loaded. If the Flash access was the result of a speculative prefetch to the

next sequential line, it is first loaded into the least-recently-used buffer. The status of this buffer is not

changed to most-recently-used until a subsequent buffer hit occurs.

17.2.9 Read cycles — buffer hit

Single cycle read responses to the AHB are possible with the platform Flash controller when the requested

read access was previously loaded into one of the bank0 page buffers. In these “buffer hit” cases, read data

is returned to the AHB data phase with a 0 wait state response.

Likewise, the bank1 logic includes a single 128-bit temporary holding register and sequential accesses that

“hit” in this register are also serviced with a 0 wait state response.

17.2.10 Write cycles

In a write cycle, address, write data, and control signals are launched off the same edge of hclk at the

completion of the first AHB data phase cycle. Write cycles to the Flash array are initiated by driving a valid

access address on bkn_fl_addr[23:0], driving write data on bkn_fl_wdata[63:0], and asserting

bkn_fl_wr_en. Again, the controller drives the address and control information for the required setup time

before the rising edge of hclk, and provides the required amount of hold time. The platform Flash

controller then waits for the appropriate number of write wait states before terminating the write operation.

On the cycle following the programmed wait state value, the platform Flash controller asserts hready_out

to indicate to the AHB port that the cycle has terminated.

17.2.11 Error termination

The platform Flash controller follows the standard procedure when an AHB bus cycle is terminated with

an ERROR response. First, the platform Flash controller asserts hresp[0] and negates hready_out to signal

an error has occurred. On the following clock cycle, the platform Flash controller asserts hready_out and

holds both hresp[0] and hready_out asserted until hready_in is asserted.

The first case that can cause an error response to the AHB is when an access is attempted by an AHB

master whose corresponding Read Access Control or Write Access Control settings do not allow the

access, thus causing a protection violation. In this case, the platform Flash controller does not initiate a

Flash array access.

The second case that can cause an error response to the AHB is when an access is performed to the Flash

array and is terminated with a Flash error response. See Section 17.2.13, “Flash error response operation.

This may occur for either a read or a write operation.

The third case that can cause an error response to the AHB is when a write access is attempted to the Flash

array and is disallowed by the state of the bkn_fl_ary_access control input. This case is similar to case 1.

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A fourth case involves an attempted read access while the Flash array is busy doing a write (program) or

erase operation if the appropriate read-while-write control field is programmed for this response. The 3-bit

read-while-write control allows for immediate termination of an attempted read, or various

stall-while-write/erase operations are occurring.

The platform Flash controller can also terminate the current AHB access if hready_in is asserted before

the end of the current bus access. While this circumstance should not occur, this does not result in an error

condition being reported, as this behavior is initiated by the AHB. In this circumstance, the platform Flash

controller control state machine completes any Flash array access in progress (without signaling the AHB)

before handling a new access request.

17.2.12 Access pipelining

The platform Flash controller does not support access pipelining since this capability is not supported by

the Flash array. As a result, the APC (Address Pipelining Control) field should typically be the same value

as the RWSC (Read Wait State Control) field for best performance, that is, BKn_APC = BKn_RWSC. It

cannot be less than the RWSC.

17.2.13 Flash error response operation

The Flash array may signal an error response by asserting bkn_fl_xfr_err to terminate a requested access

with an error. This may occur due to an uncorrectable ECC error, or because of improper sequencing

during program/erase operations. When an error response is received, the platform Flash controller does

not update or validate a bank0 page read buffer nor the bank1 temporary holding register. An error

response may be signaled on read or write operations. For more information on the specifics related to

signaling of errors, including Flash ECC, refer to subsequent sections in this chapter. For additional

information on the system registers that capture the faulting address, attributes, data and ECC information,

see Chapter 15, “Error Correction Status Module (ECSM).

17.2.14 Bank0 page read buffers and prefetch operation

The logic associated with bank0 of the platform Flash controller contains four 128-bit page read buffers

that hold data read from the Flash array. Each buffer operates independently, and is filled using a single

array access. The buffers are used for both prefetch and normal demand fetches.

The organization of each page buffer is described as follows in a pseudo-code representation. The

hardware structure includes the buffer address and valid bit, along with 128 bits of page read data and

several error flags.

struct { // bk0_page_buffer

reg addr[23:4];// page address

reg valid; // valid bit

reg rdata[127:0];// page read data

reg xfr_error; // transfer error indicator from Flash array

reg multi_ecc_error;// multi-bit ECC error indicator from Flash array

reg single_ecc_error;// single-bit correctable ECC indicator from Flash array

} bk0_page_buffer[4];

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For the general case, a page buffer is written at the completion of an error-free Flash access and the valid

bit asserted. Subsequent Flash accesses that “hit” the buffer, that is, the current access address matches the

address stored in the buffer, can be serviced in 0 AHB wait states as the stored read data is routed from the

given page buffer back to the requesting bus master.

As noted in Section 17.2.13, “Flash error response operation a page buffer is not marked as valid if the

Flash array access terminated with any type of transfer error. However, the result is that Flash array

accesses that are tagged with a single-bit correctable ECC event are loaded into the page buffer and

validated. For additional comments on this topic, see Section 17.2.14.4, “Buffer invalidation.

Prefetch triggering is controllable on a per-master and access-type basis. Bus masters may be enabled or

disabled from triggering prefetches, and triggering may be further restricted based on whether a read

access is for instruction or data. A read access to the platform Flash controller may trigger a prefetch to

the next sequential page of array data on the first idle cycle following the request. The access address is

incremented to the next-higher 16-byte boundary, and a Flash array prefetch is initiated if the data is not

already resident in a page buffer. Prefetched data is always loaded into the least-recently-used buffer.

Buffers may be in one of six states, listed here in prioritized order:

1. Invalid—the buffer contains no valid data.

2. Used—the buffer contains valid data that has been provided to satisfy an AHB burst type read.

3. Valid—the buffer contains valid data that has been provided to satisfy an AHB single type read.

4. Prefetched—the buffer contains valid data that has been prefetched to satisfy a potential future

AHB access.

5. Busy AHB—the buffer is currently being used to satisfy an AHB burst read.

6. Busy Fill—the buffer has been allocated to receive data from the Flash array, and the array access

is still in progress.

Selection of a buffer to be loaded on a miss is based on the following replacement algorithm:

1. First, the buffers are examined to determine if there are any invalid buffers. If there are multiple

invalid buffers, the one to be used is selected using a simple numeric priority, where buffer 0 is

selected first, then buffer 1, etc.

2. If there are no invalid buffers, the least-recently-used buffer is selected for replacement.

Once the candidate page buffer has been selected, the Flash array is accessed and read data loaded into the

buffer. If the buffer load was in response to a miss, the just-loaded buffer is immediately marked as

most-recently-used. If the buffer load was in response to a speculative fetch to the next-sequential line

address after a buffer hit, the recently-used status is not changed. Rather, it is marked as most-recently-used

only after a subsequent buffer hit.

This policy maximizes performance based on reference patterns of Flash accesses and allows for

prefetched data to remain valid when non-prefetch enabled bus masters are granted Flash access.

Several algorithms are available for prefetch control that trade off performance versus power. They are

defined by the Bx_Py_PFLM (prefetch limit) register field. More aggressive prefetching increases power

slightly due to the number of wasted (discarded) prefetches, but may increase performance by lowering

average read latency.

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In order for prefetching to occur, a number of control bits must be enabled. Specifically, the global buffer

enable (Bx_Py_BFE) must be set, the prefetch limit (Bx_Py_PFLM) must be non-zero and either

instruction prefetching (Bx_Py_IPFE) or data prefetching (Bx_Py_DPFE) enabled. Refer to

Section 17.3.6, “Registers description for a description of these control fields.

17.2.14.1 Instruction/data prefetch triggering

Prefetch triggering may be enabled for instruction reads via the Bx_Py_IPFE control field, while

prefetching for data reads is enabled via the Bx_Py_DPFE control field. Additionally, the Bx_Py_PFLIM

field must also be set to enable prefetching. Prefetches are never triggered by write cycles.

17.2.14.2 Per-master prefetch triggering

Prefetch triggering may be also controlled for individual bus masters. AHB accesses indicate the

requesting master via the hmaster[3:0] inputs. Refer to Section 17.3.7.7.3, “Platform Flash Access

Protection Register (PFAPR) for details on these controls.

17.2.14.3 Buffer allocation

Allocation of the line read buffers is controlled via page buffer configuration (Bx_Py_BCFG) field. This

field defines the operating organization of the four page buffers. The buffers can be organized as a “pool”

of available resources (with all four buffers in the pool) or with a fixed partition between buffers allocated

to instruction or data accesses. For the fixed partition, two configurations are supported. In one

configuration, buffers 0 and 1 are allocated for instruction fetches and buffers 2 and 3 for data accesses. In

the second configuration, buffers 0, 1, and 2 are allocated for instruction fetches and buffer 3 reserved for

data accesses.

17.2.14.4 Buffer invalidation

The page read buffers may be invalidated under hardware or software control.

Any falling edge transition of the array’s bkn_fl_done signal causes the page read buffers to be marked as

invalid. This input is negated by the Flash array at the beginning of all program/erase operations as well

as in certain other cases. Buffer invalidation occurs at the next AHB non-sequential access boundary, but

does not affect a burst from a page read buffer in progress.

Software may invalidate the buffers by clearing the Bx_Py_BFE bit, which also disables the buffers.

Software may then re-assert the Bx_Py_BFE bit to its previous state, and the buffers will have been

invalidated.

One special case needing software invalidation relates to page buffer “hits” on Flash data that was tagged

with a single-bit ECC event on the original array access. Recall that the page buffer structure includes an

status bit signaling the array access detected and corrected a single-bit ECC error. On all subsequent buffer

hits to this type of page data, a single-bit ECC event is signaled by the platform Flash controller.

Depending on the specific hardware configuration, this reporting of a single-bit ECC event may generate

an ECC alert interrupt. In order to prevent repeated ECC alert interrupts, the page buffers need to be

invalidated by software after the first notification of the single-bit ECC event.

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Finally, the buffers are invalidated by hardware on any non-sequential access with a non-zero value on

haddr[28:24] to support wait state emulation.

17.2.15 Bank1 temporary holding register

Recall the bank1 logic within the Flash includes a single 128-bit data register, used for capturing read data.

Since this bank does not support prefetching, the read data for the referenced address is bypassed directly

back to the AHB data bus. The page is also loaded into the temporary data register and subsequent accesses

to this page can hit from this register, if it is enabled (B1_Py_BFE).

The organization of the temporary holding register is described as follows, in a pseudo-code

representation. The hardware structure includes the buffer address and valid bit, along with 128 bits of

page read data and several error flags and is the same as an individual bank0 page buffer.

struct { // bk1_page_buffer

reg addr[23:4];// page address

reg valid; // valid bit

reg rdata[127:0];// page read data

reg xfr_error; // transfer error indicator from Flash array

reg multi_ecc_error;// multi-bit ECC error indicator from Flash array

reg single_ecc_error;// single-bit correctable ECC indicator from Flash array

} bk1_page_buffer;

For the general case, a temporary holding register is written at the completion of an error-free Flash access

and the valid bit asserted. Subsequent Flash accesses that “hit” the buffer, that is, the current access address

matches the address stored in the temporary holding register, can be serviced in 0 AHB wait states as the

stored read data is routed from the temporary register back to the requesting bus master.

The contents of the holding register are invalidated by the falling edge transition of bk1_fl_done and on

any non-sequential access with a non-zero value on haddr[28:24] (to support wait state emulation) in the

same manner as the bank0 page buffers. Additionally, the B1_Py_BFE register bit can be cleared by

software to invalidate the contents of the holding register.

As noted in Section 17.2.13, “Flash error response operation the temporary holding register is not marked

as valid if the Flash array access terminated with any type of transfer error. However, the result is that Flash

array accesses that are tagged with a single-bit correctable ECC event are loaded into the temporary

holding register and validated. Accordingly, one special case needing software invalidation relates to

holding register “hits” on Flash data that was tagged with a single-bit ECC event. Depending on the

specific hardware configuration, the reporting of a single-bit ECC event may generate an ECC alert

interrupt. In order to prevent repeated ECC alert interrupts, the page buffers need to be invalidated by

software after the first notification of the single-bit ECC event.

The bank1 temporary holding register effectively operates like a single page buffer.

17.2.16 Read-While-Write functionality

The platform Flash controller supports various programmable responses for read accesses while the Flash

is busy performing a write (program) or erase operation. For all situations, the platform Flash controller

uses the state of the Flash array’s bkn_fl_done output to determine if it is busy performing some type of

high-voltage operation, namely, if bkn_fl_done = 0, the array is busy.

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Specifically, there are two 3-bit read-while-write (BKn_RWWC) control register fields that define the

platform Flash controller’s response to these types of access sequences. There are five unique responses

that are defined by the BKn_RWWC setting: one immediately reports an error on an attempted read, and

four settings that support various stall-while-write capabilities. Consider the details of these settings.

•BKn_RWWC = 0b0xx

— For this mode, any attempted Flash read to a busy array is immediately terminated with an

AHB error response and the read is blocked in the controller and not seen by the Flash array.

•BKn_RWWC = 0b111

— This defines the basic stall-while-write capability and represents the default reset setting. For

this mode, the platform Flash controller module stalls any read reference until the Flash has

completed its program/erase operation. If a read access arrives while the array is busy or if a

falling-edge on bkn_fl_done occurs while a read is still in progress, the AHB data phase is

stalled by negating hready_out and saving the address and attributes into holding registers.

Once the array has completed its program/erase operation, the platform Flash controller uses

the saved address and attribute information to create a pseudo address phase cycle to “retry”

the read reference and sends the registered information to the array as bkn_fl_rd_en is asserted.

Once the retried address phase is complete, the read is processed normally and once the data is

valid, it is forwarded to the AHB bus and hready_out negated to terminate the system bus

transfer.

•BKn_RWWC = 0b110

— This setting is similar to the basic stall-while-write capability provided when

BKn_RWWC = 0b111 with the added ability to generate a notification interrupt if a read

arrives while the array is busy with a program/erase operation. There are two notification

interrupts, one for each bank.

•BKn_RWWC = 0b101

— Again, this setting provides the basic stall-while-write capability with the added ability to

terminate any program/erase operation if a read access is initiated. For this setting, the read

request is captured and retried as described for the basic stall-while-write, plus the

program/erase operation is terminated by the platform Flash controller’s assertion of the

bkc_fl_abort signal. The bkn_fl_abort signal remains asserted until bkn_fl_done is driven high.

For this setting, there are no notification interrupts generated.

•BKn_RWWC = 0b100

— This setting provides the basic stall-while-write capability with the ability to terminate any

program/erase operation if a read access is initiated plus the generation of a termination

notification interrupt. For this setting, the read request is captured and retried as described for

the basic stall-while-write, the program/erase operation is terminated by the platform Flash

controller’s assertion of the bkn_fl_abort signal and a termination notification interrupt

generated. There are two termination notification interrupts, one for each bank.

As detailed above, there are a total of four interrupt requests associated with the stall-while-write

functionality. These interrupt requests are captured as part of ECSM’s Interrupt Register and logically

summed together to form a single request to the interrupt controller.

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For example timing diagrams of the stall-while-write and terminate-while-write operations, see

Figure 17-6 and Figure 17-7 respectively.

17.2.17 Wait state emulation

Emulation of other memory array timings are supported by the platform Flash controller on read cycles to

the Flash. This functionality may be useful to maintain the access timing for blocks of memory that were

used to overlay Flash blocks for the purpose of system calibration or tuning during code development.

The platform Flash controller inserts additional wait states according to the values of haddr[28:24],where

haddr represents the Flash address. When these inputs are non-zero, additional cycles are added to AHB

read cycles. Write cycles are not affected. In addition, no page read buffer prefetches are initiated, and

buffer hits are ignored.

Table 17-4 and Table 17-5 show the relationship of haddr[28:24] to the number of additional primary wait

states. These wait states are applied to the initial access of a burst fetch or to single-beat read accesses on

the AHB system bus.

Note that the wait state specification consists of two components: haddr[28:26] and haddr[25:24] and

effectively extends the Flash read by (8 × haddr[25:24] + haddr[28:26]) cycles.

Table 17-3. Platform Flash controller stall-while-write interrupts

MIR[n] Interrupt description

ECSM.MIR[7] Platform Flash bank0 termination notification, MIR[FB0AI]

ECSM.MIR[6] Platform Flash bank0 stall notification, MIR[FB0SI]

ECSM.MIR[5] Platform Flash bank1 termination notification, MIR[FB1AI]

ECSM.MIR[4] Platform Flash bank1 stall notification, MIR[FB1S1]

Table 17-4. Additional wait state encoding

Memory address

haddr[28:26] Additional wait states

000 0

001 1

010 2

011 3

100 4

101 5

110 6

111 7

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Table 17-5 shows the relationship of haddr[25:24] to the number of additional wait states. These are

applied in addition to those specified by haddr[28:26] and thus extend the total wait state specification

capability.

17.2.18 Timing diagrams

Since the platform Flash controller is typically used in platform configurations with a cacheless core, the

operation of the processor accesses to the platform memories, for example Flash and SRAM, plays a major

role in the overall system performance. Given the core/platform pipeline structure, the platform’s memory

controllers (PFlash, PRAM) are designed to provide a 0 wait state data phase response to maximize

processor performance. The following diagrams illustrate operation of various cycle types and responses

referenced earlier in this chapter including stall-while-read (Figure 17-6) and terminate-while-read

(Figure 17-7) diagrams.

Table 17-5. Extended additional wait state encoding

Memory address

haddr[25:24]

Additional wait states

(added to those specified by

haddr[28:26])

00 0

01 8

10 16

11 24

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Figure 17-2. 1-cycle access, no buffering, no prefetch

nonseq seq seq

addr y addr y+4 addr y+12

C(y) C(y+4)

okay okay okay okay okay okay okay okay

C(y) C(y+4)

Read, no buffering, no prefetch, APC = 0, RWSC = 0, PFLM = 0

12345678

addr y

seq

addr y+8

y+4 y+8

C(y+8) C(y+12)

y+12

addr y+4 addr y+8

C(y+8) C(y+12)

hclk

htrans

haddr, hprot

hwrite

hrdata

hwdata

hready_out

hresp

bkn_fl_addr

bkn_fl_rd_en

bkn_fl_wr_en

bkn_fl_rdata

addr+12

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Figure 17-3. 3-cycle access, no prefetch, buffering disabled

nonseq seq seq

addr y

addr y+4 addr y+12

C(y) C(y+4)

okay okay okay okay okay okay okay okay

C(y)

Burst Read, buffer miss, no prefetch, APC=2, RWSC=2, PFLM=0

123456

addr y

seq

addr y+8

y+4

addr y+4

C(y+4)

y+8

addr y+8

hclk

htrans

haddr,hprot

hwrite

hrdata

hwdata

hready_out

hresp

bkn_fl_addr

bkn_fl_rd_en

bkn_fl_wr_en

bkn_fl_rdata

bkn_fl_xfr_err

addr y

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Figure 17-4. 3-cycle access, no prefetch, buffering enabled

nonseq seq seq

addr y addr y+4 addr y+12

C(y) C(y+4) C(y+8) C(y+12)

okay okay okay okay okay okay okay okay

C(y)

Burst Read, buffer miss, no prefetch, APC = 2, RWSC = 2, PFLM = 0

123456 78

addr y

seq

addr y+8

hclk

htrans

haddr,hprot

hwrite

hrdata

hwdata

hready_out

hresp

bkn_fl_addr

bkn_fl_wr_en

bkn_fl_rdata

bkn_fl_xfr_err

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Figure 17-5. 3-cycle access, prefetch and buffering enabled

nonseq seq seq

addr y addr y+4 addr y+12

C(y) C(y+4) C(y+8) C(y+12)

okay okay okay okay okay okay okay okay

C(y)

Burst Read, buffer miss, prefetch, APC = 2, RWSC = 2, PFLM = 2

123456

addr y

seq

addr y+8

y+16

C(y+16)

seq seq

addr y+16

C(y+16)

y+32

addr y+16 addr y+32

hclk

htrans

haddr, hprot

hwrite

hrdata

hwdata

hready_out

hresp

bkn_fl_addr

bkn_fl_rd_en

bkn_fl_wr_en

bkn_fl_rdata

bkn_fl_xfr_err

addr y+20

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Figure 17-6. 3-cycle access, stall-and-retry with BKn_RWWC = 11x

As shown in Figure 17-6, the 3-cycle access to address y is interrupted when an operation causes the

bkn_done signal to be negated, signaling that the array bank is busy with a high-voltage program or erase

event. Eventually, this array operation completes (at the end of cycle 4) and bkn_done returns to a logical

1. In cycle 6, the platform Flash controller module retries the read to address y that was interrupted by the

negation of bkn_done in cycle 3. Note that throughout cycles 2–9, the AHB bus pipeline is stalled with a

read to address y in the AHB data phase and a read to address y + 4 in the address phase. Depending on

the state of the least-significant-bit of the BKn_RWWC control field, the hardware may also signal a stall

notification interrupt (if BKn_RWWC = 110). The stall notification interrupt is shown as the optional

assertion of ECSM’s MIR[FBnSI] (Flash bank n stall interrupt).

nonseq

seq

addr y

addr y+4

C(y)

C(y+4)

okay

okay okay okay okay okay okay

C(y)

Burst Read, Stall-and-Retry, APC = 2, RWSC = 2, PFLM = 2

123456 78

addr y

seq

addr y+8

y+16 y+16

okay okay

addr y+16addr y (retry)

hclk

htrans

haddr, hprot

hwrite

hrdata

hwdata

hready_out

hresp

bkn_fl_addr

bkn_fl_rd_en

bkn_fl_wr_en

bkn_fl_rdata

bkn_fl_xfr_err

bkn_done

bkn_abort

ecsm_mir[fbnsi]

ecsm_mir[fbnai]

910

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MPC5602P Microcontroller Reference Manual, Rev. 4

326 Freescale Semiconductor

Figure 17-7. 3-cycle access, terminate-and-retry with BKn_RWWC = 10x

Figure 17-7 shows the terminate-while-write timing diagram. In this example, the 3-cycle access to

address y is interrupted when an operation causes the bkn_done signal to be negated, signaling that the

array bank is busy with a high-voltage program or erase event. Based on the setting of BKn_RWWC, once

the bkn_done signal is detected as negated, the platform Flash controller asserts bkn_abort, which forces

the Flash array to cancel the high-voltage program or erase event. The array operation completes (at the

end of cycle 4) and bkn_done returns to a logical 1. It should be noted that the time spent in cycle 4 for

Figure 17-7 is considerably less than the time in the same cycle in Figure 17-6 (because of the terminate

operation). In cycle 6, the platform Flash controller module retries the read to address y that was

interrupted by the negation of bkn_done in cycle 3. Note that throughout cycles 2–9, the AHB bus pipeline

is stalled with a read to address y in the AHB data phase and a read to address y+4 in the address phase.

Depending on the state of the least-significant-bit of the BKn_RWWC control field, the hardware may also

signal an termination notification interrupt (if BKn_RWWC = 100). The stall notification interrupt is

shown as the optional assertion of ECSM’s MIR[FBnAI] (Flash bank n termination interrupt).

nonseq seq

addr y addr y+4

C(y) C(y+4)

okay okay okay okay okay okay okay okay

C(y)

Burst Read, Abort-and-Retry, APC = 2, RWSC = 2, PFLM = 2

123456 78

addr y

seq

addr y+8

y+16 y+16

okay okay

addr y+16addr y (retry)

hclk

htrans

haddr, hprot

hwrite

hrdata

hwdata

hready_out

hresp

bkn_fl_addr

bkn_fl_rd_en

bkn_fl_wr_en

bkn_fl_rdata

bkn_fl_xfr_err

bkn_done

bkn_abort

ecsm_mir[fbnsi]

ecsm_mir[fbnai]

910

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 327

17.3 Flash memory

17.3.1 Introduction

The Flash module provides electrically programmable and erasable non-volatile memory (NVM), which

may be used for instruction and/or data storage.

The Flash module is arranged as two functional units: the Flash core and the memory interface.

The Flash core is composed of arrayed non-volatile storage elements, sense amplifiers, row decoders,

column decoders and charge pumps. The arrayed storage elements in the Flash core are sub-divided into

physically separate units referred to as blocks (or sectors).

The memory interface contains the registers and logic which control the operation of the Flash core. The

memory interface is also the interface between the Flash module and a bus interface unit (BIU), and may

contain the ECC logic and redundancy logic. The BIU connects the Flash module to a system bus.

The MPC5602P provides two Flash modules: one 256 KB code Flash module, and one 64 KB data

module.

17.3.2 Main features

• High read parallelism (128 bits)

• Error Correction Code (SEC-DED) to enhance data retention

• Double word program (64 bits)

• Sector erase

• Single bank architecture

— Read-While-Modify not available within an individual module

— Read-While-Modify can be performed between the two Flash modules

• Erase suspend available (program suspend not available)

• Software programmable program/erase protection to avoid unwanted writes

• Censored mode against piracy

• Shadow Sector available on code Flash module

17.3.3 Block diagram

17.3.3.1 Data Flash

The data Flash module contains one module, composed of a Single Bank: Bank 0, normally used for code

storage. No Read-While-Modify operations are possible.

The Modify operations are managed by an embedded Flash Program/Erase Controller (FPEC). Commands

to the FPEC are given through a user registers interface.

The read data bus is 32 bits wide, while the data Flash registers are on a separate 32-bit wide bus.

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

328 Freescale Semiconductor

The high voltages needed for Program/Erase operations are internally generated. Figure 17-8 shows the

data Flash module structure.

Figure 17-8. Data Flash module structure

17.3.3.2 Code Flash

The code Flash module contains the matrix modules normally used for Code storage. No

Read-While-Modify operations are possible.

The Modify operations are managed by an embedded Flash Program/Erase Controller (FPEC). Commands

to the FPEC are given through a User Registers Interface.

The read data bus is 128 bits wide, while the Flash registers are on a separate 32-bit wide bus.

The high voltages needed for Program/Erase operations are internally generated. Figure 17-9 shows the

code Flash module structure.

Flash

Controller

Data Flash

Program/Erase

Registers

64 KB

+ 8 KB TestFlash

HV generator

Matrix

Flash Bank 1

Interface

Registers

Interface

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 329

Figure 17-9. Code Flash module structure

17.3.4 Functional description

17.3.4.1 Macrocell structure

The Flash macrocell provides high density non-volatile memories with high-speed read access.

The Flash module is addressable by word (32 bits) or double-word (64 bits) for programming, and by page

(128 bits) for reads. Reads done to the Flash always return 128 bits, although read page buffering may be

done in the platform BIU.

Each read of the Flash module retrieves a page, or 4 consecutive words (128 bits) of information. The

address for each word retrieved within a page differ from the other addresses in the page only by address

bits (3:2).

The Flash page read architecture supports both cache and burst mode at the BIU level for high-speed read

application.

The Flash module supports fault tolerance through Error Correction Code (ECC) and/or error detection.

The ECC implemented within the Flash module will correct single bit failures and detect double bit

failures.

The Flash module uses an embedded hardware algorithm implemented in the memory interface to program

and erase the Flash core.

Control logic that works with the software block enables, and software lock mechanisms, is included in

the embedded hardware algorithm to guard against accidental program/erase.

+ 16 KB TestFlash

HV generator

Matrix Registers

Interface

Flash Bank 0

Interface

+ 16 KB Shadow

Flash

Controller

Code Flash

Program/Erase

Registers

256 KB

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

330 Freescale Semiconductor

The hardware algorithm perform the steps necessary to ensure that the storage elements are programmed

and erased with sufficient margin to guarantee data integrity and reliability.

A programmed bit in the Flash module reads as logic level 0 (or low).

An erased bit in the Flash module reads as logic level 1 (or high).

Program and erase of the Flash module requires multiple system clock cycles to complete.

The erase sequence may be suspended.

The program and erase sequences may be terminated.

17.3.4.2 Flash module sectorization

The code Flash module supports 256 KB of user memory, plus 16 KB of test memory (a portion of which

is one-time programmable by the user). An extra 16 KB sector is available as Shadow space usable for user

option bits or censorship.

The code Flash and data modules are each composed of a single bank: Bank 0 (code Flash) and Bank 1

(data Flash). Read-While-Modify within a module is not supported, but can be performed by reading from

one module while writing to another.

The code Flash Bank 0 is divided in 8 sectors including a reserved sector named TestFlash, in which One

Time Programmable (OTP) user data are stored, and a Shadow Sector in which user erasable configuration

values can be stored (see Table 17-6).

The data Flash Bank 1 is divided in five sectors including a reserved sector named TestFlash (see

Table 17-7).

Table 17-6. 288 KB code Flash module sectorization

Bank Sector Addresses Size Address space

B0 B0F0 0x0000_0000–0x0000_7FFF 32 KB Low Address Space

B0 B0F1 0x0000_8000–0x0000_BFFF 16 KB Low Address Space

B0 B0F2 0x0000_C000–0x0000_FFFF 16 KB Low Address Space

B0 B0F3 0x0001_0000–0x0001_7FFF 32 KB Low Address Space

B0 B0F4 0x0001_8000–0x0001_FFFF 32 KB Low Address Space

B0 B0F5 0x0002_0000–0x0003_FFFF 128 KB Low Address Space

B0 Reserved 0x0004_0000–0x0007_FFFF 256 KB Mid Address Space

B0 Reserved 0x0008_0000–0x001F_FFFF 1536 KB High Address Space

B0 B0SH 0x0020_0000–0x0020_3FFF 16 KB Shadow Address Space

B0 Reserved 0x0020_4000–0x003F_FFFF 2032 KB Shadow Address Space

B0 B0TF 0x0040_0000–0x0040_3FFF 16 KB Test Address Space

B0 Reserved 0x0040_4000–0x007F_FFFF 4080 KB Test Address Space

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 331

Each Flash module is divided into blocks to implement independent program/erase protection. A software

mechanism is provided to independently lock/unlock each block in address space against program and

erase.

17.3.4.2.1 TestFlash block

The TestFlash block exists outside the normal address space and is programmed and read independently

of the other blocks. The independent TestFlash block is included also to support systems that require

non-volatile memory for security and/or to store system initialization information.

A section of the TestFlash is reserved to store the non-volatile information related to redundancy,

configuration, and protection.

ECC is also applied to TestFlash. The usage of reserved TestFlash sectors is detailed in Table 17-8.

Erase of the TestFlash block is always locked.

Table 17-7. 64 KB data Flash module sectorization

Bank Sector Addresses Size (KB) Address space

B1 B1F0 0x0080_0000 to 0x0080_3FFF 16 Low Address Space

B1 B1F1 0x0080_4000 to 0x0080_7FFF 16 Low Address Space

B1 B1F2 0x0080_8000 to 0x0080_BFFF 16 Low Address Space

B1 B1F3 0x0080_C000 to 0x0080_FFFF 16 Low Address Space

B1 Reserved 0x0081_0000 to 0x00C0_1FFF 4040 Reserved

B1 B1TF 0x00C0_2000 to 0x00C0_3FFF 8 Test Address Space

B1 Reserved 0x00C0_4000 to 0x00FF_FFFF 4080 Reserved

Table 17-8. TestFlash structure

Name Description

Addresses Size

(bytes)

Code TestFlash Data TestFlash

— Reserved 0x0040_0000–0x0040_1FFF — 8192

— Reserved 0x0040_2000–0x0040_3CFF 0x00C0_2000– 0x00C0_3CFF 7424

— User Reserved 0x0040_3D00–0x0040_3DE7 0x00C0_3D00–0x00C0_3DE7 232

NVLML Non-volatile Low/Mid address

space block Locking register

0x0040_3DE8–0x0040_3DEF 0x00C0_3DE8–0x00C0_3DEF 8

— User Reserved 0x0040_3DF0–0x0040_3DF7 0x00C0_3DF0–0x00C0_3DF7 8

NVSLL Non-volatile Secondary

Low/mid add space block Lock

0x0040_3DF8–0x0040_3DFF 0x00C0_3DF8–0x00C0_3DFF 8

— User Reserved 0x0040_3E00–0x0040_3EFF 0x00C0_3E00–0x00C0_3EFF 256

— Reserved 0x0040_3F00–0x0040_3FFF 0x00C0_3F00–0x00C0_3FFF 256

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332 Freescale Semiconductor

TestFlash block programming restrictions, in terms of how ECC is calculated, are similar to array

programming restrictions. Only one program is allowed per 64-bit ECC segment.

Locations of the Code TestFlash block marked as reserved cannot be programmed by the user application.

Locations of the Data TestFlash block marked as reserved cannot be programmed by the user application.

17.3.4.2.2 Shadow block

A Shadow block is present in each Code flash module, but not in the Data flash module. The Shadow block

can be enabled by the BIU.

When the Shadow space is enabled, all the operations are mapped to the Shadow block.

User mode program and erase of the shadow block are enabled only when MCR[PEAS] is set.

The Shadow block may be locked/unlocked against program or erase by using the LML[TSLK] and

SLL[STSLK] bitfields.

Program of the Shadow block has similar restriction as the array in terms of how ECC is calculated. Only

one program is allowed per 64-bit ECC segment between erases.

Erase of the Shadow block is done similarly as an sectors erase.

The Shadow block contains specified data that are needed for user features.

The user area of Shadow block may be used for user-defined functions (possibly to store boot code, other

configuration words, or factory process codes).

The usage of the Shadow sector is detailed in Table 17-9.

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 333

17.3.5 Operating modes

The following operating modes are available in the Flash module:

•Reset

• User mode

• Low-power mode

• Power-down mode

17.3.5.1 Reset

A reset is the highest priority operation for the Flash module and terminates all other operations.

The Flash module uses reset to initialize registers and status bits to their default reset values.

If the Flash module is executing a program or erase operation (MCR[PGM] = 1 or MCR[ERS] = 1) and a

reset is issued, the operation is suddenly terminated and the module disables the high voltage logic without

damage to the high voltage circuits. Reset terminates all operations and forces the Flash module into User

mode ready to receive accesses.

Reset and power-down must not be used as a systematic way to terminate a program or erase operation.

After reset is deasserted, read register access may be done, although it should be noted that registers that

require updating from shadow information or other inputs may not read updated values until MCR[DONE]

transitions. MCR[DONE] may be polled to determine if the Flash module has transitioned out of reset.

Notice that the registers cannot be written until MCR[DONE] is high.

17.3.5.2 User mode

In User mode, the Flash module may be read, written (register writes and interlock writes), programmed,

or erased.

Table 17-9. Shadow sector structure

Name Description Addresses

Size

(bytes

)

— User Area 0x0020_0000–0x0020_3DCF 15824

— Reserved 0x0020_3DD0–0x0020_3DD7 8

NVPWD0–1 Non-volatile private censorship password 0–1 registers 0x0020_3DD8–0x0020_3DDF 8

NVSCI0–1 Non-volatile system censorship information 0–1 registers 0x0020_3DE0–0x0020_3DE7 8

— Reserved 0x0020_3DE8–0x0020_3DFF 24

NVBIU2–3 Non-volatile bus interface unit 2–3 registers 0x0020_3E00–0x0020_3E0F 16

— Reserved 0x0020_3E10–0x0020_3E17 8

NVUSRO Non-volatile user options register 0x0020_3E18–0x0020_3E1F 8

— Reserved 0x0020_3E20–0x0020_3FFF 480

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334 Freescale Semiconductor

The default state of the Flash module is the read state.

The main, shadow, and test address space can be read only in the read state.

The Flash registers are always available for reads. When the module is in power-down mode, most (but

not all) registers are available for reads. The exceptions are documented.

The Flash module enters the read state on reset.

The module is in the read state under two sets of conditions:

• The read state is active when the module is enabled (User mode read).

• The read state is active when MCR[ERS] and MCR[ESUS] are set and MCR[PGM] is cleared

(Erase Suspend).

No Read-While-Modify is available within an individual module, although one module can be read while

the other is being written or otherwise modified.

Flash core reads return 128 bits (1 page = 2 double words).

Flash core reads are done through the BIU.

Array reads attempted to invalid locations will result in indeterminate data. Invalid locations occur when

addressing is done to blocks that do not exist in non 2n array sizes.

Interlock writes attempted to invalid locations, will result in an interlock occurring, but attempts to

program these blocks will not occur since they are forced to be locked. Erase will occur to selected and

unlocked blocks even if the interlock write is to an invalid location.

Simultaneous read cycles on the code Flash block and read/write cycles on the data Flash block are

possible. However, simultaneous read/write accesses within a single block are not permitted.

Chip Select, Write Enable, addresses, and data input of registers are not internally latched and must be kept

stable by the CPU for all the read/write access that lasts two clock cycles.

17.3.5.3 Low-power mode

The Low-power mode turns off most of the DC current sources within the Flash module.

The module (Flash core and registers) is not accessible for read or write operations once it has entered

Low-power mode.

Wake-up time from Low-power mode is faster than wake-up time from Power-down mode.

The user may not read some registers (UMISR0–4, UT1–2 and part of UT0) until the Low-power mode is

exited. Write access is locked on all the registers in Low-power mode.

When exiting from Low-power mode, the Flash module returns to its previous state in all cases, unless it

was in the process of executing an erase high voltage operation at the time of entering Low-power mode.

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 335

If the Flash module is put into Low-power mode during an erase operation, the MCR[ESUS] bit is set to 1.

The user may resume the erase operation when the Flash module exits from Low-power mode by clearing

MCR[ESUS]. MCR[EHV] must be set to resume the erase operation.

If the Flash module is put in Low-power mode during a program operation, the operation is completed in

all cases. Low-power mode is entered only after the programming ends.

Power-down mode cannot be entered when Low-power mode is active. The module must first be set to

User mode (or reset) when cycling between Low-power mode and Power-down mode.

17.3.5.4 Power-down mode

The Power-down mode allows turning off all Flash DC current sources so that power dissipation is limited

only to leakage in this mode.

In Power-down mode, no reads from or writes to the Flash are possible.

When enabled, the Flash module returns to its previous state in all cases, unless in the process of executing

an erase high voltage operation at the time of entering Power-down mode. If the Flash module is put into

Power-down mode during an erase operation, the MCR[ESUS] bit is set to 1. The user may resume the

erase operation when the Flash module exits Power-down mode by clearing the MCR[ESUS] bit.

MCR[EHV] must be set to resume the erase operation.

If the Flash module is placed in Power-down mode during a program operation, the operation will be

completed in any case and the Power-down mode is entered only after the programming is completed.

If the Flash module is put in Power-down mode and the vector table remains mapped in the Flash address

space, the user must observe than the Flash module will require a longer interrupt response time. This

should be accomplished by adding several wait states.

Low-power mode cannot be entered when Power-down mode is active. The module must first be set to

User mode (or reset) when cycling between Low-power mode and Power-down mode.

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MPC5602P Microcontroller Reference Manual, Rev. 4

336 Freescale Semiconductor

17.3.6 Registers description

The Flash user registers mapping is shown in Table 17-10. Except as noted, registers and offsets are

identical for the code Flash and data Flash blocks.

Table 17-10. Flash registers

Offset from

xxxx_BASE

(0xFFFE_C000)

0x0000 Module Configuration Register (MCR) on page 339

0x0004

Low/mid Address Space Block Locking Register (LML)

on page 344

0x0008 Reserved

0x000C Secondary Low/mid Address Space Block Lock Register

(SLL)

on page 346

0x0010 Low/mid Address Space Block Select Register (LMS) on page 349

0x0014 Reserved

0x0018 Address Register (ADR) on page 349

0x001C Platform Flash Configuration Register 0 (PFCR0)1

1This register is not implemented on the data Flash block.

on page 351

0x0020 Platform Flash Configuration Register 1 (PFCR1)1on page 354

0x0024 Platform Flash Access Protection Register (PFAPR)1on page 356

0x0028 Reserved

0x003C User Test Register 0 (UT0) on page 357

0x0040 User Test Register 1 (UT1) on page 359

0x0044 User Test Register 2 (UT2)1on page 360

0x0048 User Multiple Input Signature Register 0 (UMISR0) on page 360

0x004C User Multiple Input Signature Register 1 (UMISR1) on page 361

0x0050 User Multiple Input Signature Register 2 (UMISR2)1on page 362

0x0054 User Multiple Input Signature Register 3 (UMISR3)1on page 362

0x0058 User Multiple Input Signature Register 4 (UMISR4)1on page 363

0x005C–0x3FFF

Reserved

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 337

17.3.7 Register map

Table 17-11. Flash 256 KB bank0 register map

Address

offset

name

0123456789101112131415

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

0x00MCREDC0000SIZE2SIZE1SIZE00LAS2LAS1LAS0000MAS

EERRWE00PEASDONEPEG0000PGMPSUSERSESUSEHV

0x04LMLLME0000000000TSLK0000

LLK15 LLK14 LLK13 LLK12 LLK11 LLK10 LLK9 LLK8 LLK7 LLK6 LLK5 LLK4 LLK3 LLK2 LLK1 LLK0

0x08 Reserved

0x0C SLL

SLE0000000000

STSLK

SLK15 SLK14 SLK13 SLK12 SLK11 SLK10 SLK9 SLK8 SLK7 SLK6 SLK5 SLK4 SLK3 SLK2 SLK1 SLK0

0x10LMS0000000000000000

LSL15 LSL14 LSL13 LSL12 LSL11 LSL10 LSL9 LSL8 LSL7 LSL6 LSL5 LSL4 LSL3 LSL2 LSL1 LSL0

0x14 Reserved

0x18ADR000000000AD22AD21AD20AD19AD18AD17AD16

AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 0 0 0

0x1C PFCR0 BI031 BI030 BI029 BI028 BI027 BI026 BI025 BI024 BI023 BI022 BI021 BI020 BI019 BI018 BI017 BI016

BI015 BI014 BI013 BI012 BI011 BI010 BI009 BI008 BI007 BI006 BI005 BI004 BI003 BI002 BI001 BI000

0x20 PFCR1 BI131 BI130 BI129 BI128 BI127 BI126 BI125 BI124 BI123 BI122 BI121 BI120 BI119 BI118 BI117 BI116

BI115 BI114 BI113 BI112 BI111 BI110 BI109 BI108 BI107 BI106 BI105 BI104 BI103 BI102 BI101 BI100

0x24 PFAPR BI231 BI230 BI229 BI228 BI227 BI226 BI225 BI224 BI223 BI222 BI221 BI220 BI219 BI218 BI217 BI216

BI215 BI214 BI213 BI212 BI211 BI210 BI209 BI208 BI207 BI206 BI205 BI204 BI203 BI202 BI201 BI200

0x28 Reserved

0x3CUT0UTE0000000DSI7DSI6DSI5DSI4DSI3DSI2DSI1DSI0

000000000XMREMRVEIEAISAIEAID

0x40 UT1 DAI31 DAI30 DAI29 DAI28 DAI27 DAI26 DAI25 DAI24 DAI23 DAI22 DAI21 DAI20 DAI19 DAI18 DAI17 DAI16

DAI15 DAI14 DAI13 DAI12 DAI11 DAI10 DAI09 DAI08 DAI07 DAI06 DAI05 DAI04 DAI03 DAI02 DAI01 DAI00

0x44 UT2 DAI63 DAI62 DAI61 DAI60 DAI59 DAI58 DAI57 DAI56 DAI55 DAI54 DAI53 DAI52 DAI51 DAI50 DAI49 DAI48

DAI47 DAI46 DAI45 DAI44 DAI43 DAI42 DAI41 DAI40 DAI39 DAI38 DAI37 DAI36 DAI35 DAI34 DAI33 DAI32

0x48

UMISR0 MS031 MS030 MS029 MS028 MS027 MS026 MS025 MS024 MS023 MS022 MS021 MS020 MS019 MS018 MS017 MS016

MS015 MS014 MS013 MS012 MS011 MS010 MS009 MS008 MS007 MS006 MS005 MS004 MS003 MS002 MS001 MS000

0x4C

UMISR1 MS063 MS062 MS061 MS060 MS059 MS058 MS057 MS056 MS055 MS054 MS053 MS052 MS051 MS050 MS049 MS048

MS047 MS046 MS045 MS044 MS043 MS042 MS041 MS040 MS039 MS038 MS037 MS036 MS035 MS034 MS033 MS032

0x50

UMISR2 MS095 MS094 MS093 MS092 MS091 MS090 MS089 MS088 MS087 MS086 MS085 MS084 MS083 MS082 MS081 MS080

MS079 MS078 MS077 MS076 MS075 MS074 MS073 MS072 MS071 MS070 MS069 MS068 MS067 MS066 MS065 MS064

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

338 Freescale Semiconductor

0x54

UMISR3 MS127 MS126 MS125 MS124 MS123 MS122 MS121 MS120 MS119 MS118 MS117 MS116 MS115 MS114 MS113 MS112

MS111 MS110 MS109 MS108 MS107 MS106 MS105 MS104 MS103 MS102 MS101 MS100 MS099 MS098 MS097 MS096

0x58

UMISR4 MS159 MS158 MS157 MS156 MS155 MS154 MS153 MS152 MS151 MS150 MS149 MS148 MS147 MS146 MS145 MS144

MS143 MS142 MS141 MS140 MS139 MS138 MS137 MS136 MS135 MS134 MS133 MS132 MS131 MS130 MS129 MS128

Table 17-12. Flash 64 KB bank1 register map

Address

offset

name

0123456789101112131415

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

0x00MCREDC0000SIZE2SIZE1SIZE00LAS2LAS1LAS0000MAS

EERRWE00PEASDONEPEG0000PGMPSUSERSESUSEHV

0x04LMLLME0000000000TSLK0000

LLK15 LLK14 LLK13 LLK12 LLK11 LLK10 LLK9 LLK8 LLK7 LLK6 LLK5 LLK4 LLK3 LLK2 LLK1 LLK0

0x08 Reserved

0x0CSLLSLE0000000000

STSLK

0000

SLK15 SLK14 SLK13 SLK12 SLK11 SLK10

SLK9 SLK8 SLK7 SLK6 SLK5 SLK4 SLK3 SLK2 SLK1 SLK0

0x10LMS0000000000000000

LSL15 LSL14 LSL13 LSL12 LSL11 LSL10 LSL9 LSL8 LSL7 LSL6 LSL5 LSL4 LSL3 LSL2 LSL1 LSL0

0x14 Reserved

0x18ADR000000000AD22AD21AD20AD19AD18AD17AD16

AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 0 0 0

0x1C–

0x3B

Reserved

0x3CUT0UTE0000000DSI7DSI6DSI5DSI4DSI3DSI2DSI1DSI0

000000000XMREMRVEIEAISAIEAID

0x40 UT1 DAI31 DAI30 DAI29 DAI28 DAI27 DAI26 DAI25 DAI24 DAI23 DAI22 DAI21 DAI20 DAI19 DAI18 DAI17 DAI16

DAI15 DAI14 DAI13 DAI12 DAI11 DAI10 DAI09 DAI08 DAI07 DAI06 DAI05 DAI04 DAI03 DAI02 DAI01 DAI00

0x44–

0x47

Reserved

0x48

UMISR0

MS031 MS030 MS029 MS028 MS027 MS026 MS025 MS024 MS023 MS022 MS021 MS020 MS019 MS018 MS017 MS016

MS015 MS014 MS013 MS012 MS011 MS010 MS009 MS008 MS007 MS006 MS005 MS004 MS003 MS002 MS001 MS000

0x4C

UMISR1

MS063 MS062 MS061 MS060 MS059 MS058 MS057 MS056 MS055 MS054 MS053 MS052 MS051 MS050 MS049 MS048

MS047 MS046 MS045 MS044 MS043 MS042 MS041 MS040 MS039 MS038 MS037 MS036 MS035 MS034 MS033 MS032

Table 17-11. Flash 256 KB bank0 register map (continued)

Address

offset

name

0123456789101112131415

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

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In the following sections, some non-volatile registers are described. Please notice that such entities are not

Flip-Flops, but locations of TestFlash or Shadow sectors with a special meaning.

During the Flash initialization phase, the FPEC reads these non-volatile registers and updates their related

volatile registers. When the FPEC detects ECC double errors in these special locations, it behaves in the

following way:

• In case of a failing system locations (configurations, device options, redundancy, EmbAlgo

firmware), the initialization phase is interrupted and a Fatal Error is flagged.

• In case of failing user locations (protections, censorship, BIU, ...), the volatile registers are filled

with all 1s and the Flash initialization ends by clearing the MCR[PEG] bit.

17.3.7.1 Module Configuration Register (MCR)

The Module Configuration Register enables and monitors all the modify operations of each Flash module.

Identical MCRs are provided in the code Flash and the data Flash blocks.

0x50

–

0x5B

Reserved

Address:

Base + 0x0000 Access: User read/write

0123456789101112131415

REDC0000

SIZE2 SIZE1 SIZE0

0 LAS2 LAS1 LAS0 0 0 0 MAS

Wr1c

Reset00000—

1The value for this bit is different between the code and data Flash modules. See the bitfield description.

—1—10—

1 100000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R EER RWE 0 0

PEAS

DONE

PEG 0 0 0 0 PGM

PSUS

ERS

ESUS

EHV

Wr1c r1c

Reset0000011000000000

Figure 17-10. Module Configuration Register (MCR)

Table 17-12. Flash 64 KB bank1 register map (continued)

Address

offset

name

0123456789101112131415

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

340 Freescale Semiconductor

Table 17-13. MCR field descriptions

Field Description

EDC

ECC Data Correction

EDC provides information on previous reads. If a ECC Single Error detection and correction occurs,

the EDC bit is set to 1. This bit must then be cleared, or a reset must occur before this bit will return

to a 0 state. This bit may not be set to 1 by the user.

In the event of a ECC Double Error detection, this bit is not set.

If EDC is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing

of EDC) were not corrected through ECC.

Since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. A write of 0

will have no effect.

0 Reads are occurring normally.

1 An ECC Single Error occurred and was corrected during a previous read.

1:4 Reserved (Read Only)

A write to these bits has no effect. A read of these bits always outputs 0.

SIZE[2:0]

5:7

Array space SIZE 2–0

The value of SIZE field depends on the size of the Flash module:

000 128 KB

001 256 KB (the value for the MPC5602P device in the code Flash module)

010 512 KB

011 Reserved (1024 KB)

100 Reserved (1536 KB)

101 Reserved (2048 KB)

110 64 KB (the value for the device in the data Flash module)

111 Reserved

Note: The value for this bitfield is different between the code and data Flash modules.

8Reserved (Read Only)

A write to these bits has no effect. A read of these bits always outputs 0.

LAS[2:0]

9:11

Low Address Space 2–0

The value of the LAS field corresponds to the configuration of the Low Address Space:

000 Reserved

001 Reserved

010 32 KB + (2 × 16 KB) + (2 × 32 KB) + 128 KB (the value for the MPC5602Pdevice in the code

Flash module)

011 Reserved

100 Reserved

101 Reserved

110 4 × 16 KB (the value for the MPC5602Pdevice in the data Flash module)

111 Reserved

Note: The value for this bitfield is different between the code and data Flash modules.

12:14 Reserved (Read Only)

A write to these bits has no effect. A read of these bits always outputs 0.

MAS

Mid Address Space

The value of the MAS field corresponds to the configuration of the Mid Address Space:

0 0 KB or 2 × 128 KB

1Reserved

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 341

EER

ECC Event Error

EER provides information on previous reads. When an ECC Double Error detection occurs, the EER

bit is set to 1.

This bit must then be cleared, or a reset must occur before this bit will return to a 0 state. This bit may

not be set to 1 by the user.

In the event of a ECC Single Error detection and correction, this bit will not be set.

If EER is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing

of EER) were correct.

Since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. A write of 0

will have no effect.

0 Reads are occurring normally.

1 An ECC Double Error occurred during a previous read.

RWE

Read-while-Write event Error

RWE provides information on previous reads when a Modify operation is on going. If a RWW Error

occurs, the RWE bit is set to 1. Read-While-Write Error means that a read access to the Flash module

has occurred while the FPEC was performing a program or Erase operation or an Array Integrity

Check.

This bit must then be cleared, or a reset must occur before this bit will return to a 0 state. This bit may

not be set to 1 by the user.

If RWE is not set, or remains 0, this indicates that all previous RWW reads (from the last reset, or

clearing of RWE) were correct.

Since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. A write of 0

will have no effect.

0 Reads are occurring normally.

1 A RWW Error occurred during a previous read.

Note: If stall/terminate-while-write is used, the software should ignore the setting of the RWE flag and

should clear this flag after each erase operation. If stall/terminate-while-write is not used,

software can handle the RWE error normally.

18:19 Reserved (Read Only)

A write to these bits has no effect. A read of these bits always outputs 0.

PEAS

Program/Erase Access Space

PEAS indicates which space is valid for program and Erase operations: main array space or

shadow/test space.

PEAS = 0 indicates that the main address space is active for all Flash module program and erase

operations.

PEAS = 1 indicates that the test or shadow address space is active for program and erase.

The value in PEAS is captured and held with the first interlock write done for Modify operations. The

value of PEAS is retained between sampling events (that is, subsequent first interlock writes).

0 Shadow/Test address space is disabled for program/erase and main address space enabled.

1 Shadow/Test address space is enabled for program/erase and main address space disabled.

Table 17-13. MCR field descriptions (continued)

Field Description

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

342 Freescale Semiconductor

DONE

Modify Operation Done

DONE indicates if the Flash module is performing a high voltage operation.

DONE is set to 1 on termination of the Flash module reset.

DONE is cleared to 0 just after a 0-to-1 transition of EHV, which initiates a high voltage operation, or

after resuming a suspended operation.

DONE is set to 1 at the end of program and erase high voltage sequences.

DONE is set to 1 (within tPABT or tEABT

, equal to P/E Abort Latency) after a 1-to-0 transition of EHV,

which terminates a high voltage program/erase operation.

DONE is set to 1 (within tESUS, time equal to Erase Suspend Latency) after a 0-to-1 transition of

ESUS, which suspends an erase operation.

0 Flash is executing a high voltage operation.

1 Flash is not executing a high voltage operation.

PEG

Program/Erase Good

The PEG bit indicates the completion status of the last Flash program or erase sequence for which

high voltage operations were initiated. The value of PEG is updated automatically during the program

and erase high voltage operations.

Aborting a program/erase high voltage operation causes PEG to be cleared to 0, indicating the

sequence failed.

PEG is set to 1 when the Flash module is reset, unless a Flash initialization error has been detected.

The value of PEG is valid only when PGM = 1 and/or ERS = 1 and after DONE transitions from 0 to

1 due to a termination or the completion of a program/erase operation. PEG is valid until PGM/ERS

makes a 1-to-0 transition or EHV makes a 0-to-1 transition.

The value in PEG is not valid after a 0-to-1 transition of DONE caused by ESUS being set to logic 1.

If program or erase are attempted on blocks that are locked, the response is PEG = 1, indicating that

the operation was successful, and the content of the block were properly protected from the program

or erase operation.

If a program operation tries to program at 1 bits that are at 0, the program operation is correctly

executed on the new bits to be programmed at 0, but PEG is cleared, indicating that the requested

operation has failed.

In Array Integrity Check or Margin Mode, PEG is set to 1 when the operation is completed, regardless

the occurrence of any error. The presence of errors can be detected only comparing checksum value

stored in UMIRS[0:1].

0 Program or erase operation failed; or program, erase, Array Integrity Check, or Margin Mode was

terminated.

1 Program or erase operation successful; or Array Integrity Check or Margin Mode completed

successfully.

23:26 Reserved (Read Only)

A write to these bits has no effect. A read of these bits always outputs 0.

PGM

Program

PGM sets up the Flash module for a program operation.

A 0-to-1 transition of PGM initiates a program sequence.

A 1-to-0 transition of PGM ends the program sequence.

PGM can be set only under User mode Read (ERS is low and UT0[AIE] is low). PGM can be cleared

by the user only when EHV is low and DONE is high. PGM is cleared on reset.

0 Flash is not executing a program sequence.

1 Flash is executing a program sequence.

PSUS

Program Suspend

Writing to this bit has no effect, but the written data can be read back.

Table 17-13. MCR field descriptions (continued)

Field Description

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 343

A number of MCR bits are protected against write when another bit, or set of bits, is in a specific state.

These write locks are covered on a bit by bit basis in the preceding description, but those locks do not

consider the effects of trying to write two or more bits simultaneously.

The Flash module does not allow the user to write bits simultaneously which would put the device into an

illegal state. This is implemented through a priority mechanism among the bits. Table 17-14 shows the bit

changing priorities.

ERS

Erase

ERS sets up the Flash module for an Erase operation.

A 0-to-1 transition of ERS initiates an Erase sequence.

A 1-to-0 transition of ERS ends the Erase sequence.

ERS can be set only under User mode Read (PGM is low and UT0[AIE] is low). ERS can be cleared

by the user only when ESUS and EHV are low and DONE is high. ERS is cleared on reset.

0 Flash is not executing an Erase sequence.

1 Flash is executing an Erase sequence.

ESUS

Erase Suspend

ESUS indicates that the Flash module is in Erase Suspend or in the process of entering a Suspend

state. The Flash module is in Erase Suspend when ESUS = 1 and DONE = 1.

ESUS can be set high only when ERS = 1 and EHV = 1, and PGM = 0.

A 0-to-1 transition of ESUS starts the sequence that sets DONE and places the Flash in erase

suspend. The Flash module enters Suspend within tESUS of this transition.

ESUS can be cleared only when DONE = 1 and EHV = 1, and PGM = 0.

A 1-to-0 transition of ESUS with EHV = 1 starts the sequence that clears DONE and returns the

Module to Erase.

The Flash module cannot exit Erase Suspend and clear DONE while EHV is low.

ESUS is cleared on reset.

0 Erase sequence is not suspended.

1 Erase sequence is suspended.

EHV

Enable High Voltage

The EHV bit enables the Flash module for a high voltage program/Erase operation. EHV is cleared

on reset.

EHV must be set after an interlock write to start a program/Erase sequence. EHV may be set under

one of the following conditions:

• Erase (ERS = 1, ESUS = 0, UT0[AIE] = 0)

• Program (ERS = 0, ESUS = 0, PGM = 1, UT0[AIE] = 0)

In normal operation, a 1-to-0 transition of EHV with DONE high and ESUS low terminates the current

program/Erase high voltage operation.

When an operation is terminated, there is a 1-to-0 transition of EHV with DONE low and the eventual

Suspend bit low. A termination causes the value of PEG to be cleared, indicating a failing

program/Erase; address locations being operated on by the terminated operation contain

indeterminate data after a termination. A suspended operation cannot be terminated. Terminating a

high voltage operation leaves the Flash module addresses in an indeterminate data state. This may

be recovered by executing an Erase on the affected blocks.

EHV may be written during Suspend. EHV must be high to exit Suspend. EHV may not be written

after ESUS is set and before DONE transitions high. EHV may not be cleared after ESUS is cleared

and before DONE transitions low.

0 Flash is not enabled to perform an high voltage operation.

1 Flash is enabled to perform an high voltage operation.

Table 17-13. MCR field descriptions (continued)

Field Description

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

344 Freescale Semiconductor

If the user attempts to write two or more MCR bits simultaneously, only the bit with the lowest priority

level is written.

17.3.7.2 Low/Mid Address Space Block Locking register (LML)

The Low/Mid Address Space Block Locking register provides a means to protect blocks from being

modified. These bits, along with bits in the SLL register, determine if the block is locked from program or

erase. An “OR” of LML and SLL determine the final lock status. Identical LML registers are provided in

the code Flash and the data Flash blocks.

In the code Flash module, the LML register has a related Non-Volatile Low/Mid Address Space Block

Locking register (NVLML) located in TestFlash that contains the default reset value for LML. The

NVLML register is read during the reset phase of the Flash module and loaded into the LML. The reset

value is 0x00XX_XXXX, initially determined by the NVLML value from test sector.

Table 17-14. MCR bits set/clear priority levels

Priority level MCR bits

1ERS

2PGM

3EHV

4ESUS

Address:

Base + 0x0004 Access: User read/write

0123456789101112131415

RLME0000000000

TSLK 0 0 0 0

Reset00000000000x00xx

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RLLK

LLK

Resetxxxxxxxxxxxxxxxx

Figure 17-11. Low/Mid Address Space Block Locking register (LML)

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 345

17.3.7.3 Non-Volatile Low/Mid Address Space Block Locking register (NVLML)

The NVLML register is a 64-bit register, the 32 most significant bits of which (bits 63:32) are “don’t care”

bits that are eventually used to manage ECC codes. Identical NVLML registers are provided in the code

Flash and the data Flash blocks.

Address:

Base + 0x40_3DE8 Access: User read/write

0123456789101112131415

R00000000000

TSLK 0 0 0 0

Reset00000000000x00xx

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RLLK

LLK

Resetxxxxxxxxxxxxxxxx

Figure 17-12. Non-Volatile Low/Mid Address Space Block Locking register (NVLML)

Table 17-15. LML and NVLML field descriptions

Field Description

LME1

Low/Mid Address Space Block Enable

This bit enables the Lock registers (TSLK and LLK[15:0]) to be set or cleared by registers writes.

This bit is a status bit only. The method to set this bit is to write a password, and if the password

matches, the LME bit is set to reflect the status of enabled, and is enabled until a reset operation

occurs. For LME the password 0xA1A11111 must be written to the LML register.

0 Low Address Locks are disabled: TSLK and LLK[15:0] cannot be written.

1 Low Address Locks are enabled: TSLK and LLK[15:0] can be written.

1:10 Reserved (Read Only)

A write to these bits has no effect. A read of these bits always outputs 0.

TSLK

Test/Shadow Address Space Block Lock

This bit locks the block of Test and Shadow Address Space from program and Erase (Erase is any

case forbidden for Test block).

A value of 1 in the TSLK register signifies that the Test/Shadow block is locked for program and

Erase. A value of 0 in the TSLK register signifies that the Test/Shadow block is available to receive

program and Erase pulses.

The TSLK register is not writable once an interlock write is completed until MCR[DONE] is set at

the completion of the requested operation. Likewise, the TSLK register is not writable if a high

voltage operation is suspended.

Upon reset, information from the TestFlash block is loaded into the TSLK register. The TSLK bit

may be written as a register. Reset will cause the bit to go back to its TestFlash block value. The

default value of the TSLK bit (assuming erased fuses) would be locked.

TSLK is not writable unless LME is high.

0 Test/Shadow Address Space Block is unlocked and can be modified (if also SLL[STSLK] = 0).

1 Test/Shadow Address Space Block is locked and cannot be modified.

12:13 Reserved (Read Only)

A write to these bits has no effect. A read of these bits always outputs 0.

14:15 Reserved

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MPC5602P Microcontroller Reference Manual, Rev. 4

346 Freescale Semiconductor

17.3.7.4 Secondary Low/Mid Address Space Block Locking register (SLL)

The Secondary Low/Mid Address Space Block Locking register provides an alternative means to protect

blocks from being modified. These bits, along with bits in the LML register, determine if the block is

locked from program or Erase. An “OR” of LML and SLL determine the final lock status. Identical SLL

registers are provided in the code Flash and the data Flash blocks.

In the code Flash module, the SLL register has a related Non-Volatile Secondary Low/Mid Address Space

Block Locking register (NVSLL) located in TestFlash that contains the default reset value for SLL. The

reset value is 0x00XX_XXXX, initially determined by NVSLL.

The NVSLL register is read during the reset phase of the Flash module and loaded into the SLL.

LLK[15:0]

16:31

Low Address Space Block Lock 15-0

These bits lock the blocks of Low Address Space from program and Erase.

For code Flash, LLK[5:0] are related to sectors B0F[5:0], respectively. See Ta bl e 1 7 - 6 for more

information.

For data Flash, LLK[3:0] are related to sectors B1F[3:0], respectively. See Ta b l e 1 7 - 7 for more

information.

A value of 1 in a bit of the LLK bitfield signifies that the corresponding block is locked for program

and Erase.

A value of 0 in a bit of the LLK bitfield signifies that the corresponding block is available to receive

program and Erase pulses.

The LLK bitfield is not writable once an interlock write is completed until MCR[DONE] is set at the

completion of the requested operation. Likewise, the LLK bitfield is not writable if a high voltage

operation is suspended.

Upon reset, information from the TestFlash block is loaded into the LLK bitfields. The LLK bits may

be written as a register. Reset will cause the bits to go back to their TestFlash block value. The

default value of the LLK bits (assuming erased fuses) would be locked.

In the event that blocks are not present (due to configuration or total memory size), the LLK bits

will default to locked, and will not be writable. The reset value is always 1 (independent of the

TestFlash block), and register writes have no effect.

In the code Flash macrocell, bits LLK[15:6] are read-only and locked at 1.

In the data Flash macrocell, bits LLK[15:4] are read-only and locked at 1.

LLK is not writable unless LME is high.

0 Low Address Space Block is unlocked and can be modified (if also SLL[SLK] = 0).

1 Low Address Space Block is locked and cannot be modified.

1This field is present only in LML

Table 17-15. LML and NVLML field descriptions (continued)

Field Description

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 347

17.3.7.5 Non-Volatile Secondary Low/Mid Address Space Block Locking register

(NVSLL)

The NVSLL register is a 64-bit register, the 32 most significant bits of which (bits 63:32) are “don’t care”

bits that are eventually used to manage ECC codes. Identical NVSLL registers are provided in the code

Flash and the data Flash blocks.

Address:

Base + 0x000C Access: User read/write

0123456789101112131415

RSLE0000000000

STS

0 0 0 0

Reset00000000000x00xx

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RSLK

SLK

Resetxxxxxxxxxxxxxxxx

Figure 17-13. Secondary Low/mid address space block Locking reg (SLL)

Address:

Base + 0x40_3DF8 Access: User read/write

0123456789101112131415

R00000000000

STS

0 0 0 0

Reset00000000000x00xx

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RSLK

SLK

Resetxxxxxxxxxxxxxxxx

Figure 17-14. Non-Volatile Secondary Low/Mid Address Space Block Locking register (NVSLL)

Table 17-16. SLL and NVSLL field descriptions

Field Description

SLE1

Secondary Low/Mid Address Space Block Enable

This bit enables the Lock registers (STSLK and SLK[15:0]) to be set or cleared by registers writes.

This bit is a status bit only. The method to set this bit is to write a password, and if the password

matches, the SLE bit is set to reflect the status of enabled, and is enabled until a reset operation

occurs. For SLE the password 0xC3C3_3333 must be written to the SLL register.

0 Secondary Low/Mid Address Locks are disabled: STSLK and SLK[15:0] cannot be written.

1 Secondary Low/Mid Address Locks are enabled: STSLK and SLK[15:0] can be written.

1:10 Reserved (Read Only)

A write to these bits has no effect. A read of these bits always outputs 0.

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MPC5602P Microcontroller Reference Manual, Rev. 4

348 Freescale Semiconductor

STSLK

Secondary Test/Shadow address space block LocK

This bit is used as an alternate means to lock the block of Test and Shadow Address Space from

program and Erase (Erase is any case forbidden for Test block).

A value of 1 in the STSLK bitfield signifies that the Test/Shadow block is locked for program and

Erase.

A value of 0 in the STSLK register signifies that the Test/Shadow block is available to receive

program and Erase pulses.

The STSLK register is not writable once an interlock write is completed until MCR[DONE] is set at

the completion of the requested operation. Likewise, the STSLK register is not writable if a high

voltage operation is suspended.

Upon reset, information from the TestFlash block is loaded into the STSLK register. The STSLK bit

may be written as a register. Reset will cause the bit to go back to its TestFlash block value. The

default value of the STSLK bit (assuming erased fuses) would be locked.

STSLK is not writable unless SLE is high.

0 Test/Shadow Address Space Block is unlocked and can be modified (if also LML[TSLK] = 0).

1 Test/Shadow Address Space Block is locked and cannot be modified.

12:13 Reserved (Read Only)

A write to these bits has no effect. A read of these bits always outputs 0.

14:15 Reserved

SLK[15:0]

16:31

Secondary Low Address Space Block Lock 15–0

These bits are used as an alternate means to lock the blocks of Low Address Space from program

and Erase.

For code Flash, SLK[5:0] are related to sectors B0F[5:0], respectively. See Ta b l e 1 7 - 6 for more

information.

For data Flash, SLK[3:0] are related to sectors B1F[3:0], respectively. See Ta bl e 1 7 - 7 for more

information.

A value of 1 in a bit of the SLK register signifies that the corresponding block is locked for program

and Erase.

A value of 0 in a bit of the SLK register signifies that the corresponding block is available to receive

program and Erase pulses.

The SLK register is not writable once an interlock write is completed until MCR[DONE] is set at the

completion of the requested operation. Likewise, the SLK register is not writable if a high voltage

operation is suspended.

Upon reset, information from the TestFlash block is loaded into the SLK registers. The SLK bits may

be written as a register. Reset causes the bits to go back to their TestFlash block value. The default

value of the SLK bits (assuming erased fuses) would be locked.

In the event that blocks are not present (due to configuration or total memory size), the SLK bits

default to locked, and are not writable. The reset value will always be 1 (independent of the

TestFlash block), and register writes will have no effect.

In the code Flash macrocell, bits SLK[15:6] are read-only and locked at 1.

In the data Flash macrocell, bits SLK[15:4] are read-only and locked at 1.

SLK is not writable unless SLE is high.

0 Low Address Space Block is unlocked and can be modified (if also LML[LLK] = 0).

1 Low Address Space Block is locked and cannot be modified.

1This field is present only in SLL

Table 17-16. SLL and NVSLL field descriptions (continued)

Field Description

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 349

17.3.7.6 Low/Mid Address Space Block Select register (LMS)

The Low/Mid Address Space Block Select register provides a means to select blocks to be operated on

during erase. Identical LMS registers are provided in the code Flash and the data Flash blocks.

17.3.7.7 Address Register (ADR)

The Address Register provides the first failing address in the event module failures (ECC, RWW, or FPEC)

or the first address at which a ECC single error correction occurs.

Address:

Base + 0x0010 Access: User read/write

0123456789101112131415

R0000000000000 0 0 0

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RLSL

LSL

Reset0000000000000000

Figure 17-15. Low/Mid Address Space Block Select register (LMS)

Table 17-17. LMS field descriptions

Field Description

0:13 Reserved (Read Only)

A write to these bits has no effect. A read of these bits always outputs 0.

14:15 Reserved

LSL[15:0]

16:31

Low Address Space Block Select 15–0

A value of 1 in the select register signifies that the block is selected for erase.

A value of 0 in the select register signifies that the block is not selected for erase. The reset value

for the select register is 0, or unselected.

For code Flash, LSL[5:0] are related to sectors B0F[5:0], respectively. See Table 17-6 for more

information.

For data Flash, LSL[3:0] are related to sectors B1F[3:0], respectively. See Table 17-7 for more

information.

The blocks must be selected (or unselected) before doing an erase interlock write as part of the

Erase sequence. The select register is not writable once an interlock write is completed or if a high

voltage operation is suspended.

In the event that blocks are not present (due to configuration or total memory size), the

corresponding LSL bits will default to unselected, and will not be writable. The reset value will

always be 0, and register writes will have no effect.

In the code Flash macrocell, bits LSL[15:6] are read-only and locked at 0.

In the data Flash macrocell, bits LSL[15:4] are read-only and locked at 0.

0 Low Address Space Block is unselected for Erase.

1 Low Address Space Block is selected for Erase.

Chapter 17 Flash Memory

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350 Freescale Semiconductor

Address:

Base + 0x0018 Access: User read/write

0123456789101112131415

R00000000 0 AD

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RAD

3000

Reset0000000000000000

Figure 17-16. Address Register (ADR)

Table 17-18. ADR field descriptions

Field Description

0:8 Reserved (Read Only)

A write to these bits has no effect. A read of these bits always outputs 0.

AD[22:3]

9:28

Address 22–3

ADR provides the first failing address in the event of ECC error (MCR[EER] set) or the first failing

address in the event of RWW error (MCR[RWE] set), or the address of a failure that may have

occurred in a FPEC operation (MCR[PEG] cleared). ADR also provides the first address at which a

ECC single error correction occurs (MCR[EDC] set).

The ECC double error detection takes the highest priority, followed by the RWW error, the FPEC

error, and the ECC single error correction. When accessed ADR will provide the address related to

the first event occurred with the highest priority. The priorities between these four possible events is

summarized in Table 17-19.

This address is always a double word address that selects 64 bits.

In case of a simultaneous ECC double error detection on both double words of the same page, bit

AD3 will output 0. The same is valid for a simultaneous ECC single error correction on both double

words of the same page.

In User mode, ADR is read only.

29:31 Reserved

Write these bits has no effect and read these bits always outputs 0.

Table 17-19. ADR content: priority list

Priority level Error flag ADR content

1 MCR[EER] = 1 Address of first ECC Double Error

2 MCR[RWE] = 1 Address of first RWW Error

3 MCR[PEG] = 0 Address of first FPEC Error

4 MCR[EDC] = 1 Address of first ECC Single Error Correction

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 351

17.3.7.7.1 Platform Flash Configuration Register 0 (PFCR0)

The Platform Flash Configuration Register 0 (PFCR0) defines the configuration associated with Flash

memory bank0, which corresponds to the code Flash. The register is described in Figure 17-17 and

Table 17-20.

NOTE

This register is not implemented on the data Flash block.

Address:

Base + 0x001C Access: User read/write

0123456789101112131415

BK0_APC BK0_WWSC BK0_RWSC

BK0_RWWC

Reset0001100011000111

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

BK0_RWWC

0000000

BK0_RWWC

B0_P0_BCFG

B0_P0_DPFE

B0_P0_IPFE

B0_P0_PFLM

B0_P0_BFE

Reset1000000011101101

Figure 17-17. Platform Flash Configuration Register 0 (PFCR0)

Table 17-20. PFCR0 field descriptions

Field Description

0-4

BK0_APC

Bank0 Address Pipelining Control

This field controls the number of cycles between Flash array access requests. This field must be

set to a value appropriate to the operating frequency of the PFlash. Higher operating frequencies

require non-zero settings for this field for proper Flash operation. This field is set to 0b00010 by

hardware reset.

00000 Accesses may be initiated on consecutive (back-to-back) cycles.

00001 Access requests require one additional hold cycle.

00010 Access requests require two additional hold cycles.

...

11110 Access requests require 30 additional hold cycles.

11111 Access requests require 31 additional hold cycles.

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

352 Freescale Semiconductor

5-9

BK0_WWSC

Bank0 Write Wait State Control

This field controls the number of wait states to be added to the Flash array access time for writes.

This field must be set to a value appropriate to the operating frequency of the PFlash. Higher

operating frequencies require non-zero settings for this field for proper Flash operation. This field

is set to an appropriate value by hardware reset. This field is set to 0b00010 by hardware reset.

00000 No additional wait states are added.

00001 1 additional wait state is added.

00010 2 additional wait states are added.

...

111111 31 additional wait states are added.

10-14

BK0_RWSC

Bank0 Read Wait State Control

This field controls the number of wait states to be added to the Flash array access time for reads.

This field must be set to a value corresponding to the operating frequency of the PFlash and the

actual read access time of the PFlash. Higher operating frequencies require non-zero settings for

this field for proper Flash operation.

0 MHz, < 23 MHz APC = RWSC = 0.

23 MHz, < 45 MHz APC = RWSC = 1.

45 MHz, < 68 MHz APC = RWSC = 2.

68 MHz, < 90 MHz APC = RWSC = 3.

This field is set to 0b00010 by hardware reset.

00000 No additional wait states are added.

00001 1 additional wait state is added.

00010 2 additional wait states are added.

...

111111 31 additional wait states are added.

15-16,24

BK0_RWWC

Bank0 Read-While-Write Control

This 3-bit field defines the controller response to Flash reads while the array is busy with a

program (write) or erase operation.

0xx Terminate any attempted read while write/erase with an error response.

100 Generate a bus stall for a read while write/erase, enable the operation termination and

the abort notification interrupt.

101 Generate a bus stall for a read while write/erase, enable the operation abort, disable

the abort notification interrupt.

110 Generate a bus stall for a read while write/erase, enable the stall notification interrupt,

disable the abort + abort notification interrupt.

111 Generate a bus stall for a read while write/erase, disable the stall notification interrupt,

disable the abort + abort notification interrupt.

This field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the

abort and notification interrupts.

17-23 Reserved

Table 17-20. PFCR0 field descriptions (continued)

Field Description

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 353

25-26

B0_P0_BCFG

Bank0, Port 0 Page Buffer Configuration

This field controls the configuration of the four page buffers in the PFlash controller. The buffers

can be organized as a “pool” of available resources, or with a fixed partition between instruction

and data buffers.

If enabled, when a buffer miss occurs, it is allocated to the least-recently-used buffer within the

group and the just-fetched entry then marked as most-recently-used. If the Flash access is for the

next-sequential line, the buffer is not marked as most-recently-used until the given address

produces a buffer hit.

00 All four buffers are available for any Flash access, that is, there is no partitioning of the buffers

based on the access type.

01 Reserved.

10 The buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches

and buffers 2 and 3 for data accesses.

11 The buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches

and buffer 3 for data accesses.

This field is set to 2b11 by hardware reset.

B0_P0_DPFE

Bank0, Port 0 Data Prefetch Enable

This field enables or disables prefetching initiated by a data read access. This field is cleared by

hardware reset.

0 No prefetching is triggered by a data read access.

1 If page buffers are enabled (B0_P0_BFE = 1), prefetching is triggered by any data read access.

B0_P0_IPFE

Bank0, Port 0 Instruction Prefetch Enable

This field enables or disables prefetching initiated by an instruction fetch read access. This field is

set by hardware reset.

0 No prefetching is triggered by an instruction fetch read access.

1 If page buffers are enabled (B0_P0_BFE = 1), prefetching is triggered by any instruction fetch

read access.

29-30

B0_P0_PFLM

Bank0, Port 0 Prefetch Limit

This field controls the prefetch algorithm used by the PFlash controller. This field defines the

prefetch behavior. In all situations when enabled, only a single prefetch is initiated on each buffer

miss or hit. This field is set to 2b10 by hardware reset.

00 No prefetching is performed.

01 The referenced line is prefetched on a buffer miss, that is, prefetch on miss.

1xThe referenced line is prefetched on a buffer miss, or the next sequential page is prefetched

on a buffer hit (if not already present), that is, prefetch on miss or hit.

B0_P0_BFE

Bank0, Port 0 Buffer Enable

This bit enables or disables page buffer read hits. It is also used to invalidate the buffers. This bit

is set by hardware reset.

0 The page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared.

1 The page buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when

the buffers are successfully filled.

Table 17-20. PFCR0 field descriptions (continued)

Field Description

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

354 Freescale Semiconductor

17.3.7.7.2 Platform Flash Configuration Register 1 (PFCR1)

The Platform Flash Configuration Register 1 (PFCR1) defines the configuration associated with Flash

memory bank1. This corresponds to the data Flash. The register is described in Figure 17-18 and

Table 17-21.

NOTE

This register is not implemented on the data Flash block.

Address:

Base + 0x0020 Access: User read/write

0123456789101112131415

BK1_APC BK1_WWSC BK1_RWSC

BK1_RWWC

Reset0100001000010001

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

BK1_RWWC

000000

B1_P1_BFE

BK1_RWWC

000000

B1_P0_BFE

Reset1000000010000001

Figure 17-18. Platform Flash Configuration Register 1 (PFCR1)

Table 17-21. PFCR1 field descriptions

Field Description

0-4

BK1_APC

Bank1 Address Pipelining Control

This field controls the number of cycles between Flash array access requests. This field must be set

to a value appropriate to the operating frequency of the PFlash. Higher operating frequencies require

non-zero settings for this field for proper Flash operation. This field is set to 0b00010 by hardware

reset.

00000 Accesses may be initiated on consecutive (back-to-back) cycles.

00001 Access requests require one additional hold cycle.

00010 Access requests require two additional hold cycles.

...

11110 Access requests require 30 additional hold cycles.

11111 Access requests require 31 additional hold cycles.

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 355

5-9

BK1_WWSC

Bank1 Write Wait State Control

This field controls the number of wait states to be added to the Flash array access time for writes. This

field must be set to a value appropriate to the operating frequency of the PFlash. Higher operating

frequencies require non-zero settings for this field for proper Flash operation. This field is set to an

appropriate value by hardware reset. This field is set to 0b00010 by hardware reset.

00000 No additional wait states are added.

00001 1 additional wait state is added.

00010 2 additional wait states are added.

...

111111 31 additional wait states are added.

10-14

BK1_RWSC

Bank1 Read Wait State Control

This field controls the number of wait states to be added to the Flash array access time for reads. This

field must be set to a value corresponding to the operating frequency of the PFlash and the actual

read access time of the PFlash. Higher operating frequencies require non-zero settings for this field

for proper Flash operation.

0 MHz, < 23 MHz APC = RWSC = 0.

23 MHz, < 45 MHz APC = RWSC = 1.

45 MHz, < 68 MHz APC = RWSC = 2.

68 MHz, < 90 MHz APC = RWSC = 3.

This field is set to 0b00010 by hardware reset.

00000 No additional wait states are added.

00001 1 additional wait state is added.

00010 2 additional wait states are added.

...

111111 31 additional wait states are added.

15-16,24

BK1_RWWC

Bank1 Read-While-Write Control

This 3-bit field defines the controller response to Flash reads while the array is busy with a program

(write) or erase operation.

0xx Terminate any attempted read while write/erase with an error response.

100 Generate a bus stall for a read while write/erase, enable the operation abort and the abort

notification interrupt.

101 Generate a bus stall for a read while write/erase, enable the operation abort, disable the abort

notification interrupt.

110 Generate a bus stall for a read while write/erase, enable the stall notification interrupt, disable

the abort + abort notification interrupt.

111 Generate a bus stall for a read while write/erase, disable the stall notification interrupt, disable

the abort + abort notification interrupt.

This field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the abort

and notification interrupts.

17-22 Reserved, should be cleared.

Table 17-21. PFCR1 field descriptions (continued)

Field Description

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

356 Freescale Semiconductor

17.3.7.7.3 Platform Flash Access Protection Register (PFAPR)

The Platform Flash Access Protection Register (PFAPR) controls read and write accesses to the Flash

based on system master number. Prefetching capabilities are defined on a per master basis. This register

also defines the arbitration mode for controllers supporting two AHB ports. The register is described in

Figure 17-19 and Table 17-22.

The contents of the register are loaded from location 0x20_3E00 of the shadow region in the code Flash

(bank0) array at reset. To temporarily change the values of any of the fields in the PFAPR, a write to the

IPS-mapped register is performed. To change the values loaded into the PFAPR at reset, the word location

at address 0x20_3E00 of the shadow region in the Flash array must be programmed using the normal

sequence of operations. The reset value shown in Table 17-19 reflects an erased or unprogrammed value

from the shadow region.

NOTE

This register is not implemented on the data Flash block.

B1_P1_BFE

Bank1, Port 1 Buffer Enable

This bit enables or disables read hits from the 128-bit holding register. It is also used to invalidate the

contents of the holding register. This bit is set by hardware reset, enabling the use of the holding

0 The holding register is disabled from satisfying read requests.

1 The holding register is enabled to satisfy read requests on hits.

25-30 Reserved, should be cleared.

B1_P0_PFE

Bank1, Port 0 Buffer Enable

This bit enables or disables read hits from the 128-bit holding register. It is also used to invalidate the

contents of the holding register. This bit is set by hardware reset, enabling the use of the holding

0 The holding register is disabled from satisfying read requests.

1 The holding register is enabled to satisfy read requests on hits.

Address:

Base + 0x0024 Access: User read/write

0123456789101112131415

R000000 ARBM M7

PFD

Reset0000001111111111

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RM7AP M6AP M5AP M4AP M3AP M2AP M1AP M0AP

Reset1111111111111111

Figure 17-19. Platform Flash Access Protection Register (PFAPR)

Table 17-21. PFCR1 field descriptions (continued)

Field Description

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 357

17.3.7.8 User Test 0 register (UT0)

The User Test feature gives the user of the Flash module the ability to perform test features on the Flash.

The User Test 0 register allows controlling the way in which the Flash content check is done.

The UT0[MRE], UT0[MRV], UT0[AIS], UT0[EIE], and DSI[7:0] bits are not accessible whenever

MCR[DONE] or UT0[AID] are low. Reads return indeterminate data. Writes have no effect.

Table 17-22. PFAPR field descriptions

Field Description

0-5 Reserved, should be cleared.

6-7

ARBM

Arbitration Mode

This 2-bit field controls the arbitration for PFlash controllers supporting 2 AHB ports.

00 Fixed priority arbitration with AHB p0 > p1.

01 Fixed priority arbitration with AHB p1 > p0.

1xRound-robin arbitration.

8-15

MxPFD

Master x Prefetch Disable (x= 0,1,2,...,7)

These bits control whether prefetching may be triggered based on the master number of the requesting

AHB master. This field is further qualified by the PFCR0[B0_Px_DPFE, B0_Px_IPFE, Bx_Py_BFE]

bits.

0 Prefetching may be triggered by this master.

1 No prefetching may be triggered by this master.

16-31

MxAP

Master x Access Protection (x= 0,1,2,...,7)

These fields control whether read and write accesses to the Flash are allowed based on the master

number of the initiating module.

00 No accesses may be performed by this master.

01 Only read accesses may be performed by this master.

10 Only write accesses may be performed by this master.

11 Both read and write accesses may be performed by this master.

Address:

Base + 0x003C Access: User read/write

0123456789101112131415

RUTE0000000DSI7 DSI6 DSI5 DSI4 DSI3 DSI2 DSI1 DSI0

Ww1c

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R00000000 0 XMREMRV

EIE AIS AIE AID

Reset0000000000000001

Figure 17-20. User Test 0 register (UT0)

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

358 Freescale Semiconductor

Table 17-23. UT0 field descriptions

Field Description

UTE

User Test Enable

This status bit indicates when User Test is enabled. All bits in UT0–2 and UMISR0–4 are locked

when this bit is 0.

This bit is not writeable to a 1, but may be cleared. The reset value is 0.

The method to set this bit is to provide a password, and if the password matches, the UTE bit is set

to reflect the status of enabled, and is enabled until it is cleared by a register write.

For UTE the password 0xF9F9_9999 must be written to the UT0 register.

1:7 Reserved (Read Only)

A write to these bits has no effect. A read of these bits always outputs 0.

DSI7-0

8:15

Data Syndrome Input 7–0

These bits represent the input of Syndrome bits of ECC logic used in the ECC Logic Check. The

DSI7–0 bits correspond to the 8 syndrome bits on a double word.

These bits are not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return

indeterminate data, and writes have no effect.

0 The syndrome bit is forced at 0.

1 The syndrome bit is forced at 1.

16:24 Reserved (Read Only)

A write to these bits has no effect. A read of these bits always outputs 0.

25 Reserved (Read/Write)

This bit can be written and its value can be read back, but there is no function associated.

This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate

data, and writes have no effect.

MRE

Margin Read Enable

MRE enables margin reads to be done. This bit, combined with MRV, enables regular user mode

reads to be replaced by margin reads.

Margin reads are only active during Array Integrity Checks; Normal user reads are not affected by

MRE.

This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate

data, and writes have no effect.

0 Margin reads are disabled. All reads are User mode reads.

1 Margin reads are enabled.

MRV

Margin Read Value

If MRE is high, MRV selects the margin level that is being checked. Margin can be checked to an

erased level (MRV = 1) or to a programmed level (MRV = 0).

This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate

data, and writes have no effect.

0 Zero’s (programmed) margin reads are requested (if MRE = 1).

1 One’s (erased) margin reads are requested (if MRE = 1).

EIE

ECC data Input Enable

EIE enables the ECC Logic Check operation to be done.

This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate

data, and writes have no effect.

0 ECC Logic Check is disabled.

1 ECC Logic Check is enabled.

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 359

17.3.7.9 User Test 1 register (UT1)

The User Test 1 register allows to enable the checks on the ECC logic related to the 32 LSB of the Double

Word.

The User Test 1 register is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return

indeterminate data. Writes have no effect.

AIS

Array Integrity Sequence

AIS determines the address sequence to be used during array integrity checks or Margin Mode.

The default sequence (AIS = 0) is meant to replicate sequences normal user code follows, and

thoroughly checks the read propagation paths. This sequence is proprietary.

The alternative sequence (AIS = 1) is just logically sequential.

It should be noted that the time to run a sequential sequence is significantly shorter than the time

to run the proprietary sequence.

This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate

data, and writes have no effect. In Margin Mode only the linear sequence (AIS = 1) is allowed, while

the proprietary sequence (AIS = 0) is forbidden.

0 Array Integrity sequence is a proprietary sequence.

1 Array Integrity or Margin Mode sequence is sequential.

AIE

Array Integrity Enable

AIE set to 1 starts the Array Integrity Check done on all selected and unlocked blocks.

The pattern is selected by AIS, and the MISR (UMISR0–4) can be checked after the operation is

complete, to determine if a correct signature is obtained.

AIE can be set only if MCR[ERS], MCR[PGM], and MCR[EHV] are all low.

0 Array Integrity Checks are disabled.

1 Array Integrity Checks are enabled.

AID

Array Integrity Done

AID is cleared upon an Array Integrity Check being enabled (to signify the operation is on-going).

Once completed, AID is set to indicate that the Array Integrity Check is complete. At this time, the

MISR (UMISR0–4) can be checked.

0 Array Integrity Check is on-going.

1 Array Integrity Check is done.

Address:

Base + 0x0040 Access: User read/write

0123456789101112131415

RDAI

DAI

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RDAI

DAI

Reset0000000000000000

Figure 17-21. User Test 1 register (UT1)

Table 17-23. UT0 field descriptions (continued)

Field Description

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

360 Freescale Semiconductor

17.3.7.10 User Test 2 register (UT2)

The User Test 2 register allows to enable the checks on the ECC logic related to the 32 MSB of the Double

Word.

The User Test 2 register is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return

indeterminate data. Writes have no effect.

NOTE

This register is not implemented on the data Flash block.

17.3.7.11 User Multiple Input Signature Register 0 (UMISR0)

The Multiple Input Signature Register 0 (UMISR0) provides a mean to evaluate the array integrity.

UMISR0 represents the bits 31:0 of the whole 144-bit word (2 double words including ECC).

UMISR0 is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate data.

Writes have no effect.

Table 17-24. UT1 field descriptions

Field Description

DAI[31:0]

0:31

Data Array Input 31–0

These bits represent the input of the even word of ECC logic used in the ECC Logic Check. The

DAI[31:0] bits correspond to the 32 array bits representing Word 0 within the double word.

0 The array bit is forced at 0.

1 The array bit is forced at 1.

Address:

Base + 0x0044 Access: User read/write

0123456789101112131415

RDAI

DAI

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RDAI

DAI

Reset0000000000000000

Figure 17-22. User Test 2 register (UT2)

Table 17-25. UT2 field descriptions

Field Description

DAI[63:32]

0:31

Data Array Input [63:32]

These bits represent the input of the odd word of ECC logic used in the ECC Logic Check. The

DAI[63:32] bits correspond to the 32 array bits representing Word 1 within the double word.

0 The array bit is forced at 0.

1 The array bit is forced at 1.

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 361

17.3.7.12 User Multiple Input Signature Register 1 (UMISR1)

The Multiple Input Signature Register 1 (UMISR1) provides a means to evaluate the array integrity.

UMISR1 represents bits 63:32 of the whole 144-bit word (2 double words including ECC).

UMISR1 is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate data.

Writes have no effect.

Address:

Base + 0x0048 Access: User read/write

0123456789101112131415

RMS

031

030

029

028

027

026

025

024

023

022

021

020

019

018

017

016

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RMS

015

014

013

012

011

010

009

008

007

006

005

004

003

002

001

000

Reset0000000000000000

Figure 17-23. User Multiple Input Signature Register 0 (UMISR0)

Table 17-26. UMSIR0 field descriptions

Field Description

MS[031:000]

0:31

Multiple input Signature 031–000

These bits represent the MISR value obtained by accumulating the bits 31:0 of all the pages read

from the Flash memory.

The MS can be seeded to any value by writing the UMISR0 register.

Address:

Base + 0x004C Access: User read/write

0123456789101112131415

RMS

063

062

061

060

059

058

057

056

055

054

053

052

051

050

049

048

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RMS

047

046

045

044

043

042

041

040

039

038

037

036

035

034

033

032

Reset0000000000000000

Figure 17-24. User Multiple Input Signature Register 1 (UMISR1)

Table 17-27. UMISR1 field descriptions

Field Description

MS[063:032]

0:31

Multiple input Signature 063–032

These bits represent the MISR value obtained accumulating the bits 63:32 of all the pages read

from the Flash memory.

The MS can be seeded to any value by writing the UMISR1 register.

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

362 Freescale Semiconductor

17.3.7.13 User Multiple Input Signature Register 2 (UMISR2)

The Multiple Input Signature Register (UMISR2) provides a mean to evaluate the array integrity. UMISR2

represents the bits 95-64 of the whole 144-bit word (2 double words including ECC).

UMISR2 is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate data.

Writes have no effect.

NOTE

This register is not implemented on the data Flash block.

17.3.7.14 User Multiple Input Signature Register 3 (UMISR3)

The Multiple Input Signature Register 3 (UMISR3) provides a means to evaluate the array integrity.

UMISR3 represents bits 127:96 of the whole 144-bit word (2 double words including ECC).

UMISR3 is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate data.

Writes have no effect.

NOTE

This register is not implemented on the data Flash block.

Address:

Base + 0x0050 Access: User read/write

0123456789101112131415

RMS

095

094

093

092

091

090

089

088

087

086

085

084

083

082

081

080

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RMS

079

078

077

076

075

074

073

072

071

070

069

068

067

066

065

064

Reset0000000000000000

Figure 17-25. User Multiple Input Signature Register 2 (UMISR2)

Table 17-28. UMISR2 field descriptions

Field Description

MS[095:064]

0:31

Multiple input Signature 095–064

These bits represent the MISR value obtained by accumulating the bits 95:64 of all the pages read

from the Flash memory.

The MS can be seeded to any value by writing the UMISR2 register.

Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 363

17.3.7.15 User Multiple Input Signature Register 4 (UMISR4)

The Multiple Input Signature Register 4 (UMISR4) provides a means to evaluate the array integrity. The

UMISR4 represents the ECC bits of the whole 144-bit word (2 double words including ECC). Bits 8:15

are ECC bits for the odd double word and bits 24:31 are the ECC bits for the even double word. Bits 4:5

and 20:21 of UMISR4 are the double and single ECC error detection for odd and even double words,

respectively.

UMISR4 is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate data.

Writes have no effect.

NOTE

This register is not implemented on the data Flash block.

Address:

Base + 0x0054 Access: User read/write

0123456789101112131415

RMS

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RMS

111

110

109

108

107

106

105

104

103

102

101

100

099

098

097

096

Reset0000000000000000

Figure 17-26. User Multiple Input Signature Register 3 (UMISR3)

Table 17-29. UMISR3 field descriptions

Field Description

MS[127:096]

0:31

Multiple Input Signature 127–096

These bits represent the MISR value obtained accumulating bits 127:96 of all the pages read from

the Flash memory.

The MS can be seeded to any value by writing the UMISR3 register.

Address:

Base + 0x0058 Access: User read/write

0123456789101112131415

RMS

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RMS

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

Reset0000000000000000

Figure 17-27. User Multiple Input Signature Register 4 (UMISR4)

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17.3.7.16 Non-Volatile Private Censorship Password 0 register (NVPWD0)

The Non-Volatile Private Censorship Password 0 register (NVPWD0) contains the 32 LSB of the

password used to validate the Censorship information contained in NVSCI0–1 registers.

NOTE

This register is not implemented on the data Flash block.

17.3.7.17 Non-Volatile Private Censorship Password 1 register (NVPWD1)

The Non-Volatile Private Censorship Password 1 Register (NVPWD1) contains the 32 MSB of the

password used to validate the Censorship information contained in NVSCI0–1 registers.

NOTE

This register is not implemented on the data Flash block.

Table 17-30. UMISR4 field descriptions

Field Description

MS[159:128]

0:31

Multiple Input Signature 159:128

These bits represent the MISR value obtained accumulating:

• MS[135:128]—8 ECC bits for the even double word

• MS138—Single ECC error detection for even double word

• MS139—Double ECC error detection for even double word

• MS[151:144]—8 ECC bits for the odd double word

• MS154—Single ECC error detection for odd double word

• MS155—Double ECC error detection for odd double word

The MS can be seeded to any value by writing the UMISR4 register.

Address:

0x20_3DD8 Access: User read/write

0123456789101112131415

RPWD

PWD

Reset1111111011101101

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RPWD

PWD

Reset1111101011001110

Figure 17-28. Non-Volatile private Censorship Password 0 register (NVPWD0)

Table 17-31. NVPWD0 field descriptions

Field Description

PWD[31:0]

0:31

Password 31–0

The PWD[31:0] bits represent the 32 LSB of the private censorship password.

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17.3.7.18 Non-Volatile System Censoring Information 0 register (NVSCI0)

The Non-Volatile System Censoring Information 0 register (NVSCI0) stores the 32 LSB of the Censorship

Control Word of the device.

NVSCI0 is a non-volatile register located in Shadow sector. It is read during the reset phase of the Flash

module and the protection mechanisms are activated consequently.

The parts are delivered uncensored to the user. Delivery value: 0x55AA_55AA.

NOTE

This register is not implemented on the data Flash block.

Address:

0x20_3DDC Access: User read/write

0123456789101112131415

RPWD

PWD

Reset1100101011111110

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RPWD

PWD

Reset10111110111 1111

Figure 17-29. Non-Volatile Private Censorship Password 1 register (NVPWD1)

Table 17-32. NVPWD1 field descriptions

Field Description

0:31 PWD63–32: PassWorD 63–32

The PWD63–32 registers represent the 32 MSB of the Private Censorship Password.

Address:

0x20_3DE0 Access: User read/write

0123456789101112131415

RSC

Reset0101010110101010

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RCW

Reset0101010110101010

Figure 17-30. Non-Volatile System Censoring Information 0 register (NVSCI0)

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17.3.7.19 Non-Volatile System Censoring Information 1 register (NVSCI1)

The Non-Volatile System Censoring Information 1 register (NVSCI1) stores the 32 MSB of the

Censorship Control Word of the device.

NVSCI1 is a non-volatile register located in Shadow sector. It is read during the reset phase of the Flash

module and the protection mechanisms are activated consequently.

The parts are delivered uncensored to the user. Delivery value: 0x55AA_55AA.

NOTE

This register is not implemented on the data Flash block.

Table 17-33. NVSCI0 field descriptions

Field Description

SC[15:0]

0:15

Serial Censorship control word 15–0

These bits represent the 16 LSB of the Serial Censorship Control Word (SCCW).

If SC[15:0] = 0x55AA and NVSCI1 = NVSCI0, the Public Access is disabled.

If SC[15:0] 0x55AA or NVSCI1 NVSCI0, the Public Access is enabled.

CW[15:0]

16:31

Censorship control Word 15–0

These bits represent the 16 LSB of the Censorship Control Word (CCW).

If CW[15:0] = 0x55AA and NVSCI1 = NVSCI0, the Censored mode is disabled.

If CW[15:0] 0x55AA or NVSCI1 NVSCI0, the Censored mode is enabled.

Address:

0x20_3DE4 Access: User read/write

0123456789101112131415

RSC

Reset0101010110101010

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RCW

Reset0101010110101010

Figure 17-31. Non-Volatile System Censoring Information 1 register (NVSCI1)

Table 17-34. NVSCI1 field descriptions

Field Description

SC[32:16]

0:15

Serial Censorship control word 32–16

These bits represent the 16 MSB of the Serial Censorship Control Word (SCCW).

If SC[32:16] = 0x55AA and NVSCI1 = NVSCI0, the Public Access is disabled.

If SC[32:16]  0x55AA or NVSCI1 NVSCI0, the Public Access is enabled.

CW[32:16]

16:31

Censorship control Word 32–16

These bits represent the 16 MSB of the Censorship Control Word (CCW).

CW[32:16] = 0x55AA and NVSCI1 = NVSCI0, the Censored mode is disabled.

CW[32:16] 0x55AA or NVSCI1 NVSCI0, the Censored mode is enabled.

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17.3.7.20 Non-Volatile User Options register (NVUSRO)

The Non-Volatile User Options Register (NVUSRO) contains configuration information for the user

application.

NVUSRO is a 64-bit register, the 32 most significant bits of which (bits 63:32) are “don’t care” bits that

are eventually used to manage ECC codes.

NOTE

This register is not implemented on the data Flash block.

The Non-Volatile User Options Register (NVUSRO) contains configuration information for the user

application.

NVUSRO is a 64-bit register, the 32 most significant bits of which (bits 63:32) are “don’t care” bits that

are eventually used to manage ECC codes.

Address:

0x20_3E18 Access: User read/write

0123456789101112131415

RWAT

DOG

_EN

UO30

PA D 3

V5V

UO2

UO19 UO18 UO17 UO16

Resetxxxxxxxxxxxxxxxx

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

UO15 UO14 UO13 UO12 UO11 UO10 UO9 UO8 UO7 UO6 UO5 UO4 UO3 UO2 UO1 UO0

Resetxxxxxxxxxxxxxxxx

Figure 17-32. Non-Volatile User Options register (NVUSRO)

Table 17-35. NVUSRO field descriptions

Field Description

UO[28:0]

3:31

User Options 28–0

The UO[28:0] bits are reset based on the information stored in NVUSRO.

PA D 3 V 5 V

0 High Voltage supply is 5.0 V.

1 High Voltage supply is 3.3 V.

Default manufacturing value before Flash initialization is '1' (3.3 V), which should ensure correct

minimum slope for boundary scan.

UO[30]

User Option 30

The UO[30] bit is reset based on the information stored in NVUSRO.

WATCHDOG_EN

Watchdog Enable

0 Disable after reset.

1 Enable after reset.

Default manufacturing value before Flash initialization is '1'

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17.3.8 Code Flash programming considerations

17.3.8.1 Modify operation

All the modify operations of the Flash module are managed through the Flash user registers interface.

All the sectors of the Flash module belong to the same partition (Bank), therefore when a Modify operation

is active on some sectors, no read access is possible on any other sector (Read-While-Modify is not

supported).

During a Flash modify operation, any attempt to read any Flash location will output invalid data and the

MCR[RWE] bit will be automatically set. This means that the Flash block is not fetchable when a modify

operation is active and these commands must be executed from another memory (internal RAM or another

Flash block).

If a reset occurs during a modify operation, the operation is interrupted and the block is reset to read mode.

The data integrity of the Flash section where the modify operation has been terminated is not guaranteed.

The interrupted Flash modify operation must be repeated.

In general, each modify operation is started through a sequence of three steps:

1. The first instruction selects the desired operation by setting its corresponding selection bit in MCR

(MCR[PGM] or MCR[ERS]) or UT0 (UT0[MRE] or UT0[EIE]).

2. The second step defines the operands: the address and the data for programming or the sectors for

erase or margin read.

3. The third instruction starts the modify operation by setting MCR[EHV] or UT0[AIE].

Once selected, but not yet started, one operation can be canceled by resetting the operation selection bit.

A summary of the available Flash modify operations are shown in Table 17-36.

Once MCR[EHV] (or UT0[AIE]) is set, the operands cannot be modified until MCR[DONE] (or

UT0[AID]) is high.

In general, each modify operation is completed through a sequence of four steps:

1. Wait for operation completion: wait for bit MCR[DONE] (or UT0[AID]) to go high.

2. Check operation result: check bit MCR[PEG] (or compare UMISR0–4 with expected value).

3. Switch off FPEC by resetting MCR[EHV] (or UT0[AIE]).

Table 17-36. Flash modify operations

Operation Select bit Operands Start bit

Double word program MCR[PGM] Address and data by interlock writes MCR[EHV]

Sector erase MCR[ERS] LMS MCR[EHV]

Array integrity check None LMS UT0[AIE]

Margin read UT0[MRE] UT0[MRV] + LMS UT0[AIE]

ECC logic check UT0[EIE] UT0[DSI], UT1, UT2 UT0[AIE]

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4. Deselect current operation by clearing MCR[PGM] and MCR[ERS] (or UT0[MRE] and

UT0[EIE]).

If a modify operation is on-going in one of the Flash blocks, it is forbidden to start any other modify

operation on the other Flash block.

In the following sections, all the possible modify operations are described and some examples of the

sequences needed to activate them are presented.

17.3.8.1.1 Double word program

A Flash program sequence operates on any double word within the Flash core.

One or both words within a double word may be altered in a single program operation.

Whenever the Flash is programmed, ECC bits are also programmed (unless the selected address belongs

to a sector in which the ECC has been disabled in order to allow bit manipulation). ECC is handled on a

64-bit boundary. Thus, if only one word in any given 64-bit ECC segment is programmed, the adjoining

word (in that segment) should not be programmed since ECC calculation has already completed for that

64-bit segment. Attempts to program the adjoining word will probably result in an operation failure. It is

recommended that all programming operations be of 64 bits. The programming operation should

completely fill selected ECC segments within the double word.

Programming changes the value stored in an array bit from logic 1 to logic 0 only. Programming cannot

change a stored logic 0 to a logic 1.

Addresses in locked/disabled blocks cannot be programmed.

The user may program the values in any or all of 2 words of a double word with a single program sequence.

Double word-bound words have addresses that differ only in address bit 2.

The program operation consists of the following sequence of events:

1. Change the value in the MCR[PGM] bit from 0 to 1.

2. Ensure the block that contains the address to be programmed is unlocked.

a) Write the first address to be programmed with the program data.

b) The Flash module latches address bits (22:3) at this time.

c) The Flash module latches data written as well.

d) This write is referred to as a program data interlock write. An interlock write may be as large

as 64 bits, and as small as 32 bits (depending on the CPU bus).

3. If more than 1 word is to be programmed, write the additional address in the double word with data

to be programmed. This is referred to as a program data write.

The Flash module ignores address bits (22:3) for program data writes.

The eventual unwritten data word defaults to 0xFFFF_FFFF.

4. Set MCR[EHV] to 1 to start the internal program sequence, or skip to step 9 to terminate.

5. Wait until the MCR[DONE] bit goes high.

6. Confirm MCR[PEG] = 1.

7. Write a logic 0 to the MCR[EHV] bit.

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8. If more addresses are to be programmed, return to step 2.

9. Write a logic 0 to the MCR[PGM] bit to terminate the program operation.

A program operation may be initiated with the 0-to-1 transition of the MCR[PGM] bit or by clearing the

MCR[EHV] bit at the end of a previous program.

The first write after a program is initiated determines the page address to be programmed. This first write

is referred to as an interlock write. The interlock write determines whether the shadow, test, or normal

array space will be programmed by causing MCR[PEAS] to be set/cleared.

An interlock write must be performed before setting MCR[EHV]. The user may terminate a program

sequence by clearing MCR[PGM] prior to setting MCR[EHV].

After the interlock write, additional writes only affect the data to be programmed at the word location

determined by address bit 2. Unwritten locations default to a data value of 0xFFFF_FFFF. If multiple

writes are done to the same location, the data for the last write is used in programming.

While MCR[DONE] is low and MCR[EHV] is high, the user may clear MCR[EHV], resulting in a

program terminate. A program termination forces the module to step 8 of the program sequence.

A terminated program results in MCR[PEG] being cleared, indicating a failed operation. MCR[DONE]

must be checked to know when the terminating command has completed.

The data space being operated on before the termination will contain indeterminate data. This may be

recovered by repeating the same program instruction or executing an erase of the affected blocks.

Example 17-1. Double word program of data 0x55AA_55AA at address 0x00_AAA8 and data 0xAA55_AA55

at address 0x00_AAAC

MCR = 0x00000010; /* Set PGM in MCR: Select Operation */

(0x00AAA8) = 0x55AA55AA; /* Latch Address and 32 LSB data */

(0x00AAAC) = 0xAA55AA55; /* Latch 32 MSB data */

MCR = 0x00000011; /* Set EHV in MCR: Operation Start */

do /* Loop to wait for DONE=1 */

{ tmp = MCR; /* Read MCR */

} while ( !(tmp & 0x00000400) );

status = MCR & 0x00000200; /* Check PEG flag */

MCR = 0x00000010; /* Reset EHV in MCR: Operation End */

MCR = 0x00000000; /* Reset PGM in MCR: Deselect Operation */

17.3.8.1.2 Sector erase

Erase changes the value stored in all bits of the selected block(s) to logic 1.

An erase sequence operates on any combination of blocks (sectors) in the low or mid address space, or

the shadow block (if available). The test block cannot be erased.

The erase sequence is fully automated within the Flash. The user only needs to select the blocks to be

erased and initiate the erase sequence.

Locked/disabled blocks cannot be erased.

If multiple blocks are selected for erase during an erase sequence, no specific operation order must be

assumed.

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The Erase operation consists of the following sequence of events:

1. Change the value in the MCR[ERS] bit from 0 to 1.

2. Select the block(s) to be erased by writing 1s to the LMS register. If the shadow block is to be

erased, this step may be skipped, and LMS is ignored.

NOTE

Lock and Select are independent. If a block is selected and locked, no erase

will occur.

3. Write to any address in Flash. This is referred to as an erase interlock write.

4. Set MCR[EHV] to start the internal erase sequence, or skip to step 9 to terminate.

5. Wait until the MCR[DONE] bit goes high.

6. Confirm MCR[PEG] = 1.

7. Clear the MCR[EHV] bit.

8. If more blocks are to be erased, return to step 2.

9. Write a logic 0 to the MCR[ERS] bit to terminate the erase operation.

After setting MCR[ERS], one write, referred to as an interlock write, must be performed before

MCR[EHV] can be set to 1. Data words written during erase sequence interlock writes are ignored.

The user may terminate the erase sequence by clearing MCR[ERS] before setting MCR[EHV].

An erase operation may be terminated by clearing MCR[EHV], assuming MCR[DONE] is low,

MCR[EHV] is high, and MCR[ESUS] is low.

An erase termination forces the Module to step 8 of the erase sequence.

A terminated erase results in MCR[PEG] being cleared, indicating a failed operation. MCR[DONE] must

be checked to know when the terminating command has completed.

The block(s) being operated on before the termination contain indeterminate data. This may be recovered

by executing an erase on the affected blocks.

The user may not terminate an erase sequence while in erase suspend.

Example 17-2. Erase of sectors B0F1 and B0F2

MCR = 0x00000004; /* Set ERS in MCR: Select Operation */

LMS = 0x00000006; /* Set LSL2-1 in LMS: Select Sectors to erase */

(0x000000) = 0xFFFFFFFF; /* Latch a Flash Address with any data */

MCR = 0x00000005; /* Set EHV in MCR: Operation Start */

do /* Loop to wait for DONE=1 */

{ tmp = MCR; /* Read MCR */

} while ( !(tmp & 0x00000400) );

status = MCR & 0x00000200; /* Check PEG flag */

MCR = 0x00000004; /* Reset EHV in MCR: Operation End */

MCR = 0x00000000; /* Reset ERS in MCR: Deselect Operation */

The erase sequence may be suspended to allow read access to the Flash core.

It is not possible to program or to erase during an erase suspend.

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During erase suspend, all reads to blocks targeted for erase return indeterminate data.

An erase suspend can be initiated by changing the value of the MCR[ESUS] bit from 0 to 1. MCR[ESUS]

can be set to 1 at any time when MCR[ERS] and MCR[EHV] are high and MCR[PGM] is low. A 0-to-1

transition of MCR[ESUS] causes the module to start the sequence that places it in erase suspend.

The user must wait until MCR[DONE] = 1 before the Module is suspended and further actions are

attempted. MCR[DONE] will go high no more than tESUS after MCR[ESUS] is set to 1.

Once suspended, the array may be read. Flash core reads while MCR[ESUS] = 1 from the block(s) being

erased return indeterminate data.

Example 17-3. Sector Erase Suspend

MCR = 0x00000007; /* Set ESUS in MCR: Erase Suspend */

do /* Loop to wait for DONE=1 */

{ tmp = MCR; /* Read MCR */

} while ( !(tmp & 0x00000400) );

Notice that there is no need to clear MCR[EHV] and MCR[ERS] in order to perform reads during erase

suspend.

The Erase sequence is resumed by writing a logic 0 to MCR[ESUS].

MCR[EHV] must be set to 1 before MCR[ESUS] can be cleared to resume the operation.

The Module continues the erase sequence from one of a set of predefined points. This may extend the time

required for the erase operation.

Example 17-4. Sector Erase Resume

MCR = 0x00000005; /* Reset ESUS in MCR: Erase Resume */

17.3.8.1.3 User Test mode

User Test mode is a customer-accessible mode that can be used to perform specific tests to check the

integrity of the Flash module. Three kinds of test can be performed:

• Array integrity self-check

• Margin mode read

• ECC logic check

The User Test mode is equivalent to a Modify operation. Read accesses attempted by the user during User

Test mode generate a Read-While-Write Error (the MCR[RWE] bit is set).

User Test operations are not allowed on the Test and Shadow blocks.

17.3.8.1.3.1 Array integrity self check

Array integrity is checked using a predefined address sequence (proprietary), and this operation is

executed on selected and unlocked blocks. Once the operation is completed, the results of the reads can be

checked by reading the MISR value (stored in UMISR0–4), to determine if an incorrect read, or ECC

detection was noted.

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The internal MISR calculator is a 32-bit register.

The 128-bit data, the 16-bit ECC data, and the single and double ECC errors of the two double words are

therefore captured by the MISR through five different read accesses at the same location.

The whole check is done through five complete scans of the memory address space:

1. The first pass scans only bits 31:0 of each page.

2. The second pass scans only bits 63:32 of each page.

3. The third pass scans only bits 95:64 of each page.

4. The fourth pass scans only bits 127:96 of each page.

5. The fifth pass scans only the ECC bits (8 + 8) and the single and double ECC errors (2 + 2) of both

double words of each page.

The 128-bit data and the 16-bit ECC data are sampled before the eventual ECC correction, while the single

and double error flags are sampled after the ECC evaluation.

Only data from existing and unlocked locations are captured by the MISR.

The MISR can be seeded to any value by writing the UMISR0–4 registers.

The Array Integrity Self Check consists of the following sequence of events:

1. Set UT0[UTE] by writing the related password in UT0.

2. Select the block(s) to be checked by writing 1s to the LMS register.

Note that Lock and Select are independent. If a block is selected and locked,

no Array Integrity Check will occur.

3. Set eventually UT0[AIS] bit for a sequential addressing only.

4. Write a logic 1 to the UT0[AIE] bit to start the Array Integrity Check.

5. Wait until the UT0[AID] bit is set.

6. Compare the contents of the UMISR0–4 registers with the expected results.

7. Write a logic 0 to the UT0[AIE] bit.

8. If more blocks are to be checked, return to step 2.

It is recommended to leave UT0[AIS] at 0 and use the proprietary address sequence that checks the read

path more fully, although this sequence takes more time.

NOTE

During the execution of the Array Integrity Check operation it is forbidden

to modify the content of Block Select (LMS) and Lock (LML, SLL)

registers, otherwise the MISR value can vary in an unpredictable way.

While UT0[AID] is low and UT0[AIE] is high, the user may clear UT0[AIE], resulting in an Array

Integrity Check termination.

UT0[AID] must be checked to know when the terminating command has completed.

Example 17-5. Array Integrity Check of sectors B0F1 and B0F2

UT0 = 0xF9F99999; /* Set UTE in UT0: Enable User Test */

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LMS = 0x00000006; /* Set LSL2-1 in LMS: Select Sectors */

UT0 = 0x80000002; /* Set AIE in UT0: Operation Start */

do /* Loop to wait for AID=1 */

{ tmp = UT0; /* Read UT0 */

} while ( !(tmp & 0x00000001) );

data0 = UMISR0; /* Read UMISR0 content*/

data1 = UMISR1; /* Read UMISR1 content*/

data2 = UMISR2; /* Read UMISR2 content*/

data3 = UMISR3; /* Read UMISR3 content*/

data4 = UMISR4; /* Read UMISR4 content*/

UT0 = 0x00000000; /* Reset UTE and AIE in UT0: Operation End */

17.3.8.1.3.2 Margin read

The Margin read procedure (either Margin 0 or Margin 1) can be run on unlocked blocks in order to

unbalance the Sense Amplifiers with respect to standard read conditions so that all the read accesses reduce

the margin vs. 0 (UT0[MRV] = 0) or vs. 1 (UT0[MRV] = 1). Locked sectors are ignored by MISR

calculation and ECC flagging.

The results of the margin reads can be checked by comparing the checksum value in UMISR[0:4].

Since Margin reads are done at voltages that differ than the normal read voltage, the lifetime expectancy

of the Flash macrocell is impacted by the execution of Margin reads.

Repeated Margin reads will result in degradation of the Flash array, and will shorten the expected lifetime

experienced at normal read levels.

For these reasons, Margin reads are allowed only at the factory. Margin reads are forbidden for use by user

applications.

In any case the charge losses detected through the Margin mode cannot be considered failures of the device

and no failure analysis will be opened on them.

The Margin Read Setup operation consists of the following sequence of events:

1. Set UTE in UT0 by writing the related password in UT0.

2. Select the block(s) to be checked by writing 1s to the LMS register.

Note that Lock and Select are independent. If a block is selected and locked,

no Array Integrity Check will occur.

3. Set UT0[AIS] bit for a sequential addressing only.

4. Change the value in the UT0[MRE] bit from 0 to 1.

5. Select the Margin level: UT0[MRV] = 0 for 0s margin, UT0[MRV] = 1 for 1s margin.

6. Write a logic 1 to the UT0[AIE] bit to start the Margin Read.

7. Wait until the UT0[AID] bit goes high.

8. Compare UMISR[0:4] content with the expected result.

9. Write a logic 0 to the UT0[AIE], UT0[MRE] and UT0[MRV] bits.

10. If more blocks are to be checked, return to step 2.

It is mandatory to leave UT0[AIS] at 1 and use the linear address sequence (that also takes less time).

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During the execution of the Margin Mode operation it is forbidden to modify the content of Block Select

(LMS) and Lock (LML, SLL) registers, otherwise the MISR value can vary in an unpredictable way.

The read accesses will be done with the addition of a proper number of wait states to guarantee the

correctness of the result.

While UT0[AID] is low and UT0[AIE] is high, the user may clear AIE, resulting in a Array Integrity

Check termination.

UT0[AID] must be checked to know when the terminating command has completed.

Example 17-6. Margin Read Check versus 1s

UT0 = 0xF9F99999; /* Set UTE in UT0: Enable User Test */

LMS = 0x00000006; /* Set LSL2-1 in LMS: Select Sectors */

UT0 = 0x80000004; /* Set AIS in UT0: Select Operation */

UT0 = 0x80000024; /* Set MRE in UT0: Select Operation */

UT0 = 0x80000034; /* Set MRV in UT0: Select Margin versus 1’s */

UT0 = 0x80000036; /* Set AIE in UT0: Operation Start */

do /* Loop to wait for AID=1 */

{ tmp = UT0; /* Read UT0 */

} while ( !(tmp & 0x00000001) );

data0 = UMISR0; /* Read UMISR0 content*/

data1 = UMISR1; /* Read UMISR1 content*/

data2 = UMISR2; /* Read UMISR2 content*/

data3 = UMISR3; /* Read UMISR3 content*/

data4 = UMISR4; /* Read UMISR4 content*/

UT0 = 0x80000034; /* Reset AIE in UT0: Operation End */

UT0 = 0x00000000; /* Reset UTE, MRE, MRV, AIS in UT0: Deselect Op. */

17.3.8.1.3.3 ECC logic check

ECC logic can be checked by forcing the input of ECC logic: The 64 bits of data and the 8 bits of ECC

syndrome can be individually forced and they will drive simultaneously at the same value the ECC logic

of the whole page (2 double words).

The results of the ECC Logic Check can be verified by reading the MISR value.

The ECC Logic Check operation consists of the following sequence of events:

1. Set UT0[UTE] by writing the related password in UT0.

2. Write the double word input value to UT1[DAI31–0] and UT2[DAI[63–32].

3. Write the Syndrome Input value to UT0[DSI7–0].

4. Select the ECC Logic Check: write a logic 1 to the UT0[EIE] bit.

5. Write a logic 1 to the UT0[AIE] bit to start the ECC Logic Check.

6. Wait until the UT0[AID] bit goes high.

7. Compare the contents of the UMISR0–4 registers with the expected results.

8. Write a logic 0 to the UT0[AIE] bit.

Notice that when UT0[AID] = 0, the UMISR0–4 and UT1–2 registers and the UT0[MRE], UT0[MRV],

UT0[EIE], UT0[AIS], and UT0[DSI7–0] bits are not accessible. Reads return indeterminate data; writes

have no effect.

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Example 17-7. ECC logic check

UT0 = 0xF9F99999; /* Set UTE in UT0: Enable User Test */

UT1 = 0x55555555; /* Set DAI31-0 in UT1: Even Word Input Data */

UT2 = 0xAAAAAAAA; /* Set DAI63-32 in UT2: Odd Word Input Data */

UT0 = 0x80FF0000; /* Set DSI7-0 in UT0: Syndrome Input Data */

UT0 = 0x80FF0008; /* Set EIE in UT0: Select ECC Logic Check */

UT0 = 0x80FF000A; /* Set AIE in UT0: Operation Start */

do /* Loop to wait for AID=1 */

{ tmp = UT0; /* Read UT0 */

} while ( !(tmp & 0x00000001) );

data0 = UMISR0; /* Read UMISR0 content (expected 0x55555555) */

data1 = UMISR1; /* Read UMISR1 content (expected 0xAAAAAAAA) */

data2 = UMISR2; /* Read UMISR2 content (expected 0x55555555) */

data3 = UMISR3; /* Read UMISR3 content (expected 0xAAAAAAAA) */

data4 = UMISR4; /* Read UMISR4 content (expected 0x00FF00FF) */

UT0 = 0x00000000; /* Reset UTE, AIE and EIE in UT0: Operation End */

17.3.8.2 Error Correction Code (ECC)

The Flash macrocell provides a method to improve the reliability of the data stored in Flash: the usage of

an Error Correction Code. The word size is fixed at 64 bits.

Each double word of 64 bits has an associated 8 ECC bits that are programmed in such a way to guarantee

a Single Error Correction and a Double Error Detection (SEC-DED).

ECC circuitry provides correction of single bit faults and is used to achieve automotive reliability targets.

Some units will experience single bit corrections throughout the life of the product with no impact on

product reliability.

17.3.8.2.1 ECC algorithms

The Flash macrocell supports the ECC algorithm “All 1s No Error”.

17.3.8.2.2 All 1s No Error

The All 1s No Error algorithm detects as valid any double word read on a just erased sector (all the 72 bits

are 1s).

This option allows performing a Blank Check after a Sector Erase operation.

17.3.8.3 EEPROM emulation

The chosen ECC algorithm allows some bit manipulations so that a Double Word can be rewritten several

times without needing an erase of the sector. This allows to use a Double Word to store flags useful for the

EEPROM emulation.

As an example the chosen ECC algorithm allows to start from an All ‘1’s Double Word value and rewrite

whichever of its four 16-bit Half-Words to an All ‘0’s content by keeping the same ECC value.

Table 17-37 shows a set of Double Words sharing the same ECC value.

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When some Flash sectors are used to perform an EEPROM emulation, it is recomended for safety reasons

to reserve at least three sectors for this purpose.

17.3.8.4 Protection strategy

Two kinds of protection are available: Modify Protection to avoid unwanted program/erase in Flash

sectors, and Censored mode to avoid piracy.

17.3.8.4.1 Modify protection

The Flash modify protection information is stored in non-volatile Flash cells located in the TestFlash. This

information is read once during the Flash initialization phase following the exit from reset and they are

stored in Volatile registers that act as actuators.

The reset state of all the volatile modify protection registers is the protected state.

All the non-volatile modify protection registers can be programmed through a normal double word

program operation at the related locations in TestFlash.

The non-volatile modify protection registers cannot be erased.

• The non-volatile modify protection registers are physically located in TestFlash. Their bits can be

programmed to 0 only once, after which they cannot be restored to 1.

• The volatile modify protection registers are read/write registers containing bits that can be written

at 0 or 1 by the user application.

Table 17-37. Bits manipulation: double words with the same ECC value

Double word ECC value – All 1s No Error

0xFFFF_FFFF_FFFF_FFFF 0xFF

0xFFFF_FFFF_FFFF_0000 0xFF

0xFFFF_FFFF_0000_FFFF 0xFF

0xFFFF_0000_FFFF_FFFF 0xFF

0x0000_FFFF_FFFF_FFFF 0xFF

0xFFFF_FFFF_0000_0000 0xFF

0xFFFF_0000_FFFF_0000 0xFF

0x0000_FFFF_FFFF_0000 0xFF

0xFFFF_0000_0000_FFFF 0xFF

0x0000_FFFF_0000_FFFF 0xFF

0x0000_0000_FFFF_FFFF 0xFF

0xFFFF_0000_0000_0000 0xFF

0x0000_FFFF_0000_0000 0xFF

0x0000_0000_0000_0000 0xFF

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A software mechanism is provided to independently lock/unlock each Low or Mid Address Space block

against program and erase.

Software locking is done through the LML (Low/Mid Address Space Block Lock Register) register.

An alternate means to enable software locking for blocks of Low Address Space only is through the SLL

(Secondary Low/Mid Address Space Block Lock Register).

All these registers have a non-volatile image stored in TestFlash (NVLML, NVSLL), so that the locking

information is kept on reset.

On delivery the TestFlash non-volatile image is at all 1s, meaning all sectors are locked.

By programming the non-volatile locations in TestFlash, the selected sectors can be unlocked.

Because the TestFlash is one-time programmable (that is, not erasable), once the sectors have been

unlocked, they cannot be locked again.

Of course, on the contrary, all the volatile registers can be written at 0 or 1 at any time, therefore the user

application can lock and unlock sectors when desired.

17.3.8.4.2 Censored mode

The Censored mode information is stored in non-volatile Flash cells located in the Shadow Sector. This

information is read once during the Flash initialization phase following the exit from Reset and they are

stored in Volatile registers that act as actuators.

The reset state of all the volatile censored mode registers is the protected state.

All the non-volatile censored mode registers can be programmed through a normal double word program

operation at the related locations in the Shadow Sector.

The non-volatile censored mode registers can be erased by erasing the Shadow Sector.

• The non-volatile censored mode registers are physically located in the Shadow Sector their bits can

be programmed to 0 and eventually restored to 1 by erasing the Shadow Sector.

• The volatile censored mode registers are registers not accessible by the user application.

The Flash block provides two levels of protection against piracy:

• If bits NVSCI0[CW[15:0]] are programmed to 0x55AA and NVSC1 = NVSCI0, Censored mode

is disabled. All other possible values enable Censored mode.

• If bits NVSCI0[SC[15:0]] are programmed to 0x55AA and NVSC1 = NVSCI0, Public Access is

disabled. All other possible values enable Public Access.

The parts are delivered to the user with Censored mode and public access disabled.

The chosen Flash ECC algorithm allows to modify the censorship status without erasing the Shadow

sector, as shown in Table 17-38.

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Table 17-38. Bits manipulation: censorship management

Censored mode Public access NVSCI0 NVSCI1

Enabled Enabled 0xFFFF_FFFF 0xFFFF_FFFF

Disabled Enabled 0xFFFF_55AA 0xFFFF_55AA

Enabled Disabled 0x55AA_FFFF 0x55AA_FFFF

Disabled Disabled 0x55AA_55AA 0x55AA_55AA

Enabled Disabled 0x55AA_0000 0x55AA_0000

Disabled Enabled 0x0000_55AA 0x0000_55AA

Enabled Enabled 0x0000_0000 0x0000_0000

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Chapter 18 Enhanced Direct Memory Access (eDMA)

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Chapter 18

Enhanced Direct Memory Access (eDMA)

18.1 Introduction

This chapter describes the enhanced Direct Memory Access (eDMA) Controller, a second-generation

module capable of performing complex data transfers with minimal intervention from a host processor.

18.2 Overview

The enhanced direct memory access (eDMA) controller hardware microarchitecture includes a DMA

engine that performs source and destination address calculations, and the actual data movement

operations, along with SRAM-based local memory containing the transfer control descriptors (TCD) for

the channels.

Figure 18-1 is a block diagram of the eDMA module.

Figure 18-1. eDMA block diagram

Slave Interface

eDMA

eDMA done

System Bus

Data path Control

Address

Program model/

Slave write data

Slave write address

Bus write data

Slave read data

Bus address

eDMA Engine

TCD0

TCDn–1*

eDMA peripheral

Bus read data

channel arbitration

request

path

SRAM

Transfer Control Descriptor

(TCD)

SRAM

*n= 16 channels

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18.3 Features

The eDMA is a highly programmable data transfer engine, which has been optimized to minimize the

required intervention from the host processor. It is intended for use in applications where the data size to

be transferred is statically known, and is not defined within the data packet itself. The eDMA module

features:

• All data movement via dual-address transfers: read from source, write to destination

• Programmable source, destination addresses, transfer size, plus support for enhanced addressing

modes

• 16-channel implementation performs complex data transfers with minimal intervention from a host

processor

— 32 bytes of data registers, used as temporary storage to support burst transfers

(refer to SSIZE bit)

— Connections to the crossbar switch for bus mastering the data movement

• Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations

— 32-byte TCD per channel stored in local memory

— An inner data transfer loop defined by a minor byte transfer count

— An outer data transfer loop defined by a major iteration count

• Channel activation via one of three methods:

— Explicit software initiation

— Initiation via a channel-to-channel linking mechanism for continual transfers

— Peripheral-paced hardware requests (one per channel)

NOTE

For all three methods, one activation per execution of the minor loop is

required.

• Support for fixed-priority and round-robin channel arbitration

• Channel completion reported via optional interrupt requests

— One interrupt per channel, optionally asserted at completion of major iteration count

— Error terminations are enabled per channel, and logically summed together to form a single

error interrupt.

• Support for scatter/gather DMA processing

• Any channel can be programmed so that it can be suspended by a higher priority channel’s

activation, before completion of a minor loop.

Throughout this chapter, n is used to reference the channel number. Additionally, data sizes are defined as

byte (8-bit), halfword (16-bit), word (32-bit) and doubleword (64-bit).

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18.4 Modes of operation

18.4.1 Normal mode

In normal mode, the eDMA transfers data between a source and a destination. The source and destination

can be a memory block or an I/O block capable of operation with the eDMA.

18.4.2 Debug mode

If enabled by EDMA_CR[EDBG] and the CPU enters debug mode, the eDMA does not grant a service

request when the debug input signal is asserted. If the signal asserts during a data block transfer as

described by a minor loop in the current active channel’s TCD, the eDMA continues the operation until

the minor loop completes.

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18.5 Memory map and register definition

18.5.1 Memory map

The eDMA programming model is partitioned into two regions:

Region 1 defines control registers; Region 2 defines the local transfer control for the descriptor memory.

Table 18-1 is a 32-bit view of the eDMA memory map.

Table 18-1. eDMA memory map

Offset from

EDMA_BASE

(0xFFF4_4000)

0x0000 EDMA_CR—Control Register on page 387

0x0004 EDMA_ESR—eDMA Error

Status Register

on page 387

0x0008 Reserved

0x000C EDMA_ERQL—eDMA Enable

Request Register

on page 390

0x0010 Reserved

0x0014 EDMA_EEIRL—eDMA Enable

Error Interrupt Register

on page 391

0x0018 EDMA_SERQR—eDMA Set

Enable Request Register

on page 392

0x0019 EDMA_CERQR—eDMA Clear

Enable Request Register

on page 392

0x001A EDMA_SEEI—eDMA Set

Enable Error Interrupt Register

on page 393

0x001B EDMA_CEEI—eDMA Clear

Enable Error Interrupt Register

on page 393

0x001C EDMA_CIRQR—eDMA Clear

Interrupt Request Register

on page 394

0x001D EDMA_CER—eDMA Clear

Error Register

on page 395

0x001E EDMA_SSBR—eDMA Set

START Bit Register

on page 395

0x001F EDMA_CDSBR—eDMA Clear

DONE Status Register

on page 396

0x0020 Reserved

0x0024 EDMA_IRQRL—eDMA Interrupt

Request Register

on page 396

0x0028 Reserved

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0x002C EDMA_ERL—eDMA Error

on page 397

0x0030 Reserved

0x0034 EDMA_HRSL—eDMA

Hardware Request Status

on page 398

0x0038–0x00FF Reserved

0x0100 EDMA_CPR0—eDMA Channel

0 Priority Register

on page 399

0x0101 EDMA_CPR1—eDMA Channel

1 Priority Register

on page 399

0x0102 EDMA_CPR2—eDMA Channel

2 Priority Register

on page 399

0x0103 EDMA_CPR3—eDMA Channel

3 Priority Register

on page 399

0x0104 EDMA_CPR4—eDMA Channel

4 Priority Register

on page 399

0x0105 EDMA_CPR5—eDMA Channel

5 Priority Register

on page 399

0x0106 EDMA_CPR6—eDMA Channel

6 Priority Register

on page 399

0x0107 EDMA_CPR7—eDMA Channel

7 Priority Register

on page 399

0x0108 EDMA_CPR8—eDMA Channel

8 Priority Register

on page 399

0x0109 EDMA_CPR9—eDMA Channel

9 Priority Register

on page 399

0x010A EDMA_CPR10—eDMA

Channel 10 Priority Register

on page 399

0x010B EDMA_CPR11—eDMA

Channel 11 Priority Register

on page 399

0x010C EDMA_CPR12—eDMA

Channel 12 Priority Register

on page 399

0x010D EDMA_CPR13—eDMA

Channel 13 Priority Register

on page 399

0x010E EDMA_CPR14—eDMA

Channel 14 Priority Register

on page 399

0x010F EDMA_CPR15—eDMA

Channel 15 Priority Register

on page 399

Table 18-1. eDMA memory map (continued)

Offset from

EDMA_BASE

(0xFFF4_4000)

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0x0110–0x0FFF Reserved

0x1000 TCD00—Transfer Control

Descriptor 0

on page 400

0x1020 TCD01—Transfer Control

Descriptor 1

on page 400

0x1040 TCD02—Transfer Control

Descriptor 2

on page 400

0x1060 TCD03—Transfer Control

Descriptor 3

on page 400

0x1080 TCD04—Transfer Control

Descriptor 4

on page 400

0x10A0 TCD05—Transfer Control

Descriptor 5

on page 400

0x10C0 TCD06—Transfer Control

Descriptor 6

on page 400

0x10E0 TCD07—Transfer Control

Descriptor 7

on page 400

0x1100 TCD08—Transfer Control

Descriptor 8

on page 400

0x1120 TCD09—Transfer Control

Descriptor 9

on page 400

0x1140 TCD10—Transfer Control

Descriptor 10

on page 400

0x1160 TCD11—Transfer Control

Descriptor 11

on page 400

0x1180 TCD12—Transfer Control

Descriptor 12

on page 400

0x11A0 TCD13—Transfer Control

Descriptor 13

on page 400

0x11C0 TCD14—Transfer Control

Descriptor 14

on page 400

0x11E0 TCD15—Transfer Control

Descriptor 15

on page 400

0x1200

–0x3FFF

Reserved

Table 18-1. eDMA memory map (continued)

Offset from

EDMA_BASE

(0xFFF4_4000)

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18.5.2 Register descriptions

Read operations on reserved bits in a register return undefined data. Do not write operations to reserved

bits. Writing to reserved bits in a register can generate errors. The maximum register bit-width for this

device is 16 bits wide.

18.5.2.1 eDMA Control Register (EDMA_CR)

The 32-bit EDMA_CR defines the basic operating configuration of the eDMA.

The eDMA arbitrates channel service requests in one group of 16 channels.

Arbitration can be configured to use either fixed-priority or round-robin. In fixed-priority arbitration, the

highest priority channel requesting service is selected to execute. The priorities are assigned by the channel

priority registers. In round-robin arbitration mode, the channel priorities are ignored and the channels are

cycled through, from channel 15 down to channel 0, without regard to priority.

Refer to Section 18.5.2.16, “eDMA Channel n Priority Registers (EDMA_CPRn).

Address:

Base + 0x0000 Access: User read/write

0123456789101112131415

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000000000000

ERCA

EDBG

Reset0000000000000000

Figure 18-2. eDMA Control Register (EDMA_CR)

Table 18-2. EDMA_CR field descriptions

Field Description

0-28 Reserved.

ERCA

Enable round-robin channel arbitration.

0 Fixed-priority arbitration is used for channel selection within each group.

1 Round-robin arbitration is used for channel selection within each group.

EDBG

Enable debug.

0 The assertion of the system debug control input is ignored.

1 The assertion of the system debug control input causes the eDMA to stall the start of a new

channel. Executing channels are allowed to complete. Channel execution resumes when either

the system debug control input is negated or the EDBG bit is cleared.

31 Reserved.

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18.5.2.2 eDMA Error Status Register (EDMA_ESR)

The EDMA_ESR provides information concerning the last recorded channel error. Channel errors can be

caused by a configuration error (an illegal setting in the transfer control descriptor or an illegal priority

A configuration error is caused when the starting source or destination address, source or destination

offsets, minor loop byte count, and the transfer size represent an inconsistent state. The addresses and

offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a

multiple of the source and destination transfer sizes. All source reads and destination writes must be

configured to the natural boundary of the programmed transfer size respectively.

In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal within

a group, or any group priority levels being equal among the groups. For either type of priority

configuration error, the ERRCHN field is undefined. All channel priority levels within a group must be

unique and all group priority levels among the groups must be unique when fixed arbitration mode is

enabled.

If a scatter/gather operation is enabled upon channel completion, a configuration error is reported if the

scatter/gather address (DLAST_SGA) is not aligned on a 32-byte boundary. If minor loop channel linking

is enabled upon channel completion, a configuration error is reported when the link is attempted if the

TCD.CITER.E_LINK bit does not equal the TCD.BITER.E_LINK bit. All configuration error conditions

except scatter/gather and minor loop link error are reported as the channel is activated and assert an error

interrupt request if enabled. When properly enabled, a scatter/gather configuration error is reported when

the scatter/gather operation begins at major loop completion. A minor loop channel link configuration

error is reported when the link operation is serviced at minor loop completion.

If a system bus read or write is terminated with an error, the data transfer is immediately stopped and the

appropriate bus error flag is set. In this case, the state of the channel’s transfer control descriptor is updated

by the eDMA engine with the current source address, destination address, and minor loop byte count at the

point of the fault. If a bus error occurs on the last read prior to beginning the write sequence, the write

executes using the data captured during the bus error. If a bus error occurs on the last write prior to

switching to the next read sequence, the read sequence executes before the channel is terminated due to

the destination bus error.

The occurrence of any type of error causes the eDMA engine to stop the active channel, and the appropriate

channel bit in the eDMA error register to be asserted. At the same time, the details of the error condition

are loaded into the EDMA_ESR. The major loop complete indicators, setting the transfer control

descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is

detected. After the error status has been updated, the eDMA engine continues to operate by servicing the

next appropriate channel. A channel that experiences an error condition is not automatically disabled. If a

channel is terminated by an error and then issues another service request before the error is fixed, that

channel executes and terminates with the same error condition.

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Address:

Base + 0x0004 Access: User read-only

0123456789101112131415

RVLD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R GPE CPE ERRCHN SAE SOE DAE DOE NCE SGE SBE DBE

Reset0000000000000000

Figure 18-3. eDMA Error Status Register (EDMA_ESR)

Table 18-3. EDMA_ESR field descriptions

Field Description

VLD

Logical OR of all EDMA_ERH and EDMA_ERL status bits.

0 No EDMA_ER bits are set.

1 At least one EDMA_ER bit is set indicating a valid error exists that has not been cleared.

1–15 Reserved.

GPE

Group priority error.

0 No group priority error.

1 The last recorded error was a configuration error among the group priorities indicating not all group

priorities are unique.

CPE

Channel priority error.

0 No channel priority error.

1 The last recorded error was a configuration error in the channel priorities within a group, indicating

not all channel priorities within a group are unique.

18–23

ERRCHN[0:5]

Error channel number. Channel number of the last recorded error (excluding GPE and CPE errors).

Note: Do not rely on the number in the ERRCHN field for group and channel priority errors. Group

and channel priority errors need to be resolved by inspection. The application code must

interrogate the priority registers to find groups or channels with duplicate priority level.

SAE

Source address error.

0 No source address configuration error.

1 The last recorded error was a configuration error detected in the TCD.SADDR field, indicating

TCD.SADDR is inconsistent with TCD.SSIZE.

SOE

Source offset error.

0 No source offset configuration error.

1 The last recorded error was a configuration error detected in the TCD.SOFF field, indicating

TCD.SOFF is inconsistent with TCD.SSIZE.

DAE

Destination address error.

0 No destination address configuration error.

1 The last recorded error was a configuration error detected in the TCD.DADDR field, indicating

TCD.DADDR is inconsistent with TCD.DSIZE.

DOE

Destination offset error.

0 No destination offset configuration error.

1 The last recorded error was a configuration error detected in the TCD.DOFF field, indicating

TCD.DOFF is inconsistent with TCD.DSIZE.

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18.5.2.3 eDMA Enable Request Register (EDMA_ERQRL)

The EDMA_ERQRL provides a bit map for the 16 implemented channels to enable the request signal for

each channel. EDMA_ERQRL maps to channels 15–0.

The state of any given channel enable is directly affected by writes to this register; the state is also affected

by writes to the EDMA_SERQR and EDMA_CERQR. The EDMA_CERQR and EDMA_SERQR are

provided so that the request enable for a single channel can easily be modified without the need to perform

a read-modify-write sequence to the EDMA_ERQRL.

Both the DMA request input signal and this enable request flag must be asserted before a channel’s

hardware service request is accepted. The state of the eDMA enable request flag does not affect a channel

service request made explicitly through software or a linked channel request.

NCE

NBYTES/CITER configuration error.

0 No NBYTES/CITER configuration error.

1 The last recorded error was a configuration error detected in the TCD.NBYTES or TCD.CITER

fields, indicating the following conditions exist:

• TCD.NBYTES is not a multiple of TCD.SSIZE and TCD.DSIZE, or

• TCD.CITER is equal to zero, or

• TCD.CITER.E_LINK is not equal to TCD.BITER.E_LINK.

SGE

Scatter/gather configuration error.

0 No scatter/gather configuration error.

1 The last recorded error was a configuration error detected in the TCD.DLAST_SGA field,

indicating TCD.DLAST_SGA is not on a 32-byte boundary. This field is checked at the beginning

of a scatter/gather operation after major loop completion if TCD.E_SG is enabled.

SBE

Source bus error.

0 No source bus error.

1 The last recorded error was a bus error on a source read.

DBE

Destination bus error.

0 No destination bus error.

1 The last recorded error was a bus error on a destination write.

Address:

Base + 0x000C Access: User read/write

0123456789101112131415

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RERQ

ERQ

Reset0000000000000000

Figure 18-4. eDMA Enable Request Low Register (EDMA_ERQRL)

Table 18-3. EDMA_ESR field descriptions (continued)

Field Description

Chapter 18 Enhanced Direct Memory Access (eDMA)

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As a given channel completes the processing of its major iteration count, there is a flag in the transfer

control descriptor that can affect the ending state of the EDMA_ERQR bit for that channel. If the

TCD.D_REQ bit is set, then the corresponding EDMA_ERQR bit is cleared after the major loop is

complete, disabling the DMA hardware request. Otherwise if the D_REQ bit is cleared, the state of the

EDMA_ERQR bit is unaffected.

18.5.2.4 eDMA Enable Error Interrupt Register (EDMA_EEIRL)

The EDMA_EEIRL provides a bit map for the 16 channels to enable the error interrupt signal for each

channel. EDMA_EEIRL maps to channels 15-0.

The state of any given channel’s error interrupt enable is directly affected by writes to these registers; it is

also affected by writes to the EDMA_SEEIR and EDMA_CEEIR. The EDMA_SEEIR and

EDMA_CEEIR are provided so that the error interrupt enable for a single channel can easily be modified

without the need to perform a read-modify-write sequence to the EDMA_EEIRL.

Both the DMA error indicator and this error interrupt enable flag must be asserted before an error interrupt

request for a given channel is asserted.

Table 18-4. EDMA_ERQRL field descriptions

Field Description

16–31

ERQn

Enable DMA hardware service request n.

0 The DMA request signal for channel n is disabled.

1 The DMA request signal for channel n is enabled.

Address:

Base + 0x0014 Access: User read/write

0123456789101112131415

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

EEI15 EEI14 EEI13 EEI12 EEI11 EEI10 EEI09 EEI08 EEI07 EEI06 EEI05 EEI04 EEI03 EEI02 EEI01 EEI00

Reset0000000000000000

Figure 18-5. eDMA Enable Error Interrupt Low Register (EDMA_EEIRL)

Table 18-5. EDMA_EEIRL field descriptions

Field Description

16–31

EEIn

Enable error interrupt n.

0 The error signal for channel n does not generate an error interrupt.

1 The assertion of the error signal for channel n generate an error interrupt request.

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18.5.2.5 eDMA Set Enable Request Register (EDMA_SERQR)

The EDMA_SERQR provides a simple memory-mapped mechanism to set a given bit in the

EDMA_ERQRL to enable the DMA request for a given channel. The data value on a register write causes

the corresponding bit in the EDMA_ERQRL to be set. Setting bit 1 (SERQn) provides a global set

function, forcing the entire contents of EDMA_ERQRL to be asserted. Reads of this register return all

zeroes.

18.5.2.6 eDMA Clear Enable Request Register (EDMA_CERQR)

The EDMA_CERQR provides a simple memory-mapped mechanism to clear a given bit in the

EDMA_ERQRL to disable the DMA request for a given channel. The data value on a register write causes

the corresponding bit in the EDMA_ERQRL to be cleared. Setting bit 1 (CERQn) provides a global clear

function, forcing the entire contents of the EDMA_ERQRL to be zeroed, disabling all DMA request

inputs. Reads of this register return all zeroes.

Address: Base + 0x0018 Access: User write-only

01234567

R00000000

WSERQ[0:6]

Reset00000000

Figure 18-6. eDMA Set Enable Request Register (EDMA_SERQR)

Table 18-6. EDMA_SERQR field descriptions

Field Descriptions

0 Reserved.

1–7

SERQ[0:6]

Set enable request.

0–15 Set corresponding bit in EDMA_ERQRL

16–63Reserved

64–127Set all bits in EDMA_ERQRL

Note: Bit 2 (SERQ1) is not used.

Address: Base + 0x0019 Access: User write-only

01234567

R00000000

WCERQ[0:6]

Reset00000000

Figure 18-7. eDMA Clear Enable Request Register (EDMA_CERQR)

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18.5.2.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)

The EDMA_SEEIR provides a simple memory-mapped mechanism to set a given bit in the

EDMA_EEIRL to enable the error interrupt for a given channel. The data value on a register write causes

the corresponding bit in the EDMA_EEIRL to be set. Setting bit 1 (SEEIn) provides a global set function,

forcing the entire contents of EDMA_EEIRL to be asserted. Reads of this register return all zeroes.

18.5.2.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)

The EDMA_CEEIR provides a simple memory-mapped mechanism to clear a given bit in the

EDMA_EEIRL to disable the error interrupt for a given channel. The data value on a register write causes

the corresponding bit in the EDMA_EEIRL to be cleared. Setting bit 1 (CEEIn) provides a global clear

function, forcing the entire contents of the EDMA_EEIRL to be zeroed, disabling error interrupts for all

channels. Reads of this register return all zeroes.

Table 18-7. EDMA_CERQR field descriptions

Field Description

0 Reserved.

1–7

CERQ[0:6]

Clear enable request.

0–15 Clear corresponding bit in EDMA_ERQRL

16–63Reserved

64–127Clear all bits in EDMA_ERQRL

Note: Bit 2 (CERQ1) is not used.

Address: Base + 0x001A Access: User write-only

01234567

R00000000

WSEEI[0:6]

Reset00000000

Figure 18-8. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)

Table 18-8. EDMA_SEEIR field descriptions

Field Description

0 Reserved.

1–7

SEEI[0:6]

Set enable error interrupt.

0–15 Set corresponding bit in EDMA_EIRRL

16–63 Reserved

64–127 Set all bits in EDMA_EEIRL

Note: Bit 2 (SEEI1) is not used.

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18.5.2.9 eDMA Clear Interrupt Request Register (EDMA_CIRQR)

The EDMA_CIRQR provides a simple memory-mapped mechanism to clear a given bit in the

EDMA_IRQRL to disable the interrupt request for a given channel. The given value on a register write

causes the corresponding bit in the EDMA_IRQRL to be cleared. Setting bit 1 (CINTn) provides a global

clear function, forcing the entire contents of the EDMA_IRQRL to be zeroed, disabling all DMA interrupt

requests. Reads of this register return all zeroes.

Address: Base + 0x001B Access: User write-only

01234567

R00000000

WCEEI[0:6]

Reset00000000

Figure 18-9. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)

Table 18-9. EDMA_CEEIR field descriptions

Field Description

0 Reserved.

1–7

CEEI[0:6]

Clear enable error interrupt.

0–15 Clear corresponding bit in EDMA_EEIRL

16–63 Reserved

64–127 Clear all bits in EDMA_EEIRL

Note: Bit 2 (CEEI1) is not used.

Address: Base + 0x001C Access: User write-only

01234567

R00000000

WCINT[0:6]

Reset00000000

Figure 18-10. eDMA Clear Interrupt Request (EDMA_CIRQR)

Table 18-10. EDMA_CIRQR field descriptions

Field Description

0 Reserved.

1–7

CINT[0:6]

Clear interrupt request.

0–15 Clear corresponding bit in EDMA_IRQRL

16–63 Reserved

64–127 Clear all bits in EDMA_IRQRL

Note: Bit 2 (CINT1) is not used.

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18.5.2.10 eDMA Clear Error Register (EDMA_CERR)

The EDMA_CERR provides a simple memory-mapped mechanism to clear a given bit in the EDMA_ERL

to disable the error condition flag for a given channel. The given value on a register write causes the

corresponding bit in the EDMA_ERL to be cleared. Setting bit 1 (CERn) provides a global clear function,

forcing the entire contents of the EDMA_ERL to be zeroed, clearing all channel error indicators. Reads of

this register return all zeroes.

18.5.2.11 eDMA Set START Bit Register (EDMA_SSBR)

The EDMA_SSBR provides a simple memory-mapped mechanism to set the START bit in the TCD of the

given channel. The data value on a register write causes the START bit in the corresponding transfer

control descriptor to be set. Setting bit 1 (SSBn) provides a global set function, forcing all START bits to

be set. Reads of this register return all zeroes.

Address: Base + 0x001D Access: User write-only

01234567

R00000000

WCERR[0:6]

Reset00000000

Figure 18-11. eDMA Clear Error Register (EDMA_CERR)

Table 18-11. EDMA_CERR field descriptions

Field Description

0Reserved.

1–7

CER[0:6]

Clear error indicator.

0–15 Clear corresponding bit in EDMA_ERL

16–63 Reserved

64–127 Clear all bits in EDMA_ERL

Address: Base + 0x001E Access: User write-only

01234567

R00000000

WSSB[0:6]

Reset00000000

Figure 18-12. eDMA Set START Bit Register (EDMA_SSBR)

Table 18-12. EDMA_SSBR field descriptions

Field Description

0 Reserved.

1–7

SSB[0:6]

Set START bit (channel service request).

0–15 Set the corresponding channel’s TCD START bit

16–63 Reserved

64–127 Set all TCD START bits

Note: Bit 2 (SSB1) is not used.

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18.5.2.12 eDMA Clear DONE Status Bit Register (EDMA_CDSBR)

The EDMA_CDSBR provides a simple memory-mapped mechanism to clear the DONE bit in the TCD

of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer

control descriptor to be cleared. Setting bit 1 (CDSBn) provides a global clear function, forcing all DONE

bits to be cleared.

18.5.2.13 eDMA Interrupt Request Register (EDMA_IRQRL)

The EDMA_IRQRL provide a bit map for the 16 channels signaling the presence of an interrupt request

for each channel. EDMA_IRQRL maps to channels 15–0.

The eDMA engine signals the occurrence of a programmed interrupt upon the completion of a data transfer

as defined in the transfer control descriptor by setting the appropriate bit in this register. The outputs of

this register are directly routed to the interrupt controller (INTC). During the execution of the interrupt

service routine associated with any given channel, it is software’s responsibility to clear the appropriate

bit, negating the interrupt request. Typically, a write to the EDMA_CIRQR in the interrupt service routine

is used for this purpose.

The state of any given channel’s interrupt request is directly affected by writes to this register; it is also

affected by writes to the EDMA_CIRQR. On writes to the EDMA_IRQRL, a 1 in any bit position clears

the corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding

channel’s current interrupt status. The EDMA_CIRQR is provided so the interrupt request for a single

channel can easily be cleared without the need to perform a read-modify-write sequence to the

EDMA_IRQRL.

Address: Base + 0x001F Access: User write-only

01234567

R00000000

WCDSB[0:6]

Reset00000000

Figure 18-13. eDMA Clear DONE Status Bit Register (EDMA_CDSBR)

Table 18-13. EDMA_CDSBR field descriptions

Field Description

0 Reserved.

1–7

CDSB[0:6]

Clear DONE status bit.

0–15 Clear the corresponding channel’s DONE bit

16–63 Reserved

64–127 Clear all TCD DONE bits

Note: Bit 2 (CDSB1) is not used.

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18.5.2.14 eDMA Error Register (EDMA_ERL)

The EDMA_ERL provides a bit map for the 16 channels signaling the presence of an error for each

channel. EDMA_ERL maps to channels 15-0.

The eDMA engine signals the occurrence of a error condition by setting the appropriate bit in this register.

The outputs of this register are enabled by the contents of the EDMA_EEIR, then logically summed across

groups of 16 and 32 channels to form several group error interrupt requests that are then routed to the

interrupt controller. During the execution of the interrupt service routine associated with any DMA errors,

it is software’s responsibility to clear the appropriate bit, negating the error interrupt request. Typically, a

write to the EDMA_CERR in the interrupt service routine is used for this purpose. Recall the normal DMA

channel completion indicators, setting the transfer control descriptor DONE flag and the possible assertion

of an interrupt request, are not affected when an error is detected.

The contents of this register can also be polled and a non-zero value indicates the presence of a channel

error, regardless of the state of the EDMA_EEIR. The EDMA_ESR[VLD] bit is a logical OR of all bits in

this register and it provides a single bit indication of any errors. The state of any given channel’s error

indicators is affected by writes to this register; it is also affected by writes to the EDMA_CERR. On writes

to EDMA_ERL, a 1 in any bit position clears the corresponding channel’s error status. A 0 in any bit

position has no affect on the corresponding channel’s current error status. The EDMA_CERR is provided

so the error indicator for a single channel can easily be cleared.

Address:

Base + 0x0024 Access: User read/write

0123456789101112131415

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RINT

INT

Reset0000000000000000

Figure 18-14. eDMA Interrupt Request Low Register (EDMA_IRQRL)

Table 18-14. EDMA_IRQRL field descriptions

Field Description

16–31

INTn

eDMA interrupt request n.

0 The interrupt request for channel n is cleared.

1 The interrupt request for channel n is active.

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18.5.2.15 DMA Hardware Request Status (DMAHRSL)

The DMAHRSL registers provide a bit map for the implemented channels 16 to show the current hardware

request status for each channel. DMAHRSL covers channels 31:00. Hardware request status reflects the

current state of the registered and qualified (via the DMAERQ field) ipd_req lines as seen by the eDMA’s

arbitration logic. This view into the hardware request signals may be used for debug purposes.

Address:

Base + 0x002C Access: User read/write

0123456789101112131415

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RERR

ERR

Reset0000000000000000

Figure 18-15. eDMA Error Low Register (EDMA_ERL)

Table 18-15. EDMA_ERL field descriptions

Field Description

16–31

ERRn

eDMA Error n.

0 An error in channel n has not occurred.

1 An error in channel n has occurred.

Address:

Base + 0x0034 Access: User read/write

0123456789101112131415

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RHRS

HRS

Reset0000000000000000

Figure 18-16. EDMA Hardware Request Status Register Low (EDMA_HRSL)

Table 18-16. EDMA_HRSL field descriptions

Field Description

16–31

HRSn

DMA Hardware Request Status

0 A hardware service request for channel n is not present.

1 A hardware service request for channel n is present.

Note: The hardware request status reflects the state of the request as seen by the arbitration logic.

Therefore, this status is affected by the EDMA_ERQRL[ERQn] bit.

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18.5.2.16 eDMA Channel n Priority Registers (EDMA_CPRn)

When the fixed-priority channel arbitration mode is enabled (EDMA_CR[ERCA] = 0), the contents of

these registers define the unique priorities associated with each channel within a group. The channel

priorities are evaluated by numeric value; that is, 0 is the lowest priority, 1 is the next higher priority, then

2, 3, etc. If software chooses to modify channel priority values, then the software must ensure that the

channel priorities contain unique values, otherwise a configuration error is reported. The range of the

priority value is limited to the values of 0 through 15. When read, the GRPPRI bits of the EDMA_CPRn

resides. GRPPRI bits are not affected by writes to the EDMA_CPRn registers. The group priority is

assigned in the EDMA_CR.

Refer to Figure 18-2 and Table 18-2 for the EDMA_CR definition.

Channel preemption is enabled on a per-channel basis by setting the ECP bit in the EDMA_CPRn register.

Channel preemption allows the executing channel’s data transfers to be temporarily suspended in favor of

starting a higher priority channel. After the preempting channel has completed all of its minor loop data

transfers, the preempted channel is restored and resumes execution. After the restored channel completes

one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting

service, the restored channel is suspended and the higher priority channel is serviced. Nested preemption

(attempting to preempt a preempting channel) is not supported. After a preempting channel begins

execution, it cannot be preempted. Preemption is only available when fixed arbitration is selected for both

group and channel arbitration modes.

The following table describes the fields in the eDMA channel n priority register:

Address: Base + 0x100 + n Access: User read/write

01234567

RECP 000 CHPRI

Reset0000 —

1The reset value for the channel priority fields, GRPPRI[0–1] and CHPRI[0–3] is the

channel number for the priority register;

EDMA_CPR15[CHPRI] = 0b1111.

Figure 18-17. eDMA Channel n Priority Register (EDMA_CPRn)

Table 18-17. EDMA_CPRn field descriptions

Field Description

ECP

Enable channel preemption.

0 Channel n cannot be suspended by a higher priority channel’s service request.

1 Channel n can be temporarily suspended by the service request of a higher priority channel.

1-3 Reserved.

4–7

CHPRI[0:3]

Channel n arbitration priority. Channel priority when fixed-priority arbitration is enabled. The reset

value for the channel priority fields CHPRI[0–3], is equal to the corresponding channel number for

each priority register; that is, EDMA_CPR31[CHPRI] = 0b1111.

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18.5.2.17 Transfer Control Descriptor (TCD)

Each channel requires a 256-bit transfer control descriptor for defining the desired data movement

operation. The channel descriptors are stored in the local memory in sequential order: channel 0,

channel 1,... channel 15. The definitions of the TCD are presented as 23 variable-length fields.

Table 18-18 defines the fields of the basic TCD structure.

Table 18-18. TCDn 32-bit memory structure

eDMA Bit Offset Bit

Length TCDn Field Name TCDn

Abbreviation Word #

0x1000 + (32 × n) + 0 32 Source address SADDR Word 0

0x1000 + (32 × n) + 32 5 Source address modulo SMOD Word 1

0x1000 + (32 × n) + 37 3 Source data transfer size SSIZE

0x1000 + (32 × n) + 40 5 Destination address modulo DMOD

0x1000 + (32 × n) + 45 3 Destination data transfer size DSIZE

0x1000 + (32 × n) + 48 16 Signed Source Address Offset SOFF

0x1000 + (32 × n) + 64 32 Inner minor byte count NBYTES Word 2

0x1000 + (32 × n) + 96 32 Last Source Address Adjustment SLAST Word 3

0x1000 + (32 × n) +

128

32 Destination Address DADDR Word 4

0x1000 + (32 × n) +

160

1 Channel-to-channel Linking on Minor Loop

Complete

CITER.E_LINK Word 5

0x1000 + (32 × n) +

161

6 Current Major Iteration Count or

Link Channel Number

CITER or

CITER.LINKCH

0x1000 + (32 × n) +

167

9 Current Major Iteration Count CITER

0x1000 + (32 × n) +

176

16 Destination Address Offset (Signed) DOFF

0x1000 + (32 × n) +

192

32 Last Destination Address Adjustment /

Scatter Gather Address

DLAST_SGA Word 6

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Figure 18-18 defines the fields of the TCDn structure.

0x1000 + (32 × n) +

224

1 Channel-to-channel Linking on Minor Loop

Complete

BITER.E_LINK Word 7

0x1000 + (32 × n) +

225

6 Starting Major Iteration Count or

Link Channel Number

BITER or

BITER.LINKCH

0x1000 + (32 × n) +

231

9 Starting Major Iteration Count BITER

0x1000 + (32 × n)

+240

2 Bandwidth Control BWC

0x1000 + (32 × n) +

242

6 Link Channel Number MAJOR.LINKCH

0x1000 + (32 × n) +

248

1 Channel Done DONE

0x1000 + (32 × n) +

249

1 Channel Active ACTIVE

0x1000 + (32 × n) +

250

1 Channel-to-channel Linking on Major Loop

Complete

MAJOR.E_LINK

0x1000 + (32 × n) +

251

1 Enable Scatter/Gather Processing E_SG

0x1000 + (32 × n) +

252

1 Disable Request D_REQ

0x1000 + (32 × n) +

253

1 Channel Interrupt Enable When Current Major

Iteration Count is Half Complete

INT_HALF

0x1000 + (32 × n) +

254

1 Channel Interrupt Enable When Current Major

Iteration Count Complete

INT_MAJ

0x1000 + (32 × n) +

255

1 Channel Start START

Table 18-18. TCDn 32-bit memory structure (continued)

eDMA Bit Offset Bit

Length TCDn Field Name TCDn

Abbreviation Word #

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NOTE

The TCD structures for the eDMA channels shown in Figure 18-18 are

implemented in internal SRAM. These structures are not initialized at reset.

Therefore, all channel TCD parameters must be initialized by the

application code before activating that channel.

Table 18-19 gives a detailed description of the TCNn fields.

Word

Offset

0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031

0x0 SADDR

0x4 SMOD SSIZE DMOD DSIZE SOFF

0x8 NBYTES

0xC SLAST

0x10 DADDR

0x14

CITER.E_ LINK

CITER1 or

CITER.LINKCH

1If channel linking on minor link completion is disabled, TCD bits [161:175] form a 15-bit CITER field;

if channel-to-channel linking is enabled, CITER becomes a 9-bit field.

CITER1DOFF

0x18 DLAST_SGA

0x1C

BITER.E_ LINK

BITER2 or

BITER.LINKCH

2If channel linking on minor link completion is disabled, TCD bits [225:239] form a 15-bit BITER field;

if channel-to-channel linking is enabled, BITER becomes a 9-bit field.

BITER2BWC MAJOR LINKCH

DONE

ACTIVE

MAJOR.E_LINK

E_SG

D_REQ

INT_HALF

INT_MAJ

START

Figure 18-18. TCD structure

Table 18-19. TCDn field descriptions

Bits

Word Offset

[n:n]

Field Name Description

0–31

0x0 [0:31]

SADDR

[0:31]

Source address. Memory address pointing to the source data.

Word 0x0, bits 0–31.

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32–36

0x4 [0:4]

SMOD

[0:4]

Source address modulo.

0 Source address modulo feature is disabled.

not 0 This value defines a specific address range that is specified to be either the

value after SADDR + SOFF calculation is performed or the original register

value. The setting of this field provides the ability to easily implement a

circular data queue. For data queues requiring power-of-2 “size” bytes, start

the queue at a 0-modulo-size address and set the SMOD field to the value

for the queue, freezing the desired number of upper address bits. The value

programmed into this field specifies the number of lower address bits that are

allowed to change. For this circular queue application, the SOFF is typically

set to the transfer size to implement post-increment addressing with the

SMOD function constraining the addresses to a 0-modulo-size range.

37–39

0x4 [5:7]

SSIZE

[0:2]

Source data transfer size.

000 8-bit

001 16-bit

010 32-bit

011 64-bit

100 32-bit

101 32-byte burst (64-bit x 4)

110 Reserved

111 Reserved

The attempted specification of a ‘reserved’ encoding causes a configuration error.

40–44

0x4 [8:12]

DMOD

[0:4]

Destination address modulo. Refer to the SMOD[0:5] definition.

45–47

0x4 [13:15]

DSIZE

[0:2]

Destination data transfer size. Refer to the SSIZE[0:2] definition.

48–63

0x4 [16:31]

SOFF

[0:15]

Source address signed offset. Sign-extended offset applied to the current source

address to form the next-state value as each source read is completed.

64–95

0x8 [0:31]

NBYTES

[0:31]

Inner “minor” byte transfer count. Number of bytes to be transferred in each service

request of the channel. As a channel is activated, the contents of the appropriate

TCD is loaded into the eDMA engine, and the appropriate reads and writes

performed until the complete byte transfer count has been transferred. This is an

indivisible operation and cannot be stalled or halted. Once the minor count is

exhausted, the current values of the SADDR and DADDR are written back into the

local memory, the major iteration count is decremented and restored to the local

memory. If the major iteration count is completed, additional processing is

performed.

Note: The NBYTES value of 0x0000_0000 is interpreted as 0x1_0000_0000, thus

specifying a four GB transfer.

96–127

0xC [0:31]

SLAST

[0:31]

Last source address adjustment. Adjustment value added to the source address at

the completion of the outer major iteration count. This value can be applied to

“restore” the source address to the initial value, or adjust the address to reference

the next data structure.

128–159

0x10 [0:31]

DADDR

[0:31]

Destination address. Memory address pointing to the destination data.

Table 18-19. TCDn field descriptions (continued)

Bits

Word Offset

[n:n]

Field Name Description

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160

0x14 [0]

CITER.E_LINK Enable channel-to-channel linking on minor loop completion. As the channel

completes the inner minor loop, this flag enables the linking to another channel,

defined by CITER.LINKCH[0:5]. The link target channel initiates a channel service

request via an internal mechanism that sets the TCD.START bit of the specified

channel. If channel linking is disabled, the CITER value is extended to 15 bits in

place of a link channel number. If the major loop is exhausted, this link mechanism

is suppressed in favor of the MAJOR.E_LINK channel linking.

0 The channel-to-channel linking is disabled.

1 The channel-to-channel linking is enabled.

Note: This bit must be equal to the BITER.E_LINK bit otherwise a configuration

error is reported.

161–166

0x14 [1:6]

CITER

[0:5]

CITER.LINKCH

[0:5]

Current “major” iteration count or link channel number.

If channel-to-channel linking is disabled (TCD.CITER.E_LINK = 0), then

• No channel-to-channel linking (or chaining) is performed after the inner minor

loop is exhausted. TCD bits [161:175] form a 15-bit CITER field.

otherwise

• After the minor loop is exhausted, the eDMA engine initiates a channel service

request at the channel defined by CITER.LINKCH[0:5] by setting that channel’s

TCD.START bit.

167–175

0x14 [7:15]

CITER

[6:14]

Current “major” iteration count. This 9 or 15-bit count represents the current major

loop count for the channel. It is decremented each time the minor loop is completed

and updated in the transfer control descriptor memory. After the major iteration

count is exhausted, the channel performs a number of operations (for example, final

source and destination address calculations), optionally generating an interrupt to

signal channel completion before reloading the CITER field from the beginning

iteration count (BITER) field.

Note: When the CITER field is initially loaded by software, it must be set to the

same value as that contained in the BITER field.

Note: If the channel is configured to execute a single service request, the initial

values of BITER and CITER must be 0x0001.

176–191

0x14 [16:31]

DOFF

[0:15]

Destination address signed offset. Sign-extended offset applied to the current

destination address to form the next-state value as each destination write is

completed.

192–223

0x18 [0:31]

DLAST_SGA

[0:31]

Last destination address adjustment or the memory address for the next transfer

control descriptor to be loaded into this channel (scatter/gather).

If scatter/gather processing for the channel is disabled (TCD.E_SG = 0) then

• Adjustment value added to the destination address at the completion of the outer

major iteration count.

This value can be applied to “restore” the destination address to the initial value, or

adjust the address to reference the next data structure.

Otherwise

• This address points to the beginning of a 0-modulo-32 byte region containing the

next transfer control descriptor to be loaded into this channel. This channel

reload is performed as the major iteration count completes. The scatter/gather

address must be 0-modulo-32 byte, otherwise a configuration error is reported.

Table 18-19. TCDn field descriptions (continued)

Bits

Word Offset

[n:n]

Field Name Description

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224

0x1C [0]

BITER.E_LINK Enables channel-to-channel linking on minor loop complete. As the channel

completes the inner minor loop, this flag enables the linking to another channel,

defined by BITER.LINKCH[0:5]. The link target channel initiates a channel service

request via an internal mechanism that sets the TCD.START bit of the specified

channel. If channel linking is disabled, the BITER value is extended to 15 bits in

place of a link channel number. If the major loop is exhausted, this link mechanism

is suppressed in favor of the MAJOR.E_LINK channel linking.

0 The channel-to-channel linking is disabled.

1 The channel-to-channel linking is enabled.

Note: When the TCD is first loaded by software, this field must be set equal to the

corresponding CITER field, otherwise a configuration error is reported. As

the major iteration count is exhausted, the contents of this field is reloaded

into the CITER field.

225–230

0x1C [1:6]

BITER

[0:5]

BITER.LINKCH

[0:5]

Beginning or starting “major” iteration count or link channel number.

If channel-to-channel linking is disabled (TCD.BITER.E_LINK = 0), then

• No channel-to-channel linking (or chaining) is performed after the inner minor

loop is exhausted. TCD bits [225:239] form a 15-bit BITER field.

Otherwise

• After the minor loop is exhausted, the eDMA engine initiates a channel service

request at the channel, defined by BITER.LINKCH[0:5], by setting that channel’s

TCD.START bit.

Note: When the TCD is first loaded by software, this field must be set equal to the

corresponding CITER field, otherwise a configuration error is reported. As

the major iteration count is exhausted, the contents of this field is reloaded

into the CITER field.

231–239

0x1C [7:15]

BITER

[6:14]

Beginning or starting major iteration count. As the transfer control descriptor is first

loaded by software, this field must be equal to the value in the CITER field. As the

major iteration count is exhausted, the contents of this field is reloaded into the

CITER field.

Note: If the channel is configured to execute a single service request, the initial

values of BITER and CITER must be 0x0001.

240–241

0x1C [16:17]

BWC

[0:1]

Bandwidth control. This two-bit field provides a mechanism to effectively throttle the

amount of bus bandwidth consumed by the eDMA. In general, as the eDMA

processes the inner minor loop, it continuously generates read/write sequences

until the minor count is exhausted. This field forces the eDMA to stall after the

completion of each read/write access to control the bus request bandwidth seen by

the system bus crossbar switch (XBAR).

To minimize start-up latency, bandwidth control stalls are suppressed for the first

two system bus cycles and after the last write of each minor loop.

00 No eDMA engine stalls

01 Reserved

10 eDMA engine stalls for four cycles after each r/w

11 eDMA engine stalls for eight cycles after each r/w

Table 18-19. TCDn field descriptions (continued)

Bits

Word Offset

[n:n]

Field Name Description

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242–247

0x1C [18:23]

MAJOR.LINKC

[0:5]

Link channel number. If channel-to-channel linking on major loop complete is

disabled (TCD.MAJOR.E_LINK = 0) then:

• No channel-to-channel linking (or chaining) is performed after the outer major

loop counter is exhausted.

Otherwise

• After the major loop counter is exhausted, the eDMA engine initiates a channel

service request at the channel defined by MAJOR.LINKCH[0:5] by setting that

channel’s TCD.START bit.

248

0x1C [24]

DONE Channel done. This flag indicates the eDMA has completed the outer major loop. It

is set by the eDMA engine as the CITER count reaches zero; it is cleared by

software or hardware when the channel is activated (when the channel has begun

to be processed by the eDMA engine, not when the first data transfer occurs).

Note: This bit must be cleared to write the MAJOR.E_LINK or E_SG bits.

249

0x1C [25]

ACTIVE Channel active. This flag signals the channel is currently in execution. It is set when

channel service begins, and is cleared by the eDMA engine as the inner minor loop

completes or if any error condition is detected.

250

0x1C [26]

MAJOR.E_LINK Enable channel-to-channel linking on major loop completion. As the channel

completes the outer major loop, this flag enables the linking to another channel,

defined by MAJOR.LINKCH[0:5]. The link target channel initiates a channel service

request via an internal mechanism that sets the TCD.START bit of the specified

channel.

NOTE: To support the dynamic linking coherency model, this field is forced to zero

when written to while the TCD.DONE bit is set.

0 The channel-to-channel linking is disabled.

1 The channel-to-channel linking is enabled.

251

0x1C [27]

E_SG Enable scatter/gather processing. As the channel completes the outer major loop,

this flag enables scatter/gather processing in the current channel. If enabled, the

eDMA engine uses DLAST_SGA as a memory pointer to a 0-modulo-32 address

containing a 32-byte data structure that is loaded as the transfer control descriptor

into the local memory.

NOTE: To support the dynamic scatter/gather coherency model, this field is forced

to zero when written to while the TCD.DONE bit is set.

0 The current channel’s TCD is “normal” format.

1 The current channel’s TCD specifies a scatter gather format. The DLAST_SGA

field provides a memory pointer to the next TCD to be loaded into this channel

after the outer major loop completes its execution.

252

0x1C [28]

D_REQ Disable hardware request. If this flag is set, the eDMA hardware automatically

clears the corresponding EDMA_ERQL bit when the current major iteration count

reaches zero.

0 The channel’s EDMA_ERQL bit is not affected.

1 The channel’s EDMA_ERQL bit is cleared when the outer major loop is

complete.

Table 18-19. TCDn field descriptions (continued)

Bits

Word Offset

[n:n]

Field Name Description

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18.6 Functional description

This section provides an overview of the microarchitecture and functional operation of the eDMA module.

18.6.1 eDMA microarchitecture

The eDMA module is partitioned into two major modules: the eDMA engine and the transfer control

descriptor local memory. Additionally, the eDMA engine is further partitioned into four submodules, as

shown in the following list:

• eDMA engine

— Address path: This module implements registered versions of two channel transfer control

descriptors: channel ‘x’ and channel ‘y,’ and is responsible for all the master bus address

calculations. All the implemented channels provide the exact same functionality. This

hardware structure allows the data transfers associated with one channel to be preempted after

the completion of a read/write sequence if a higher priority channel service request is asserted

while the first channel is active. After a channel is activated, it runs until the minor loop is

completed unless preempted by a higher priority channel. This capability provides a

mechanism (optionally enabled by EDMA_CPRn[ECP]) where a large data move operation

can be preempted to minimize the time another channel is blocked from execution.

When any other channel is activated, the contents of its transfer control descriptor is read from

the local memory and loaded into the registers of the other address path channel{x,y}. After

the inner minor loop completes execution, the address path hardware writes the new values for

253

0x1C [29]

INT_HALF Enable an interrupt when major counter is half complete.

If this flag is set, the channel generates an interrupt request by setting the bit in the

EDMA_ERQL when the current major iteration count reaches the halfway point.

The eDMA engine performs the compare (CITER == (BITER >> 1)). This halfway

point interrupt request supports double-buffered (aka ping-pong) schemes, or

where the processor needs an early indication of the data transfer’s progress during

data movement. CITER = BITER = 1 with INT_HALF enabled generates an

interrupt as it satisfies the equation (CITER == (BITER >> 1)) after a single

activation.

0 The half-point interrupt is disabled.

1 The half-point interrupt is enabled.

254

0x1C [30]

INT_MAJ Enable an interrupt when major iteration count completes. If this flag is set, the

channel generates an interrupt request by setting the appropriate bit in the

EDMA_ERQL when the current major iteration count reaches zero.

0 The end-of-major loop interrupt is disabled.

1 The end-of-major loop interrupt is enabled.

255

0x1C [31]

START Channel start. If this flag is set, the channel is requesting service. The eDMA

hardware automatically clears this flag after the channel begins execution.

0 The channel is not explicitly started.

1 The channel is explicitly started via a software initiated service request.

Table 18-19. TCDn field descriptions (continued)

Bits

Word Offset

[n:n]

Field Name Description

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408 Freescale Semiconductor

the TCDn.{SADDR, DADDR, CITER} back into the local memory. If the major iteration

count is exhausted, additional processing is performed, including the final address pointer

updates, reloading the TCDn.CITER field, and a possible fetch of the next TCDn from memory

as part of a scatter/gather operation.

— Data path: This module implements the actual bus master read/write datapath. It includes 32

bytes of register storage (matching the maximum transfer size) and the necessary mux logic to

support any required data alignment. The system read data bus is the primary input, and the

system write data bus is the primary output.

The address and data path modules directly support the 2-stage pipelined system bus. The

address path module represents the 1st stage of the bus pipeline (the address phase), while the

data path module implements the 2nd stage of the pipeline (the data phase).

— Program model/channel arbitration: This module implements the first section of eDMA’s

programming model as well as the channel arbitration logic. The programming model registers

are connected to the slave bus (not shown). The eDMA peripheral request inputs and eDMA

interrupt request outputs are also connected to this module (via the Control logic).

— Control: This module provides all the control functions for the eDMA engine. For data

transfers where the source and destination sizes are equal, the eDMA engine performs a series

of source read, destination write operations until the number of bytes specified in the inner

‘minor loop’ byte count has been moved.

A minor loop interaction is defined as the number of bytes to transfer (nbytes) divided by the

transfer size. Transfer size is defined as the following:

if (SSIZE < DSIZE)

transfer size = destination transfer size (# of bytes)

else

transfer size = source transfer size (# of bytes)

Minor loop TCD variables are SOFF, SMOD, DOFF, DMOD, NBYTES, SADDR, DADDR,

BWC, ACTIVE, AND START. Major loop TCD variables are DLAST, SLAST, CITER,

BITER, DONE, D_REQ, INT_MAJ, MAJOR_LNKCH, and INT_HALF.

For descriptors where the sizes are not equal, multiple access of the smaller size data are

required for each reference of the larger size. As an example, if the source size references 16-bit

data and the destination is 32-bit data, two reads are performed, then one 32-bit write.

• TCD local memory

— Memory controller: This logic implements the required dual-ported controller, handling

accesses from both the eDMA engine as well as references from the slave bus. As noted earlier,

in the event of simultaneous accesses, the eDMA engine is given priority and the slave

transaction is stalled. The hooks to a BIST controller for the local TCD memory are included

in this module.

— Memory array: The TCD is implemented using a single-ported, synchronous compiled RAM

memory array.

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18.6.2 eDMA basic data flow

The basic flow of a data transfer can be partitioned into three segments. As shown in Figure 18-19, the first

segment involves the channel service request. In the diagram, this example uses the assertion of the eDMA

peripheral request signal to request service for channel n. Channel service request via software and the

TCDn.START bit follows the same basic flow as an eDMA peripheral request. The eDMA peripheral

request input signal is registered internally and then routed through the eDMA engine, first through the

control module, then into the program model/channel arbitration module. In the next cycle, the channel

arbitration is performed, either using the fixed-priority or round-robin algorithm. After the arbitration is

complete, the activated channel number is sent through the address path and converted into the required

address to access the TCD local memory. Next, the TCD memory is accessed and the required descriptor

read from the local memory and loaded into the eDMA engine address path channel{x,y} registers. The

TCD memory is organized 64-bits in width to minimize the time needed to fetch the activated channel’s

descriptor and load it into the eDMA engine address path channel{x,y} registers.

Figure 18-19. eDMA operation, part 1

In the second part of the basic data flow as shown in Figure 18-20, the modules associated with the data

transfer (address path, data path and control) sequence through the required source reads and destination

writes to perform the actual data movement. The source reads are initiated and the fetched data is

temporarily stored in the data path module until it is gated onto the system bus during the destination write.

Slave Interface

eDMA

eDMA Peripheral Request

System Bus

Data Path Control

Address

Program Model/

Slave Write Data

Slave Write Address

Bus Write Data

Slave Read Data

Bus Address

eDMA Engine

TCD0

TCDn–1*

eDMA Interrupt Request

Bus Read Data

Channel Arbitration

eDMA Done Handshake

Path

SRAM

Transfer Control Descriptor

(TCD)

SRAM

*n = 16 channels

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This source read/destination write processing continues until the inner minor byte count has been

transferred. The eDMA Done Handshake signal is asserted at the end of the minor byte count transfer.

Figure 18-20. eDMA operation, part 2

After the inner minor byte count has been moved, the final phase of the basic data flow is performed. In

this segment, the address path logic performs the required updates to certain fields in the channel’s TCD:

for example., SADDR, DADDR, CITER. If the outer major iteration count is exhausted, then additional

operations are performed. These include the final address adjustments and reloading of the BITER field

into the CITER. Additionally, assertion of an optional interrupt request occurs at this time, as does a

possible fetch of a new TCD from memory using the scatter/gather address pointer included in the

descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in

Figure 18-21.

Slave Interface

eDMA

eDMA Interrupt Request

System Bus

Program Model/

Slave Write Data

Slave Write Address

Bus Write Data

Slave Read Data

Bus Address

eDMA Engine

TCD0

TCDn–1*

eDMA Peripheral

Bus Read Data

Channel Arbitration

Request

SRAM

Transfer Control Descriptor

(TCD)

SRAM

Data Path Control

Address

Path

eDMA Done Handshake

*n = 16 channels

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Figure 18-21. eDMA operation, part 3

18.6.3 eDMA performance

This section addresses the performance of the eDMA module, focusing on two separate metrics. In the

traditional data movement context, performance is best expressed as the peak data transfer rates achieved

using the eDMA. In most implementations, this transfer rate is limited by the speed of the source and

destination address spaces. In a second context where device-paced movement of single data values

to/from peripherals is dominant, a measure of the requests that can be serviced in a fixed time is a more

useful metric. In this environment, the speed of the source and destination address spaces remains

important, but the microarchitecture of the eDMA also factors significantly into the resulting metric.

The peak transfer rates for several different source and destination transfers are shown in Table 18-20. The

following assumptions apply to Table 18-20 and Table 18-21:

• Internal SRAM can be accessed with zero wait-states when viewed from the system bus data phase.

• All slave reads require two wait-states, and slave writes three wait-states, again viewed from the

system bus data phase.

• All slave accesses are 32-bits in size.

Slave Interface

eDMA

eDMA Done

System Bus

Slave Write Data

Slave Write Address

Bus Write Data

Slave Read Data

Bus Address

eDMA Engine

TCD0

TCDn–1*

eDMA Peripheral

Bus Read Data

Request

SRAM

Transfer Control Descriptor

(TCD)

SRAM

Data Path Address

Path Control

Program Model/

Channel Arbitration

*n = 16 channels

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Table 18-20 presents a peak transfer rate comparison, measured in MBs per second where the

internal-SRAM-to-internal-SRAM transfers occur at the core’s datapath width; that is, either 32- or 64-bits

per access. For all transfers involving the slave bus, 32-bit transfer sizes are used. In all cases, the transfer

rate includes the time to read the source plus the time to write the destination.

The second performance metric is a measure of the number of DMA requests that can be serviced in a

given amount of time. For this metric, it is assumed the peripheral request causes the channel to move a

single slave-mapped operand to/from internal SRAM. The same timing assumptions used in the previous

example apply to this calculation. In particular, this metric also reflects the time required to activate the

channel. The eDMA design supports the following hardware service request sequence:

• Cycle 1: eDMA peripheral request is asserted.

• Cycle 2: The eDMA peripheral request is registered locally in the eDMA module and qualified.

(TCD.START bit initiated requests start at this point with the registering of the slave write to TCD

bit 255).

• Cycle 3: Channel arbitration begins.

• Cycle 4: Channel arbitration completes. The transfer control descriptor local memory read is

initiated.

• Cycle 5–6: The first two parts of the activated channel’s TCD is read from the local memory. The

memory width to the eDMA engine is 64 bits, so the entire descriptor can be accessed in four

cycles.

Table 18-20. eDMA peak transfer rates (MB/Sec)

System Speed,

Transfer Size

Internal SRAM-to-

Internal SRAM

32-bit Slave-to-

Internal SRAM

Internal SRAM-to-

32-bit Slave

(buffering disabled)

Internal SRAM-to-

32-bit Slave

(buffering enabled)

66.7 MHz, 32-bit 66.7 66.7 53.3 88.7

66.7 MHz, 64-bit 133.3 66.7 53.3 88.7

66.7 MHz, 256-bit1

1A 256-bit transfer occurs as a burst of four 64-bit beats.

213.4 N/A2

2Not applicable: burst access to a slave port is not supported.

N/A2N/A2

83.3 MHz, 32-bit 83.3 83.3 66.7 110.8

83.3 MHz, 64-bit 166.7 83.3 66.7 110.8

83.3 MHz, 256-bit1266.6 N/A2N/A2N/A2

100.0 MHz, 32-bit 100.0 100.0 80.0 133.0

100.0 MHz, 64-bit 200.0 100.0 80.0 133.0

100.0 MHz, 256-bit1320.0 N/A2N/A2N/A2

132.0 MHz, 32-bit 132.0 132.0 105.6 175.6

132.0 MHz, 64-bit 264.0 132.0 105.6 175.6

132.0 MHz, 256-bit1422.4 N/A2N/A2N/A2

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• Cycle 7: The first system bus read cycle is initiated, as the third part of the channel’s TCD is read

from the local memory. Depending on the state of the crossbar switch, arbitration at the system bus

can insert an additional cycle of delay here.

• Cycle 8 – n: The last part of the TCD is read in. This cycle represents the 1st data phase for the

read, and the address phase for the destination write.

The exact timing from this point is a function of the response times for the channel’s read and write

accesses. In this case of an slave read and internal SRAM write, the combined data phase time is 4 cycles.

For an SRAM read and slave write, it is 5 cycles.

• Cycle n+ 1: This cycle represents the data phase of the last destination write.

• Cycle n+ 2: The eDMA engine completes the execution of the inner minor loop and prepares to

write back the required TCDn fields into the local memory. The control/status fields at word offset

0x1C in TCDn are read. If the major loop is complete, the MAJOR.E_LINK and E_SG bits are

checked and processed if enabled.

• Cycle n+ 3: The appropriate fields in the first part of the TCDn are written back into the local

memory.

• Cycle n+ 4: The fields in the second part of the TCDn are written back into the local memory. This

cycle coincides with the next channel arbitration cycle start.

• Cycle n+ 5: The next channel to be activated performs the read of the first part of its TCD from

the local memory. This is equivalent to Cycle 4 for the first channel’s service request.

Assuming zero wait states on the system bus, DMA requests can be processed every 9 cycles. Assuming

an average of the access times associated with slave-to-SRAM (4 cycles) and SRAM-to-slave (5 cycles),

DMA requests can be processed every 11.5 cycles (4 + (4 + 5)/2 + 3). This is the time from Cycle 4 to

Cycle “n 5.” The resulting peak request rate, as a function of the system frequency, is shown in

Table 18-21. This metric represents millions of requests per second.

A general formula to compute the peak request rate (with overlapping requests) is:

PEAKreq = freq / [entry + (1 + read_ws) + (1 + write_ws) + exit] Eqn. 18-1

where:

PEAKreq — peak request rate

freq — system frequency

entry — channel startup (four cycles)

Table 18-21. eDMA peak request Rate (MReq/sec)

System Frequency

(MHz)

Request Rate

(Zero Wait States)

Request Rate

(with Wait States)

66.6 7.4 5.8

83.3 9.2 7.2

100.0 11.1 8.7

133.3 14.8 11.6

150.0 16.6 13.0

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read_ws — wait states seen during the system bus read data phase

write_ws — wait states seen during the system bus write data phase

exit — channel shutdown (three cycles)

For example: consider a system with the following characteristics:

• Internal SRAM can be accessed with one wait-state when viewed from the system bus data phase.

• All slave reads require two wait-states, and slave writes three wait-states, again viewed from the

system bus data phase.

• System operates at 150 MHz.

For an SRAM to slave transfer,

PEAKreq = 150 MHz / [4 + (1 + 1) + (1 + 3) + 3] cycles = 11.5 Mreq/sec Eqn. 18-2

For an slave to SRAM transfer,

PEAKreq = 150 MHz / [4 + (1 + 2) + (1 + 1) + 3] cycles = 12.5 Mreq/sec Eqn. 18-3

Assuming an even distribution of the two transfer types, the average peak request rate is:

PEAKreq = (11.5 Mreq/sec + 12.5 Mreq/sec) / 2 = 12.0 Mreq/sec Eqn. 18-4

The minimum number of cycles to perform a single read/write, zero wait states on the system bus, from a

cold start (no channel is executing, eDMA is idle) are the following:

• 11 cycles for a software (TCD.START bit) request

• 12 cycles for a hardware (eDMA peripheral request signal) request

Two cycles account for the arbitration pipeline and one extra cycle on the hardware request resulting from

the internal registering of the eDMA peripheral request signals. For the peak request rate calculations

above, the arbitration and request registering is absorbed in or overlap the previous executing channel.

NOTE

When channel linking or scatter/gather is enabled, a two-cycle delay is

imposed on the next channel selection and startup. This allows the link

channel or the scatter/gather channel to be eligible and considered in the

arbitration pool for next channel selection.

18.7 Initialization / application information

18.7.1 eDMA initialization

A typical initialization of the eDMA has the following sequence:

1. Write the EDMA_CR if a configuration other than the default is desired.

2. Write the channel priority levels into the EDMA_CPRn registers if a configuration other than the

default is desired.

3. Enable error interrupts in the EDMA_EEIRL and/or EDMA_EEIRH registers (optional).

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4. Write the 32-byte TCD for each channel that can request service.

5. Enable any hardware service requests via the EDMA_ERQRH and/or EDMA_ERQRL registers.

6. Request channel service by either software (setting the TCD.START bit) or by hardware (slave

device asserting its eDMA peripheral request signal).

After any channel requests service, a channel is selected for execution based on the arbitration and priority

levels written into the programmer's model. The eDMA engine reads the entire TCD, including the

primary transfer control parameter shown in Table 18-22, for the selected channel into its internal address

path module. As the TCD is being read, the first transfer is initiated on the system bus unless a

configuration error is detected. Transfers from the source (as defined by the source address, TCD.SADDR)

to the destination (as defined by the destination address, TCD.DADDR) continue until the specified

number of bytes (TCD.NBYTES) have been transferred. When the transfer is complete, the eDMA

engine's local TCD.SADDR, TCD.DADDR, and TCD.CITER are written back to the main TCD memory

and any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post

processing is executed: for example, interrupts, major loop channel linking, and scatter/gather operations,

if enabled.

Figure 18-22 shows how each DMA request initiates one minor loop transfer (iteration) without CPU

intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA

preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration

count (biter).

Table 18-22. TCD primary control and status fields

TCD Field

Name Description

START Control bit to explicitly start channel when using a software initiated DMA service

(Automatically cleared by hardware)

ACTIVE Status bit indicating the channel is currently in execution

DONE Status bit indicating major loop completion (Cleared by software when using a

software initiated DMA service)

D_REQ Control bit to disable DMA request at end of major loop completion when using a

hardware-initiated DMA service

BWC Control bits for “throttling” bandwidth control of a channel

E_SG Control bit to enable scatter-gather feature

INT_HALF Control bit to enable interrupt when major loop is half complete

INT_MAJ Control bit to enable interrupt when major loop completes

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Figure 18-22. Example of multiple loop iterations

Figure 18-23 lists the memory array terms and how the TCD settings interrelate.

Figure 18-23. Memory array terms

18.7.2 DMA programming errors

The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor

data. Most programming errors are reported on a per channel basis with the exception of two errors: group

priority error and channel priority error, or EDMA_ESR[GPE] and EDMA_ESR[CPE], respectively.

For all error types other than group or channel priority errors, the channel number causing the error is

recorded in the EDMA_ESR. If the error source is not removed before the next activation of the problem

channel, the error is detected and recorded again.

DMA Request

Minor Loop 3

Current Major Loop

Iteration Count

(CITER)

Example Memory Array

•

DMA Request

Minor Loop 2

•

DMA Request

Minor Loop 1

•

Major Loop

xADDR:

(Starting Address)

xSIZE:

(Size of one data

Minor Loop

(NBYTES in

Minor Loop, often

the same value

as xSIZE)

Offset (xOFF): Number of

bytes added to current

address after each transfer

(Often the same value

as xSIZE)

•

Minor Loop

Each DMA Source (S) and

Destination (D) has its own:

• Address (xADDR)

• Size (xSIZE)

• Offset (xOFF)

xLAST: Number of bytes

added to current address

Peripheral queues typically

have size and offset

equal to NBYTES

•

after Major Loop

(Typically used to

loop back)

transfer)

•

Last Minor Loop

• Modulo (xMOD)

• Last Address Adjustment

(xLAST) where x = S or D

•

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If priority levels are not unique, the highest (channel/group) priority that has an active request is selected,

but the lowest numbered (channel/group) with that priority is selected by arbitration and executed by the

eDMA engine. The hardware service request handshake signals, error interrupts and error reporting are

associated with the selected channel.

18.7.3 DMA request assignments

The assignments between the DMA requests from the modules to the channels of the eDMA are shown in

Table 18-23. The source column is written in C language syntax. The syntax is

module_instance.register[bit].

18.7.4 DMA arbitration mode considerations

18.7.4.1 Fixed-channel arbitration

In this mode, the channel service request from the highest priority channel is selected to execute. The

advantage of this scenario is that latency can be small for channels that need to be serviced quickly.

Preemption is available in this scenario only.

18.7.4.2 Fixed-group arbitration, round-robin channel arbitration

Channels are serviced starting with the highest channel number and rotating through to the lowest channel

number without regard to the channel priority levels assigned within the group.

Table 18-23. DMA request summary for eDMA

DMA Request Ch. Source Description

DMA_MUX_CHCONFIG0_SOURCE 0 DMA_MUX.CHCONFIG0[SOURCE] DMA MUX channel 0 source

DMA_MUX_CHCONFIG1_SOURCE 1 DMA_MUX.CHCONFIG1[SOURCE] DMA MUX channel 1 source

DMA_MUX_CHCONFIG2_SOURCE 2 DMA_MUX.CHCONFIG2[SOURCE] DMA MUX channel 2 source

DMA_MUX_CHCONFIG3_SOURCE 3 DMA_MUX.CHCONFIG3[SOURCE] DMA MUX channel 3 source

DMA_MUX_CHCONFIG4_SOURCE 4 DMA_MUX.CHCONFIG4[SOURCE] DMA MUX channel 4 source

DMA_MUX_CHCONFIG5_SOURCE 5 DMA_MUX.CHCONFIG5[SOURCE] DMA MUX channel 5 source

DMA_MUX_CHCONFIG6_SOURCE 6 DMA_MUX.CHCONFIG6[SOURCE] DMA MUX channel 6 source

DMA_MUX_CHCONFIG7_SOURCE 7 DMA_MUX.CHCONFIG7[SOURCE] DMA MUX channel 7 source

DMA_MUX_CHCONFIG8_SOURCE 8 DMA_MUX.CHCONFIG8[SOURCE] DMA MUX channel 8 source

DMA_MUX_CHCONFIG9_SOURCE 9 DMA_MUX.CHCONFIG9[SOURCE] DMA MUX channel 9 source

DMA_MUX_CHCONFIG10_SOURCE 10 DMA_MUX.CHCONFIG10[SOURCE] DMA MUX channel 10 source

DMA_MUX_CHCONFIG11_SOURCE 11 DMA_MUX.CHCONFIG11[SOURCE] DMA MUX channel 11 source

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18.7.5 DMA transfer

18.7.5.1 Single request

To perform a simple transfer of ‘n’ bytes of data with one activation, set the major loop to 1

(TCD.CITER = TCD.BITER = 1). The data transfer begins after the channel service request is

acknowledged and the channel is selected to execute. After the transfer completes, the TCD.DONE bit is

set and an interrupt is generated if correctly enabled.

For example, the following TCD entry is configured to transfer 16 bytes of data. The eDMA is

programmed for one iteration of the major loop transferring 16 bytes per iteration. The source memory has

a byte-wide memory port located at 0x1000. The destination memory has a word-wide port located at

0x2000. The address offsets are programmed in increments to match the size of the transfer; one byte for

the source and four bytes for the destination. The final source and destination addresses are adjusted to

return to their beginning values.

TCD.CITER = TCD.BITER = 1

TCD.NBYTES = 16

TCD.SADDR = 0x1000

TCD.SOFF = 1

TCD.SSIZE = 0

TCD.SLAST = –16

TCD.DADDR = 0x2000

TCD.DOFF = 4

TCD.DSIZE = 2

TCD.DLAST_SGA= –16

TCD.INT_MAJ = 1

TCD.START = 1 (Initialize all other fields before writing to this bit)

All other TCD fields = 0

This generates the following sequence of events:

1. Slave write to the TCD.START bit requests channel service.

2. The channel is selected by arbitration for servicing.

3. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1.

4. eDMA engine reads: channel TCD data from local memory to internal register file.

5. The source to destination transfers are executed as follows:

a) read_byte (0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003)

b) write_word (0x2000)  first iteration of the minor loop

c) read_byte (0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007)

d) write_word (0x2004)  second iteration of the minor loop

e) read_byte (0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b)

f) write_word (0x2008)  third iteration of the minor loop

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g) read_byte (0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f)

h) write_word (0x200c)  last iteration of the minor loop  major loop complete

6. eDMA engine writes: TCD.SADDR = 0x1000, TCD.DADDR = 0x2000,

TCD.CITER = 1 (TCD.BITER).

7. eDMA engine writes: TCD.ACTIVE = 0, TCD.DONE = 1, EDMA_IRQRn=1.

8. The channel retires.

The eDMA goes idle or services the next channel.

18.7.5.2 Multiple requests

The next example is the same as previous with the exception of transferring 32 bytes via two hardware

requests. The only fields that change are the major loop iteration count and the final address offsets. The

eDMA is programmed for two iterations of the major loop transferring 16 bytes per iteration. After the

channel’s hardware requests are enabled in the EDMA_ERQR, channel service requests are initiated by

the slave device (set ERQR after TCD; TCD.START = 0).

TCD.CITER = TCD.BITER = 2

TCD.NBYTES = 16

TCD.SADDR = 0x1000

TCD.SOFF = 1

TCD.SSIZE = 0

TCD.SLAST = –32

TCD.DADDR = 0x2000

TCD.DOFF = 4

TCD.DSIZE = 2

TCD.DLAST_SGA = –32

TCD.INT_MAJ = 1

TCD.START = 0 (Initialize all other fields before writing this bit.)

All other TCD fields = 0

This generates the following sequence of events:

1. First hardware (eDMA peripheral request) request for channel service.

2. The channel is selected by arbitration for servicing.

3. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1.

4. eDMA engine reads: channel TCD data from local memory to internal register file.

5. The source to destination transfers execute as follows:

a) read_byte (0x1000), read_byte (0x1001), read_byte (0x1002), read_byte (0x1003)

b) write_word (0x2000)  first iteration of the minor loop

c) read_byte (0x1004), read_byte (0x1005), read_byte (0x1006), read_byte (0x1007)

d) write_word (0x2004)  second iteration of the minor loop

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e) read_byte (0x1008), read_byte (0x1009), read_byte (0x100a), read_byte (0x100b)

f) write_word (0x2008)  third iteration of the minor loop

g) read_byte (0x100c), read_byte (0x100d), read_byte (0x100e), read_byte (0x100f)

h) write_word (0x200c)  last iteration of the minor loop

6. eDMA engine writes: TCD.SADDR = 0x1010, TCD.DADDR = 0x2010, TCD.CITER = 1.

7. eDMA engine writes: TCD.ACTIVE = 0.

8. The channel retires  one iteration of the major loop.

The eDMA goes idle or services the next channel.

9. Second hardware (eDMA peripheral request) requests channel service.

10. The channel is selected by arbitration for servicing.

11. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1.

12. eDMA engine reads: channel TCD data from local memory to internal register file.

13. The source to destination transfers execute as follows:

a) read_byte (0x1010), read_byte (0x1011), read_byte (0x1012), read_byte (0x1013)

b) write_word (0x2010)  first iteration of the minor loop

c) read_byte (0x1014), read_byte (0x1015), read_byte (0x1016), read_byte (0x1017)

d) write_word (0x2014)  second iteration of the minor loop

e) read_byte (0x1018), read_byte (0x1019), read_byte (0x101a), read_byte (0x101b)

f) write_word (0x2018)  third iteration of the minor loop

g) read_byte (0x101c), read_byte (0x101d), read_byte (0x101e), read_byte (0x101f)

h) write_word (0x201c)  last iteration of the minor loop  major loop complete

14. eDMA engine writes: TCD.SADDR = 0x1000, TCD.DADDR = 0x2000,

TCD.CITER = 2 (TCD.BITER).

15. eDMA engine writes: TCD.ACTIVE = 0, TCD.DONE = 1, EDMA_IRQRn=1.

16. The channel retires  major loop complete.

The eDMA goes idle or services the next channel.

18.7.5.3 Modulo feature

The modulo feature of the eDMA provides the ability to easily implement a circular data queue in which

the size of the queue is a power of 2. MOD is a 5-bit field for the source and destination in the TCD, and

specifies which lower address bits are incremented from their original value after the address + offset

calculation. All upper address bits remain the same as in the original value. Clearing this field to 0 disables

the modulo feature.

Table 18-24 shows how the transfer addresses are specified based on the setting of the MOD field. Here a

circular buffer is created where the address wraps to the original value while the 28 upper address bits

(0x1234567x) retain their original value. In this example the source address is set to 0x12345670, the

offset is set to 4 bytes and the mod field is set to 4, allowing for a 24 byte (16-byte) size queue.

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18.7.6 TCD status

18.7.6.1 Minor loop complete

There are two methods to test for minor loop completion when using software initiated service requests.

The first method is to read the TCD.CITER field and test for a change. Another method can be extracted

from the following sequence. The second method is to test the TCD.START bit AND the TCD.ACTIVE

bit. The minor loop complete condition is indicated by both bits reading zero after the TCD.START was

written to a one. Polling the TCD.ACTIVE bit can be inconclusive because the active status can be missed

if the channel execution is short in duration.

The TCD status bits execute the following sequence for a software activated channel:

1. TCD.START = 1, TCD.ACTIVE = 0, TCD.DONE = 0 (issued service request via software)

2. TCD.START = 0, TCD.ACTIVE = 1, TCD.DONE = 0 (executing)

3. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 0 (completed minor loop and is idle) or

4. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 1 (completed major loop and is idle)

The best method to test for minor loop completion when using hardware initiated service requests is to

read the TCD.CITER field and test for a change. The hardware request and acknowledge handshakes

signals are not visible in the programmer’s model.

The TCD status bits execute the following sequence for a hardware activated channel:

1. eDMA peripheral request asserts (issued service request via hardware)

2. TCD.START = 0, TCD.ACTIVE = 1, TCD.DONE = 0 (executing)

3. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 0 (completed minor loop and is idle) or

4. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 1 (completed major loop and is idle)

For both activation types, the major loop complete status is explicitly indicated via the TCD.DONE bit.

The TCD.START bit is cleared automatically when the channel begins execution regardless of how the

channel was activated.

Table 18-24. Modulo feature example

Transfer Number Address

1 0x12345670

2 0x12345674

3 0x12345678

4 0x1234567C

5 0x12345670

6 0x12345674

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18.7.6.2 Active channel TCD reads

the eDMA reads the true TCD.SADDR, TCD.DADDR, and TCD.NBYTES values if read while a channel

is executing. The true values of the SADDR, DADDR, and NBYTES are the values the eDMA engine is

currently using in its internal register file and not the values in the TCD local memory for that channel.

The addresses (SADDR and DADDR) and NBYTES (decrements to zero as the transfer progresses) can

give an indication of the progress of the transfer. All other values are read back from the TCD local

memory.

18.7.6.3 Preemption status

Preemption is only available when fixed arbitration is selected for both group and channel arbitration

modes. A preempt-able situation is one in which a preempt-enabled channel is running and a higher

priority request becomes active. When the eDMA engine is not operating in fixed group, fixed channel

arbitration mode, the determination of the relative priority of the actively running and the outstanding

requests become undefined. Channel and/or group priorities are treated as equal (or more exactly,

constantly rotating) when round-robin arbitration mode is selected.

The TCD.ACTIVE bit for the preempted channel remains asserted throughout the preemption. The

preempted channel is temporarily suspended while the preempting channel executes one iteration of the

major loop. Two TCD.ACTIVE bits set at the same time in the overall TCD map indicates a higher priority

channel is actively preempting a lower priority channel.

18.7.7 Channel linking

Channel linking (or chaining) is a mechanism where one channel sets the TCD.START bit of another

channel (or itself) thus initiating a service request for that channel. This operation is automatically

performed by the eDMA engine at the conclusion of the major or minor loop when properly enabled.

The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major

loop). The TCD.CITER.E_LINK field determines whether a minor loop link is requested. When enabled,

the channel link is made after each iteration of the minor loop except for the last.

When the major loop is exhausted, only the major loop channel link fields are used to determine whether

to make a channel link. For example, with the initial fields of:

TCD.CITER.E_LINK = 1

TCD.CITER.LINKCH = 0xC

TCD.CITER value = 0x4

TCD.MAJOR.E_LINK = 1

TCD.MAJOR.LINKCH = 0x7

channel linking executes as:

1. Minor loop done  set channel 12 TCD.START bit

2. Minor loop done  set channel 12 TCD.START bit

3. Minor loop done  set channel 12 TCD.START bit

4. Minor loop done, major loop done  set channel 7 TCD.START bit

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When minor loop linking is enabled (TCD.CITER.E_LINK = 1), the TCD.CITER field uses a nine bit

vector to form the current iteration count.

When minor loop linking is disabled (TCD.CITER.E_LINK = 0), the TCD.CITER field uses a 15-bit

vector to form the current iteration count. The bits associated with the TCD.CITER.LINKCH field are

concatenated onto the CITER value to increase the range of the CITER.

NOTE

After configuration, the TCD.CITER.E_LINK bit and the

TCD.BITER.E_LINK bit must be equal or a configuration error is reported.

The CITER and BITER vector widths must be equal to calculate the major

loop, half-way done interrupt point.

Table 18-25 summarizes how a DMA channel can “link” to another DMA channel, i.e, use another

channel’s TCD, at the end of a loop.

18.7.8 Dynamic programming

This section provides recommended methods to change the programming model during channel execution.

18.7.8.1 Dynamic channel linking and dynamic scatter/gather

Dynamic channel linking and dynamic scatter/gather is the process of changing the

TCD.MAJOR.E_LINK or TCD.E_SG bits during channel execution. These bits are read from the TCD

local memory at the end of channel execution thus allowing the user to enable either feature during channel

execution.

Because the user is allowed to change the configuration during execution, a coherency model is needed.

Consider the scenario where the user attempts to execute a dynamic channel link by enabling the

TCD.MAJOR.E_LINK bit at the same time the eDMA engine is retiring the channel. The

TCD.MAJOR.E_LINK is set in the programmer’s model, but it is unclear whether the link completed

before the channel retired.

Use the following coherency model when executing a dynamic channel link or dynamic scatter/gather

request:

1. Set the TCD.MAJOR.E_LINK bit

Table 18-25. Channel linking parameters

Desired Link

Behavior TCD Control Field Name Description

Link at end of

Minor Loop

citer.e_link Enable channel-to-channel linking on minor loop

completion (current iteration)

citer.linkch Link channel number when linking at end of minor loop

(current iteration)

Link at end of

Major Loop

major.e_link Enable channel-to-channel linking on major loop

completion

major.linkch Link channel number when linking at end of major loop

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2. Read the TCD.MAJOR.E_LINK bit

3. Test the TCD.MAJOR.E_LINK request status:

a) If the bit is set, the dynamic link attempt was successful.D

b) If the bit is cleared, the channel had already retired before the dynamic link completed.

This same coherency model is true for dynamic scatter/gather operations. For both dynamic requests, the

TCD local memory controller forces the TCD.MAJOR.E_LINK and TCD.E_SG bits to zero on any writes

to a channel’s TCD after that channel’s TCD.DONE bit is set indicating the major loop is complete.

NOTE

The user must clear the TCD.DONE bit before writing the

TCD.MAJOR.E_LINK or TCD.E_SG bits. The TCD.DONE bit is cleared

automatically by the eDMA engine after a channel begins execution.

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Chapter 19

DMA Channel Mux (DMA_MUX)

19.1 Introduction

19.1.1 Overview

The DMA Mux allows to route a configurable amount of DMA sources (slots) to a configurable amount

of DMA channels. This is illustrated in Figure 19-1.

Figure 19-1. DMA Mux block diagram

19.1.2 Features

The DMA Mux has these major features:

• 16 independently selectable DMA channel routers

— 4 channels with normal or periodic triggering capability

— 12 channels with normal capability

Source #1

Source #2

Source #3

Source #21

DMA Channel #1

DMA Channel #15

DMA Channel #0

DMA_CH_MUX

Trigger #1

Trigger #4

Always #1

Always #9

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• Each channel router can be assigned to 1 of 21 possible peripheral DMA sources

19.1.3 Modes of operation

The following operation modes are available:

• Disabled Mode

In this mode, the DMA channel is disabled. Since disabling and enabling of DMA channels is done

primarily via the DMA configuration registers, this mode is used mainly as the reset state for a

DMA channel in the DMA Channel Mux. It may also be used to temporarily suspend a DMA

channel while reconfiguration of the system takes place (for example, changing the period of a

DMA trigger).

• Normal Mode

In this mode, a DMA source (such as DSPI_0_TX or DSPI_0_RX example) is routed directly to

the specified DMA channel. The operation of the DMA Mux in this mode is completely transparent

to the system.

• Periodic Trigger Mode

In this mode, a DMA source may only request a DMA transfer (such as when a transmit buffer

becomes empty or a receive buffer becomes full) periodically. Configuration of the period is done

in the registers of the Periodic Interrupt Timer (PIT).

DMA channels 0–3 may be used in all the modes listed above but channels 4–15 may be configured only

to disabled or normal mode.

19.2 External signal description

19.2.1 Overview

The DMA Mux has no external pins.

19.3 Memory map and register definition

This section provides a detailed description of all memory-mapped registers in the DMA Mux.

19.3.1 Memory map

Table 19-1 shows the memory map for the DMA Mux. Note that all addresses are offsets; the absolute

address may be computed by adding the specified offset to the base address of the DMA Mux.

Table 19-1. DMA_MUX memory map

Offset from

DMA_MUX_BASE

(0xFFFD_C000)

0x0000 Channel #0 Configuration (CHCONFIG0) on page 428

0x0001 Channel #1 Configuration (CHCONFIG1) on page 428

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0x0002 Channel #2 Configuration (CHCONFIG2) on page 428

0x0003 Channel #3 Configuration (CHCONFIG3) on page 428

0x0004 Channel #4 Configuration (CHCONFIG4) on page 428

0x0005 Channel #5 Configuration (CHCONFIG5) on page 428

0x0006 Channel #6 Configuration (CHCONFIG6) on page 428

0x0007 Channel #7 Configuration (CHCONFIG7) on page 428

0x0008 Channel #8 Configuration (CHCONFIG8) on page 428

0x0009 Channel #9 Configuration (CHCONFIG9) on page 428

0x000A Channel #10 Configuration (CHCONFIG10) on page 428

0x000B Channel #11 Configuration (CHCONFIG11) on page 428

0x000C Channel #12 Configuration (CHCONFIG12) on page 428

0x000D Channel #13 Configuration (CHCONFIG13) on page 428

0x000E Channel #14 Configuration (CHCONFIG14) on page 428

0x000F Channel #15 Configuration (CHCONFIG15) on page 428

0x0010 Channel #16 Configuration (CHCONFIG16) on page 428

0x0011 Channel #17 Configuration (CHCONFIG17) on page 428

0x0012 Channel #18 Configuration (CHCONFIG18) on page 428

0x0013 Channel #19 Configuration (CHCONFIG19) on page 428

0x0014 Channel #20 Configuration (CHCONFIG20) on page 428

0x0015 Channel #21 Configuration (CHCONFIG21) on page 428

0x0016 Channel #22 Configuration (CHCONFIG22) on page 428

0x0017 Channel #23 Configuration (CHCONFIG23) on page 428

0x0018 Channel #24 Configuration (CHCONFIG24) on page 428

0x0019 Channel #25 Configuration (CHCONFIG25) on page 428

0x001A Channel #26 Configuration (CHCONFIG26) on page 428

0x001B Channel #27 Configuration (CHCONFIG27) on page 428

0x001C Channel #28 Configuration (CHCONFIG28) on page 428

0x001D Channel #29 Configuration (CHCONFIG29) on page 428

0x001E Channel #30 Configuration (CHCONFIG30) on page 428

0x001F–0x3FFF Reserved

Table 19-1. DMA_MUX memory map (continued)

Offset from

DMA_MUX_BASE

(0xFFFD_C000)

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All registers are accessible via 8-bit, 16-bit or 32-bit accesses. However, 16-bit accesses must be aligned

to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example,

CHCONFIG0 through CHCONFIG3 are accessible by a 32-bit READ/WRITE to address ‘Base +

0x0000’, but performing a 32-bit access to address ‘Base + 0x0001’ is illegal.

19.3.2 Register descriptions

19.3.2.1 Channel Configuration Registers

Each of the DMA channels can be independently enabled/disabled and associated with one of the #SRC +

#ALE total DMA sources in the system.

Address: Base + #n Access: User read/write

76543210

ENBL TRIG SOURCE

Reset00000000

Figure 19-2. Channel Configuration Registers (CHCONFIG#n)

Table 19-2. CHCONFIG#x field descriptions

Field Description

ENBL

DMA Channel Enable

ENBL enables the DMA Channel.

0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The

DMA has separate channel enables/disables that should be used to disable or reconfigure a DMA

channel.

1 DMA channel is enabled.

TRIG

DMA Channel Trigger Enable (for triggered channels only)

TRIG enables the periodic trigger capability for the DMA Channel.

0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel routes the

specified source to the DMA channel.

1 Triggering is enabled.

5–0

SOURCE

DMA Channel Source (slot)

SOURCE specifies which DMA source, if any, is routed to a particular DMA channel. See Table 19-4.

Table 19-3. Channel and trigger enabling

ENBL TRIG Function Mode

0 X DMA Channel is disabled Disabled Mode

1 0 DMA Channel is enabled with no triggering (transparent) Normal Mode

1 1 DMA Channel is enabled with triggering Periodic Trigger

Mode

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NOTE

Setting multiple CHCONFIG registers with the same Source value will

result in unpredictable behavior.

NOTE

Before changing the trigger or source settings a DMA channel must be

disabled via the CHCONFIG[#n].ENBL bit.

19.4 DMA request mapping

Table 19-4. DMA channel mapping

DMA_CH_MUX

channel Module DMA requesting

module DMA Mux input #

1 DSPI_0 DSPI_0 TX DMA MUX Source #1

2 DSPI_0 DSPI_0 RX DMA MUX Source #2

3 DSPI_1 DSPI_1 TX DMA MUX Source #3

4 DSPI_1 DSPI_1 RX DMA MUX Source #4

5 DSPI_2 DSPI_2 TX DMA MUX Source #5

6 DSPI_2 DSPI_2 RX DMA MUX Source #6

7 Not connected DMA MUX Source #7

8 Not connected DMA MUX Source #8

9 CTU_0 CTU DMA MUX Source #9

10 CTU_0 CTU FIFO 1 DMA MUX Source #10

11 CTU_0 CTU FIFO 2 DMA MUX Source #11

12 CTU_0 CTU FIFO 3 DMA MUX Source #12

13 CTU_0 CTU FIFO 4 DMA MUX Source #13

14 flexpwm_0 FlexPWM WR DMA MUX Source #14

15 Not connected DMA MUX Source #15

16 etimer_0 eTimer_0 CH0 DMA MUX Source #16

17 etimer_0 eTimer_0 CH1 DMA MUX Source #17

18 Not connected DMA MUX Source #18

19 Not connected DMA MUX Source #19

20 adc_0 ADC_0 DMA MUX Source #20

21 Not connected DMA MUX Source #21

22 — ALWAYS requestors DMA MUX Source #22

23 — ALWAYS requestors DMA MUX Source #23

24 — ALWAYS requestors DMA MUX Source #24

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19.5 Functional description

This section provides a complete functional description of the DMA Mux. The primary purpose of the

DMA Mux is to provide flexibility in the system’s use of the available DMA channels. As such,

configuration of the DMA Mux is intended to be a static procedure done during execution of the system

boot code. However, if the procedure outlined in Section 19.6.2, “Enabling and configuring sources is

followed, the configuration of the DMA Mux may be changed during the normal operation of the system.

Functionally, the DMA Mux channels may be divided into two classes: Channels that implement the

normal routing functionality plus periodic triggering capability, and channels that implement only the

normal routing functionality.

19.5.1 DMA channels with periodic triggering capability

Besides the normal routing functionality, the first four channels of the DMA Mux provide a special

periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes,

frames or packets at fixed intervals without the need for processor intervention. The trigger is generated

by the Periodic Interrupt Timer (PIT); as such, the configuration of the periodic triggering interval is done

via configuration registers in the PIT. Please refer to Chapter 30, “Periodic Interrupt Timer (PIT) for more

information on this topic.

NOTE

Because of the dynamic nature of the system (i.e., DMA channel priorities,

bus arbitration, interrupt service routine lengths, etc.), the number of clock

cycles between a trigger and the actual DMA transfer cannot be guaranteed.

25 — ALWAYS requestors DMA MUX Source #25

26 — ALWAYS requestors DMA MUX Source #26

27 — ALWAYS requestors DMA MUX Source #27

28 — ALWAYS requestors DMA MUX Source #28

29 — ALWAYS requestors DMA MUX Source #29

30 — ALWAYS requestors DMA MUX Source #30

Table 19-4. DMA channel mapping (continued)

DMA_CH_MUX

channel Module DMA requesting

module DMA Mux input #

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Figure 19-3. DMA mux triggered channels diagram

The DMA channel triggering capability allows the system to “schedule” regular DMA transfers, usually

on the transmit side of certain peripherals, without the intervention of the processor. This trigger works by

gating the request from the peripheral to the DMA until a trigger event has been seen. This is illustrated in

Figure 19-4.

Figure 19-4. DMA mux channel triggering: normal operation

Once the DMA request has been serviced, the peripheral will negate its request, effectively resetting the

gating mechanism until the peripheral re-asserts its request AND the next trigger event is seen. This means

that if a trigger is seen, but the peripheral is not requesting a transfer, that triggered will be ignored. This

situation is illustrated in Figure 19-5.

DMA Channel #0

DMA Channel #3

Trigger #4

Trigger #2

Trigger #1

Source #1

Source #2

Source #3

Source #21

Always #1

Always #9

Peripheral Request

Tr i g g e r

DMA Request

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Figure 19-5. DMA mux channel triggering: ignored trigger

This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful

for two types of situations:

• Periodically polling external devices on a particular bus. As an example, the transmit side of an SPI

is assigned to a DMA channel with a trigger, as described above. Once setup, the SPI will request

DMA transfers (presumably from memory) as long as its transmit buffer is empty. By using a

trigger on this channel, the SPI transfers can be automatically performed every 5 µs (as an

example). On the receive side of the SPI, the SPI and DMA can be configured to transfer receive

data into memory, effectively implementing a method to periodically read data from external

devices and transfer the results into memory without processor intervention.

• Using the GPIO Ports to drive or sample waveforms. By configuring the DMA to transfer data to

one or more GPIO ports, it is possible to create complex waveforms using tabular data stored in

on-chip memory. Conversely, using the DMA to periodically transfer data from one or more GPIO

ports, it is possible to sample complex waveforms and store the results in tabular form in on-chip

memory.

A more detailed description of the capability of each trigger (for example, resolution, range of values, etc.)

may be found in Chapter 30, “Periodic Interrupt Timer (PIT).

Peripheral Request

Tr i g g e r

DMA Request

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19.5.2 DMA channels with no triggering capability

Channels 4–15 of the DMA Mux provide the normal routing functionality as described in Section 19.1.3,

“Modes of operation.

Figure 19-6. DMA mux channel 4–15 block diagram

19.6 Initialization/application information

19.6.1 Reset

The reset state of each individual bit is shown within the register description section (see Section 19.3.2,

“Register descriptions). In summary, after reset, all channels are disabled and must be explicitly enabled

before use.

19.6.2 Enabling and configuring sources

Enabling a source with periodic triggering:

1. Determine with which DMA channel the source will be associated. Remember that only the first

four DMA channels have periodic triggering capability.

2. Clear the ENBL and TRIG bits of the DMA channel.

Source #1

Source #2

Source #3

Source #21

Always #1

Always #9

DMA Channel #4

DMA Channel #15

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3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be

enabled at this point.

4. In the PIT, configure the corresponding timer.

5. Select the source to be routed to the DMA channel. Write to the corresponding CHCONFIG

Example 19-1. Configure source #5 Transmit for use with DMA channel 2, with periodic triggering capability

1. Write 0x00 to CHCONFIG2 (Base Address + 0x02).

2. Configure Channel 2 in the DMA, including enabling the channel.

3. Configure Timer 3 in the Periodic Interrupt Timer (PIT) for the desired trigger interval.

4. Write 0xC5 to CHCONFIG2 (Base Address + 0x02).

The following code example illustrates steps 1 and 4 above:

In File registers.h:

#define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */

/* Following example assumes char is 8-bits */

volatile unsigned char *CHCONFIG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000);

volatile unsigned char *CHCONFIG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001);

volatile unsigned char *CHCONFIG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002);

volatile unsigned char *CHCONFIG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003);

volatile unsigned char *CHCONFIG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004);

volatile unsigned char *CHCONFIG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005);

volatile unsigned char *CHCONFIG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006);

volatile unsigned char *CHCONFIG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007);

volatile unsigned char *CHCONFIG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008);

volatile unsigned char *CHCONFIG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009);

volatile unsigned char *CHCONFIG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A);

volatile unsigned char *CHCONFIG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B);

volatile unsigned char *CHCONFIG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C);

volatile unsigned char *CHCONFIG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D);

volatile unsigned char *CHCONFIG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E);

volatile unsigned char *CHCONFIG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F);

In File main.c:

#include "registers.h"

*CHCONFIG2 = 0x00;

*CHCONFIG2 = 0xC5;

Enabling a source without periodic triggering:

1. Determine with which DMA channel the source will be associated. Remember that only DMA

channels 0–7 have periodic triggering capability.

2. Clear the ENBL and TRIG bits of the DMA channel.

3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be

enabled at this point.

4. Select the source to be routed to the DMA channel. Write to the corresponding CHCONFIG

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Example 19-2. Configure source #5 Transmit for use with DMA Channel 2, with no periodic triggering

capability.

1. Write 0x00 to CHCONFIG2 (Base Address + 0x02).

2. Configure Channel 2 in the DMA, including enabling the channel.

3. Write 0x85 to CHCONFIG2 (Base Address + 0x02).

The following code example illustrates steps 1 and 3 above: