SEMICONDUCTOR TECHNICAL DATA ! High-Performance Silicon-Gate CMOS The MC54/74HC4049 consists of six inverting buffers, and the MC54/74HC4050 consists of six noninverting buffers. They are identical in pinout to the MC14049UB and MC14050B metal-gate CMOS buffers. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The input protection circuitry on these devices has been modified by eliminating the VCC diodes to allow the use of input voltages up to 15 volts. Thus, the devices may be used as logic-level translators that convert from a high voltage to a low voltage while operating at the low-voltage power supply. They allow MC14000-series CMOS operating up to 15 volts to be interfaced with High-Speed CMOS at 2 to 6 volts. The protection diodes to GND are Zener diodes, which protect the inputs from both positive and negative voltage transients. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 5 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 36 FETs or 9 Equivalent Gates (4049) 24 FETs or 6 Equivalent Gates (4050) J SUFFIX CERAMIC PACKAGE CASE 620-10 16 1 N SUFFIX PLASTIC PACKAGE CASE 648-08 16 1 D SUFFIX SOIC PACKAGE CASE 751B-05 16 1 ORDERING INFORMATION MC54HCXXXXJ MC74HCXXXXN MC74HCXXXXD Ceramic Plastic SOIC PIN ASSIGNMENT LOGIC DIAGRAMS HC4049 (INVERTING BUFFER) 2 A0 4 A1 A2 A3 7 6 9 10 11 12 VCC 1 16 NC Y0 2 15 Y5 A0 3 14 A5 Y1 4 13 NC A1 5 12 Y4 Y2 6 11 A4 A2 7 10 Y3 GND 8 9 A3 HC4050 (NONINVERTING BUFFER) Y0 A0 Y1 A1 Y2 A2 Y3 A3 2 3 4 5 7 6 9 10 11 12 Y0 Y1 Y2 NC = NO CONNECTION Y3 FUNCTION TABLE A4 A5 14 15 Y4 Y5 A4 A5 14 15 Y4 Y5 PIN 1 = VCC PIN 8 = GND PINS 13, 16 = NO CONNECTION 10/95 Motorola, Inc. 1995 1 REV 6 Y Outputs A Input HC4049 HC4060 L H H L L H IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII MC54/74HC4049 MC54/74HC4050 MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Vin DC Input Voltage (Referenced to GND) Vout DC Output Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0 V - 1.5 to + 18 V - 0.5 to VCC + 0.5 V DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package 750 500 mW Tstg Storage Temperature - 65 to + 150 _C Iin TL This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields referenced to the GND pin, only. Extra precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, the ranges GND Vin 15 V and GND Vout VCC are recommended. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP) v v v 260 300 v * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIII IIII IIIIIIIIIIIIII IIIIII IIIIII IIIIIIIII IIIIIIIIIIIII IIIIIIIII IIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III v v IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII v IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Min DC Supply Voltage (Referenced to GND) Max Unit 2.0 6.0 V Vin DC Input Voltage (Referenced to GND) 0 VCC to 15 V Vout DC Output Voltage (Referenced to GND) 0 VCC V - 55 + 125 _C 0 0 0 1000 500 400 ns TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V - 55 to 25_C 85_C 125_C Unit VIH Minimum High-Level Input Voltage Vout = VCC - 0.1 V |Iout| 20 A 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V Minimum High-Level Output Voltage Vin = VIH |Iout| 20 A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 4.5 6.0 0.26 0.26 0.33 0.33 0.40 0.40 6.0 6.0 0.1 0.5 1.0 5.0 1.0 5.0 VOH Vin = VIH or VIL |Iout| |Iout| VOL Maximum Low-Level Output Voltage Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| |Iout| Iin Maximum Input Leakage Current 4.0 mA 5.2 mA Vin = VCC or GND Vin = 15 V 4.0 mA 5.2 mA V A Vin = 15 V or GND 6.0 2 20 40 A Iout = 0 A NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). ICC MOTOROLA Maximum Quiescent Supply Current (per Package) 2 High-Speed CMOS Logic Data DL129 -- Rev 6 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII v IIII v III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII MC54/74HC4049 MC54/74HC4050 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit VCC V - 55 to 25_C 85_C 125_C tPLH, tPHL Maximum Propagation Delay, Input A to Output Y (Figures 1 and 2) 2.0 4.5 6.0 85 17 14 105 21 18 130 26 22 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns 10 10 10 pF Symbol Cin Parameter Maximum Input Capacitance Unit NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Buffer)* pF 27 * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). tr tf tr 90% 50% 10% INPUT A tPHL GND tPLH tPLH tTHL 90% 50% 10% tTLH Figure 1a. Switching Waveforms (HC4049) GND tPHL OUTPUT Y tTLH VCC 90% 50% 10% INPUT A 90% 50% 10% OUTPUT Y tf VCC tTHL Figure 1b. Switching Waveforms (HC4050) TEST POINT OUTPUT DEVICE UNDER TEST CL* * Includes all probe and jig capacitance Figure 2. Test Circuit High-Speed CMOS Logic Data DL129 -- Rev 6 3 MOTOROLA MC54/74HC4049 MC54/74HC4050 LOGIC DETAIL HC4049 (1/6 of the Device) A Y HC4050 (1/6 of the Device) A Y TYPICAL APPLICATIONS LSTTL to Low-Voltalge HSCMOS 5V High-Voltage CMOS to HSCMOS 3V IN VDD* OUT LSTTL DEVICE HC4049 HC4050 IN OUT IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII HC DEVICE STANDARD CMOS HC4049 HC4050 HC DEVICE *Table 1. Supply Examples NOTE: To determine the noise immunity for the LSTTL to low-voltage configuration, use Eq. 1 and Eq. 2: (TTL) VOH - (CMOS) VIH Eq. 1 (TTL) VOL - (CMOS) VIL Eq. 2 For the supply levels shown: 2.4 - 3 (75%) = 2.4 - 2.25 = 0.15 V 0.4 - 3 (15%) = 0.4 - 0.45 = 0.05 V Therefore, worst case noise immunity is 50 mV. For supply levels greater than 4.5 volts use the 74HCT04A for direct interface to TTL outputs. MOTOROLA VCC* 4 VDD VCC 15 V 2V 12 V 5V 12 V 3V High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC4049 MC54/74HC4050 OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 620-10 ISSUE V -A - 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. -B - L C DIM A B C D E F G J K L M N -T K N SEATING - PLANE E M F J 16 PL 0.25 (0.010) G D 16 PL 0.25 (0.010) T A M 9 1 8 T B N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R -A - 16 M C DIM A B C D F G H J K L M S L S -T - SEATING PLANE K H D 16 PL 0.25 (0.010) M M J G T A M D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A - 16 1 P 8 PL 0.25 (0.010) 8 M B M G K F R X 45 C -T SEATING - PLANE J M D 16 PL 0.25 (0.010) High-Speed CMOS Logic Data DL129 -- Rev 6 M T B S A S 5 INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B - MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 -- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B F S S INCHES MIN MAX 0.750 0.785 0.240 0.295 -- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 MOTOROLA MC54/74HC4049 MC54/74HC4050 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA CODELINE 6 *MC54/74HC4049/D* MC54/74HC4049/D High-Speed CMOS Logic Data DL129 -- Rev 6