MC74HC4050N - Motorola / Freescale Semiconductor



SEMICONDUCTOR TECHNICAL DATA

1REV 6

 Motorola, Inc. 1995

10/95

! 

  

High–Performance Silicon–Gate CMOS

The MC54/74HC4049 consists of six inverting buffers, and the

MC54/74HC4050 consists of six noninverting buffers. They are identical in

pinout to the MC14049UB and MC14050B metal–gate CMOS buffers. The

device inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

The input protection circuitry on these devices has been modified by

eliminating the VCC diodes to allow the use of input voltages up to 15 volts.

Thus, the devices may be used as logic–level translators that convert from a

high voltage to a low voltage while operating at the low–voltage power

supply. They allow MC14000–series CMOS operating up to 15 volts to be

interfaced with High–Speed CMOS at 2 to 6 volts. The protection diodes to

GND are Zener diodes, which protect the inputs from both positive and

negative voltage transients.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 5 µA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

•Chip Complexity: 36 FETs or 9 Equivalent Gates (4049)

24 FETs or 6 Equivalent Gates (4050)

LOGIC DIAGRAMS

Y0A0

PIN 1 = VCC

PIN 8 = GND

PINS 13, 16 = NO CONNECTION

HC4049

(INVERTING BUFFER)

Y0A0

HC4050

(NONINVERTING BUFFER)





PIN ASSIGNMENT

FUNCTION TABLE

125

VCC

GND

AY Outputs

Input HC4049 HC4060

L H L

H L H

NC = NO CONNECTION

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC54HCXXXXJ

MC74HCXXXXN

MC74HCXXXXD

Ceramic

Plastic

SOIC

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

MC54/74HC4049 MC54/74HC4050

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 1.5 to + 18

ÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎÎ

± 20

ÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

± 25

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

± 50

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

ÎÎÎÎÎÎ

750

500

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

(Ceramic DIP)

ÎÎÎÎÎÎ

260

300

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/

C from 65

to 125

Ceramic DIP: – 10 mW/

C from 100

to 125

SOIC Package: – 7 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎ

VCC

to 15

ÎÎÎ

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

1000

500

400

ÎÎÎ

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = VCC – 0.1 V

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

1.5

3.15

4.2

ÎÎÎÎ

1.5

3.15

4.2

ÎÎÎÎ

1.5

3.15

4.2

ÎÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

0.3

0.9

1.2

ÎÎÎÎ

0.3

0.9

1.2

ÎÎÎÎ

0.3

0.9

1.2

ÎÎÎ

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout|

4.0 mA

|Iout|

5.2 mA

ÎÎÎÎ

4.5

6.0

ÎÎÎ

3.98

5.48

ÎÎÎÎ

3.84

5.34

ÎÎÎÎ

3.70

5.20

ÎÎÎ

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout|

4.0 mA

|Iout|

5.2 mA

ÎÎÎÎ

4.5

6.0

ÎÎÎ

0.26

ÎÎÎÎ

0.33

ÎÎÎÎ

0.40

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

Vin = 15 V

ÎÎÎÎ

6.0

ÎÎÎ

± 0.1

0.5

ÎÎÎÎ

± 1.0

5.0

ÎÎÎÎ

± 1.0

5.0

ÎÎÎ

µA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply

Current (per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = 15 V or GND

Iout = 0 µA

ÎÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains circuitry to

protect the inputs against damage

due to high static voltages or electric

fields referenced to the GND pin,

only. Extra precautions must be

taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance

circuit. For proper operation, the

ranges GND

Vin

15 V and

GND

Vout

VCC are recom-

mended.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

MC54/74HC4049 MC54/74HC4050

High–Speed CMOS Logic Data

DL129 — Rev 6 3 MOTOROLA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Input A to Output Y

(Figures 1 and 2)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

105

ÎÎÎÎ

130

ÎÎÎ

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 1 and 2)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

110

ÎÎÎ

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Buffer)*

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Buffer)*

*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

Figure 1a. Switching Waveforms (HC4049) Figure 1b. Switching Waveforms (HC4050)

INPUT A

tPLH

tPHL

trtfVCC

GND

tTHL tTLH

OUTPUT Y

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 2. Test Circuit

trtf

GND

tPHL

tPLH

tTLH tTHL

10%

50%

90%

10%

50%

90%

50%

10%

50%

90%

INPUT A

OUTPUT Y

VCC

MC54/74HC4049 MC54/74HC4050

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

HC4049

(1/6 of the Device)

HC4050

(1/6 of the Device)

LOGIC DETAIL

TYPICAL APPLICATIONS

LSTTL to Low–Voltalge HSCMOS High–Voltage CMOS to HSCMOS

IN OUT

3 V5 V

LSTTL

DEVICE HC4049

HC4050 HC DEVICE

IN OUT

VCC*VDD*

STANDARD

CMOS HC4049

HC4050 HC DEVICE

NOTE: To determine the noise immunity for the LSTTL to low–voltage

configuration, use Eq. 1 and Eq. 2:

(TTL) VOH – (CMOS) VIH Eq. 1

(TTL) VOL – (CMOS) VIL Eq. 2

For the supply levels shown:

2.4 – 3 (75%) = 2.4 – 2.25 = 0.15 V

0.4 – 3 (15%) = 0.4 – 0.45 = 0.05 V

Therefore, worst case noise immunity is 50 mV.

For supply levels greater than 4.5 volts use

the 74HCT04A for direct interface to TTL outputs.

*Table 1. Supply Examples

ÎÎÎÎÎ

VDD

ÎÎÎÎÎ

VCC

ÎÎÎÎÎ

15 V

ÎÎÎÎÎ

2 V

ÎÎÎÎÎ

12 V

ÎÎÎÎÎ

5 V

ÎÎÎÎÎ

12 V

ÎÎÎÎÎ

3 V

MC54/74HC4049 MC54/74HC4050

High–Speed CMOS Logic Data

DL129 — Rev 6 5 MOTOROLA

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

ISSUE V

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

19.05

6.10

—

0.39

1.40

0.21

3.18

19.93

7.49

5.08

0.50

1.65

0.38

4.31

0.51 15

1.01

1.27 BSC

2.54 BSC

7.62 BSC

MIN MINMAX MAX

INCHES MILLIMETERS

DIM 0.750

0.240

—

0.015

0.055

0.008

0.125

0.785

0.295

0.200

0.020

0.065

0.015

0.170

0.050 BSC

0.100 BSC

0.300 BSC

0.020 15

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIM F MAY NARROW TO 0.76 (0.030) WHERE

THE LEAD ENTERS THE CERAMIC BODY.

1 8

916

–A

–

–B

–

D 16 PL

–T

–

SEATING

PLANE

J 16 PL

0.25 (0.010) T A

MS0.25 (0.010) T B

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

1 8

916

HGD 16 PL

–T

–

SEATING

PLANE

KJM

T A0.25 (0.010) M M

0.25 (0.010) T B A

MS S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

9.80

3.80

1.35

0.35

0.40

0.19

0.10

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

916

–A

–

–B

–

D16 PL

–T

–

SEATING

PLANE

R X 45°

P 8 PL

0.25 (0.010) B

M M

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

MC54/74HC4049 MC54/74HC4050

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

How to reach us:

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and specifically disclaims any and all liability , including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different

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MC54/74HC4049/D

*MC54/74HC4049/D*

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