PE43711 Product Specification UltraCMOS(R) RF Digital Step Attenuator, 9 kHz-6 GHz Features Figure 1 * PE43711 Functional Diagram * Flexible attenuation steps of 0.25 dB, 0.5 dB and 1 dB up to 31.75 dB * Glitch-less attenuation state transitions Switched Attenuator Array RF Input RF Output * Monotonicity: 0.25 dB up to 4GHz, 0.5 dB up to 5 GHz and 1 dB up to 6 GHz * Extended +105 C operating temperature * Parallel and Serial programming interfaces * Packaging--24-lead 4 x 4 mm QFN Applications Parallel Control x7 * 3G/4G wireless infrastructure * Land mobile radio (LMR) system Serial In Control Logic Interface * Point-to-point communication system CLK LE P/S Product Description The PE43711 is a 50, HaRPTM technology-enhanced, 7-bit RF digital step attenuator (DSA) that supports a broad frequency range from 9 kHz to 6 GHz. It features glitch-less attenuation state transitions and supports 1.8V control voltage and an extended operating temperature range to +105 C, making this device ideal for many broadband wireless applications. The PE43711 is a pin-compatible upgraded version of the PE43502, PE43503, PE43602 and PE43702. An integrated digital control interface supports both Serial and Parallel programming of the attenuation, including the capability to program an initial attenuation state at power-up. The PE43711 covers a 31.75 dB attenuation range in 0.25 dB, 0.5 dB and 1 dB steps. It is capable of maintaining 0.25 dB monotonicity through 4 GHz, 0.5 dB monotonicity through 5 GHz and 1 dB monotonicity through 6 GHz. In addition, no external blocking capacitors are required if 0 VDC is present on the RF ports. The PE43711 is manufactured on Peregrine's UltraCMOS(R) process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate. (c)2014-2015, Peregrine Semiconductor Corporation. All rights reserved. * Headquarters: 9380 Carroll Park Drive, San Diego, CA, 92121 Product Specification DOC-44414-2 - (3/2015) www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Peregrine's HaRP technology enhancements deliver high linearity and excellent harmonics performance. It is an innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Absolute Maximum Ratings Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. ESD Precautions When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 1. Latch-up Immunity Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 1 * Absolute Maximum Ratings for PE43711 Parameter/Condition Min Max Unit Supply voltage, VDD -0.3 5.5 V Digital input voltage -0.3 3.6 V Figure 5 +31 dBm dBm +150 C ESD voltage HBM, all pins(1) 3000 V ESD voltage CDM, all pins(2) 1000 V RF input power, 50 9 kHz-48 MHz >48 MHz-6 GHz Storage temperature range -65 Notes: 1) Human body model (MIL-STD 883 Method 3015). 2) Charged device model (JEDEC JESD22-C101). Page 2 DOC-44414-2 - (3/2015) www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Recommended Operating Conditions Table 2 lists the recommending operating condition for the PE43711. Devices should not be operated outside the recommended operating conditions listed below. Table 2 * Recommended Operating Condition for PE43711 Parameter Min Supply voltage, VDD Typ 2.3 Supply current, IDD 150 Max Unit 5.5 V 200 A Digital input high 1.17 3.6 V Digital input low -0.3 0.6 V 17.5 A RF input power, CW(1) 9 kHz-48 MHz >48 MHz-6 GHz Figure 5 +23 dBm dBm RF input power, pulsed(2) 9 kHz-48 MHz >48 MHz-6 GHz Figure 5 +28 dBm dBm +105 C Digital input current Operating temperature range -40 +25 Notes: 1) 100% duty cycle, all bands, 50. 2) Pulsed, 5% duty cycle of 4620 s period, 50. DOC-44414-2 - (3/2015) Page 3 www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Electrical Specifications Table 3 provides the PE43711 key electrical specifications at 25 C, VDD = 3.3V, RF1 = RFIN, RF2 = RFOUT (ZS = ZL = 50), unless otherwise specified. Table 3 * PE43711 Electrical Specifications Parameter Condition Frequency Operating frequency Attenuation range Min Typ 9 kHz 0.25 dB step 0.5 dB step 1 dB step Unit 6 GHz As shown 0-31.75 0-31.50 0-31.00 9 kHz-1.0 GHz 1.0-2.2 GHz 2.2-4.0 GHz 4.0-6.0 GHz Insertion loss Max 1.3 1.6 1.9 2.4 dB dB dB 1.5 1.85 2.4 2.8 dB dB dB dB 0.25 dB step 0-31.75 dB 9 kHz-2.2 GHz (0.15 + 1.5% of attenuation setting) dB 0-31.75 dB >2.2-3.0 GHz (0.15 + 2.5% of attenuation setting) dB 0-31.75 dB >3.0-4.0 GHz (0.25 + 3.5% of attenuation setting) dB 0-31.5 dB 9 kHz-2.2 GHz (0.15 + 1.5% of attenuation setting) dB 0-31.5 dB >2.2-3.0 GHz (0.15 + 2.5% of attenuation setting) dB 0-31.5 dB >3.0-5.0 GHz (0.25 + 3.5% of attenuation setting) dB 9 kHz-2.2 GHz (0.15 + 1.5% of attenuation setting) dB >2.2-3.0 GHz (0.15 + 2.5% of attenuation setting) dB >3.0-5.0 GHz (0.25 + 3.5% of attenuation setting) dB >5.0-6.0 GHz (0.25 + 6.0% of attenuation setting) dB 0.5 dB step Attenuation error 1 dB step 0-31 dB 0-31 dB 0-31 dB 0-31 dB Return loss Input port or output port 9 kHz-4 GHz 4-6 GHz Page 4 14 16 dB dB DOC-44414-2 - (3/2015) www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Table 3 * PE43711 Electrical Specifications (Cont.) Parameter Relative phase Condition Frequency All states Input 0.1dB compression point(*) Min Typ Max Unit 9 kHz-4 GHz 4-6 GHz 31 48 deg deg 48 MHz-6 GHz 31 dBm 4 GHz 6 GHz 57 56 dBm dBm Input IP3 Two tones at +18 dBm, 20 MHz spacing RF Trise/Tfall 10%/90% RF 200 ns Settling time RF settled to within 0.05 dB of final value 1.6 s Switching time 50% CTRL to 90% or 10% RF 275 ns 0.3 dB Attenuation transient (envelope) 2 GHz Note: * The input 0.1dB compression point is a linearity figure of merit. Refer to Table 2 for the operating RF input power (50). DOC-44414-2 - (3/2015) Page 5 www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Switching Frequency Truth Tables The PE43711 has a maximum 25 kHz switching rate. Table 4-Table 5 provide the truth tables for the PE43711. Switching frequency is defined to be the speed at which the DSA can be toggled across attenuation states. Switching time is the time duration between the point the control signal reaches 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. Spurious Performance The typical spurious performance of the PE43711 is -130 dBm. Glitch-less Attenuation State Transitions The PE43711 features a novel architecture to provide the best-in-class glitch-less transition behavior when changing attenuation states. When RF input power is applied, the output power spikes are greatly reduced (0.3 dB) during attenuation state changes when comparing to previous generations of DSAs. Table 4 * Parallel Truth Table Parallel Control Setting D6 D5 D4 D3 D2 D1 D0 Attenuation Setting RF1-RF2 L L L L L L L Reference IL L L L L L L H 0.25 dB L L L L L H L 0.5 dB L L L L H L L 1 dB L L L H L L L 2 dB L L H L L L L 4 dB L H L L L L L 8 dB H L L L L L L 16 dB H H H H H H H 31.75 dB Table 5 * Serial Attenuation Word Truth Table Attenuation Word D7 D6 D5 D4 D3 D2 D1 D0 (LSB) Attenuation Setting RF1-RF2 L L L L L L L L Reference IL L L L L L L L H 0.25 dB L L L L L L H L 0.5 dB L L L L L H L L 1 dB L L L L H L L L 2 dB L L L H L L L L 4 dB L L H L L L L L 8 dB L H L L L L L L 16 dB L H H H H H H H 31.75 dB Page 6 DOC-44414-2 - (3/2015) www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Serial Register Map Figure 2 provides the Serial register map for the PE43711. Figure 2 * Serial Register Map MSB (last in) LSB (first in) Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 D7 D6 D5 D4 D3 D2 D1 D0 Bit must be set to logic low Attenuation Word The attenuation word is derived directly from the value of the attenuation state. To find the attenuation word, multiply the value of the state by four, then convert to binary. For example, to program the 12.5 dB state: 4 x 12.5 = 50 50 00110010 Serial Input: 00110010 DOC-44414-2 - (3/2015) Page 7 www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Programming Options that all Parallel control inputs be grounded when the DSA is used in Serial mode. Parallel/Serial Selection Power-up Control Settings Either a Parallel or Serial interface can be used to control the PE43711. The P/S bit provides this selection, with P/S = LOW selecting the Parallel interface and P/S = HIGH selecting the Serial interface. Parallel Mode Interface The Parallel interface consists of seven CMOScompatible control lines that select the desired attenuation state, as shown in Table 4. The Parallel interface timing requirements are defined by Figure 4 (Parallel Interface Timing Diagram), Table 8 (Parallel and Direct Interface AC Characteristics) and switching time (Table 3). For Latched Parallel programming, the Latch Enable (LE) should be held LOW while changing attenuation state control values then pulse LE HIGH to LOW (per Figure 4) to latch new attenuation state into the device. For Direct Parallel programming, the LE line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct mode is ideal for manual control of the device (using hardwire, switches or jumpers). Serial Interface The Serial interface is an 8-bit Serial-In, Parallel-Out shift register buffered by a transparent latch. The 8bits make up the Attenuation Word that controls the DSA. Figure 3 illustrates an example timing diagram for programming a state. The PE43711 will always initialize to the maximum attenuation setting (31.75 dB) on power-up for both the Serial and Latched Parallel modes of operation and will remain in this setting until the user latches in the next programming word. In Direct Parallel mode, the DSA can be preset to any state within the 31.75 dB range by pre-setting the Parallel control pins prior to power-up. In this mode, there is a 400 s delay between the time the DSA is powered-up to the time the desired state is set. During this power-up delay, the device attenuates to the maximum attenuation setting (31.75 dB) before defaulting to the user defined state. If the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). Dynamic operation between Serial and Parallel programming modes is possible. If the DSA powers up in Serial mode (P/S= HIGH), all the Parallel control inputs DI[6:0] must be set to logic LOW. Prior to toggling to Parallel mode, the DSA must be programmed serially to ensure D[7] is set to logic LOW. If the DSA powers up in either Latched or Direct Parallel mode, all Parallel pins DI[6:0] must be set to logic LOW prior to toggling to Serial mode (P/S= HIGH), and held LOW until the DSA has been programmed serially to ensure bit D[7] is set to logic LOW. The sequencing is only required once on power-up. Once completed, the DSA may be toggled between Serial and Parallel programming modes at will. The Serial interface is controlled using three CMOScompatible signals: SI, Clock (CLK) and LE. The SI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in LSB first. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. The Attenuation Word truth table is listed in Table 5. A programming example of the serial register is illustrated in Figure 2. The Serial timing diagram is illustrated in Figure 3. It is required Page 8 DOC-44414-2 - (3/2015) www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Figure 3 * Serial Timing Diagram Bits can either be set to logic high or logic low D[7] must be set to logic low DI[6:0] TDIH TDISU P/S TPSSU TPSIH D[0] SI D[1] D[2] D[3] D[4] D[5] D[6] D[7] TSISU TSIH CLK TCLKH TCLKL LE TLESU TLEPW DO[6:0] TPD Valid Figure 4 * Latched Parallel/Direct Parallel Timing Diagram P/S TPSSU TPSIH DI[6:0] Valid TDISU LE TDIH TLEPW DO[6:0] TDIPD Valid TPD Table 6 * Latch and Clock Specifications Latch Enable Shift Clock Function 0 Shift register clocked X Contents of shift register transferred to attenuator core DOC-44414-2 - (3/2015) Page 9 www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Table 7 * Serial Interface AC Characteristics(*) Parameter/Condition Min Serial clock frequency, FCLK Max Unit 10 MHz Serial clock HIGH time, TCLKH 30 ns Serial clock LOW time, TCLKL 30 ns Last Serial clock rising edge setup time to Latch Enable rising edge, TLESU 10 ns Latch Enable minimum pulse width, TLEPW 30 ns Serial data setup time, TSISU 10 ns Serial data hold time, TSIH 10 ns Parallel data setup time, TDISU 100 ns Parallel data hold time, TDIH 100 ns Address setup time, TASU 100 ns Address hold time, TAH 100 ns Parallel/Serial setup time, TPSSU 100 ns Parallel/Serial hold time, TPSIH 100 ns Digital register delay (internal), TPD 10 ns Max Unit Note: * VDD = 3.3V or 5.0V, -40 C < TA < +105 C, unless otherwise specified. Table 8 * Parallel and Direct Interface AC Characteristics(*) Parameter/Condition Min Latch Enable minimum pulse width, TLEPW 30 ns Parallel data setup time, TDISU 100 ns Parallel data hold time, TDIH 100 ns Parallel/Serial setup time, TPSSU 100 ns Parallel/Serial hold time, TPSIH 100 ns Digital register delay (internal), TPD 10 ns Digital register delay (internal, direct mode only), TDIPD 5 ns Note: * VDD = 3.3V or 5.0V, -40 C < TA < +105 C, unless otherwise specified. Page 10 DOC-44414-2 - (3/2015) www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Maximum RF Input Power (dBm) Figure 5 * Power De-rating Curve, 9 kHz-6 GHz, -40 to +105 C Ambient, 50 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 0.01 0.05 P0.1 dB Compression ( 48 MHz) Pulsed ( 48 MHz) CW & Pulsed (< 48 MHz) CW ( 48 MHz) 0.50 5.00 50.00 500.00 5000.00 Frequency (MHz) DOC-44414-2 - (3/2015) Page 11 www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Typical Performance Data Figure 6-Figure 32 show the typical performance data at 25 C and VDD = 3.3V, RF1 = RFIN, RF2 = RFOUT (ZS = ZL = 50) unless otherwise specified. Figure 6 * Insertion Loss vs Temperature -40C 25C 85C 105C 0 Insertion Loss (dB) -1 -2 -3 -4 -5 -6 0 1 2 3 4 5 6 Frequency (GHz) Page 12 DOC-44414-2 - (3/2015) www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Figure 7 * Input Return Loss vs Attenuation Setting 0 dB 0.25 dB 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 28 dB 31.75 dB 2 3 0 -5 Return Loss (dB) -10 -15 -20 -25 -30 -35 -40 -45 0 1 4 5 6 Frequency (GHz) Figure 8 * Output Return Loss vs Attenuation Setting 0 dB 0.25 dB 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 28 dB 31.75 dB 2 3 0 -5 Return Loss (dB) -10 -15 -20 -25 -30 -35 -40 -45 0 1 4 5 6 Frequency (GHz) DOC-44414-2 - (3/2015) Page 13 www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Figure 9 * Input Return Loss for 16 dB Attenuation Setting vs Temperature -40C 25C 85C 105C 0 -5 Return Loss (dB) -10 -15 -20 -25 -30 -35 -40 -45 0 1 2 3 4 5 6 5 6 Frequency (GHz) Figure 10 * Output Return Loss for 16 dB Attenuation Setting vs Temperature -40C 25C 85C 105C 0 Return Loss (dB) -5 -10 -15 -20 -25 -30 -35 0 1 2 3 4 Frequency (GHz) Page 14 DOC-44414-2 - (3/2015) www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Relative Phase Error (deg) Figure 11 * Relative Phase Error vs Attenuation Setting 0 dB 0.25 dB 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.75 dB 60 50 40 30 20 10 0 -10 0 1 2 3 4 5 6 Frequency (GHz) Figure 12 * Relative Phase Error for 31.75 dB Attenuation Setting vs Frequency 0.9 GHz 1.8 GHz 2.2 GHz 3 GHz 4 GHz 5 GHz 6 GHz Relative Phase Error (deg) 60 50 40 30 20 10 0 -40 25 85 105 Temperature (C) DOC-44414-2 - (3/2015) Page 15 www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Figure 13 * Attenuation Error @ 900 MHz vs Temperature -40C 25C 85C 105C Attenuation Error (dB) 0.5 0.25 0 -0.25 -0.5 0 4 8 12 16 20 24 28 32 24 28 32 Attenuation Setting (dB) Figure 14 * Attenuation Error @ 1800 MHz vs Temperature -40C 25C 85C 105C Attenuation Error (dB) 0.5 0.25 0 -0.25 -0.5 0 4 8 12 16 20 Attenuation Setting (dB) Page 16 DOC-44414-2 - (3/2015) www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Figure 15 * Attenuation Error @ 2200 MHz vs Temperature -40C 25C 85C 105C Attenuation Error (dB) 0.5 0.25 0 -0.25 -0.5 0 4 8 12 16 20 24 28 32 24 28 32 Attenuation Setting (dB) Figure 16 * Attenuation Error @3000 MHz vs Temperature -40C 25C 85C 105C Attenuation Error (dB) 0.75 0.5 0.25 0 -0.25 0 4 8 12 16 20 Attenuation Setting (dB) DOC-44414-2 - (3/2015) Page 17 www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Figure 17 * Attenuation Error @ 4000 MHz vs Temperature -40C 25C 85C 105C Attenuation Error (dB) 0.75 0.5 0.25 0 -0.25 0 4 8 12 16 20 24 28 32 Attenuation Setting (dB) Figure 18 * IIP3 vs Attenuation Setting 0 dB 3.5 dB 7.5 dB 11 dB 14 dB 17.5 dB 21.5 dB 24.75 dB 28 dB 31.75 dB Input IP3 (dBm) 70 65 60 55 50 3 4 5 6 Frequency (GHz) Page 18 DOC-44414-2 - (3/2015) www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Figure 19 * 0.25 dB Step Attenuation vs Frequency(*) 1 GHz 2.2 GHz 3 GHz 4 GHz 0.2 Step Attenuation (dB) 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 0 4 8 12 16 20 24 28 32 28 32 Attenuation Setting (dB) Note: * Monotonicity is held so long as step attenuation does not cross below -0.25 dB. Figure 20 * 0.25 dB Step, Actual vs Frequency 1 GHz 2.2 GHz 3 GHz 4 GHz Actual Attenuation (dB) 35 30 25 20 15 10 5 0 0 4 8 12 16 20 24 Ideal Attenuation (dB) DOC-44414-2 - (3/2015) Page 19 www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Figure 21 * 0.25 dB Major State Bit Error vs Attenuation Setting 0.25 dB 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.75 dB Attenuation Error (dB) 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0 1 2 3 4 Frequency (GHz) Figure 22 * 0.25 dB Attenuation Error vs Frequency 1 GHz 2.2 GHz 3 GHz 4 GHz Attenuation Error (dB) 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0 4 8 12 16 20 24 28 32 Attenuation Setting (dB) Page 20 DOC-44414-2 - (3/2015) www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Figure 23 * 0.5 dB Step Attenuation vs Frequency(*) 1 GHz 2.2 GHz 3 GHz 4 GHz 5 GHz 0.2 Step Attenuation (dB) 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 0 4 8 12 16 20 24 28 32 28 32 Attenuation Setting (dB) Note: * Monotonicity is held so long as step attenuation does not cross below -0.5 dB. Figure 24 * 0.5 dB Step, Actual vs Frequency 1 GHz 2.2 GHz 3 GHz 4 GHz 5 GHz 35 Actual Attenuation (dB) 30 25 20 15 10 5 0 0 4 8 12 16 20 24 Ideal Attenuation (dB) DOC-44414-2 - (3/2015) Page 21 www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Figure 25 * 0.5 dB Major State Bit Error vs Attenuation Setting 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.5 dB 1 Attenuation Error (dB) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0 1 2 3 4 5 Frequency (GHz) Figure 26 * 0.5 dB Attenuation Error vs Frequency 1 GHz 2.2 GHz 3 GHz 4 GHz 5 GHz 1 Attenuation Error (dB) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0 4 8 12 16 20 24 28 32 Attenuation Setting (dB) Page 22 DOC-44414-2 - (3/2015) www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Figure 27 * 1 dB Step Attenuation vs Frequency(*) 1 GHz 2.2 GHz 3 GHz 4 GHz 5 GHz 6 GHz 0.25 Step Attenuation (dB) 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 0 4 8 12 16 20 24 28 32 Attenuation Setting (dB) Note: * Monotonicity is held so long as step attenuation does not cross below -1 dB. Figure 28 * 1 dB Step, Actual vs Frequency 1 GHz 2.2 GHz 3 GHz 4 GHz 5 GHz 6 GHz 35 Actual Attenuation (dB) 30 25 20 15 10 5 0 0 4 8 12 16 20 24 28 32 Ideal Attenuation (dB) DOC-44414-2 - (3/2015) Page 23 www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Figure 29 * 1 dB Major State Bit Error vs Attenuation Setting 1 dB 2 dB 4 dB 8 dB 16 dB 31 dB 1 Attenuation Error (dB) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0 1 2 3 4 5 6 Frequency (GHz) Figure 30 * 1 dB Attenuation Error vs Frequency 1 GHz 2.2 GHz 3 GHz 4 GHz 5 GHz 6 GHz 1 Attenuation Error (dB) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0 4 8 12 16 20 24 28 32 Attenuation Setting (dB) Page 24 DOC-44414-2 - (3/2015) www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Figure 31 * Attenuation Transient (15.75-16 dB), Typical Switching Time = 275 ns Power (dBm) -15.4 Envelope Power (dBm) -15.6 Trigger starts ~730 ns -15.8 -16.0 -16.2 Glitch = 0.17 dB -16.4 -16.6 -16.8 -17.0 0 400 800 1200 1600 2000 2400 2800 3200 2800 3200 Time (ns) Figure 32 * Attenuation Transient (16-15.75 dB), Typical Switching Time = 275 ns Power (dBm) -15.4 Envelope Power (dBm) -15.6 Trigger starts ~730 ns -15.8 -16.0 Glitch = 0.03 dB -16.2 -16.4 -16.6 -16.8 -17.0 0 400 800 1200 1600 2000 2400 Time (ns) DOC-44414-2 - (3/2015) Page 25 www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Evaluation Kit Latched Parallel Programming Procedure The digital step attenuator evaluation board (EVB) was designed to ease customer evaluation of the PE43711 digital step attenuator. The PE43711 EVB supports Direct Parallel, Latched Parallel and Serial modes. For automated Latched Parallel programming, connect the USB dongle board and cable that is provided with the evaluation kit (EVK) from the USB port of the PC to the J5 header of the PE43711 EVB, and set the LE and D0-D6 SP3T switches to the EXT position. Position the Parallel/Serial (P/S) select switch to the Parallel position. The evaluation software is written to operate the DSA in Parallel mode. Ensure that the software GUI is set to Latched Parallel mode. Use the software GUI to enable the desired attenuation state. The software GUI automatically programs the DSA each time an attenuation state is enabled. Evaluation Kit Setup Connect the EVB with the USB dongle board and USB cable as shown in Figure 33. Direct Parallel Programming Procedure Direct Parallel programming is suitable for manual operation without software programming. For manual Direct Parallel programming, position the Parallel/ Serial (P/S) select switch to the Parallel position. The LE switch must be switched to HIGH position. Switches D0-D6 are SP3T switches that enable the user to manually program the parallel bits. When D0- D6 are toggled to the HIGH position, logic high is presented to the parallel input. When toggled to the LOW position, logic low is presented to the parallel input. Setting LE and D0-D6 to the EXT position presents as OPEN, which is set for software programming of Latched Parallel and Serial modes. Table 4 depicts the Parallel truth table. Serial Programming Procedure For automated Serial programming, connect the USB dongle board and cable that is provided with the EVK from the USB port of the PC to the J5 header of the PE43711 EVB, and set the LE and D0-D6 SP3T switches to the EXT position. Position the Parallel/ Serial (P/S) select switch to the Serial position. The software GUI is written to operate the DSA in Serial mode. Use the software GUI to enable each setting to the desired attenuation state. The software GUI automatically programs the DSA each time an attenuation state is enabled. Figure 33 * Evaluation Kit for PE43711 Page 26 DOC-44414-2 - (3/2015) www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Figure 34 * Evaluation Kit Layout for PE43711 DOC-44414-2 - (3/2015) Page 27 www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Pin Information Table 9 * Pin Descriptions for PE43711 Pin No. VDD Supply voltage 3 P/S Serial/Parallel mode select 4, 6-13, 15 GND 5 RF1(2) RF1 port (RF input) 14 RF2(2) RF2 port (RF output) 16 LE 17 CLK Serial interface Clock input 18 SI Serial interface Data input 19 C16 (D6)(1) Parallel control bit, 16 dB 20 C8 (D5)(1) Parallel control bit, 8 dB 21 C4 (D4)(1) Parallel control bit, 4 dB 22 C2 (D3)(1) Parallel control bit, 2 dB 23 C1 (D2)(1) Parallel control bit, 1 dB 24 C0.5 (D1)(1) Pad GND C8 20 C4 21 C2 22 C1 23 C0.5 24 C0.25 1 18 SI VDD 2 17 CLK P/S 3 16 LE GND 4 15 GND RF1 5 14 RF2 GND 6 13 GND 12 GND 11 GND 10 GND 9 GND 8 GND 7 Exposed Ground Pad GND C0.25 (D0)(1) Attenuation control bit, 0.25 dB 2 Figure 35 * Pin Configuration (Top View) Pin 1 Dot Marking Description C16 1 Pin Name 19 This section provides pinout information for the PE43711. Figure 35 shows the pin map of this device for the available package. Table 9 provides a description for each pin. Ground Serial interface Latch Enable input Parallel control bit, 0.5 dB Exposed pad: ground for proper operation Notes: 1) Ground C0.25, C0.5, C1, C2, C4, C8, and C16 if not in use. 2) RF pins 5 and 14 must be at 0 VDC. The RF pins do not require DC blocking capacitors for proper operation if the 0 VDC requirement is met. Page 28 DOC-44414-2 - (3/2015) www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Packaging Information This section provides packaging data including the moisture sensitivity level, package drawing, package marking and tape-and-reel information. Moisture Sensitivity Level The moisture sensitivity level rating for the PE43711 in the 24-lead 4 x 4 mm QFN package is MSL1. Package Drawing Figure 36 * Package Mechanical Drawing for 24-lead 4 x 4 x 0.85 mm QFN 0.10 C A 4.00 2.700.05 (2X) 0.400.05 (x24) B 0.50 13 0.60 (x24) 0.30 (x24) 0.50 (x20) 18 (x20) 12 19 4.00 2.700.05 2.75 0.250.05 (x24) 24 7 0.10 C 6 1 2.50 Ref. (2X) Pin #1 Corner BOTTOM VIEW TOP VIEW 0.10 C 0.10 0.05 0.850.05 0.05 C 4.40 Chamfer 0.30 x 45 2.75 4.40 RECOMMENDED LAND PATTERN C A B C ALL FEATURES SEATING PLANE 0.203 Ref. 0.05 C SIDE VIEW Top-Marking Specification Figure 37 * Package Marking Specifications for PE43711 43711 YYWW ZZZZZZ = YY = WW = ZZZZZZ = Pin 1 indicator Last two digits of assembly year Assembly work week Assembly lot code (Maximum six characters) DOC-44414-2 - (3/2015) Page 29 www.psemi.com PE43711 UltraCMOS(R) RF Digital Step Attenuator Tape and Reel Specification Figure 38 * Tape and Reel Specifications for 24-lead 4 x 4 x 0.85 mm QFN Direction of Feed Section A-A P1 P0 see note 1 T P2 see note 3 D1 D0 A E F see note 3 B0 A0 K0 A0 B0 K0 D0 D1 E F P0 P1 P2 T W0 4.35 4.35 1.10 1.50 + 0.10/ -0.00 1.50 min 1.75 0.10 5.50 0.05 4.00 8.00 2.00 0.05 0.30 0.05 12.00 0.30 A W0 Pin 1 Notes: 1. 10 Sprocket hole pitch cumulative tolerance 0.2 2. Camber in compliance with EIA 481 3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole Dimensions are in millimeters unless otherwise specified Page 30 Device Orientation in Tape DOC-44414-2 - (3/2015) www.psemi.com PE43711 Ordering Information Table 10 lists the available ordering codes for the PE43711 as well as available shipping methods. Table 10 * Order Codes for PE43711 Order Codes Description Packaging Shipping Method PE43711A-Z PE43711 Digital step attenuator Green 24-lead 4 x 4 mm QFN 3000 units / T&R EK43711-02 PE43711 Evaluation kit Evaluation kit 1 / Box Document Categories Advance Information Not Recommended for New Designs (NRND) The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. This product is in production but is not recommended for new designs. Preliminary Specification This product is currently going through the EOL process. It has a specific last-time buy date. The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. End of Life (EOL) Obsolete This product is discontinued. Orders are no longer accepted for this product. Product Specification The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). Sales Contact For additional information, contact Sales at sales@psemi.com. Disclaimers The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Patent Statement Peregrine products are protected under one or more of the following U.S. patents: patents.psemi.com Copyright and Trademark (c)2014-2015, Peregrine Semiconductor Corporation. All rights reserved. The Peregrine name, logo, UTSi and UltraCMOS are registered trademarks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. Product Specification www.psemi.com DOC-44414-2 - (3/2015)