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GS1674 Adaptive Cable Equalizer

Data Sheet

54168 - 2 September 2012

GS1674 Adaptive Cable Equalizer

GS1674

www.semtech.com

The GS1674 is a high-speed BiCMOS integrated circuit designed to equalize and restore signals received over 75Ω coaxial

cable. The device is optimized for performance at 270Mb/s and 1.485Gb/s, and features DC restoration to compensate for

the DC content of SMPTE pathological test patterns.

The Carrier Detect output pin (CD) indicates whether a valid input signal has been detected. It can be connected directly to

the MUTE pin to mute the output on loss of carrier. The sensitivity of the carrier detect can be easily programmed to allow

the GS1674 to distinguish between low-amplitude SDI signals and noise at the input of the device. The equalizing and DC

restore stages are disengaged when the BYPASS pin is HIGH. No equalization occurs in Bypass mode.

The GS1674 is footprint and drop-in compatible with existing GS1574A and LMH0044 designs, with no additional

application changes required.

Key Features

• Replaces the LMH0044

• SMPTE 292M, SMPTE 344M and SMPTE 259M

compliant

•Automatic cable equalization

• Performance optimized for 270Mb/s and 1.485Gb/s.

Typical equalized length of Belden 1694A cable:

220m at 1.485Gb/s

400m at 270Mb/s

• Supports DVB-ASI at 270Mb/s

• Manual bypass (useful for low data rates with slow

rise/fall times)

• Programmable carrier detect with squelch threshold

adjustment

• Standard EIA/JEDEC logic control and status signal

levels

• Single 3.3V power supply operation

• 195mW power consumption (typical)

• Wide temperature range of -40ºC to +85ºC

• Small footprint QFN package (4mm x 4mm)

• Drop-in compatible with the GS1574A. Forward

compatible with Gennum's 3G EQ products.

• Pb-free and RoHS compliant

Typical Application Circuit

GS1674

SDI

VEE_D

MUTE

VCC_D

AGC

BYPASS

VEE_A

NOTE: All resistors in Ohms, capacitors in Farads,

and inductors in Henrys, unless otherwise noted.

* Value dependent on layout

VEE_A

AGC

VCC_A

SDO

10nF

SDO

4.7µF

SDO

MUTE

VCC

BYPASS

SQ_ADJ

1µF

6.8nH*

75Ω

SDI

1µF

75Ω

1µF

37.4Ω

VCC

1415

SQ_ADJ

VEE_D

4.7µF

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Data Sheet

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Contents

Key Features ........................................................................................................................................................1

Typical Application Circuit.............................................................................................................................1

1. Pin Out...............................................................................................................................................................3

1.1 GS1674 Pin Assignment .................................................................................................................3

1.2 GS1674 Pin Descriptions ................................................................................................................3

2. Electrical Characteristics ............................................................................................................................5

2.1 Absolute Maximum Ratings ..........................................................................................................5

2.2 DC Electrical Characteristics ........................................................................................................5

2.3 AC Electrical Characteristics ........................................................................................................6

2.4 Typical Performance Curves ........................................................................................................7

3. Detailed Description.....................................................................................................................................8

3.1 Serial Data Inputs .............................................................................................................................8

3.2 Cable Equalization ...........................................................................................................................8

3.3 Programmable Squelch Adjust (SQ_ADJ) .................................................................................9

3.4 Mute and Carrier Detect .................................................................................................................9

3.5 Output Rise/Fall Times ................................................................................................................ 10

4. Application Information .......................................................................................................................... 11

4.1 High-Gain Adaptive Cable Equalizers .................................................................................... 11

4.2 PCB Layout ....................................................................................................................................... 11

4.3 Typical Application Circuit ........................................................................................................ 11

5. Input/Output Circuits ............................................................................................................................... 12

6. Package & Ordering Information .......................................................................................................... 13

6.1 Package Dimensions ..................................................................................................................... 13

6.2 Packaging Data ............................................................................................................................... 13

6.3 Recommended PCB Footprint ................................................................................................... 14

6.4 Marking Diagram ........................................................................................................................... 14

6.5 Solder Reflow Profiles .................................................................................................................. 15

6.6 Ordering Information ................................................................................................................... 15

Revision History .............................................................................................................................................. 16

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Data Sheet

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1. Pin Out

1.1 GS1674 Pin Assignment

Figure 1-1: GS1674 Pin Out

1.2 GS1674 Pin Descriptions

5678

16 15 14 13

SDI

SDO

VEE_A

Ground Pad

(bottom of package)

AGC

BYPASS

SQ_ADJ

VEE_D

VCC_A

MUTE

VCC_D

GS1674

16-pin QFN

(top view)

AGC

VEE_A VEE_D

Table 1-1: GS1674 Pin Descriptions

Pin Number Name Timing Type Description

1, 4 VEE_A Analog Power Most negative power supply for analog circuitry.

Connect to GND.

2, 3 SDI, SDI Analog Input Serial digital differential input.

5, 6AGC, AGC Analog – External AGC capacitor.

Connect pin 5 and pin 6 together as shown in the GS1674 Typical

Application Circuit on page 11.

7BYPASS Not

Synchronous

Input Forces the Equalizing and DC RESTORE stages into bypass mode

when HIGH. No equalization occurs in this mode. (Internal

pull-down).

8SQ_ADJAnalog Input Squelch Adjust.

Adjusts the approximate amount of cable equalized before CD goes

low. See Section 3.3 and Section 3.4. (Internal pull-down).

9, 12 VEE_D Analog Power Most negative power supply for the digital circuitry and output

buffer.

Connect to GND.

10, 11 SDO, SDO Analog Output Equalized serial digital differential output.

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Data Sheet

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13 VCC_D Analog Power Most positive power supply for the digital I/O pins of the device.

Connect to +3.3V DC.

14 MUTE Not

Synchronous

Input CONTROL SIGNAL INPUT

levels are LVCMOS/LVTTL compatible. (3.3V Tolerant)

Controls output behaviour on SDO and SDO. (Internal pull-down).

See Section 3.4.

15 CDNot

Synchronous

Output STATUS SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

Indicates the presence of an input signal.

See Section 3.4.

16VCC_A Analog Power Most positive power supply for the analog circuitry of the device.

Connect to +3.3V DC.

–Center Pad– Power Internally bonded to VEE_A.

NOTE:

For 3G migration, pins 4 and 9 are input select pins.

Table 1-1: GS1674 Pin Descriptions (Continued)

Pin Number Name Timing Type Description

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Data Sheet

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2. Electrical Characteristics

2.1 Absolute Maximum Ratings

2.2 DC Electrical Characteristics

Parameter Value

Supply Voltage -0.5V to +3.6V DC

Input ESD Voltage (HBM) 5kV

Storage Temperature Range -50°C < Ts < 125°C

Input Voltage Range (any input) -0.3 to (VCC +0.3)V

Operating Temperature Range -20°C to +85°C

Functional Temperature Range -40°C to +85°C

Solder Reflow Temperature 260°C

Table 2-1: DC Electrical Characteristics

VCC = 3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown

Parameter Symbol Conditions Min Typ Max Units Notes

Supply Voltage VCC – 3.135 3.3 3.465V –

Power Consumption PDTA = 25°C– 195 250 mW –

Supply Current IsTA = 25°C–59–mA–

Output Common Mode

Voltage

VCMOUT TA = 25°C–V

CC - (ΔVSDO)/2 – V –

Input Common Mode Voltage VCMIN TA = 25°C–1.8–V–

SQ_ADJ DC Voltage (to mute

signal)

–0m, T

A = 25°C–3.2–V–

SQ_ADJ Range – TA = 25°C–0.9–V–

CD Output Voltage VCD(OH) Carrier not

present

2.4 – – V –

VCD(OL) Carrier present – – 0.4 V –

Mute Input Voltage Required

to Force Outputs to Mute

VMute Min to Mute 2.0 – – V –

Mute Input Voltage Required

to Force Outputs Active

VMute Max to

Activate

––0.8V–

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Data Sheet

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2.3 AC Electrical Characteristics

Table 2-2: AC Electrical Characteristics

VCC = 3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown

Parameter Symbol Conditions Min Typ Max Units Notes

Serial input data rate DRSDO – 143 – 1485 Mb/s –

Input Voltage Swing ΔVSDI TA =25°C, differential,

270Mb/s and 1.485Gb/s

720 800 950 mVp-p 1

Output Voltage Swing ΔVSDO 100Ω load, TA =25°C,

differential

680 800 900 mVp-p –

Output Jitter of Various

Cable Lengths and Data

Rates

– 1.485Gb/s

Belden 1694A: 0-220m

–0.25– UI –

– 270Mb/s

Belden 1694A: 0-400m

––0.2UI2,

Output Rise/Fall time – 1.485Gb/s 20% - 80% 35 6590ps –

– 270Mb/s (see Section 3.5)

Mismatch in rise/fall time – – – – 30 ps –

Duty cycle distortion – – – – 30 ps –

Overshoot – – – – 10 % –

Input Return Loss – – 15 21 – dB–

Input Resistance–Single-ended–1.9–kΩ–

Input Capacitance–Single-ended–1.3– pF–

Output Resistance–Single-ended–50– Ω–

NOTES:

1. 0m cable length.

2. All parts are production tested. In order to guarantee jitter over the full range of specification (VCC = 3.3V ±5%, TA = -20°C to +85°C, and

720-880mV launch swing from the SDI cable driver) the recommended applications circuit must be used.

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Data Sheet

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2.4 Typical Performance Curves

VCC=3.3V, room temperature, 800mV launch swing

Figure 2-1: Jitter vs. Cable Length (270 Mb/s)

Figure 2-2: Jitter vs. Cable Length (1485 Mb/s)

200

400

600

Jitter (ps)

0100 200 300 400

Cable Length (m)

100

Jitter (ps)

050 100 150

Cable Length (m)

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Data Sheet

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3. Detailed Description

Figure 3-1: GS1674 Functional Block Diagram

The GS1674 is a high-speed BiCMOS IC designed to equalize serial digital signals.

The GS1674 can equalize HD and SD serial digital signals, and will typically equalize

200m at 1.

485Gb/

s and 400m at 270Mb/s. The GS1674 is powered from a single +3.3V

power supply, and consumes approximately 195mW of power.

3.1 Serial Data Inputs

The Serial Data Input signals can be connected to the input pins (SDI/SDI) in either a

differential or single-ended configuration. AC-coupling of the inputs is recommended,

as the SDI and SDI inputs are internally biased at approximately 1.8V.

3.2 Cable Equalization

The input signal passes through a variable gain equalizing stage, whose frequency

response closely matches the inverse of the cable loss characteristic. In addition, the

variation of the frequency response with control voltage imitates the variation of the

inverse cable loss characteristic with cable length.

The edge energy of the equalized signal is monitored by a detector circuit which

produces an error signal corresponding to the difference between the desired edge

energy and the actual edge energy. This error signal is integrated by both an internal and

an external AGC filter capacitor providing a steady control voltage for the gain stage. As

the frequency response of the gain stage is automatically varied by the application of

negative feedback, the edge energy of the equalized signal is kept at a constant level

which is representative of the original edge energy at the transmitter. The equalized

signal is also DC-restored, effectively restoring the logic threshold of the equalized

signal to its correct level independent of shifts due to AC-coupling.

Equalizer Output

AGC

SDI

MUTE

SDO

BYPASS CD

SDI SDO

AGCAGC

SQ_ADJ

Squelch Adjust

Carrier Detect

Mute

Restore

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Data Sheet

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3.3 Programmable Squelch Adjust (SQ_ADJ)

The GS1674 incorporates a programmable Squelch Adjust (SQ_ADJ) threshold.

This feature can be useful in applications where there are multiple input channels using

the GS1674 and the maximum gain can be limited to avoid crosstalk.

The SQ_ADJ pin acts to change the threshold of the Carrier Detect (CD) pin, through

voltage level variances. When the input signal drops below a certain threshold, the CD

pin will be driven high, indicating that there is not a valid input signal. In order to enable

automatic muting of the output of the GS1674, the CD pin should be connected directly

to the MUTE pin. In applications where programmable squelch adjust is not required, the

SQ_ADJ pin may be left unconnected. Figure 3-2 shows the relationship between the

SQ_ADJ voltage and cable length at which CD will assert or deassert.

This feature has been designed for use in applications such as routers, where signal

crosstalk and circuit noise cause the Equalizer to output erroneous data when no input

signal is present. The use of a Carrier Detect function with a fixed internal reference

does not solve this problem, since the signal to noise ratio on the circuit board could be

significantly less than the default signal detection level set by the on chip reference.

Figure 3-2: SQ_ADJ vs. Cable Length (VCC=3.3V, room temperature, 800mV

launch swing)

3.4 Mute and Carrier Detect

The GS1674 includes a MUTE input pin that allows the application interface to mute the

Serial Digital Output at any time. Set the MUTE pin HIGH to mute SDO and SDO. In this

case, the outputs will mute regardless of the setting of the BYPASS pin.

A Carrier Detect output pin (CD) indicates the presence of a valid signal at the input of

the GS1674. When CD is LOW, the device has detected a valid input on SDI and SDI.

When CD is HIGH, the device has not detected a valid input. The CD output pin may be

connected directly to the MUTE input pin to enable automatic muting of the GS1674

when no valid input signal has been detected.

NOTE 1: CD will only detect loss of carrier for data rates greater than 19Mb/s.

NOTE 2: If the maximum cable length is exceeded (set by the SQ_ADJ pin) and the

device is not in Bypass mode, the CD pin will not be driven low, even if a carrier is

present.

SQ_ADJ (V)

3.2

3.0

2.8

2.6

2.4

2.2

2.0

Cable Length (m)

050 100 150 200 250 300 350 400 450

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Data Sheet

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3.5 Output Rise/Fall Times

Figure 3-3: Typical Rise/Fall Time for 270Mb/s Data Rate (VCC=3.3V, room

temperature, 800mV launch swing)

The GS1674 was designed to limit bandwidth as cable length is increased. During

normal HD (1.485Gb/s), and SD (270Mb/s) operation, the impact of this is minimal on rise

and fall time over the operating range from 0-200m. Above 200m, this bandwidth

limitation becomes more significant, and reduction in rise and fall time is observed. This

means that for SD (270Mb/s) operation at cable lengths greater than 200m, rise and fall

times are slow as shown in Figure 3-3 above. This is beneficial because at 270Mb/s, one

unit interval is equal to 3.7ns, so rise and fall times less than 100ps are not required, and

slower rise and fall times actually help to reduce EMI.

Table 3-1: Mute Input Table

Mute Function

0SDO and SDO operate normally

1SDO and SDO are forced to a steady

state (either HIGH or LOW)

Table 3-2: CD Output Table

CD Input Status

0Valid Input on SDI, SDI pins

1 Input is not valid

200

Rise/Fall Time (ps)

0100 200 300 400

Cable Length (m)

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Data Sheet

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4. Application Information

4.1 High-Gain Adaptive Cable Equalizers

The GS1674 is Gennum's latest HD-optimized adaptive cable equalizer. In order to

continue to extend the cable length that an equalizer will remain operational over, it is

necessary to have high-gain in the equalizer.

A video cable equalizer must provide wide band gain over a range of frequencies in

order to accommodate the range of data rates and signal patterns that are present in a

SMPTE compliant serial video stream.

The GS1674 has an increase in gain over the GS1574A at critical HD frequencies, and

because of this, the GS1674 may be sensitive to signals at the input that the GS1574A will

not be sensitive to.

Small levels of signal or noise present at the input pins of the Equalizer may cause

chatter at the output. In order to prevent this from happening, particular attention must

be paid to board layout.

4.2 PCB Layout

Special attention must be paid to component layout when designing Serial Digital

Interfaces for HDTV. An FR-4 dielectric can be used, however, controlled impedance

transmission lines are required for PCB traces longer than approximately 1cm. Note the

following PCB artwork features used to optimize performance:

• The PCB ground plane is removed under the GS1674 input components to minimize

parasitic capacitance

• The PCB ground plane is removed under the GS1674 output components to

minimize parasitic capacitance

• High-speed traces are curved to minimize impedance changes

4.3 Typical Application Circuit

Figure 4-1: GS1674 Typical Application Circuit

GS1674

SDI

VEE_D

MUTE

VCC_D

AGC

BYPASS

VEE_A

NOTE: All resistors in Ohms, capacitors in Farads,

and inductors in Henrys, unless otherwise noted.

* Value dependent on layout

VEE_A

AGC

VCC_A

SDO

10nF

SDO

4.7µF

SDO

MUTE

VCC

BYPASS

SQ_ADJ

1µF

6.8nH*

75Ω

SDI

1µF

75Ω

1µF

37.4Ω

VCC

1415

SQ_ADJ

VEE_D

4.7µF

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Data Sheet

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5. Input/Output Circuits

Figure 5-1: Input Equivalent Circuit Figure 5-2: SQ_ADJ Equivalent Circuit

Figure 5-3: Output Circuit

Figure 5-4: MUTE and BYPASS Circuits Figure 5-5: CD Circuit

5.25k

SDI SDI

SQ_ADJ

82.4k

SDOSDO

MUTE,

BYPASS

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6. Package & Ordering Information

6.1 Package Dimensions

6.2 Packaging Data

4.00+/-0.05

0.15

0.10 C

16X

0.08 C

SEATING PLANE

0.85+/-0.05

0.00-0.05

0.65/2

0.65

DETAIL B

SCALE:NTS

DATUM A OR B

TERMINAL TIP

0.20 REF

DATUM B

DETAIL B

0.65

16X

0.35+/-0.05

0.10

0.05 C

DATUM A

2.76+/-0.10

0.40+/-0.05

2.76+/-0.10

DETAIL B

CENTER TAB

PIN 1 AREA

PIN #1

IDENTIFICATION

Φ0.4500

Parameter Value

Package Type 4mm x 4mm 16-pin QFN

Package Drawing ReferenceJEDEC M0220

Moisture Sensitivity Level 3

Junction to Case Thermal Resistance, θj-c31.0°C/W

Junction to Air Thermal Resistance, θj-a (at zero airflow) 43.8°C/W

Psi, ψ11.0°C/W

Pb-free and RoHS compliant Yes

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Data Sheet

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6.3 Recommended PCB Footprint

The center pad should be connected to the most negative power supply plane for analog

circuitry in the device (VEE_A) by a minimum of 5 vias.

NOTE: Suggested dimensions only. Final dimensions should conform to customer

design rules and process optimizations.

6.4 Marking Diagram

0.35

0.55

2.76

3.70

2.763.70

NOTE: All dimensions

are in millimeters.

0.65

Center Pad

Pin 1

Indicator

HD-SDI

GS1674

XXXXE3

YYWW

GS1674 - Package Mark

XXXX - Last 4 digits (excluding decimal)

of SAP Batch Assembly (FIN)

as listed on Packing Slip

E3 - Pb-free & Green Indicator

YYWW - Date Code

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Data Sheet

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6.5 Solder Reflow Profiles

The GS1674 is available in a Pb-free package. It is recommended that the Pb-free

package be soldered with Pb-free paste using the reflow profile shown in Figure 6-1.

Figure 6-1: Maximum Pb-free Solder Reflow Profile

6.6 Ordering Information

Revision History

25°C

150°C

200°C

217°C

260°C

250°C

Time

Temperature

8 min. max

60-180 sec. max

60-150 sec.

20-40 sec.

3°C/sec max

6°C/sec max

Part Number Package Temperature Range

GS1674 GS1674-INE3 16-pin QFN -40°C to 85°C

GS1674 GS1674-INTE3 16-pin QFN Tape &

Reel (250pcs)

-40°C to 85°C

Version ECR PCN Date Changes and/or Modifications

2 15858654547 September 2012 Change in Input ESD Voltage (HBM)

parameter in 2.1 Absolute Maximum Ratings

1 154866 –September 2010 Increased cable length to 220m at 1.485Gb/s.

0 154128 – May 2010 Converted to Data Sheet. Changed pin 4 and

pin 9 names in Pin Out and Application

Information.

A 153462– March 2010 New document.

owner. The information presented in this document does not form part of any quotation or contract, is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or

intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected

operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or

electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or

operation outside the specified range.

SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN

LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH

PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK.

Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall

indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all

claims, costs damages and attorney fees which could arise.

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

DOCUMENT IDENTIFICATION

DATA SHEET

Information relating to this product and the application or design described

herein is believed to be reliable, however such information is provided as a

guide only and Semtech assumes no liability for any errors in this document, or

for the application or design described herein. Semtech reserves the right to

make changes to the product or this document at any time without notice.

GS1674 Adaptive Cable Equalizer

Data Sheet

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Contact Information

Semtech Corporation

Gennum Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: (805) 498-2111, Fax: (805) 498-3804

www.semtech.com

CAUTION

ELECTROSTATIC SENSITIVE DEVICES

DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A

STATIC-FREE WORKSTATION