REV. D
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Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD8007/AD8008
Ultralow Distortion
High Speed Amplifiers
FEATURES
Extremely Low Distortion
Second Harmonic
–88 dBc @ 5 MHz
–83 dBc @ 20 MHz (AD8007)
–77 dBc @ 20 MHz (AD8008)
Third Harmonic
–101 dBc @ 5 MHz
–92 dBc @ 20 MHz (AD8007)
–98 dBc @ 20 MHz (AD8008)
High Speed
650 MHz, –3 dB Bandwidth (G = +1)
1000 V/␮s Slew Rate
Low Noise
2.7 nV/
√
Hz Input Voltage Noise
22.5 pA/
√
Hz Input Inverting Current Noise
Low Power
9 mA/Amplifier Typ Supply Current
Wide Supply Voltage Range
5 V to 12 V
0.5 mV Typical Input Offset Voltage
Small Packaging
SOIC-8, MSOP, and SC70 Packages Available
APPLICATIONS
Instrumentation
IF and Baseband Amplifiers
Filters
A/D Drivers
DAC Buffers
CONNECTION DIAGRAMS
GENERAL DESCRIPTION
The AD8007 (single) and AD8008 (dual) are high perfor-
mance current feedback amplifiers with ultralow distortion
and noise. Unlike other high performance amplifiers, the low
price and low quiescent current allow these amplifiers to be
used in a wide range of applications. ADI’s proprietary second
generation eXtra-Fast Complementary Bipolar (XFCB)
process enables such high performance amplifiers with low
power consumption.
The AD8007/AD8008 have 650 MHz bandwidth, 2.7 nV/√Hz
voltage noise, –83 dB SFDR @ 20 MHz (AD8007), and –77 dBc
SFDR @ 20 MHz (AD8008).
With the wide supply voltage range (5 V to 12 V) and wide band-
width, the AD8007/AD8008 are designed to work in a variety of
applications. The AD8007/AD8008 amplifiers have a low power
supply current of 9 mA/amplifier.
The AD8007 is available in a tiny SC70 package as well as a
standard 8-lead SOIC. The dual AD8008 is available in both
8-lead SOIC and 8-lead MSOP packages. These amplifiers are
rated to work over the industrial temperature range of –40°C
to +85°C.
FREQUENCY – MHz
–30
–40
–110 1 10010
DISTORTION – dBc
–70
–80
–90
–100
–50
–60
THIRD
G = +2
R
L
= 150⍀
V
S
= 5V
V
OUT
= 2V p-p
SECOND
Figure 1. AD8007 Second and Third Harmonic
Distortion vs. Frequency
SOIC (R) SC70 (KS-5)
8
7
6
5
1
2
3
4
NC = NO CONNECT
NC
–IN
+IN
NC
+V
S
V
OUT
NC
–V
S
AD8007
(Top View)
5
1
2
3
–IN
+IN
+V
S
V
OUT
–V
S
4
AD8007
(Top View)
SOIC (R)
and MSOP (RM)
1
V
OUT1
–IN1
+IN1
–V
S
+V
S
V
OUT2
–IN2
+IN2
8
27
36
45
AD8008
(Top View)
REV. D–2–
AD8007/AD8008–SPECIFICATIONS
(@ TA = 25ⴗC, RS = 200 ⍀, RL = 150 ⍀, RF = 499 ⍀, Gain = +2, unless otherwise noted.)
AD8007/AD8008
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth G = +1, V
O
= 0.2 V p-p, R
L
= 1 kΩ540 650 MHz
G = +1, V
O
= 0.2 V p-p, R
L
= 150 Ω250 500 MHz
G = +2, V
O
= 0.2 V p-p, R
L
= 150 Ω180 230 MHz
G = +1, V
O
= 2 V p-p, R
L
= 1 kΩ200 235 MHz
Bandwidth for 0.1 dB Flatness V
O
= 0.2 V p-p, G = +2, R
L
= 150 Ω50 90 MHz
Overdrive Recovery Time ±2.5 V Input Step, G = +2, R
L
= 1 kΩ30 ns
Slew Rate G = +1, V
O
= 2 V Step 900 1000 V/µs
Settling Time to 0.1% G = +2, V
O
= 2 V Step 18 ns
Settling Time to 0.01% G = +2, V
O
= 2 V Step 35 ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic f
C
= 5 MHz, V
O
= 2 V p-p –88 dBc
f
C
= 20 MHz, V
O
= 2 V p-p –83/–77 dBc
Third Harmonic f
C
= 5 MHz, V
O
= 2 V p-p –101 dBc
f
C
= 20 MHz, V
O
= 2 V p-p –92/–98 dBc
IMD f
C
= 19.5 MHz to 20.5 MHz, R
L
= 1 kΩ,
V
O
= 2 V p-p –77 dBc
Third Order Intercept f
C
= 5 MHz, R
L
= 1 kΩ43.0/42.5 dBm
f
C
= 20 MHz, R
L
= 1 kΩ42.5 dBm
Crosstalk (AD8008) f = 5 MHz, G = +2 –68 dB
Input Voltage Noise f = 100 kHz 2.7 nV/√Hz
Input Current Noise –Input, f = 100 kHz 22.5 pA/√Hz
+Input, f = 100 kHz 2 pA/√Hz
Differential Gain Error NTSC, G = +2, R
L
= 150 Ω0.015 %
Differential Phase Error NTSC, G = +2, R
L
= 150 Ω0.010 Degree
DC PERFORMANCE
Input Offset Voltage 0.5 4 mV
Input Offset Voltage Drift 3µV/°C
Input Bias Current +Input 4 8 µA
–Input 0.4 6 µA
Input Bias Current Drift +Input 16 nA/°C
–Input 9 nA/°C
Transimpedance V
O
= ±2.5 V, R
L
= 1 kΩ1.0 1.5 MΩ
R
L
= 150 Ω0.4 0.8 MΩ
INPUT CHARACTERISTICS
Input Resistance +Input 4 MΩ
Input Capacitance +Input 1 pF
Input Common-Mode Voltage Range –3.9 to +3.9 V
Common-Mode Rejection Ratio V
CM
= ±2.5 V 56 59 dB
OUTPUT CHARACTERISTICS
Output Saturation Voltage V
CC
– V
OH
, V
OL
– V
EE
,
R
L
= 1 kΩ1.1 1.2 V
Short Circuit Current, Source 130 mA
Short Circuit Current, Sink 90 mA
Capacitive Load Drive 30% Overshoot 8 pF
POWER SUPPLY
Operating Range 5 12 V
Quiescent Current per Amplifier 9 10.2 mA
Power Supply Rejection Ratio
+PSRR 59 64 dB
–PSRR 59 65 dB
V
S
= ⴞ5 V
REV. D
AD8007/AD8008
–3–
(@ TA = 25ⴗC, RS = 200 ⍀, RL = 150 ⍀, RF = 499 ⍀, Gain = +2, unless otherwise noted.)
AD8007/AD8008
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth G = +1, V
O
= 0.2 V p-p, R
L
= 1 kΩ520 580 MHz
G = +1, V
O
= 0.2 V p-p, R
L
= 150 Ω350 490 MHz
G = +2, V
O
= 0.2 V p-p, R
L
= 150 Ω190 260 MHz
G = +1, V
O
= 1 V p-p, R
L
= 1 kΩ270 320 MHz
Bandwidth for 0.1 dB Flatness Vo = 0.2 V p-p, G = +2, R
L
= 150 Ω72 120 MHz
Overdrive Recovery Time 2.5 V Input Step, G = +2, R
L
= 1 kΩ30 ns
Slew Rate G = +1, V
O
= 2 V Step 665 740 V/µs
Settling Time to 0.1% G = +2, V
O
= 2 V Step 18 ns
Settling Time to 0.01% G = +2, V
O
= 2 V Step 35 ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic f
C
= 5 MHz, V
O
= 1 V p-p –96/–95 dBc
f
C
= 20 MHz, V
O
= 1 V p-p –83/–80 dBc
Third Harmonic f
C
= 5 MHz, V
O
= 1 V p-p –100 dBc
f
C
= 20 MHz, V
O
= 1 V p-p –85/–88 dBc
IMD f
C
= 19.5 MHz to 20.5 MHz, R
L
= 1 kΩ,–89/–87 dBc
V
O
= 1 V p-p
Third Order Intercept f
C
= 5 MHz, R
L
= 1 kΩ43.0 dBm
f
C
= 20 MHz, R
L
= 1 kΩ42.5/41.5 dBm
Crosstalk (AD8008) Output to Output f = 5 MHz, G = +2 –68 dB
Input Voltage Noise f = 100 kHz 2.7 nV/√Hz
Input Current Noise –Input, f = 100 kHz 22.5 pA/√Hz
+Input, f = 100 kHz 2 pA/√Hz
DC PERFORMANCE
Input Offset Voltage 0.5 4 mV
Input Offset Voltage Drift 3µV/°C
Input Bias Current +Input 4 8 µA
–Input 0.7 6 µA
Input Bias Current Drift +Input 15 nA/°C
–Input 8 nA/°C
Transimpedance V
O
= 1.5 V to 3.5 V, R
L
= 1 kΩ0.5 1.3 MΩ
R
L
= 150 Ω0.4 0.6 MΩ
INPUT CHARACTERISTICS
Input Resistance +Input 4 MΩ
Input Capacitance +Input 1 pF
Input Common-Mode Voltage Range 1.1 to 3.9 V
Common-Mode Rejection Ratio V
CM
= 1.75 V to 3.25 V 54 56 dB
OUTPUT CHARACTERISTICS
Output Saturation Voltage V
CC
– V
OH
, V
OL
– V
EE
,
R
L
= 1 kΩ1.05 1.15 V
Short Circuit Current, Source 70 mA
Short Circuit Current, Sink 50 mA
Capacitive Load Drive 30% Overshoot 8 pF
POWER SUPPLY
Operating Range 5 12 V
Quiescent Current per Amplifier 8.1 9 mA
Power Supply Rejection Ratio
+PSRR 59 62 dB
–PSRR 59 63 dB
V
S
= 5 V
REV. D–4–
AD8007/AD8008
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8007/AD8008 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . See Figure 2
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . ±V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ±1.0 V
Output Short Circuit Duration . . . . . . . . . . . . . . See Figure 2
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (soldering 10 sec) . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8007/AD8008
packages is limited by the associated rise in junction temperature
(T
J
) on the die. The plastic encapsulating the die will locally reach
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic will change its proper-
ties. Even temporarily exceeding this temperature limit may
change the stresses that the package exerts on the die, perma-
nently shifting the parametric performance of the AD8007/
AD8008. Exceeding a junction temperature of 175°C for an
extended period of time can result in changes in the silicon
devices, potentially causing failure.
The still-air thermal properties of the package and PCB (θ
JA
),
ambient temperature (T
A
), and the total power dissipated in the
package (P
D
) determine the junction temperature of the die.
The junction temperature can be calculated as follows:
TT P
ADA
JJ
=+ ×
()
θ
The power dissipated in the package (P
D
) is the sum of the quies-
cent power dissipation and the power dissipated in the package
due to the load drive for all outputs. The quiescent power is the
voltage between the supply pins (V
S
) times the quiescent current
(I
S
). Assuming the load (R
L
) is referenced to midsupply, the
total drive power is V
S
/2 ⫻ I
OUT
, some of which is dissipated in the
package and some in the load (V
OUT
⫻ I
OUT
). The difference
between the total drive power and the load power is the drive
power dissipated in the package.
P
D
= quiescent power + (total drive power – load power):
PVI VV
R
V
R
DSS
S OUT
L
OUT
L
=×
()
+×
−
2
2
RMS output voltages should be considered. If R
L
is referenced
to V
S
, as in single-supply operation, then the total drive power
is V
S
⫻I
OUT
.
If the rms signal levels are indeterminate, then consider the
worst case, when V
OUT
= V
S
/4 for R
L
to midsupply:
PVI
V
R
DSS
S
L
=×
()
+
4
2
In single-supply operation, with R
L
referenced to V
S
, worst case is
VV
OUT
S
=2
Airflow will increase heat dissipation, effectively reducing θ
JA
.
Also, more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes will
reduce the θ
JA
. Care must be taken to minimize parasitic capaci-
tances at the input leads of high speed op amps as discussed in
the board layout section.
Figure 2 shows the maximum safe power dissipation in the pack-
age versus ambient temperature for the SOIC-8 (125°C/W),
MSOP (150°C/W), and SC70 (210°C/W) packages on a JEDEC
standard 4-layer board. θ
JA
values are approximations.
AMBIENT TEMPERATURE – ⴗC
2.0
1.5
0
–60 100–40
MAXIMUM POWER DISSIPATION – W
–20 0 20 406080
1.0
0.5
SOIC-8
SC70-5
MSOP-8
Figure 2. Maximum Power Dissipation vs.
Temperature for a 4-Layer Board
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for
the AD8007/AD8008 will likely cause catastrophic failure.
REV. D
AD8007/AD8008
–5–
ORDERING GUIDE
Package
Model Temperature Range Description Package Outline Branding
AD8007AR –40°C to +85°C8-Lead SOIC R-8
AD8007AR-REEL –40°C to +85°C8-Lead SOIC R-8
AD8007AR-REEL7 –40°C to +85°C8-Lead SOIC R-8
AD8007AKS-R2 –40°C to +85°C5-Lead SC70 KS-5 HTA
AD8007AKS-REEL –40°C to +85°C5-Lead SC70 KS-5 HTA
AD8007AKS-REEL7 –40°C to +85°C5-Lead SC70 KS-5 HTA
AD8008AR –40°C to +85°C8-Lead SOIC R-8
AD8008AR-REEL7 –40°C to +85°C8-Lead SOIC R-8
AD8008AR-REEL –40°C to +85°C8-Lead SOIC R-8
AD8008ARM –40°C to +85°C8-Lead MSOP RM-8 H2B
AD8008ARM-REEL –40°C to +85°C8-Lead MSOP RM-8 H2B
AD8008ARM-REEL7 –40°C to +85°C8-Lead MSOP RM-8 H2B
REV. D–6–
AD8007/AD8008–Typical Performance Characteristics
FREQUENCY – MHz
3
2
–5
1 10010
NORMALIZED GAIN – dB
–1
–2
–3
–4
1
0
–6
–7 1000
G = +1
G = +2
G = +10
G = –1
TPC 1. Small Signal Frequency Response for Various Gains
FREQUENCY – MHz
3
2
–5
10010
GAIN – dB
–1
–2
–3
–4
1
0
–6
–7 1000
RL = 150⍀, VS = +5V
RL = 150⍀, VS = ⴞ5V
RL = 1k⍀, VS = ⴞ5V
G = +1
TPC 2. Small Signal Frequency Response for V
S
and R
LOAD
FREQUENCY – MHz
3
2
–5
10010
GAIN – dB
–1
–2
–3
–4
1
0
–6
–7 1000
RS = 249⍀
RS = 301⍀
RS = 200⍀
G = +1
RL = 1k⍀
TPC 3. Small Signal Frequency Response for
Various R
S
Values
FREQUENCY – MHz
6.4
6.3
5.6
10010
GAIN – dB
6.0
5.9
5.8
5.7
6.2
6.1
5.5
5.4 1000
G = +2
VS = +5V
VS = ⴞ5V
TPC 4. 0.1 dB Gain Flatness; V
S
= +5,
±
5 V
FREQUENCY – MHz
9
8
1
10010
GAIN – dB
5
4
3
2
7
6
0
–1 1000
G = +2
RL = 150⍀
VS = +5V
RL = 150⍀, VS = ⴞ5V
RL = 1k⍀, VS = ⴞ5V
RL = 1k⍀, VS = +5V
TPC 5. Small Signal Frequency Response for V
S
and R
LOAD
FREQUENCY – MHz
9
8
1
10010
GAIN – dB
5
4
3
2
7
6
0
–1 1000
G = +2
RF = RG = 249⍀
RF = RG = 324⍀
RF = RG = 649⍀
RF = RG = 499⍀
TPC 6. Small Signal Frequency Response for Various
Feedback Resistors, R
F
=R
G
(VS = ⴞ5 V, RL = 150 ⍀, RS = 200 ⍀, RF = 499 ⍀, unless otherwise noted.)
REV. D
AD8007/AD8008
–7–
FREQUENCY – MHz
10
9
2
1 10010
GAIN – dB
6
5
4
3
8
7
1
01000
G = +2 20pF
0pF
20pF AND
10⍀ SNUB
20pF AND
20⍀ SNUB
499⍀
499⍀
200⍀
49.9⍀
RSNUB
CLOAD
TPC 7. Small Signal Frequency Response for Capacitive
Load and Snub Resistor
FREQUENCY – MHz
3
2
–5
10010
GAIN – dB
–1
–2
–3
–4
1
0
–6
–7 1000
VS = +5V, +85ⴗC
VS = ⴞ5V, –40ⴗC
VS = +5V, –40ⴗC
VS = ⴞ5V, +85ⴗC
G = +1
TPC 8. Small Signal Frequency Response over
Temperature, V
S
= +5 V,
±
5 V
FREQUENCY – MHz
3
2
–5
1 10010
NORMALIZED GAIN – dB
–1
–2
–3
–4
1
0
–6
–7 1000
VOUT = 2V p-p
G = +1 G = +2
G = +10
G = –1
TPC 9. Large Signal Frequency Response for Various Gains
FREQUENCY – Hz
10M
1M
10k 1M100k
TRANSIMPEDANCE – ⍀
1k
100
10
1
100k
10k
10M 100M 1G
0
–30
–90
–150
–210
–270
–330
PHASE – Degrees
2G
TRANSIMPEDANCE
PHASE
30
90
–180
TPC 10. Transimpedance and Phase vs. Frequency
FREQUENCY – MHz
9
8
1
10010
GAIN – dB
5
4
3
2
7
6
0
–1 1000
G = +2
VS = +5V, +85ⴗC
VS = ⴞ5V, –40ⴗC
VS = +5V, –40ⴗC
VS = ⴞ5V, +85ⴗC
TPC 11. Small Signal Frequency Response over
Temperature, V
S
= +5 V,
±
5 V
FREQUENCY – MHz
9
8
1
10010
GAIN – dB
5
4
3
2
7
6
0
–1 1000
RL = 150⍀, VS = ⴞ5V, VO = 2V p-p
RL = 1k⍀, VS = ⴞ5V, VO = 2V p-p
RL = 150⍀, VS = +5V, VO = 1V p-p
RL = 1k⍀, VS = +5V, VO = 1V p-p
G = +2
TPC 12. Large Signal Frequency Response for V
S
and R
LOAD
REV. D–8–
AD8007/AD8008
FREQUENCY – MHz
–90
101
DISTORTION – dBc
–50
–60
–70
–80
–40
–100
–110 100
G = ⴙ1
VS = 5V
VO = 1V p-p
HD2, RL = 150⍀
HD3, RL = 150⍀
HD2, RL = 1k⍀
HD3, RL = 1k⍀
TPC 13. AD8007 Second and Third Harmonic Distortion
vs. Frequency and R
L
FREQUENCY – MHz
–90
101
DISTORTION – dBc
–50
–60
–70
–80
–40
–100
–110 100
G = ⴙ1
V
S
= ⴞ5V
V
O
= 2V p-p
HD2, R
L
= 150⍀
HD3, R
L
= 150⍀
HD2, R
L
= 1k⍀
HD3, R
L
= 1k⍀
TPC 14. AD8007 Second and Third Harmonic Distortion
vs. Frequency and R
L
FREQUENCY – MHz
–90
101
DISTORTION – dBc
–50
–60
–70
–80
–40
–100
–110
100
V
S
= ⴞ5V
V
O
= 2V p-p
R
L
= 150⍀
HD2, G = ⴙ1
HD3, G = ⴙ1
HD2, G = ⴙ10
HD3, G = ⴙ10
–30
TPC 15. AD8007 Second and Third Harmonic Distortion
vs. Frequency and Gain
FREQUENCY – MHz
–90
101
DISTORTION – dBc
–50
–60
–70
–80
–40
–100
–110
100
G = ⴙ2
V
S
= 5V
V
O
= 1V p-p
HD2, R
L
= 150⍀
HD3, R
L
= 150⍀
HD2, R
L
= 1k⍀
HD3, R
L
= 1k⍀
TPC 16. AD8007 Second and Third Harmonic Distortion
vs. Frequency and R
L
FREQUENCY – MHz
–90
101
DISTORTION – dBc
–50
–60
–70
–80
–40
–100
–110 100
G = ⴙ2
V
S
= ⴞ5V
V
O
= 2V p-p
HD2, R
L
= 150⍀
HD3, R
L
= 150⍀
HD2, R
L
= 1k⍀
HD3, R
L
= 1k⍀
TPC 17. AD8007 Second and Third Harmonic Distortion
vs. Frequency and R
L
FREQUENCY – MHz
–90
101
DISTORTION – dBc
–50
–60
–70
–80
–40
–100
–110
100
G = +2
V
S
= 5V
R
L
= 150⍀
–30
HD2, V
O
= 2V p-p
HD3, V
O
= 2V p-p
HD2, V
O
= 4V p-p
HD3, V
O
= 4V p-p
TPC 18. AD8007 Second and Third Harmonic Distortion
vs. Frequency and V
OUT
REV. D
AD8007/AD8008
–9–
FREQUENCY – MHz
10010
HD2, RL = 1k⍀
HD2, RL = 150⍀
HD3, RL = 1k⍀
HD3, RL = 150⍀
G = 1
VS = 5V
VO = 1V p-p
–40
1
DISTORTION – dBc
–110
–100
–90
–80
–70
–60
–50
TPC 19. AD8008 Second and Third Harmonic
Distortion vs. Frequency and R
L
FREQUENCY – MHz
–40
1 10010
DISTORTION – dBc
HD2, R
L
= 1k⍀
HD2, R
L
= 150⍀
HD3, R
L
= 1k⍀ HD3, R
L
= 150⍀
G = 1
V
S
= 5V
V
O
= 1V p-p
–110
–100
–90
–80
–70
–60
–50
TPC 20. AD8008 Second and Third Harmonic
Distortion vs. Frequency and R
L
FREQUENCY – MHz
10010
HD2, G = 10
VS = 5V
VO = 2V p-p
RL = 150 ⍀
HD2, G = 1
HD3, G = 1
HD3, G = 10
–40
1
DISTORTION – dBc
–110
–100
–90
–80
–70
–60
–50
–30
TPC 21. AD8008 Second and Third Harmonic
Distortion vs. Frequency and Gain
FREQUENCY – MHz
10010
HD2, RL = 1k⍀
HD2, RL = 150⍀
HD3, RL = 1k⍀
HD3, RL = 150⍀
G = 2
VS = 5V
VO = 1V p-p
–40
1
DISTORTION – dBc
–110
–100
–90
–80
–70
–60
–50
TPC 22. AD8008 Second and Third Harmonic
Distortion vs. Frequency and R
L
FREQUENCY – MHz
10010
HD2, RL = 150⍀
HD3, RL = 1k⍀
HD3, RL = 150⍀
G = 2
VS = 5V
VO = 2V p-p
–40
1
DISTORTION – dBc
–110
–100
–90
–80
–70
–60
–50
HD2, RL = 1k⍀
TPC 23. AD8008 Second and Third Harmonic
Distortion vs. Frequency and R
L
FREQUENCY – MHz
10010
HD2, V
O
= 2V p-p
G = 2
R
L
= 150⍀
V
S
= 5V
–40
–110
–100
–90
–80
–70
–60
–50
–30
1
DISTORTION – dBc
HD2, V
O
= 4V p-p
HD3, V
O
= 2V p-p
HD3, V
O
= 4V p-p
TPC 24. AD8008 Second and Third Harmonic
Distortion vs. Frequency and V
OUT
(VS = ⴞ5 V, RS = 200 ⍀, RF = 499 ⍀, RL = 150 ⍀, @ 25°C, unless otherwise noted.)
REV. D–10–
AD8007/AD8008
VOUT – V p-p
–90 1.51
DISTORTION – dBc
–70
–75
–80
–85
–65
2
G = ⴙ2
VS = 5V
FO = 20MHz
2.5
HD2, RL = 150⍀
HD3, RL = 150⍀
HD2, RL = 1k⍀
HD3, RL = 1k⍀
–60
TPC 25. AD8007 Second and Third Harmonic
Distortion vs. V
OUT
and R
L
FREQUENCY – MHz
38
5
THIRD ORDER INTERCEPT – dBm
42
41
40
39
43
G = +2
VS = ⴞ5V
VO = 2V p-p
RL = 1k⍀
37
36
35
10 15 20 25 30 35 40 45 50 55 60 65 70
44
TPC 26. AD8007 Third Order Intercept vs. Frequency
V
OUT
– V p-p
–90 1.51
–70
–75
–80
–85
–65
2
G = ⴙ2
V
S
= 5V
F
O
= 20MHz
2.5
HD2, R
L
= 150⍀
HD3, R
L
= 150⍀
HD2, R
L
= 1k⍀
HD3, R
L
= 1k⍀
TPC 27. AD8008 Second and Third Harmonic
Distortion vs. V
OUT
and R
L
V
OUT
– V p-p
–90
21
DISTORTION – dBc
–70
–75
–80
–85
–65
34
G = ⴙ2
V
S
= ⴞ5V
F
O
= 20MHz
–95
–100
–105
–110
56
HD2, R
L
= 150⍀
HD3, R
L
= 150⍀
HD2, R
L
= 1k⍀
HD3, R
L
= 1k⍀
TPC 28. AD8007 Second and Third Harmonic
Distortion vs. V
OUT
and R
L
FREQUENCY – MHz
38
42
41
40
39
43
70
44
G = ⴙ2
VS = 5V
VO = 2V p-p
RL = 1k⍀
37
36
35 6560555045403530252015105
THIRD ORDER INTERCEPT – dBm
TPC 29. AD8008 Third Order Intercept vs. Frequency
VOUT – V p-p
–90
1
–70
–75
–80
–85
–65
26
G = ⴙ2
VS = 5V
FO = 20MHz
HD2, RL = 1k⍀
HD2, RL = 150⍀
HD3, RL = 150⍀
HD3, RL = 1k⍀
–95
–100
–105
–110 345
TPC 30. AD8008 Second and Third Harmonic
Distortion vs. V
OUT
and R
L
REV. D
AD8007/AD8008
–11–
FREQUENCY – Hz
10 1k100
VOLTAG E NOISE – nV/ Hz
100
10
110k 100k 1M
2.7nV/ Hz
TPC 31. Input Voltage Noise vs. Frequency
FREQUENCY – Hz
100k 10M1M
OUTPUT IMPEDANCE – ⍀
100
10
1
100M 1G
1000
0.1
0.01
G = ⴙ2
TPC 32. Output Impedance vs. Frequency
FREQUENCY – Hz
100M 1G
CMRR – dB
–10
–20
–30
100k 1M
0
10M
–40
–50
–60
–70
VS = ⴞ5V, ⴙ5V
TPC 33. CMRR vs. Frequency
FREQUENCY – Hz
10 10k100
CURRENT NOISE – pA/ Hz
100
10
1
100k 1M
1000
10M1k
NONINVERTING CURRENT NOISE 2.0pA/ Hz
INVERTING CURRENT NOISE 22.5pA / Hz
TPC 34. Input Current Noise vs. Frequency
FREQUENCY – Hz
100k 1G
CROSSTALK – dB
–100
1M 10M 100M
–90
–80
–70
–60
–50
–40
–20
–30 G = ⴙ2
R = 150⍀
V
S
= ⴞ5V
V
M
= 1V p-p
SIDE B DRIVEN
SIDE A DRIVEN
TPC 35. AD8008 Crosstalk vs. Frequency (Output to Output)
FREQUENCY – Hz
20
10
10k 1M100k
PSRR – dB
–20
–30
–40
–50
0
–10
10M 100M 1G
–60
–70
–80
+PSRR
–PSRR
TPC 36. PSRR vs. Frequency
(VS = ⴞ5 V, RL = 150 ⍀, RS = 200 ⍀, RF = 499 ⍀, unless otherwise noted.)
REV. D–12–
AD8007/AD8008
50mV/DIV
G = ⴙ1R
L
= 150⍀, V
S
= ⴙ5V AND ⴞ5V
R
L
= 1k⍀, V
S
= ⴙ5V AND ⴞ5V
010
20 30 40 50
TIME – ns
TPC 37. Small Signal Transient Response for
R
L
= 150
Ω
, 1 k
Ω
and V
S
= +5 V,
±
5 V
1V/DIV
G = +1 R
L
= 150⍀
R
L
= 1k⍀
01020304050
TIME – ns
TPC 38. Large Signal Transient Response for
R
L
= 150
Ω
, 1 k
Ω
G = ⴙ2
1V/DIV
010 20304050
TIME – ns
C
LOAD
= 0pF
C
LOAD
= 10pF
C
LOAD
= 20pF
TPC 39. Large Signal Transient Response
for Capacitive Load = 0 pF, 10 pF, and 20 pF
G = +2
50mV/DIV
01020304050
TIME – ns
R
L
= 150⍀, V
S
= +5V AND 5V
R
L
= 1k⍀, V
S
= +5V AND 5V
TPC 40. Small Signal Transient Response for
R
L
= 150
Ω
, 1 k
Ω
and V
S
= +5 V,
±
5 V
G = –1
1V/DIV
01020304050
TIME – ns
INPUT
OUTPUT
TPC 41. Large Signal Transient Response, G
= –1,
R
L
=150
Ω
50mV/DIV
CL = 0pF
CL = 20pF CL = 20pF
RSNUB = 10⍀
499⍀
499⍀
200⍀
49.9⍀
R
SNUB
C
LOAD
+
–
G = ⴙ2
010 20304050
TIME – ns
TPC 42. Small Signal Transient Response: Effect of
Series Snub Resistor when Driving Capacitive Load
REV. D
AD8007/AD8008
–13–
0 100 200
TIME – ns
INPUT (1V/DIV)
RL = 150⍀
RL = 1k⍀
OUTPUT (2V/DIV)
ⴚVS
ⴙVS
300 400 500
G = ⴙ2
TPC 43. Output Overdrive Recovery, R
L
= 1 k
Ω
,
150
Ω
, V
IN
=
±
2.5 V
0
TIME – ns
51015202530354045
G = +2
0.1
0
SETTLING TIME – %
0.2
0.3
0.4
0.5
ⴚ0.1
ⴚ0.2
ⴚ0.3
ⴚ0.4
ⴚ0.5
18ns
TPC 44. 0.1% Settling Time, 2 V Step
R
L
– ⍀
–1
2000
V
OUT
– V
3
2
1
0
4
400 600
–2
–3
–4
800 1000
G = +10
V
S
= 5V
V
IN
= 0.75V
TPC 45. V
OUT
Swing vs. R
LOAD
, V
S
=
±
5 V, G = +10,
V
IN
=
±
0.75 V
REV. D–14–
AD8007/AD8008
THEORY OF OPERATION
The AD8007 (single) and AD8008 (dual) are current feedback
amplifiers optimized for low distortion performance. A simplified
conceptual diagram of the AD8007 is shown in Figure 3. It closely
resembles a classic current feedback amplifier comprised of a
complementary emitter-follower input stage, a pair of signal mir-
rors, and a diamond output stage. However, in the case of the
AD8007/AD8008, several modifications have been made to greatly
improve the distortion performance over that of a classic current
feedback topology.
IDI
–
+VS
–VS
CJ1
CJ2
Q1
Q2
IN–
–
–
–
D1
D2
I1
I2
IN+
I3
I4
IDO
Q3
Q4
Q5
Q6
+VS
–VS
RF
OUT
RG
M2
M1
HiZ
Figure 3. Simplified Schematic of AD8007
The signal mirrors have been replaced with low distortion, high
precision mirrors. They are shown as “M1” and “M2” in Figure 3.
Their primary function from a distortion standpoint is to greatly
reduce the effect of highly nonlinear distortion caused by capaci-
tances C
J
1 and C
J
2. These capacitors represent the collector-to-base
capacitances of the mirrors’ output devices.
A voltage imbalance arises across the output stage, as measured
from the high impedance node “HiZ” to the output node
“Out.” This imbalance is a result of delivering high output
currents and is the primary cause of output distortion. Circuitry
is included to sense this output voltage imbalance and generate
a compensating current “I
DO
.” When injected into the circuit,
I
DO
reduces the distortion that would be generated at the output
stage. Similarly, the nonlinear voltage imbalance across the
input stage (measured from the noninverting to the inverting
input) is sensed, and a current “I
DI
” is injected to compensate
for input-generated distortion.
The design and layout are strictly top-to-bottom symmetric in
order to minimize the presence of even-order harmonics.
USING THE AD8007/AD8008
Supply Decoupling for Low Distortion
Decoupling for low distortion performance requires careful
consideration. The commonly adopted practice of returning the
high frequency supply decoupling capacitors to physically sepa-
rate (and possibly distant) grounds can lead to degraded
even-order harmonic performance. This situation is shown in
Figure 4 using the AD8007 as an example. Note that for a sinu-
soidal input, each decoupling
capacitor returns to its ground a
quasi-rectified current carrying
high even-order harmonics.
+V
S
–V
S
R
G
499⍀
R
S
200⍀
IN
R
F
499⍀
GND 1
GND 2
OUT
AD8007
+
+10␮F
10␮F
0.1␮F
0.1␮F
Figure 4. High Frequency Capacitors Returned
to Physically Separate Grounds (Not Recommended)
The decoupling scheme shown in Figure 5 is preferable. Here,
the two high frequency decoupling capacitors are first tied
together at a common node, and are then returned to the
ground plane through a single connection. By first adding the
two currents flowing through each high frequency decoupling
capacitor, one is ensuring that the current returned into the
ground plane is only at the fundamental frequency.
+VS
–VS
RG
499⍀
RS
200⍀
IN
RF
499⍀
OUT
AD8007
+
+10␮F
0.1␮F
10␮F
0.1␮F
Figure 5. High Frequency Capacitors Returned
to Ground at a Single Point (Recommended)
Whenever physical layout considerations prevent the decoupling
scheme shown in Figure 5, the user can connect one of the high
frequency decoupling capacitors directly across the supplies and
connect the other high frequency decoupling capacitor to ground.
This is shown in Figure 6.
REV. D
AD8007/AD8008
–15–
+V
S
–V
S
R
G
499⍀
R
S
200⍀
IN
R
F
499⍀
OUT
AD8007
+
+
10␮F
10␮F
C1
0.1␮F
C2
0.1␮F
Figure 6. High Frequency Capacitors Connected
across the Supplies (Recommended)
Layout Considerations
The standard noninverting configuration with recommended power
supply bypassing is shown in Figure 6. The 0.1 µF high fre-
quency decoupling capacitors should be X7R or NPO chip
components. Connect C2 from the +V
S
pin to the –V
S
pin. Con-
nect C1 from the +V
S
pin to signal ground.
The length of the high frequency bypass capacitor leads is critical.
Parasitic inductance due to long leads will work against the low
impedance created by the bypass capacitor. The ground for the
load impedance should be at the same physical location as the
bypass capacitor grounds. For the larger value capacitors, which
are intended to be effective at lower frequencies, the current
return path distance is less critical.
LAYOUT AND GROUNDING CONSIDERATIONS
Grounding
A ground plane layer is important in densely packed PC boards
to minimize parasitic inductances. However, an understanding of
where the current flows in a circuit is critical to implementing
effective high speed circuit design. The length of the current path
is directly proportional to the magnitude of parasitic induc-
tances and thus the high frequency impedance of the path. High
speed currents in an inductive ground return will create an
unwanted voltage noise. Broad ground plane areas will reduce
the parasitic inductance.
Input Capacitance
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
Even 1 pF or 2 pF of capacitance will reduce the input imped-
ance at high frequencies, in turn increasing the amplifier’s gain,
causing peaking of the frequency response or even oscillations
if severe enough. It is recommended that the external passive com-
ponents that are connected to the input pins be placed as close as
possible to the inputs to avoid parasitic capacitance. The ground
and power planes must be kept at a distance of at least 0.05 mm
from the input pins on all layers of the board.
Output Capacitance
To a lesser extent, parasitic capacitances on the output can cause
peaking of the frequency response. There are two methods to
effectively minimize its effect:
1. Put a small value resistor in series with the output to isolate
the load capacitance from the amplifier’s output stage.
(See TPC 7.)
2. Increase the phase margin by (a) increasing the amplifier’s
gain or (b) adding a pole by placing a capacitor in parallel
with the feedback resistor.
Input-to-Output Coupling
To minimize capacitive coupling, the input and output signal
traces should not be parallel. This helps reduce unwanted posi-
tive feedback.
External Components and Stability
The AD8007 and AD8008 are current feedback amplifiers and,
to a first order, the feedback resistor determines the bandwidth
and stability. The gain, load impedance, supply voltage, and
input impedances also have an effect.
TPC 6 shows the effect of changing R
F
on bandwidth and peaking
for a gain of +2. Increasing R
F
will reduce peaking but also
reduce the bandwidth. TPC 1 shows that for a given R
F
, increasing
the gain will also reduce peaking and bandwidth. Table I shows
the recommended R
F
and R
G
values that optimize bandwidth with
minimal peaking.
Table I. Recommended Component Values
Gain R
F
(Ω)R
G
(Ω)R
S
(Ω)
–1 499 499 200
+1 499 NA 200
+2 499 499 200
+5 499 124 200
+10 499 54.9 200
The load resistor will also affect bandwidth as shown in TPCs 2
and 5. A comparison between TPCs 2 and 5 also demonstrates
the effect of gain and supply voltage.
When driving loads with a capacitive component, stability is
improved by using a series snub resistor R
SNUB
at the output.
The frequency and pulse responses for various capacitive loads
are illustrated in TPCs 7 and 42, respectively.
For noninverting configurations, a resistor in series with the input,
R
S
, is needed to optimize stability for Gain = +1, as illustrated
in TPC 3. For larger noninverting gains, the effect of a series
resistor is reduced.
REV. D–16–
AD8007/AD8008
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) ⴛ 45ⴗ
8ⴗ
0ⴗ
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
85
41
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
0.80
0.60
0.40
8ⴗ
0ⴗ
85
4
1
4.90
BSC
PIN 1
0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COPLANARITY
0.10
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MO-187AA
5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
0.30
0.15
1.00
0.90
0.70
SEATING
PLANE
1.10 MAX
0.22
0.08 0.46
0.36
0.26
3
5 4
1 2
2.00 BSC
PIN 1
2.10 BSC
0.65 BSC
1.25 BSC
0.10 MAX
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203AA
REV. D
AD8007/AD8008
–17–
Revision History
Location Page
6/03—Data Sheet changed from REV. C to REV. D
Change to Layout Considerations section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Deleted Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Deleted EVALUATION BOARD section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10/02—Data Sheet changed from REV. B to REV. C
CONNECTION DIAGRAMS captions updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ORDERING GUIDE updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5 edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9/02—Data Sheet changed from REV. A to REV. B.
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8/02—Data Sheet changed from REV. 0 to REV. A.
Added AD8008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Added SOIC-8 (RN) and MSOP-8 (RM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to MAXIMUM POWER DISSIPATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
New Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
New TPCs 19–24 and TPCs 27, 29, 30, and 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Changes to EVALUATION BOARD section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MSOP-8 (RM) added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
–18–
–19–
C02866–0–6/03(D)
–20–