The Leader in High Temperature Semiconductor Solutions CHT-ATLAS Version: 3.5 5-Mar-15 (Last Modification Date) Dual Channel Power Transistor Driver General description Features CHT-ATLAS is a high-temperature, high reliability power transistor driver integrated circuit specifically designed to drive widebandgap power transistors, in particular Gallium Nitride (GaN) and Silicon Carbide Operating junction temperature: from -55C to +225C Gate drive supply voltage: 5 to 30V 2 channels Separate logic level control inputs Output current: up to 2 x 2A @ (SiC) devices including normally-On and 225C normally-Off JFETs, MOSFETs and BJTs. Propagation delay: 40 ns typ It is also used with standard silicon Rise time / fall time: 10ns Typ. MOSFETs and IGBTs in standard tempera- (with CLoad=1nF and VCC=15V) ture applications (e.g. 125C) where it Soft-shut down brings an increase in reliability and lifetime High Impedance mode by an order of magnitude compared to tra- Capable to drive normally-On and ditional solutions. The circuit features 2 independent push-pull channels capable of normally-Off devices sourcing/sinking 2A each. When configured together to drive a single power switch, the combination of the 2 distinct channels al- Validated at 225C for 1000 hours (and still on-going) Package: CSOIC28 Applications lows driving of specific devices that require for instance a dynamic pulse of current in Intelligent Power Modules (IPM) combination with a continuous current in Power conversion, power generation and actuator controls in aeronautics order to be properly turned-on. The circuit includes a soft-shut-down capability that Solar inverters slowly shuts down the power transistor in Motor drives, battery chargers and DC-DC converters in EV / HEV case of fault. Power conversion and motor drive in railway Switched mode power supplies (SMPS) Wind turbine power converters PUBLIC Doc. DS-100781 V3.5 WWW.CISSOID.COM 1 of 2 5-Mar-15 Contact : Gonzalo Picun (+32-10-489214)Mar. 15 CHT-ATLAS-Dual Channel Power Transistor Driver DATASHEET (Last Modification Date) Functional Block Diagram CHT-ATLAS CBSTA_T CP_A VCC5PA SSDA_IN HighZA Level Shifter & AntiShoot through Logic INA PVCCA HS_A OUTPA CBSTA_B SSDA OUTNA PVSSA LS_A VSSA PVSSA CBSTB_T CP_B VCC5PB SSDB_IN HighZB INB Level Shifter & AntiShoot through Logic PVCCB HS_B OUTPB CBSTB_B SSDB OUTNB PVSSB LS_B VSSB PVSSB PVCC PUBLIC Doc. DS-100781 V3.5 WWW.CISSOID.COM PVCC 2 of 12 5-Mar-15 Contact : Gonzalo Picun (+32-10-489214)Mar. 15 CHT-ATLAS-Dual Channel Power Transistor Driver DATASHEET (Last Modification Date) Package Configuration and Pin Description: Pin # 1 Pin Name SSDA 2 3 PVCC INA 4 HIGHZA 5 SSDA_IN 6 VCC5PA (input) 7 VSSA 8 VSSB 9 VCC5PB (input) 10 SSDB_IN 11 HIGHZB 12 INB 13 14 PVCC SSDB 15 CBSTB_T 16 CBSTB_B 17 OUTPB 18 19 20 OUTNB PVCCB PVSSB1 21 PVSSB2 22 PVSSA2 23 PVSSA1 24 25 26 PVCCA OUTNA OUTPA 27 CBSTA_B 28 CBSTA_T SOIC28 SSDA 1 28 CBSTA_T PVCC 2 27 CBSTA_B INA 3 26 OUTPA HIGHZA 4 25 OUTNA SSDA_IN 5 24 PVCCA VCC5PA 6 23 PVSSA1 VSSA 7 22 PVSSA2 VSSB 8 21 PVSSB2 VCC5PB 9 20 PVSSB1 SSDB_IN 10 19 PVCCB HIGHZB 11 18 OUTNB INB 12 17 OUTPB PVCC 13 16 CBSTB_B SSDB 14 15 CBSTB_T Pin Description Soft Shutdown output pin of channel A. When SSDA_IN pin is low, this node is pulled down to PVSSA. To be connected to PVCCA and PVCCB Schmitt triggered input of channel A driver. 5V CMOS input with respect to VSS. Schmitt triggered input of the tri-state control signal for channel A driver. 5V CMOS input with respect to VSSA. When driven low, sink, source and SSDA output transistors are turned off (see ATLAS Logic Table). Channel A output is in high impedance. Schmitt triggered input controlling the soft shut-down transistor for the channel A (see ATLAS Logic Table) 5V positive power supply with respect to VSSA. To be bypassed to VSSA by a 1F capacitor. Analogue negative power supply for channel A Analogue negative power supply for channel B 5V positive power supply with respect to VSSB. To be bypassed to VSSB by a 1F capacitor. Schmitt triggered input controlling the soft shut-down transistor for the channel B (see ATLAS Logic Table) Schmitt triggered input of the tri-state control signal for Channel B driver. 5V CMOS input with respect to VSSB. When driven low, both sink and source output transistors are turned off. Channel B output is in high impedance. Schmitt triggered input of Channel B driver. 5V CMOS input with respect to VSSB. To be connected to PVCCA and PVCCB Soft Shutdown output pin of channel B. When SSDB_IN pin is low, this node is internally pulled down to PVSSB. Connection for the top plate of the bootstrap capacitor for channel B Connection for the bottom plate of the bootstrap capacitor for channel B Channel B sourcing output (Isource_max=2A) Channel B sinking output (Isinking_max=2A) Positive power supply of channel B driver. Negative power supply for channel B (First Pin) Negative power supply for channel B (Second Pin1) Negative Power supply for channel A (Second Pin2) Negative power supply for channel A (First Pin) Positive power supply for channel A. Channel A sinking output (Isinking_max=2A) Channel A sourcing output (Isource_max=2A) Connection for the bottom plate of the bootstrap capacitor for channel A Connection for the top plate of the bootstrap capacitor for channel A 1 To minimize parasitic inductors and ringing, both PVSSB1 and PVSSB2 must be connected to the negative power supply with minimum parasitic inductors 2 To minimize parasitic inductors and ringing, both PVSSA1 and PVSSA2 must be connected to the negative power supply with minimum parasitic inductors PUBLIC Doc. DS-100781 V3.5 WWW.CISSOID.COM 3 of 12 5-Mar-15 Contact : Gonzalo Picun (+32-10-489214)Mar. 15 CHT-ATLAS-Dual Channel Power Transistor Driver DATASHEET (Last Modification Date) Logic Table INA(B) 0 1 X X Inputs SSDA_IN (SSDB_IN) 1 1 0 X HIGHZA(B) OUTPA(B) Outputs OUTNA(B) SSDA(B) 1 1 1 0 highZ PVCCA highZ highZ PVSSA highZ highZ highZ highZ highZ PVSSA highZ In normal operation pins HIGHZA/B and pins SSDA/B_IN are set to logic-1 (VCC5PA/B=5V). Applying logic-0 (0V) to pin INA/B turns the low-side driver on, pulling pin OUTA/B down to PVSSA/B. OUTPA/B is in high-impedance state. Applying logic-1 (5V) to pin INA/B, pin OUTNA/B is set to high-impedance state while the high-side driver is turned on pulling OUTPA/B to PVCCA/B. Maintaining the device enabled (HIGHZA/B set to logic-1) the soft-shutdown is activated by setting pin SSDA/B_IN to logic-0. Both high-side and low-side drivers are turned off setting pints OUTPA/B and OUTNA/B to high impedance state. SSDA/B pin is pulled down to PVSSA/B. The logic level at pin INA/B does not matter. The device is disabled when pin HIGHZA/B is set to logic-0, whatever the logic level at the other control signals. PUBLIC Doc. DS-100781 V3.5 WWW.CISSOID.COM 4 of 12 5-Mar-15 Contact : Gonzalo Picun (+32-10-489214)Mar. 15 CHT-ATLAS-Dual Channel Power Transistor Driver DATASHEET (Last Modification Date) Absolute Maximum Ratings Operating Conditions These ratings are considered individually (not in combination). If not specified, voltages are related to VSSA for channel A and to VSSB for channel B. VSSA and VSSB must be at the same potential. Supply Voltage VCC5P to VSS Supply Voltage PVCC to PVSS Junction temperature Supply Voltage PVCCA/B to PVSSA/B Supply Voltage VCC5PA/B to VSSA/B Voltage on IN, HIGHZ, SSD_IN to VSS Voltage on CBST_T to PVSS Driver Output voltage (OUT, CBST_B) Junction temperature Tj ESD Rating (expected) Human Body Model 4.75V to 5.25V 5V to 30V -55C to +225C -0.5 to 35V -0.5 to 5.5V -0.5 to VCC5P+0.5V VCC5P-0.5 to PVCC+5.5 PVSS-0.5 to PVCC+5.5 C 250C 1.5kV Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Frequent or extended exposure to absolute maximum rating conditions or above may affect device reliability. PUBLIC Doc. DS-100781 V3.5 WWW.CISSOID.COM 5 of 12 5-Mar-15 Contact : Gonzalo Picun (+32-10-489214)Mar. 15 CHT-ATLAS-Dual Channel Power Transistor Driver DATASHEET (Last Modification Date) Electrical Characteristics Unless otherwise stated: (VCC-VSS)=5V, (PVCC-PVSS)=15V, Tj=25C. Bold underlined values indicate values over the whole temperature range (-55C < T j < +225C). Parameter External Power Supply 3 External Power Supply PVCCA/B versus PVSS PVCCA/B quiescent current PVCCA/B quiescent current PVCCA/B average current Condition Min Typ 5 INA/INB=0 INA/INB=5V 20kHz, 50% duty cycle PVCCA/B = 25V CLOAD = 1nF INA/INB=0 and HighZA/B=X VCC5PA/B quiescent current VCC5PA/B quiescent cur- INA/INB=X and HighZA/B=0 rent VCC5PA/B quiescent cur- INA/INB=5V and HighZA/B=5V 4 rent VCC5PA/B average current 20kHz, 50% duty cycle External Power Supply VCC5P versus VSS Input signals (INA/B, HighZA/B) Input start threshold Input stop threshold Hysteresis Drivers 5 OUTNA/B sink current 6 OUTPA/B source current High state output resistance Low state output resistance Propagation delay when CLoad=1nF; (PVCC-PVSS)=15V output rising (50% 50%) (INOUTPA/B) Propagation delay when CLoad=1nF; (PVCC-PVSS)=15V output falling (50% 50%) (INOUTNA/B) Rise Time (10%-90%) CLoad=1nF; (PVCC-PVSS)=15V Fall Time (10%-90%) CLoad=1nF; (PVCC-PVSS)=15V Soft Shut-down outputs (SSDA/B) Delay from SSDA/B_IN to SSDA/B output Open-drain transistor ONResistance Thermal resistance Junction-to-air thermal resistance (JA) 4.75 3.03 1.1 1.68 3.43 1.39 2.04 Max 30 V 0.1 0.2 mA mA 0.4 mA 0.1 mA 0.1 mA 1 mA 0.5 mA 5.25 V 3.83 1.85 2.39 V V V 2 A 1.95 2.1 2 15 Units A 40 ns 40 ns 10 10 ns ns 120 ns 35 42 65 C/W 3 Voltage externally supplied to the chip In this case, quiescent current means the average current over several Charge-Pump turn-on/off periods 5 In practice, the maximum sink current is N multiplied by the number of ATLAS channels used in the application 6 In practice, the maximum source current is N multiplied by the number of ATLAS channels used in the application 4 PUBLIC Doc. DS-100781 V3.5 WWW.CISSOID.COM 6 of 12 5-Mar-15 Contact : Gonzalo Picun (+32-10-489214)Mar. 15 CHT-ATLAS-Dual Channel Power Transistor Driver DATASHEET (Last Modification Date) Typical Performance Characteristics 45 60 40 50 35 40 Delay [ns] Delay [ns] 30 25 20 30 15 20 10 10 5 0 -100 -50 0 0 50 100 150 200 -100 -50 0 Temperature [C] Figure 1: Turn-Low Propagation Delay vs. Temperature 7 8 6 7 Time [ns] Time [ns] 3 4 3 2 1 1 0 0 0 50 100 150 200 -100 -50 0 1.6 2 1.4 1.8 1.2 1 0.8 0.6 0.4 200 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0 50 100 150 200 -100 -50 0 Temperature [C] 50 100 150 200 Temperature [C] Figure 5: Low-state output resistance vs. Temperature Figure 6: High-state output resistance vs. Temperature 4 4.5 3.5 4 3 3.5 3 Current [A] 2.5 Current [A] 150 1.6 0.2 2 1.5 2.5 2 1.5 1 1 0.5 0.5 0 -50 100 Figure 4: Turn-High Rise Time vs. Temperature ON resistance [Ohm] ON resistance [Ohm] Figure 3: Turn-Low Fall Time vs. Temperature -100 50 Temperature [C] Temperature [C] -50 200 5 2 -100 150 6 4 -50 100 Figure 2: Turn-High Propagation Delay vs. Temperature 5 -100 50 Temperature [C] 0 0 50 100 150 200 -100 Temperature [C] 0 50 100 150 200 Temperature [C] Figure 7: Sink Current vs. Temperature PUBLIC Doc. DS-100781 V3.5 -50 Figure 8: Source Current vs. Temperature WWW.CISSOID.COM 7 of 12 5-Mar-15 Contact : Gonzalo Picun (+32-10-489214)Mar. 15 CHT-ATLAS-Dual Channel Power Transistor Driver DATASHEET (Last Modification Date) Typical performances: Switching Times Test Circuit VCC5P (+5V) PVCC (+15V) CHT-ATLAS CBSTA_T C5P = 1 mF CPVCC = 10 mF PVCC (+15V) CP_A VSS (0) VCC5P (+5V) VCC5PA SSDA_IN SSD_IN HighZA HIGHZ Level Shifter & AntiShut through Logic CBSTA = 22nF PVCCA HS_A RGPA = 10 OUTPA 1 2 CBSTA_B OUTA SSDA OUTNA 1 2 RGNA = 10 IN INA VSS (0V) COUTA = 1 nF PVSSA LS_A VSS (0V) PVSSA VSSA VSS (0 V) VSS (0 V) CBSTB_T PVCC (+15V) CP_B VCC5P (+5V) VCC5PB SSDB_IN HighZB INB Level Shifter & AntiShut through Logic PVCCB HS_B RGPB = 10 OUTPB 1 2 CBSTB_B OUTB SSDB OUTNB 1 2 RGNB = 10 COUTB = 1nF PVSSB LS_B VSS (0V) PVSSB VSSB VSS (0 V) CBSTB = 22 nF 2 13 VSS (0 V) PVCC (15V) PUBLIC Doc. DS-100781 V3.5 WWW.CISSOID.COM 8 of 12 5-Mar-15 Contact : Gonzalo Picun (+32-10-489214)Mar. 15 CHT-ATLAS-Dual Channel Power Transistor Driver DATASHEET (Last Modification Date) Application Diagrams Driving a Normally-ON SiC JFET VCC5P (VSS+5V) NS (0V) CHT-ATLAS CBSTA_T C5P VSS (-27V) CP_A PVCCA VCC5P VCC5PA SSD_IN SSDA_IN HIGHZ HighZA Level Shifter & AntiShut through Logic NS (0V) CPVCC VSS (-27V) CBSTA HS_A RGPA OUTPA NG CBSTA_B SSDA ND Normally ON SiC JFET NS (0V) OUTNA RGNA IN INA PVSSA LS_A PVSSA VSSA VSS (-27V) VSS (-27V) CBSTB_T CP_B PVCCB VCC5P VCC5PB SSDB_IN Level Shifter & AntiShut through Logic NS (0V) CBSTB HS_B RGPB OUTPB SSDB OUTNB RGNB PVSSB LS_B PVSSB VSSB VSS (-27V) The logical control signals (INA/B, HIGHZA/B, SSDA/B_IN) belong to the VCC5P supply domain (5V with respect to VSS). VSS and PVSS must be electrically tied together in the application board. CBSTB_B HighZB INB The normally-ON SiC JFET is turned off once the gate-source voltage drops below the negative pinch-off voltage of the JFET. At zero gate-source voltage, the device is fully ON. For proper gate drive, CHT-ATLAS has its positive supply pins (PVCCA/B) tied to the source of the JFET (NS). Its negative supply pins (PVSSA/B) are connected to a negative voltage power supply with respect to NS. 2 13 VSS (-27V) NS (0V) Local decoupling between PVCC(=NS) and PVSS is mandatory as large current peaks flow through those supply connections during gate switching. The decoupling capacitor must deliver the total gate charge with minimum supply voltage loss. CHT-ATLAS features 2 channels (A and B) with equal drive capabilities (>2A, <2). For higher drive capability, the channels can be connected in parallel. The high-side (pins OUTPA/B) and low-side (pin OUTNA/B) drivers inside CHT-ATLAS pull the JFET gate voltage up and down through series resistors RGPA/B and RGNA/B Resistors RGPA/B and RGNA/B limit the gate current at turn-on and turn-off and control the switching time of the JFET and therefore the dV/dt in order to reduce probability of shoot-through current (parasitic turn-on of the blocking device in a half-bridge configuration). They also help damping oscillations and limiting voltage overshoot at the JFET gate which could result from stray inductances in the gate drive circuit and which could cause damage to the devices. Typical values range from 5 to 10 ohms. At positive switching, the bootstrap capacitors CBSTA/B bias the high-side drivers above the positive supply voltage PVCC. The typical bootstrap capacitance is 22nF. After the transition, the internal charge-pumps keep the high-side drivers on till the next negative transition without any minimum switching frequency constraint. SSDA/B offer soft-shutdown of the JFET by controlling the input signal SSDA/B_IN. Both high-side and low-side drives are turned off and the gate is pulled down through RGNA/B via pin SSDA/B by weaker pull-down transistors. PUBLIC Doc. DS-100781 V3.5 WWW.CISSOID.COM 9 of 12 5-Mar-15 Contact : Gonzalo Picun (+32-10-489214)Mar. 15 CHT-ATLAS-Dual Channel Power Transistor Driver DATASHEET (Last Modification Date) Driving a Normally-OFF SiC JFET VCC5P (VSS+5V) PVCC (+15V) PVCC2 (+6V) PVSS (-15V) CHT-ATLAS CBSTA_T C5P VSS (-15V) Level Shifter & AntiShut through Logic VCC5PA SSD_IN SSDA_IN HIGHZ HighZA CPVCC CPVCC2 CPVSS PVCC2 (+6V) CP_A NS (0V) PVCCA VCC5P NS (0V) NS (0V) CBSTA HS_A RGPA OUTPA NG CBSTA_B SSDA OUTNA ND Normally OFF SiC JFET NS (0V) Unlike the normally-on JFET, the gatesource junction of the normally-off SiC JFET is forward biased in the device conduction state. In addition to the dynamic current for charging/discharging the total gate capacitance, some steadystate current has to be provided to maintain conduction after the device has been switched on. RGNA IN INA PVSSA LS_A The two channels of CHT-ATLAS are combined in a way to deliver both dynamic and steady-state currents. PVSSA VSSA VSS (-15V) VSS (-15V) CBSTB_T PVCC (+15V) CP_B PVCCB VCC5P Level Shifter & AntiShut through Logic VCC5PB SSDB_IN RGPB OUTPB CBSTB_B SSDB HighZB OUTNB INB IN_PULSE Channel A must be driven with the regular PWM control signal (IN) while channel B must be driven by a second control signal (IN_PULSE) giving a shorter impulse at the turn-on. CBSTB HS_B PVSSB LS_B PVSSB VSSB 2 13 The dynamic current is supplied by the high-side driver of channel B (OUTPB) at PVCC turn-on and the low-side driver of chan(+15V) nel A (OUTNB) at turn-off through resistances RGPB and RGNA. The steady-state current is provided by the high-side driver in channel A (OUTPA). Similar considerations as with the normally-on JFET apply to the selection of resistors RGPA and RGPB. Avoiding too small value for RGPB, the positive supply voltage PVCCB is typically +15V7. VSS (-15V) VSS (-15V) The threshold voltage of the normally-off JFET being low, the gate should best be pulled down to a negative voltage with respect to the JFET source when the device is turned off. The lower the voltage, the better the immunity to shoot-through current in a half-bridge application. The negative supply PVSS depends on the SiC device gatesource voltage rating. A typical assumption for PVSS is -15V. The steady-state current is supplied by the positive supply of channel A (PVCC2) through pin OUTPA and resistor RGPA. RGPA and PVCC2 must be sized in order to deliver the current required by the SiC device which is of the order of 100mA7. PVCC2 can be identical to PVCC but a smaller voltage could be used for power saving, a diode must then be inserted between RGPA and the gate of the SiC device. Local decoupling of PVCC, PVCC2 and PVSS to NS is mandatory. Driving a SiC MOSFET NS (0V) CHT-ATLAS PVCC (20V) PVSS (-5V) Driving a SiC MOSFET requires a gate driver capable of a large gate voltage swing and fast gate voltage transitions. CBSTA_T C5P PVCC (20V) CP_A VSS (-5V) NS (0V) VCC5PA SSD_IN SSDA_IN HIGHZ HighZA Level Shifter & AntiShut through Logic CPVCC CPVSS PVCCA NS (0V) HS_A NG OUTNA INA ND SiC MOSFET NS (0V) PVSSA LS_A PVSSA VSSA VSS (-5V) VSS (-5V) CBSTB_T NS (0V) VCC5PB SSDB_IN The high-side driver pulls the MOSFET gate voltage to PVCC (typically 20 V for best performance8) and the low-side divers pulls it down to negative PVSS8 (typically -2V to -5V). PVCC (20V) CP_B Level Shifter & AntiShut through Logic Both CHT-ATLAS channels can be connected in parallel for fast gate switching. RGPA OUTPA CBSTA_B SSDA RGNA IN NS (0V) CBSTA PVCCB CBSTB HS_B RGPB OUTPB CBSTB_B SSDB HighZB Considerations similar to those mentioned with SiC JFETS apply with respect to the gate resistances and the importance of proper decoupling of the supplies. OUTNB RGNB INB PVSSB LS_B PVSSB VSSB VSS (-5V) 2 13 VSS (-5V) PVCC (20V) 7 8 Robin Kelley et al., "Optimized Gate Driver for Enhancement-mode SiC JFET" Bob Callanan, "Application Considerations for SiC MOSFETS", Cree Inc., January 2011. PUBLIC Doc. DS-100781 V3.5 WWW.CISSOID.COM 10 of 12 5-Mar-15 Contact : Gonzalo Picun (+32-10-489214)Mar. 15 CHT-ATLAS-Dual Channel Power Transistor Driver DATASHEET (Last Modification Date) Package Drawing 17.90 9.90 2.15 0.42 7.45 4.70 0.55 0.5-1.25 Min 8.50 / Max 9.00 Min 10.00 / Max 11.00 4.70 6.75 7.45 0.20 1.27 0.42 CSOIC 28 Drawing (mm +/- 10%) Ordering Information Ordering Reference CHT-TIT3345E-CSOIC28-T PUBLIC Doc. DS-100781 V3.5 Package CSOIC-28 Temperature Range -55C to +225C WWW.CISSOID.COM Marking CHT-TIT3345E 11 of 12 5-Mar-15 Contact : Gonzalo Picun (+32-10-489214)Mar. 15 CHT-ATLAS-Dual Channel Power Transistor Driver DATASHEET (Last Modification Date) Contact & Ordering CISSOID S.A. Headquarters and contact EMEA: CISSOID S.A. - Rue Francqui, 3 - 1435 Mont Saint Guibert - Belgium T : +32 10 48 92 10 - F: +32 10 88 98 75 Email: sales@cissoid.com Sales Representatives: Visit our website: http://www.cissoid.com Disclaimer Neither CISSOID, nor any of its directors, employees or affiliates make any representations or extend any warranties of any kind, either express or implied, including but not limited to warranties of merchantability, fitness for a particular purpose, and the absence of latent or other defects, whether or not discoverable. In no event shall CISSOID, its directors, employees and affiliates be liable for direct, indirect, special, incidental or consequential damages of any kind arising out of the use of its circuits and their documentation, even if they have been advised of the possibility of such a damage. The circuits are provided "as is". CISSOID has no obligation to provide maintenance, support, updates, or modifications. PUBLIC Doc. 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