LTC6993CS6-2#TRMPBF - LINEAR TECHNOLOGY

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

TYPICAL APPLICATION

FEATURES DESCRIPTION

TimerBlox: Monostable

Pulse Generator (One Shot)

The LT C

6993 is a monostable multivibrator (also known

as a “one-shot” pulse generator) with a programmable

pulse width of 1µs to 33.6 seconds. The LTC6993 is part

of the TimerBlox

family of versatile silicon timing devices.

A single resistor, RSET, programs an internal master os-

cillator frequency, setting the LTC6993’s time base. The

output pulse width is determined by this master oscillator

and an internal clock divider, NDIV

, programmable to eight

settings from 1 to 221.

tOUT =

DIV

•R

SET

50kΩ

•1µs, NDIV = 1, 8, 64,...,221

The output pulse is initiated by a transition on the trigger

input (TRIG). Each part can be configured to generate posi-

tive or negative output pulses. The LTC6993 is available

in four versions to provide different trigger signal polarity

and retrigger capability.

DEVICE INPUT POLARITY RETRIGGER

LTC6993-1 Rising-Edge No

LTC6993-2 Rising-Edge Yes

LTC6993-3 Falling-Edge No

LTC6993-4 Falling-Edge Yes

The LTC6993 also offers the ability to dynamically adjust

the width of the output pulse via a separate control voltage.

For easy configuration of the LTC6993, download the

TimerBlox Designer tool at www.linear.com/timerblox.

Envelope Detector

APPLICATIONS

n Pulse Width Range: 1µs to 33.6 Seconds

n Configured with 1 to 3 Resistors

n Pulse Width Max Error:

– <2.3% for Pulse Width > 512µs

– <3.4% for Pulse Width of 8µs to 512µs

– <4.9% for Pulse Width of 1µs to 8µs

n Four LTC6993 Options Available:

– Rising-Edge or Falling-Edge Trigger

– Retriggerable or Non-Retriggerable

n Configurable for Positive or Negative Output Pulse

n Fast Recovery Time

n 2.25V to 5.5V Single Supply Operation

n 70µA Supply Current at 10µs Pulse Width

n 500µs Start-Up Time

n CMOS Output Driver Sources/Sinks 20mA

n –55°C to 125°C Operating Temperature Range

n Available in Low Profile (1mm) SOT-23 (ThinSOT™)

and 2mm × 3mm DFN

n Watchdog Timer

n Frequency Discriminators

n Missing Pulse Detection

n Envelope Detection

n High Vibration, High Acceleration Environments

n Portable and Battery-Powered Equipment

L, LT , LT C , LT M , Linear Technology, TimerBlox and the Linear logo are registered trademarks

and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

69931234 TA01a

LTC6993-2

OUT

V+

DIV

TRIG

GND

SET

RSET

800k

3.3V

0.1µF

SIGNAL

ENVELOPE

MODULATED

CARRIER

TRIG

2V/DIV

OUT

2V/DIV

50µs/DIV 69931234 TA01b

80kHz CARRIER

16µs

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (V+) to GND ........................................6V

Maximum Voltage on Any Pin

.................................. (GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V)

Operating Temperature Range (Note 2)

LTC6993C ............................................ –40°C to 85°C

LTC6993I .............................................–40°C to 85°C

LTC6993H .......................................... –40°C to 125°C

LTC6993MP ....................................... –55°C to 125°C

(Note 1)

ORDER INFORMATION

TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE

LTC6993CDCB-1#TRMPBF LTC6993CDCB-1#TRPBF LDXH 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C

LTC6993IDCB-1#TRMPBF LTC6993IDCB-1#TRPBF LDXH 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C

LTC6993HDCB-1#TRMPBF LTC6993HDCB-1#TRPBF LDXH 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C

LTC6993CDCB-2#TRMPBF LTC6993CDCB-2#TRPBF LDXK 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C

LTC6993IDCB-2#TRMPBF LTC6993IDCB-2#TRPBF LDXK 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C

LTC6993HDCB-2#TRMPBF LTC6993HDCB-2#TRPBF LDXK 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C

LTC6993CDCB-3#TRMPBF LTC6993CDCB-3#TRPBF LFMJ 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C

LTC6993IDCB-3#TRMPBF LTC6993IDCB-3#TRPBF LFMJ 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C

LTC6993HDCB-3#TRMPBF LTC6993HDCB-3#TRPBF LFMJ 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C

LTC6993CDCB-4#TRMPBF LTC6993CDCB-4#TRPBF LFMM 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C

LTC6993IDCB-4#TRMPBF LTC6993IDCB-4#TRPBF LFMM 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C

LTC6993HDCB-4#TRMPBF LTC6993HDCB-4#TRPBF LFMM 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C

LTC6993CS6-1#TRMPBF LTC6993CS6-1#TRPBF LTDXG 6-Lead Plastic TSOT-23 0°C to 70°C

LTC6993IS6-1#TRMPBF LTC6993IS6-1#TRPBF LTDXG 6-Lead Plastic TSOT-23 –40°C to 85°C

LTC6993HS6-1#TRMPBF LTC6993HS6-1#TRPBF LTDXG 6-Lead Plastic TSOT-23 –40°C to 125°C

TOP VIEW

OUT

GND

TRIG

V+

DIV

SET

DCB PACKAGE

6-LEAD (2mm × 3mm) PLASTIC DFN

TJMAX = 150°C, θJA = 64°C/W, θJC = 10.6°C/W

EXPOSED PAD (PIN 7) CONNECTED TO GND,

PCB CONNECTION OPTIONAL

TRIG 1

GND 2

SET 3

6 OUT

5 V+

4 DIV

TOP VIEW

S6 PACKAGE

6-LEAD PLASTIC TSOT-23

TJMAX = 150°C, θJA = 192°C/W, θJC = 51°C/W

PIN CONFIGURATION

Specified Temperature Range (Note 3)

LTC6993C ................................................ 0°C to 70°C

LTC6993I .............................................–40°C to 85°C

LTC6993H .......................................... –40°C to 125°C

LTC6993MP ....................................... –55°C to 125°C

Junction Temperature ........................................... 150°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

S6 Package ....................................................... 300°C

Lead Free Finish

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15

(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.

TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE

LTC6993CS6-2#TRMPBF LTC6993CS6-2#TRPBF LTDXJ 6-Lead Plastic TSOT-23 0°C to 70°C

LTC6993IS6-2#TRMPBF LTC6993IS6-2#TRPBF LTDXJ 6-Lead Plastic TSOT-23 –40°C to 85°C

LTC6993HS6-2#TRMPBF LTC6993HS6-2#TRPBF LTDXJ 6-Lead Plastic TSOT-23 –40°C to 125°C

LTC6993CS6-3#TRMPBF LTC6993CS6-3#TRPBF LTFMH 6-Lead Plastic TSOT-23 0°C to 70°C

LTC6993IS6-3#TRMPBF LTC6993IS6-3#TRPBF LTFMH 6-Lead Plastic TSOT-23 –40°C to 85°C

LTC6993HS6-3#TRMPBF LTC6993HS6-3#TRPBF LTFMH 6-Lead Plastic TSOT-23 –40°C to 125°C

LTC6993CS6-4#TRMPBF LTC6993CS6-4#TRPBF LTFMK 6-Lead Plastic TSOT-23 0°C to 70°C

LTC6993IS6-4#TRMPBF LTC6993IS6-4#TRPBF LTFMK 6-Lead Plastic TSOT-23 –40°C to 85°C

LTC6993HS6-4#TRMPBF LTC6993HS6-4#TRPBF LTFMK 6-Lead Plastic TSOT-23 –40°C to 125°C

LTC6993MPS6-1#TRMPBF LTC6993MPS6-1#TRPBF LTDXG 6-Lead Plastic TSOT-23 –55°C to 125°C

LTC6993MPS6-2#TRMPBF LTC6993MPS6-2#TRPBF LTDXJ 6-Lead Plastic TSOT-23 –55°C to 125°C

LTC6993MPS6-3#TRMPBF LTC6993MPS6-3#TRPBF LTFMH 6-Lead Plastic TSOT-23 –55°C to 125°C

LTC6993MPS6-4#TRMPBF LTC6993MPS6-4#TRPBF LTFMK 6-Lead Plastic TSOT-23 –55°C to 125°C

TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.

Consult LT C Marketing for parts specified with wider operating temperature ranges.

Consult LT C Marketing for information on lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ORDER INFORMATION

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tOUT Output Pulse Width 1µ 33.55 sec

∆tOUT Pulse Width Accuracy (Note 4) NDIV ≥ 512

±1.7 ±2.3

±3.0

8 ≤ NDIV ≤ 64

±2.4 ±3.4

±4.4

NDIV = 1 (LTC6993-1 or LTC6993-2)

±3.6 ±4.9

±6.0

NDIV = 1 (LTC6993-3 or LTC6993-4)

±4.0 ±5.3

±6.4

∆tOUT/∆TPulse Width Drift Over Temperature NDIV ≥ 512

NDIV ≤ 64

±0.006

±0.008

%/°C

Pulse Width Change With Supply NDIV ≥ 512 V+ = 4.5V to 5.5V

V+ = 2.25V to 4.5V

–0.6

–0.4

–0.2

–0.1

8 ≤ NDIV ≤ 64 V+ = 4.5V to 5.5V

V+ = 2.7V to 4.5V

V+ = 2.25V to 2.7V

–0.9

–0.7

–1.1

–0.2

–0.1

0.4

0.9

Lead Free Finish

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15

(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Pulse Width Jitter (Note 10) NDIV = 1 V+ = 5.5V

V+ = 2.25V

0.85

0.45

%P-P

NDIV = 8 0.20 %P-P

NDIV = 64 0.05 %P-P

NDIV = 512 0.20 %P-P

NDIV = 4096 0.03 %P-P

tSPulse Width Change Settling Time (Note 9) tMASTER = tOUT/NDIV 6 • tMASTER µs

Power Supply

V+Operating Supply Voltage Range l2.25 5.5 V

Power-On Reset Voltage l1.95 V

IS(IDLE) Supply Current (Idle) RL = ∞, RSET = 50k, NDIV ≤ 64 V+ = 5.5V

V+ = 2.25V

165

125

200

160

µA

RL = ∞, RSET = 50k, NDIV ≥ 512 V+ = 5.5V

V+ = 2.25V

135

105

175

140

µA

RL = ∞, RSET = 800k, NDIV ≤ 64 V+ = 5.5V

V+ = 2.25V

110

µA

RL = ∞, RSET = 800k, NDIV ≥ 512 V+ = 5.5V

V+ = 2.25V

100

µA

Analog Inputs

VSET Voltage at SET Pin l0.97 1.00 1.03 V

∆VSET/∆TVSET Drift Over Temperature l±75 µV/°C

RSET Frequency-Setting Resistor l50 800 kΩ

VDIV DIV Pin Voltage l0 V+V

∆VDIV/∆V+DIV Pin Valid Code Range (Note 5) Deviation from Ideal

VDIV/V+ = (DIVCODE + 0.5)/16

l±1.5 %

DIV Pin Input Current l±10 nA

Digital I/O

TRIG Pin Input Capacitance 2.5 pF

TRIG Pin Input Current TRIG = 0V to V+±10 nA

VIH High Level TRIG Pin Input Voltage (Note 6) l0.7 • V+V

VIL Low Level TRIG Pin Input Voltage (Note 6) l0.3 • V+V

IOUT(MAX) Output Current V+ = 2.7V to 5.5V ±20 mA

VOH High Level Output Voltage (Note 7) V+ = 5.5V IOUT = –1mA

IOUT = –16mA

5.45

4.84

5.48

5.15

V+ = 5.5V IOUT = –1mA

IOUT = –16mA

3.24

2.75

3.27

2.99

V+ = 2.25V IOUT = –1mA

IOUT = –8mA

2.17

1.58

2.21

1.88

VOL Low Level Output Voltage (Note 7) V+ = 5.5V IOUT = 1mA

IOUT = 16mA

0.02

0.26

0.04

0.54

V+ = 3.3V IOUT = 1mA

IOUT = 10mA

0.03

0.22

0.05

0.46

V+ = 2.25V IOUT = 1mA

IOUT = 8mA

0.03

0.26

0.07

0.54

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC6993C is guaranteed functional over the operating

temperature range of –40°C to 85°C.

Note 3: The LTC6993C is guaranteed to meet specified performance from

0°C to 70°C. The LTC6993C is designed, characterized and expected to

meet specified performance from –40°C to 85°C but it is not tested or

QA sampled at these temperatures. The LTC6993I is guaranteed to meet

specified performance from –40°C to 85°C. The LTC6993H is guaranteed

to meet specified performance from –40°C to 125°C. The LTC6993MP is

guaranteed to meet specified performance from –55°C to 125°C.

Note 4: Pulse width accuracy is defined as the deviation from the tOUT

equation, assuming RSET is used to program the pulse width.

Note 5: See Operation section, Table 1 and Figure 2 for a full explanation

of how the DIV pin voltage selects the value of DIVCODE.

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15

(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted.

Note 6: The TRIG pin has hysteresis to accommodate slow rising or falling

signals. The threshold voltages are proportional to V+. Typical values can

be estimated at any supply voltage using:

VTRIG(RISING) ≈ 0.55 • V+ + 185mV and

VTRIG(FALLING) ≈ 0.48 • V+ – 155mV

Note 7: To conform to the Logic IC Standard, current out of a pin is

arbitrarily given a negative value.

Note 8: Output rise and fall times are measured between the 10% and the

90% power supply levels with 5pF output load. These specifications are

based on characterization.

Note 9: Settling time is the amount of time required for the output to settle

within ±1% of the final pulse width after a 0.5× or 2× change in ISET

Note 10: Jitter is the ratio of the deviation of the output pulse width to the

mean of the pulse width. This specification is based on characterization

and is not 100% tested.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tPD Trigger Propagation Delay V+ = 5.5V

V+ = 3.3V

V+ = 2.25V

tWIDTH Minimum Recognized TRIG Pulse Width V+ = 3.3V 5 ns

tARM Recovery Time (LTC6993-1/LTC6993-3) –4 ns

tRETRIG Time Between Trigger Signals

(LTC6993-2/LTC6993-4)

NDIV = 1 V+ = 3.3V

NDIV > 1 V+ = 3.3V

trOutput Rise Time (Note 8) V+ = 5.5V

V+ = 3.3V

V+ = 2.25V

1.1

1.7

2.7

tfOutput Fall Time (Note 8) V+ = 5.5V

V+ = 3.3V

V+ = 2.25V

1.0

1.6

2.4

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

TYPICAL PERFORMANCE CHARACTERISTICS

tOUT Drift vs Temperature

(NDIV ≥ 512)

tOUT Drift vs Supply Voltage

(NDIV = 1, Rising Edge)

tOUT Drift vs Temperature

(NDIV ≤ 64)

V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.

tOUT Drift vs Temperature

(NDIV ≤ 64)

tOUT Drift vs Temperature

(NDIV ≤ 64)

TEMPERATURE (°C)

–50

DRIFT (%)

0.5

1.0

1.5

25 75

69931234 G01

–0.5

–25 0 50 100 125

–1.0

–1.5

RSET = 50k

3 PARTS

TEMPERATURE (°C)

–50

DRIFT (%)

0.5

1.0

1.5

25 75

69931234 G02

–0.5

–25 0 50 100 125

–1.0

–1.5

RSET = 200k

3 PARTS

TEMPERATURE (°C)

–50

DRIFT (%)

0.5

1.0

1.5

25 75

69931234 G03

–0.5

–25 0 50 100 125

–1.0

–1.5

RSET = 800k

3 PARTS

TEMPERATURE (°C)

–50

DRIFT (%)

0.5

1.0

1.5

25 75

69931234 G04

–0.5

–25 0 50 100 125

–1.0

–1.5

RSET = 50k

3 PARTS

tOUT Drift vs Temperature

(NDIV ≥ 512)

TEMPERATURE (°C)

–50

DRIFT (%)

0.5

1.0

1.5

25 75

69931234 G05

–0.5

–25 0 50 100 125

–1.0

–1.5

RSET = 200k

3 PARTS

tOUT Drift vs Temperature

(NDIV ≥ 512)

TEMPERATURE (°C)

–50

DRIFT (%)

0.5

1.0

1.5

25 75

69931234 G06

–0.5

–25 0 50 100 125

–1.0

–1.5

RSET = 800k

3 PARTS

SUPPLY (V)

–1.0

DRIFT (%)

–0.8

–0.4

–0.2

1.0

0.4

69931234 G07

–0.6

0.6

0.8

0.2

RSET = 50k

RSET = 200k

RSET = 800k

LTC6993-1/LTC6993-2

DIVCODE = 0

REFERENCED TO V+ = 4V

tOUT Drift vs Supply Voltage

(NDIV = 1, Falling Edge)

SUPPLY (V)

–1.0

DRIFT (%)

–0.8

–0.4

–0.2

1.0

0.4

69931234 G08

–0.6

0.6

0.8

0.2

RSET = 50k

RSET = 200k

RSET = 800k

LTC6993-3/LTC6993-4

DIVCODE = 0

REFERENCED TO V+ = 4V

tOUT Drift vs Supply Voltage

(NDIV > 1)

SUPPLY (V)

–1.0

DRIFT (%)

–0.8

–0.4

–0.2

1.0

0.4

69931234 G09

–0.6

0.6

0.8

0.2

RSET = 50k, NDIV = 8

RSET = 50k TO 800k, NDIV ≥ 512

RSET = 800k, NDIV = 8

REFERENCED TO V+ = 4V

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

TYPICAL PERFORMANCE CHARACTERISTICS

VSET Drift vs ISET

V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.

tOUT Error vs RSET

(NDIV = 1, Rising Edge)

RSET (kΩ)

–5

ERROR (%)

–3

–1

100 200 400 800

69931234 G10

–4

–2

LTC6993-1/LTC6993-2

DIVCODE = 0

3 PARTS

tOUT Error vs RSET

(8 ≤ NDIV ≤ 64)

RSET (kΩ)

–5

ERROR (%)

–3

–1

100 200 400 800

69931234 G11

–4

–2

3 PARTS

tOUT Error vs RSET

(NDIV ≥ 512)

RSET (kΩ)

–5

ERROR (%)

–3

–1

100 200 400 800

69931234 G12

–4

–2

3 PARTS

tOUT Error vs RSET

(NDIV = 1, Falling Edge)

RSET (kΩ)

–5

ERROR (%)

–3

–1

100 200 400 800

69931234 G13

–4

–2

LTC6993-3/LTC6993-4

DIVCODE = 0

3 PARTS

tOUT Error vs DIVCODE

(Rising Edge)

DIVCODE

ERROR (%)

2468

69931234 G14

–1

–3

–2

–4

–5 10 12 14

LTC6993-1/LTC6993-2

RSET = 50k

3 PARTS

tOUT Error vs DIVCODE

(Falling Edge)

DIVCODE

ERROR (%)

2468

69931234 G15

–1

–3

–2

–4

–5 10 12 14

LTC6993-3/LTC6993-4

RSET = 50k

3 PARTS

ISET (µA)

–1.0

0.4

0.2

0.6

0.8

1.0

10 15 20

–0.4

–0.2

–0.6

–0.8

69931234 G16

VSET (mV)

REFERENCED TO ISET = 10µA

VSET Drift vs Supply Voltage

SUPPLY (V)

–1.0

0.4

0.2

0.6

0.8

1.0

456

–0.4

–0.2

–0.6

–0.8

69931234 G17

DRIFT (mV)

REFERENCED TO V+ = 4V

VSET vs Temperature

TEMPERATURE (°C)

–50

0.980

1.000

1.010

1.005

1.015

1.020

0 25 50 100 125

0.995

0.990

0.985

–25 75

69931234 G18

VSET (V)

3 PARTS

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

TYPICAL PERFORMANCE CHARACTERISTICS

Typical VSET Distribution Supply Current vs Supply Voltage Supply Current vs Temperature

Supply Current

vs TRIG Pin Voltage Supply Current vs tOUT (5V)

V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.

VSET (V)

0.98

100

150

200

250

0.996 1.004 1.012 1.02

0.988

69931234 G19

NUMBER OF UNITS

2 LOTS

DFN AND SOT-23

1274 UNITS

Typical ISET Current Limit vs V+

TRIG Threshold Voltage

vs Supply Voltage Peak-to-Peak Jitter vs tOUT

Supply Current vs tOUT (2.5V)

tOUT (ms)

POWER SUPPLY CURRENT (µA)

100

150

200

250

0.001 0.1 1 100

69931234 G23

0.01 10

ACTIVE

IDLE

V+ = 5V

CLOAD = 5pF

RLOAD = ∞

ACTIVE CURRENT MEASURED

WITH TRIGGER PERIOD = 2 • tOUT

(50% DUTY CYCLE)

÷1

÷8

÷64

÷512

tOUT (ms)

POWER SUPPLY CURRENT (µA)

100

150

200

250

0.001 0.1 1 100

69931234 G24

0.01 10

ACTIVE

IDLE

V+ = 2.5V

CLOAD = 5pF

RLOAD = ∞

ACTIVE CURRENT MEASURED

WITH TRIGGER PERIOD = 2 • tOUT

(50% DUTY CYCLE)

÷1 ÷8 ÷64 ÷512

tOUT (ms)

0.001

0.4

JITTER (%P-P)

0.5

0.6

0.7

0.8

0.01 0.1 1 10 100

69931234 G26

0.3

0.2

0.1

0.9

1.0

÷1, 5.5V

÷1, 2.25V

÷8, 2.25V

÷8, 5.5V

÷64

÷512

÷4096

PEAK-TO-PEAK tOUT

VARIATION

MEASURED OVER

30s INTERVALS

SUPPLY VOLTAGE (V)

RST PIN VOLTAGE (V)

69931234 G25

3.5

1.0

2.0

3.0

0.5

1.5

2.5

02 43 5 6

POSITIVE GOING

NEGATIVE GOING

SUPPLY VOLTAGE (V)

ISET (µA)

69931234 G27

1000

400

800

200

600

02 43 5 6

SET PIN SHORTED TO GND

SUPPLY VOLTAGE (V)

POWER SUPPLY CURRENT (µA)

100

150

200

250

300

3 4 5 6

69931234 G20

“ACTIVE” = 50% TIMING DUTY CYCLE

RSET = 50k

÷1, ACTIVE

RSET = 50k

÷1, IDLE

RSET = 100k, ÷8, ACTIVE

RSET = 100k, ÷8, IDLE

RSET = 800k, ÷512

CLOAD = 5pF

RLOAD = ∞

TEMPERATURE (°C)

–50 –25

POWER SUPPLY CURRENT (µA)

100

150

200

250

0 25 50 75 100 125

69931234 G21

“ACTIVE” = 50% TIMING DUTY CYCLE

RSET = 100k, ÷8, ACTIVE

RSET = 50k, ÷1, ACTIVE

RSET = 100k, ÷8, IDLE

RSET = 50k, ÷1, IDLE

RSET = 800k, ÷512

CLOAD = 5pF

RLOAD = ∞

VTRIG/V+ (V/V)

POWER SUPPLY CURRENT (µA)

150

200

250

0.8

69931234 G22

100

00.2 0.4 0.6 1.0

TRIG FALLING

TRIG RISING

3.3V

TRIG RISING

3.3V

TRIG FALLING

CLOAD = 5pF

RLOAD = ∞

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

Trigger Propagation Delay (tPD)

vs Supply Voltage

Rise and Fall Time

vs Supply Voltage

Output Resistance vs Supply

Voltage

SUPPLY VOLTAGE (V)

PROPAGATION DELAY (ns)

3 4 5 6

69931234 G28

CLOAD = 5pF

SUPPLY VOLTAGE (V)

RISE/FALL TIME (ns)

6990 G29

3.0

1.5

2.5

1.0

0.5

2.0

02 43 5 6

CLOAD = 5pF

tRISE

tFALL

SUPPLY VOLTAGE (V)

OUTPUT RESISTANCE (Ω)

69931234 G30

02 43 5 6

OUTPUT SOURCING CURRENT

OUTPUT SINKING CURRENT

TYPICAL PERFORMANCE CHARACTERISTICS

V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

PIN FUNCTIONS

(DCB/S6)

V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This sup-

ply should be kept free from noise and ripple. It should be

bypassed directly to the GND pin with a 0.1µF capacitor.

DIV (Pin 2/Pin 4): Programmable Divider and Polarity

Input. The DIV pin voltage (VDIV) is internally converted

into a 4-bit result (DIVCODE). VDIV may be generated by

a resistor divider between V+ and GND. Use 1% resistors

to ensure an accurate result. The DIV pin and resistors

should be shielded from the OUT pin or any other traces

that have fast edges. Limit the capacitance on the DIV pin

to less than 100pF so that VDIV settles quickly. The MSB of

DIVCODE (POL) determines the polarity of the OUT pins.

When POL = 0 the output produces a positive pulse. When

POL = 1 the output produces a negative pulse.

SET (Pin 3/Pin 3): Pulse Width Setting Input. The voltage

on the SET pin (VSET) is regulated to 1V above GND. The

amount of current sourced from the SET pin (ISET) pro-

grams the master oscillator frequency. The ISET current

range is 1.25µA to 20µA. The output pulse will continue

indefinitely if ISET drops below approximately 500nA,

and will terminate when ISET increases again. A resistor

connected between SET and GND is the most accurate

way to set the pulse width. For best performance, use

a precision metal or thin film resistor of 0.5% or better

tolerance and 50ppm/°C or better temperature coefficient.

For lower accuracy applications an inexpensive 1% thick

film resistor may be used.

Limit the capacitance on the SET pin to less than 10pF

to minimize jitter and ensure stability. Capacitance less

than 100pF maintains the stability of the feedback circuit

regulating the VSET voltage.

TRIG (Pin 4/Pin 1): Trigger Input. Depending on the ver-

sion, a rising or falling edge on TRIG will initiate the output

pulse. LTC6993-1 and LTC6993-2 are rising-edge sensi-

tive. LTC6993-3 and LTC6993-4 are falling-edge sensitive.

The LTC6993-2 and LTC6993-4 are retriggerable, allowing

the pulse width to be extended by additional trigger signals

that occur while the output is active. The LTC6993-1/

LTC6993-3 will ignore additional trigger inputs until the

output pulse has terminated.

GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground

plane for best performance.

OUT (Pin 6/Pin 6): Output. The OUT pin swings from

GND to V+ with an output resistance of approximately

30Ω. When driving an LED or other low impedance load

a series output resistor should be used to limit source/

sink current to 20mA.

69931234 PF

LTC6993

TRIG

GND

SET

OUT

V+

DIV

0.1µF

RSET R2

V+

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

BLOCK DIAGRAM

(S6 package pin numbers shown)

69931234 BD

PROGRAMMABLE DIVIDER

÷1, 8, 64, 512, 4096,

215, 218, 221

MASTER OSCILLATOR

POR

DIGITAL

FILTER

4-BIT A/D

CONVERTER

POL

DIV

V+

OUT

TRIG

HALT OSCILLATOR

IF ISET < 500nA

MCLK

–

ISET

VSET = 1V

–

3 22

GND

SET

RSET

tOUT

TRIGGER/

RETRIGGER

LOGIC

tMASTER = •

1µs

50kΩ

VSET

ISET

QOUTPUT

POLARITY

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

OPERATION

The LTC6993 is built around a master oscillator with a 1µs

minimum period. The oscillator is controlled by the SET

pin current (ISET) and voltage (VSET), with a 1µs/50kΩ

conversion factor that is accurate to ±1.7% under typical

conditions.

tMASTER =1µs

50kΩ

•VSET

ISET

A feedback loop maintains VSET at 1V ±30mV, leaving

ISET as the primary means of controlling the pulse width.

The simplest way to generate ISET is to connect a resistor

(RSET) between SET and GND, such that ISET = VSET/RSET

The master oscillator equation reduces to:

tMASTER =1µs •RSET

50kΩ

From this equation, it is clear that VSET drift will not affect

the pulse width when using a single program resistor

(RSET). Error sources are limited to RSET tolerance and

the inherent pulse width accuracy ∆tOUT of the LTC6993.

RSET may range from 50k to 800k (equivalent to ISET

between 1.25µA and 20µA).

A trigger signal (rising or falling edge on TRIG pin) latches

the output to the active state, beginning the output pulse. At

the same time, the master oscillator is enabled to time the

duration of the output pulse. When the desired pulse width

is reached, the master oscillator resets the output latch.

The LTC6993 also includes a programmable frequency

divider which can further divide the frequency by 1, 8, 64,

512, 4096, 215, 218 or 221. This extends the pulse width

duration by those same factors. The divider ratio NDIV is

set by a resistor divider attached to the DIV pin.

tOUT =NDIV

50kΩ

•VSET

ISET

•1µs

With RSET in place of VSET/ISET the equation reduces to:

tOUT =NDIV •RSET

50kΩ

•1µs

DIVCODE

The DIV pin connects to an internal, V+ referenced 4-bit A/D

converter that determines the DIVCODE value. DIVCODE

programs two settings on the LTC6993:

1. DIVCODE determines the frequency divider setting,

NDIV

2. DIVCODE determines the polarity of OUT pin, via the

POL bit.

VDIV may be generated by a resistor divider between V+

and GND as shown in Figure 1.

Figure 1. Simple Technique for Setting DIVCODE

69931234 F01

LTC6993

V+

DIV

GND

2.25V TO 5.5V

Table 1 offers recommended 1% resistor values that ac-

curately produce the correct voltage division as well as the

corresponding NDIV and POL values for the recommended

resistor pairs. Other values may be used as long as:

1. The VDIV/V+ ratio is accurate to ±1.5% (including resis-

tor tolerances and temperature effects).

2. The driving impedance (R1||R2) does not exceed 500kΩ.

If the voltage is generated by other means (i.e., the output

of a DAC) it must track the V+ supply voltage. The last

column in Table 1 shows the ideal ratio of VDIV to the

supply voltage, which can also be calculated as:

VDIV

+=DIVCODE +0.5

16 ±1.5%

For example, if the supply is 3.3V and the desired DIVCODE

is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV.

Figure 2 illustrates the information in Table 1, showing

that NDIV is symmetric around the DIVCODE midpoint.

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

OPERATION

Table 1. DIVCODE Programming

DIVCODE POL NDIV Recommended tOUT R1 (k) R2 (k) VDIV/V+

0 0 1 1µs to 16µs Open Short ≤ 0.03125 ±0.015

1 0 8 8µs to 128µs 976 102 0.09375 ±0.015

2 0 64 64µs to 1.024ms 976 182 0.15625 ±0.015

3 0 512 512µs to 8.192ms 1000 280 0.21875 ±0.015

4 0 4,096 4.096ms to 65.54ms 1000 392 0.28125 ±0.015

5 0 32,768 32.77ms to 524.3ms 1000 523 0.34375 ±0.015

6 0 262,144 262.1ms to 4.194sec 1000 681 0.40625 ±0.015

7 0 2,097,152 2.097sec to 33.55sec 1000 887 0.46875 ±0.015

8 1 2,097,152 2.097sec to 33.55sec 887 1000 0.53125 ±0.015

9 1 262,144 262.1ms to 4.194sec 681 1000 0.59375 ±0.015

10 1 32,768 32.77ms to 524.3ms 523 1000 0.65625 ±0.015

11 1 4,096 4.096ms to 65.54ms 392 1000 0.71875 ±0.015

12 1 512 512µs to 8.192ms 280 1000 0.78125 ±0.015

13 1 64 64µs to 1.024ms 182 976 0.84375 ±0.015

14 1 8 8µs to 128µs 102 976 0.90625 ±0.015

15 1 1 1µs to 16µs Short Open ≥ 0.96875 ±0.015

0.5•V+

tOUT (ms)

69931234 F02

1000

10000

100

0.001

0.1

0.01

INCREASING VDIV

V+

POL BIT = 0

7 8

POL BIT = 1

Figure 2. Pulse Width Range and POL Bit vs DIVCODE

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

OPERATION

Monostable Multivibrator (One Shot)

The LTC6993 is a monostable multivibrator. A trigger

signal on the TRIG input will force the output to the active

(unstable) state for a programmable duration. This type

of circuit is commonly referred to as a one-shot pulse

generator.

Figures 3 details the basic operation. A rising edge on

the TRIG pin initiates the output pulse. The pulse width

(tOUT) is determined by the NDIV setting and by the resis-

tor (RSET) connected to the SET pin. Subsequent rising

edges on TRIG have no affect until the completion of the

one shot and for a short rearming time (tARM) thereafter.

To ensure proper operation, positive and negative TRIG

pulses should be at least tWIDTH wide.

The LTC6993-2 and LTC6993-4 allow the output pulse to

be “retriggered”. As shown in Figure 4, the output pulse

will stay high until tOUT after the last rising-edge on TRIG.

Successive trigger signals can extend the pulse width in-

definitely. Consecutive trigger signals must be separated

by tRETRIG to be recognized.

Negative Trigger Versions

In addition to the retrigger option, the LTC6993 family also

includes negative input (falling-edge) versions. These four

combinations are detailed in Table 2.

Table 2. Retrigger and Input Polarity Options

DEVICE INPUT POLARITY RETRIGGER

LTC6993-1 Rising-Edge No

LTC6993-2 Rising-Edge Yes

LTC6993-3 Falling-Edge No

LTC6993-4 Falling-Edge Yes

Output Polarity (POL Bit)

Each variety of LTC6993 also offers the ability to invert

the output, producing negative pulses. This option is

programmed, along with NDIV, by the choice of DIVCODE.

(The previous section describes how to program DIVCODE

using the DIV pin).

Figure 3. Non-Retriggering Timing Diagram (LTC6993-1, POL = 0)

Figure 4. Retriggering Timing Diagram (LTC6993-2, POL = 0)

tPD

tWIDTH tRETRIG

TRIG

OUT

tOUT

tPD tPD tPD

tOUT tOUT

69931234 F04

tPD

TRIG

OUT

tPD tARM

tWIDTH

tOUT tOUT tOUT

69931234 F03

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

OPERATION

Changing DIVCODE After Start-Up

Following start-up, the A/D converter will continue

monitoring VDIV for changes. Changes to DIVCODE will

be recognized slowly, as the LTC6993 places a priority on

eliminating any “wandering” in the DIVCODE. The typical

delay depends on the difference between the old and

new DIVCODE settings and is proportional to the master

oscillator period.

tDIVCODE = 16 • (∆DIVCODE + 6) • tMASTER

A change in DIVCODE will not be recognized until it is

stable, and will not pass through intermediate codes. A

digital filter is used to guarantee the DIVCODE has settled

to a new value before making changes to the output. How-

ever, if the output pulse is active during the transition, the

pulse width can take on a value between the two settings.

Start-Up Time

When power is first applied, the power-on reset (POR)

circuit will initiate the start-up time, tSTART

. The OUT pin

is held low during this time. The typical value for tSTART

ranges from 0.5ms to 8ms depending on the master oscil-

lator frequency (independent of NDIV):

tSTART(TYP) = 500 • tMASTER

During start-up, the DIV pin A/D converter must deter-

mine the correct DIVCODE before an output pulse can be

generated. The start-up time may increase if the supply

or DIV pin voltages are not stable. For this reason, it is

recommended to minimize the capacitance on the DIV

pin so it will properly track V+. Less than 100pF will not

extend the start-up time.

The DIVCODE setting is recognized at the end of the startup

up. If POL = 1, the output will transition high. Otherwise

(if POL = 0) OUT simply remains low. At this point, the

LTC6993 is ready to respond to rising/falling edges on

the TRIG input.

Figure 5a. DIVCODE Change from 0 to 2

Figure 5b. DIVCODE Change from 2 to 0

Figure 6. Start-Up Timing Diagram

DIV

500mV/DIV

TRIG

2V/DIV

OUT

2V/DIV

LTC6993-1

V+ = 3.3V

RSET = 200k

200µs/DIV 69931234 F05a

512µs

256µs

4µs

DIV

500mV/DIV

TRIG

2V/DIV

OUT

2V/DIV

LTC6993-1

V+ = 3.3V

RSET = 200k

200µs/DIV 69931234 F05b

512µs

256µs

4µs

TRIG

V+

OUT

tSTART

(TRIG IGNORED)

tOUT

POL = 1

69931234 F06

POL = 0

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

APPLICATIONS INFORMATION

Basic Operation

The simplest and most accurate method to program

the LTC6993 is to use a single resistor, RSET

, between

the SET and GND pins. The design procedure is a four

step process. Alternatively, Linear Technology offers the

easy-to-use TimerBlox Designer tool to quickly design

any LTC6993 based circuit. Download the free TimerBlox

Designer software at www.linear.com/timerblox.

Step 1: Select the POL Bit Setting.

The LTC6993 can generate positive or negative output

pulses, depending on the setting of the POL bit. The POL

bit is the DIVCODE MSB, so any DIVCODE ≥ 8 has POL = 1

and produces active-low pulses.

Step 2: Select LTC6993 Version.

Tw o input-related choices dictate the proper LTC6993 for

a given application:

• Is TRIG a rising or falling-edge input?

• Should retriggering be allowed?

Use Table 2 to select a particular variety of LTC6993.

Step 3: Select the NDIV Frequency Divider Value.

As explained earlier, the voltage on the DIV pin sets the

DIVCODE which determines both the POL bit and the NDIV

value. For a given output pulse width (tOUT), NDIV should

be selected to be within the following range:

tOUT

16µs ≤NDIV ≤tOUT

1µs

(1)

To minimize supply current, choose the lowest NDIV value.

However, in some cases a higher value for NDIV will provide

better accuracy (see Electrical Characteristics).

Table 1 can also be used to select the appropriate NDIV

values for the desired tOUT

With POL already chosen, this completes the selection of

DIVCODE. Use Table 1 to select the proper resistor divider

or VDIV/V+ ratio to apply to the DIV pin.

Step 4: Calculate and Select RSET.

The final step is to calculate the correct value for RSET

using the following equation:

RSET =50k

1µs •tOUT

NDIV

(2)

Select the standard resistor value closest to the calculated

value.

Example: Design a one-shot circuit that satisfies the fol-

lowing requirements:

• tOUT = 100µs

• Negative Output Pulse

• Rising-Edge Trigger Input

• Retriggerable Input

• Minimum power consumption

Step 1: Select the POL Bit Setting.

For inverted (negative) output pulse, choose POL = 1.

Step 2: Select the LTC6993 Version.

A rising-edge retriggerable input requires the LTC6993-2.

Step 3: Select the NDIV Frequency Divider Value.

Choose an NDIV value that meets the requirements of

Equation (1), using tOUT = 100µs:

6.25 ≤ NDIV ≤ 100

Potential settings for NDIV include 8 and 64. NDIV = 8 is

the best choice, as it minimizes supply current by us-

ing a large RSET resistor. POL = 1 and NDIV = 8 requires

DIVCODE = 14. Using Table 1, choose R1 = 102k and

R2 = 976k values to program DIVCODE = 14.

Step 4: Select RSET

Calculate the correct value for RSET using Equation (2):

RSET =50k

1µs •100µs

8=625k

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

Since 625k is not available as a standard 1% resistor,

substitute 619k if a –0.97% shift in tOUT is acceptable.

Otherwise, select a parallel or series pair of resistors such

as 309k and 316k to attain a more precise resistance.

The completed design is shown in Figure 7.

APPLICATIONS INFORMATION

Figure 7. 100µs Negative Pulse Generator

LTC6993-2

TRIG

GND

SET

OUT

V+

DIV

102k

DIVCODE = 14

69931234 F07

2.25V TO 5.5V

976k

0.1µF

RSET

625k

Figure 8. Voltage-Controlled Pulse Width

LTC6993

TRIG

GND

SET

OUT

V+

DIV

0.1µF

69931234 F08

V+

RSET

RMOD

VCTRL

69931234 F09

LTC6993

TRIG

GND

SET

OUT

V+

DIV

0.1µF R1

V+

RMOD

RSET

–

V+

0.1µF

1/2

LTC6078

LTC1659

V+

VCC REF

GND

VOUT

µP

DIN

CLK

CS/LD

NDIV • RMOD

50kΩ

tOUT =

DIN = 0 TO 4095

•

–

1+ RMOD

RSET

DIN

4096

1µs

0.1µF

Voltage-Controlled Pulse Width

With one additional resistor, the LTC6993 output pulse

width can be manipulated by an external voltage. As shown

in Figure 8, voltage VCTRL sources/sinks a current through

RMOD to vary the ISET current, which in turn modulates

the pulse width as described in Equation (3).

tOUT =NDIV •RMOD

50kΩ

•1µs

1+RMOD

RSET

–VCTRL

VSET

(3)

Digital Pulse Width Control

The control voltage can be generated by a DAC (digital-to-

analog converter), resulting in a digitally-controlled pulse

width. Many DACs allow for the use of an external refer-

ence. If such a DAC is used to provide the VCTRL voltage,

the VSET dependency can be eliminated by buffering VSET

and using it as the DAC’s reference voltage, as shown in

Figure 9. The DAC’s output voltage now tracks any VSET

variation and eliminates it as an error source. The SET pin

cannot be tied directly to the reference input of the DAC

because the current drawn by the DAC’s REF input would

affect the pulse width.

Figure 9. Digitally Controlled Pulse Width

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

ISET Extremes (Master Oscillator Frequency Extremes)

When operating with ISET outside of the recommended

1.25µA to 20µA range, the master oscillator operates

outside of the 62.5kHz to 1MHz range in which it is most

accurate.

The oscillator will still function with reduced accuracy for

ISET < 1.25µA. At approximately 500nA, the oscillator will

stop. Under this condition, the output pulse can still be

initiated, but will not terminate until ISET increases and

the master oscillator starts again.

At the other extreme, it is not recommended to operate

the master oscillator beyond 2MHz because the accuracy

of the DIV pin ADC will suffer.

Settling Time

Following a 2× or 0.5× step change in ISET

, the output

pulse width takes approximately six master clock cycles

(6 • tMASTER) to settle to within 1% of the final value. An

example is shown in Figure 10, using the circuit in Figure 8.

Coupling Error

The current sourced by the SET pin is used to bias the

internal master oscillator. The LTC6993 responds to

changes in ISET almost immediately, which provides excel-

lent settling time. However, this fast response also makes

the SET pin sensitive to coupling from digital signals, such

as the TRIG input.

Even an excellent layout will allow some coupling between

TRIG and SET. Additional error is included in the speci-

fied accuracy for NDIV = 1 to account for this. Figure 11

shows that ÷1 supply variation is dependent on coupling

from rising or falling trigger inputs and, to a lesser extent,

output polarity.

A very poor layout can actually degrade performance

further. The PCB layout should avoid routing SET next to

TRIG (or any other fast-edge, wide-swing signal).

APPLICATIONS INFORMATION

Figure 10. Typical Settling Time

VCTRL

2V/DIV

TRIG

5V/DIV

OUT

5V/DIV

PULSE WIDTH

2µs/DIV

LTC6993-1

V+ = 3.3V

DIVCODE = 0

RSET = 200k

RMOD = 464k

tOUT = 3µs AND 6µs

20µs/DIV 69931234 F10

SUPPLY (V)

–1.0

DRIFT (%)

–0.8

–0.4

–0.2

1.0

0.4

69931234 F11

–0.6

0.6

0.8

0.2

RSET = 50k

NDIV = 1

LTC6993-1

POL = 0

LTC6993-1

POL = 1

LTC6993-3

POL = 1

LTC6993-3

POL = 0

Figure 11. tOUT Drift vs Supply Voltage

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

APPLICATIONS INFORMATION

Table 2. Typical Supply Current

CONDITION TYPICAL IS(IDLE) TYPICAL ∆IS(ACTIVE)*

NDIV ≤ 64

V+•NDIV •7pF +4pF

( )

tOUT

+V+

500kΩ+2.2•ISET +50µA

V+•Duty Cycle

tOUT

•NDIV •5pF +18pF +CLOAD

( )

NDIV ≥ 512

V+•NDIV •7pF

tOUT

+V+

500kΩ+1.8 •ISET +50µA

V+•Duty Cycle

tOUT

•CLOAD

*Ignoring resistive loads (assumes RLOAD = ∞)

Power Supply Current

The Electrical Characteristics table specifies the supply

current while the part is idle (waiting to be triggered).

IS(IDLE) varies with the programmed tOUT and the supply

voltage. Once triggered, the instantaneous supply current

increases to IS(ACTIVE) while the timing circuit is active.

IS(ACTIVE) = IS(IDLE) + ∆IS(ACTIVE)

The average increase in supply current ∆IS(ACTIVE) de-

pends on the output duty cycle (or negative duty cycle,

if POL = 1), since that represents the percentage of time

that the circuit is active. IS(IDLE) and ∆IS(ACTIVE) can be

estimated using the equations in Table 2.

Figure 12 shows how the supply current increases from

IS(IDLE) as the input frequency increases. The increase is

smaller at higher NDIV settings.

DUTY CYCLE (%)

IDLE

POWER SUPPLY CURRENT (µA)

150

200

250

69931234 F12

100

020 40 60 100

V+ = 3.3V

DUTY CYCLE = fIN • tOUT

÷1, RSET = 50k

÷8, RSET = 50k

÷1, RSET = 100k

÷1, RSET = 800k

CLOAD = 5pF

RLOAD = ∞

Figure 12. IS(ACTIVE) vs Output Duty Cycle

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

Supply Bypassing and PCB Layout Guidelines

The LTC6993 is an accurate monostable multivibrator when

used in the appropriate manner. The part is simple to use

and by following a few rules, the expected performance is

easily achieved. Adequate supply bypassing and proper

PCB layout are important to ensure this.

Figure 13 shows example PCB layouts for both the SOT-23

and DCB packages using 0603 sized passive components.

The layouts assume a two layer board with a ground plane

layer beneath and around the LTC6993. These layouts are

a guide and need not be followed exactly.

1. Connect the bypass capacitor, C1, directly to the V+ and

GND pins using a low inductance path. The connection

from C1 to the V+ pin is easily done directly on the top

layer. For the DCB package, C1’s connection to GND is

also simply done on the top layer. For the SOT-23, OUT

can be routed through the C1 pads to allow a good C1

GND connection. If the PCB design rules do not allow

that, C1’s GND connection can be accomplished through

multiple vias to the ground plane. Multiple vias for both

the GND pin connection to the ground plane and the

C1 connection to the ground plane are recommended

to minimize the inductance. Capacitor C1 should be a

0.1µF ceramic capacitor.

2. Place all passive components on the top side of the

board. This minimizes trace inductance.

3. Place RSET as close as possible to the SET pin and

make a direct, short connection. The SET pin is a cur-

rent summing node and currents injected into this pin

directly modulate the output pulse width. Having a short

connection minimizes the exposure to signal pickup.

4. Connect RSET directly to the GND pin. Using a long path

or vias to the ground plane will not have a significant

affect on accuracy, but a direct, short connection is

recommended and easy to apply.

5. Use a ground trace to shield the SET pin. This provides

another layer of protection from radiated signals.

6. Place R1 and R2 close to the DIV pin. A direct, short

connection to the DIV pin minimizes the external signal

coupling.

69931234 F13

LTC6993

TRIG

GND

SET

OUT

V+

DIV

0.1µF R1

RSET

V+

DIV

SET

OUT

GND

TRIG

C1R1

V+

RSET

DCB PACKAGE

TRIG

GND

SET

OUT

V+

DIV

V+

RSET

TSOT-23 PACKAGE

Figure 13. Supply Bypassing and PCB Layout

APPLICATIONS INFORMATION

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

TYPICAL APPLICATIONS

Missing Pulse Detector

LTC6993-2

TRIG

GND

SET

OUT

V+

DIV

102k

DIVCODE = 14

(NDIV = 8, POL = 1)

69931234 TA02a

3.3V 0.1µF

976k

RSET

402k

TRIG

2V/DIV

OUT

2V/DIV

50µs/DIV 69931234 TA02b

25kHz INPUT

64µs

Use retriggerable one shot with output inverted. Output remains low as long as retrigger occurs within tOUT = 64µs.

RESET = OPEN

RUN = GND (CLOSED)

20ms

FRAME RATE

GENERATOR

1.5ms

REFERENCE

PULSE

20ms PERIOD

976k

10k

0.01µF

102k

121k

0.01µF

1.5ms PULSE

1.5ms CAL TRIM

69931234 TA03

280k

143k

10k

LTC6991

OUT

V+

DIV

RST

GND

SET

LTC6993-1

OUT

V+

DIV

TRIG

GND

SET

1.5ms Radio Control Servo Reference Pulse Generator

PULSE IN

10µs

OUTPUT PULSE

GENERATOR

100µs

DELAY

GENERATOR

182k

0.01µF

0.1µF

976k

78.7k

10µs PULSE IN

10µs PULSE OUT

100µs DELAY

OUT

LTC6993-1

OUT

V+

DIV

TRIG

GND

SET

976k

102k

61.9k

LTC6993-1

OUT

V+

DIV

TRIG

GND

SET

Pulse Delay Generator

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

TYPICAL APPLICATIONS

TRIGGER

1.5ms

PULSE

GENERATOR

20ms

RETRIGGER

LOCKOUT INTERVAL

0.1µF

PULSE OUT

280k

147k

10k

100k

2N7002 TRIGGER PULSE IN

20ms RETRIGGER LOCKOUT RETRIGGER LOCKOUT TIME

1.5ms PULSE OUT

243k

69931234 TA05

392k

LTC6993-1

OUT

V+

DIV

TRIG

GND

SET

LTC6993-1

TRIG

GND

SET

OUT

V+

DIV

RC Servo Pulse Generator Controlled Retrigger Lockout Time Interval

RETRIGGERABLE

STAIRCASE RESET

PULSE GENERATOR

280k

0.1µF

1µF

20k

100k

R10

10k

R11

1N4148

10k

STAIRCASE

OUT

4.99k

5V 0.1µF

VOUT

147k

2N7002

–

LT1490

PULSES IN

0.1µF

PULSE FREQUENCY-TO-VOLTAGE CONVERTER

–

LT1490

RESET

STAIRCASE RESET

STAIRCASE OUT

PULSES IN

RESET

69931234 TA06

RAMP

RESETS AFTER 1.5ms IF NO PULSES APPLIED

LTC6993-2

OUT

V+

DIV

TRIG

GND

SET

Staircase Generator with Reset

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

VOLTAGE VARIABLE

OUTPUT PULSE WIDTH

RAMP

0.1µF

2N2219A

2N2907

10k

PULSE IN

2N2907

R14

976k

0.1µF

PULSE OUT

STRETCHED

PULSE OUT

R15

102k

R13

113k

R16

140k

1µs TO 10µs INPUT

PULSE WIDTH

182k

0.1µF

976k

69931234 TA07

392k

–

2N2219A

2200pF

10k

RAMP VOLTAGE PROPORTIONAL

TO INPUT PULSE WIDTH

500µs RAMP RESET TIMER

LT1638

10k

4.99k

LT1009

2.5V

LTC6993-1

OUT

V+

DIV

TRIG

GND

SET

LTC6993-3

OUT

V+

DIV

TRIG

GND

SET

5 SECONDS ON

OFFTRIGGER IN

1N4004

24V

0.1µF

2N2219A

100mA

SOLENOID

DANFOSS 042 N024D

TYPE AK024D

887k

69931234 TA08

118k

TRIGGER

LTC6993-1

OUT

V+

DIV

TRIG

GND

SET

15k

RUN

RESET

TIMED (5s) TURN-OFF AFTER

LOSS OF INPUT PULSES

1N4148

12V

COTO 1022 RELAY

9001-12-01

0.1µF

2N2219A

887k

69931234 TA09

118k

ENABLE PULSES

LTC6993-2

OUT

V+

DIV

TRIG

GND

SET

Pulse Stretcher

On-Time Programmable Pulsed Solenoid Driver Safety Time-Out Relay Driver

TYPICAL APPLICATIONS

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

DCB Package

6-Lead Plastic DFN (2mm × 3mm)

(Reference LTC DWG # 05-08-1715 Rev A)

PACKAGE DESCRIPTION

S6 Package

6-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1636)

1.50 – 1.75

(NOTE 4)

2.80 BSC

0.30 – 0.45

6 PLCS (NOTE 3)

DATUM ‘A’

0.09 – 0.20

(NOTE 3) S6 TSOT-23 0302 REV B

2.90 BSC

(NOTE 4)

0.95 BSC

1.90 BSC

0.80 – 0.90

1.00 MAX 0.01 – 0.10

0.20 BSC

0.30 – 0.50 REF

PIN ONE ID

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

3.85 MAX

0.62

MAX

0.95

REF

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

1.4 MIN

2.62 REF

1.22 REF

3.00 ±0.10

(2 SIDES)

2.00 ±0.10

(2 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ± 0.10

(2 SIDES)

0.75 ±0.05

R = 0.115

TYP

R = 0.05

TYP

1.35 ±0.10

(2 SIDES)

PIN 1 BAR

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DCB6) DFN 0405

0.25 ± 0.05

0.50 BSC

PIN 1 NOTCH

R0.20 OR 0.25

× 45° CHAMFER

0.25 ± 0.05

1.35 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05

(2 SIDES)

2.15 ±0.05

0.70 ±0.05

3.55 ±0.05

PACKAGE

OUTLINE

0.50 BSC

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 7/11 Revised Description section 1 to 3

Added text to Basic Operation paragraph in Applications Information section 15

B 1/12 Added MP-grade 1, 2, 3, 5

LTC6993-1/LTC6993-2

LTC6993-3/LTC6993-4

69931234fb

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2010

LT 0112 REV B • PRINTED IN USA

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PART NUMBER DESCRIPTION COMMENTS

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LTC6906/LTC6907 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator Micropower, ISUPPLY = 35µA at 400kHz

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LTC6990 TimerBlox: Voltage-Controlled Silicon Oscillator Fixed-Frequency or Voltage-Controlled Operation

LTC6991 TimerBlox: Resettable Low Frequency Oscillator Clock Periods up to 9.5 hours

LTC6992 TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM) Simple PWM with Wide Frequency Range

LTC6994 TimerBlox: Delay Block/Debouncer Delay Rising Edge, Falling Edge or Both Edges

Consecutive Test Sequencer

LTC6994-1

GND

SET

30s

1000k

0.1µF

887k

63.4k

R10

25k

DELAY

ADJUST

274k

V+

DELAY

2s TO 30s

DELAY

START

TEST

SEQUENCE

TRIG OUT

DIV

LTC6993-1

GND

SET

0.1µF

191k

V+

TEST 1

TRIG OUT

DIV

LTC6993-3

ONE SECOND DURATION SEQUENTIAL TEST PULSES

AFTER AN ADJUSTABLE DELAY TIME

GND

SET

0.1µF

191k

V+

TEST 2

TEST 3

SHARED DIV PIN BIASING FOR EQUAL ONE-SHOT TIMERS

TRIG OUT

DIV

LTC6993-3

GND

SET

191k

1000k

681k

69931234 TA10

V+

TEST 3

TRIG OUT

DIV

0.1µF

TEST 2

TEST 1

START

DELAY