Winbond Clock Generator W83195BR/G-101 For Intel 915/925 Chipsets Date: March/10/2006 Revision: 0.7 W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS W83195BR/G-101 Data Sheet Revision History 1 Pages Dates Version Web Version n.a. 09/30/2004 0.5 n.a. All of the versions before 0.5 are for internal use 6-11, 13 11/24/2004 0.6 n.a. Correction IC version, add register default value and correction some description and default value 1-5, 7-15 3/10/2006 0.7 n.a. Please see blue color text 2 3 Main Contents 4 5 6 7 8 9 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. -I- Publication Release Date: March 2006 Revision 0.7 W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS Tables of Content1. GENERAL DESCRIPTION ......................................................................................................... 1 2. PRODUCT FEATURES .............................................................................................................. 1 3. PIN CONFIGURATION ............................................................................................................... 2 4. BLOCK DIAGRAM ...................................................................................................................... 3 5. PIN DESCRIPTION..................................................................................................................... 4 5.1 Crystal I/O...................................................................................................................................4 5.2 CPU, SRC, PCIF, and PCI Clock Outputs................................................................................4 5.3 Frequency select, and Fixed Frequency Outputs.....................................................................5 5.4 I2C Control Interface..................................................................................................................5 5.5 Power Management Pins ..........................................................................................................6 5.6 Power Pins .................................................................................................................................6 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 7 7. I2C CONTROL AND STATUS REGISTERS............................................................................... 8 7.1 Register 0: Frequency Select Register (Default = 10h)............................................................8 7.2 Register 1: CPU Clock Control (1 = Enable, 0 = Stopped) (Default: E7h)...............................8 7.3 Register 2: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh) ................................9 7.4 Register 3: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh) ................................9 7.5 Register 4: 48MHz, DOT, REF Control (1 = Enable, 0 = Stopped) (Default: FFh)..................9 7.6 Register 5: Watchdog Control (Default: 02h) ..........................................................................10 7.7 Register 6: SRC Control (1 = Enable, 0 = Stopped) (Default: FEh).......................................10 7.8 Register 7: Winbond Chip ID (Default: 22h) (Read Only).......................................................10 7.9 Register 8: M/N Program (Default: D0h).................................................................................11 7.10 Register 9: M/N Program Register (Default: 7Ah) ..................................................................11 7.11 Register 10: Reserved (Default: 3Bh) .....................................................................................12 7.12 Register 11: Spread Spectrum Programming (Default: 0Bh).................................................12 7.13 Register 12: Divisor Control (Default: 72h) .............................................................................12 7.14 Register 13: Step-less Enable Control (Default: 0Fh) ............................................................13 7.15 Register 14: Control (Default: 10h)..........................................................................................14 7.16 Register 15: Reserved (Default: ECh).....................................................................................14 7.17 Register 16: Skew Control (Default: E4h) ...............................................................................14 7.18 Register 17: Reserved (Default: 00h)......................................................................................14 7.19 Register 18: Reserved (Default: 00h)......................................................................................14 7.20 Register 19: Reserved (Default: DAh).....................................................................................15 - II - W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 7.21 Register 20: Watch dog timer (Default: 88h)...........................................................................15 7.22 Register21: Control (Default: 4Bh) ..........................................................................................15 8. 9. ACCESS INTERFACE .............................................................................................................. 16 8.1 Block Write protocol .................................................................................................................16 8.2 Block Read protocol.................................................................................................................16 8.3 Byte Write protocol...................................................................................................................16 8.4 Byte Read protocol ..................................................................................................................16 SPECIFICATIONS .................................................................................................................... 17 9.1 ABSOLUTE MAXIMUM RATINGS .........................................................................................17 9.2 General Operating Characteristics..........................................................................................17 9.3 Skew Group timing clock .........................................................................................................18 9.4 CPU 0.7V Electrical Characteristics ........................................................................................18 9.5 SRC 0.7V Electrical Characteristics ........................................................................................18 9.6 PCIF, PCI Electrical Characteristics........................................................................................19 9.7 48M Electrical Characteristics .................................................................................................19 9.8 REF Electrical Characteristics .................................................................................................20 9.9 DOT 0.7V Electrical Characteristics ........................................................................................20 10. ORDERING INFORMATION..................................................................................................... 21 11. HOW TO READ THE TOP MARKING...................................................................................... 21 12. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 22 - III - Publication Release Date: March 2006 Revision 0.7 W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 1. GENERAL DESCRIPTION The W83195BR/G-101 is a Clock Synthesizer for Intel P4 processors and Intel Grandsdale chipsets. W83195BR/G-101 provides all clocks required for high-speed microprocessor and provides step-less frequency programming, 32 different frequencies of CPU, PCI, SRC clocks setting. Simultaneously W83194BR-101 supports SRC_SATA 100MHz clock output for SATA and DOT 96MHz clock outputs for integrated graphic chipsets. All clocks are externally selectable with smooth transitions. The W83195BR/G-101 programs the registers to enable or disable each clock outputs through I2C serial bus interface and provides -0.5% down type spread spectrum or programmable spread spectrum scale to reduce EMI. The W83195BR/G-101 is driven with a 14.318 MHz reference crystal and runs on a 3.3V supply. 2. PRODUCT FEATURES * * * * * * * * * * * * * * 2 pair 0.7 V current mode Differential clock outputs for CPU 6 pair 0.7V current mode Differential clock outputs for SRC and SRC_SATA. 1 pair 0.7V current mode Differential 96MHz clock outputs for DOT. 6 PCI clock outputs for PCI 3 PCI clock free running outputs for PCI 1 48 MHz clock output for USB. 1 14.318MHz REF clock outputs. Step-less frequency programming I2C 2-Wire serial interface and support byte read/write and block read/write. -0.5% down type spread spectrum in H/W and software select mode. Programmable S.S.T. scale to reduce EMI in M/N mode. Programmable registers to enable/stop each output. Programmable clock outputs to control skew. Watch Dog Timer output * 56 pin SSOP package -1- Publication Release Date: March 2006 Revision 0.7 W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 3. PIN CONFIGURATION VDDPCI GND P C I3 P C I4 P C I5 GND VDDPCI P C IC L K _ F 0 P C IC L K _ F 1 P C IC L K _ F 2 VDD48 48M H Z GND D O TT_96M H Z D O TC _96M H Z *F S _ 1 V tt_ P W R G d # /P D *F S _ 0 SRCT1 SRCC1 VDDSRC SRCT2 SRCC2 SRCT3 SRCC3 SR C T4_SATA SR C C 4_SATA VDDSRC 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 #: Active low *: Internal pull up resistor 120K to VDD & : Internal Pull-down resistor 120K to GND -2- P C I2 P C I1 P C I0 /&F S _ 4 *F S _ 2 R E F 0 /&F S _ 3 GND X IN XOUT VDDREF *S D A T A *S C L K GND C PU C LKT0 C PU C LKC 0 VDDCPU C PU C LKT1 C PU C LKC 1 IR E F GNDA VDDA SRCT7 SRCC7 VDDSRC SRCT6 SRCC6 SRCT5 SRCC5 GND W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 4. BLOCK DIAGRAM 48M H z PLL2 D iv id e r D O TT_96M H z D O TC _96M H z X IN XOUT XTAL OSC REF0 2 PLL1 S p re a d S p e c tr u m 2 VCO CLK SR C T4_SATA SR C C 4_SATA 6 D iv id e r M /N /R a tio ROM 6 3 F S ( 0 :4 ) VTT_PW R G D # L a tc h &POR C o n tr o l L o g ic & C o n fig R e g is te r *S D A T A *S C L K I2 C In te r fa c e 6 IREF PD C P U C L K T 0 :1 C P U C L K C 0 :1 -3- S R C T 1 :3 ,5 :7 S R C C 1 :3 ,5 :7 P C I_ F 0 :2 P C I 0 :5 475 Publication Release Date: March 2006 Revision 0.7 W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 5. PIN DESCRIPTION BUFFER TYPE SYMBOL IN 5.1 Input INtp120k Latched input at power up, internal 120k pull up. INtd120k Latched input at power up, internal 120k pull down. OUT Output I/OD Bi-directional Pin, Open Drain. # Active Low * Internal 120k pull-up & Internal 120k pull-down Crystal I/O PIN 5.2 DESCRIPTION PIN NAME 50 XIN 49 XOUT TYPE DESCRIPTION IN Crystal input with internal loading capacitors (18pF) and feedback resistors. OUT Crystal output at 14.318MHz nominally with internal loading capacitors (18pF). CPU, SRC, PCIF, and PCI Clock Outputs PIN PIN NAME TYPE DESCRIPTION 44,43,41,40 CPUT [0:1] CPUC [0:1] OUT Low skew (< 125ps) 0.7V current mode differential clock outputs for host frequencies of CPU OUT Low skew (<125ps)0.7V current mode differential clock outputs for PCI-E PCI_F[0:2] OUT 3.3V free running PCI clock output. PCI0 OUT 3.3V PCI clock output. 19,20,22,23,2 SRCT[1:3,5:7] 4,25,31,30,33 SRCC[1:3,5:7] ,32,36,35 8,9,10 54 & FS4 55,56,3,4,5 PCI [1:5] INtd120k OUT Latched input for FS4 at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull down. Low skew (< 500ps) 3.3V PCI clock outputs -4- W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 5.3 Frequency select, and Fixed Frequency Outputs PIN 18 16 PIN NAME *FS0 *FS1 DESCRIPTION INtp120k Latched input for FS0 at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull up. INtp120k Latched input for FS1 at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull up. Latched input for FS2 at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull up. 53 *FS2 INtp120k 52 REF0 OUT & 3.3V REF0 14.318MHz clock output. Latched input for FS3 at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull down. FS3 INtd120k 48MHz OUT 48MHz clock output for USB. 14,15 DOTT/C_96MHz OUT 0.7V current mode 96MHz differential clock outputs for DOT 26,27 SRCT/C4_SATA OUT 0.7V current mode 100MHz differential clock outputs for SATA 12 5.4 TYPE I2C Control Interface PIN PIN NAME 47 *SDATA 46 *SCLK TYPE DESCRIPTION I/OD Serial data of I2C 2-wire control interface with internal pull-up resistor. IN Serial clock of I2C 2-wire control interface with internal pull-up resistor. -5- Publication Release Date: March 2006 Revision 0.7 W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 5.5 Power Management Pins PIN NAME PIN 39 IREF VTT_PWRGD# TYPE DESCRIPTION OUT Deciding the reference current for the differential pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current; 475 ohm is the standard value. IN Power good is a low active input signal used to determine when FS [4:0] are valid to be sample. 17 PD 5.6 INtd120k Power Down Function. This is power down pin, high active (PD). Internal 120K pull down Power Pins PIN PIN NAME TYPE DESCRIPTION 37 VDDA PWR 3.3V power supply for PLL core. 1,7 VDDP PWR 3.3V power supply for PCI. 21,28,34 VDDS PWR 3.3V power supply for SRC pair. 11 VDD48 PWR 3.3V power supply for 48MHz. 42 VDDC PWR 3.3V power supply for CPU. 48 VDDR PWR 3.3V power supply for REF. 38 GNDA PWR Ground pin for PLL core. 2,6,13,29,45,51 GND PWR Ground pin -6- W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 0 bit 7 ~ 3). FS4 FS3 FS2 FS1 FS0 CPU (MHZ) DOT (MHZ) SRC (MHZ) PCI (MHZ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 269.33 134.66 202.00 168.33 274.66 137.33 206.00 171.66 279.99 140.00 210.00 174.99 287.99 144.00 216.00 179.99 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 -7- Publication Release Date: March 2006 Revision 0.7 W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 7. I2C CONTROL AND STATUS REGISTERS 7.1 Register 0: Frequency Select Register (Default = 10h) BIT NAME PWD 7 SSEL [4] 0 6 SSEL [3] 0 5 SSEL [2] 0 4 SSEL [1] 1 3 SSEL [0] 0 2 EN_SSEL 1 0 7.2 SPSPEN EN_SAFE_FREQ DESCRIPTION TYPE Frequency selection by software via I2C R/W 0 Enable software frequency table selection SSEL [4:0]. 0 = Select frequency by hardware. 1= Select frequency by software I2C - Bit 7~ 3. R/W 0 Enable Spread Spectrum 0 = Normal 1 = Spread Spectrum enabled R/W 0 Enable reload safe frequency when the watchdog is timeout. 0 = reload the FS [2:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at Register 5 bit 4~0. R/W Register 1: CPU Clock Control (1 = Enable, 0 = Stopped) (Default: E7h) BIT PIN NO PWD DESCRIPTION TYPE 7 36,35 1 SRC7 output control R/W 6 41,40 1 CPUT1 / C1 output control R/W 5 44,43 1 CPUT0 / C0 output control R/W 4 - X Power on latched value of FS4 pin, Default: 0 (Read only). R 3 - X Power on latched value of FS3 pin, Default: 0 (Read only). R 2 - X Power on latched value of FS2 pin, Default: 1 (Read only). R 1 - X Power on latched value of FS1 pin, Default: 1 (Read only). R 0 - X Power on latched value of FS0 pin, Default: 1 (Read only). R -8- W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 7.3 Register 2: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh) BIT PIN NO PWD DESCRIPTION TYPE 7 Reserved 1 Reserved R/W 6 9,10 1 PCI_F1/PCI_F2 output control R/W 5 8 1 PCI_F0 output control R/W 4 Reserved 1 Reserved R/W 3 Reserved 1 Reserved R/W 2 5 1 PCI5 output control R/W 1 Reserved 1 Reserved R/W 0 3,4 1 PCI3, PCI4 output control R/W 7.4 Register 3: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh) BIT PIN NO PWD DESCRIPTION TYPE 7 56 1 PCI2 output control R/W 6 55 1 PCI1 output control R/W 5 54 1 PCI0 output control R/W 4 Reserved 1 Reserved R/W 3 Reserved 1 Reserved R/W 2 Reserved 1 Reserved R/W 1 Reserved 1 Reserved R/W 0 Reserved 1 Reserved R/W 7.5 BIT 7 6 5 4 3 2 1 0 Register 4: 48MHz, DOT, REF Control (1 = Enable, 0 = Stopped) (Default: FFh) PIN NO Reserved 14,15 12 Reserved Reserved 52 Reserved Reserved PWD 1 1 1 1 1 1 1 1 DESCRIPTION Reserved DOT_T/C 96MHZ output control 48MHz output control Reserved Reserved REF0 output control Reserved Reserved -9- TYPE R/W R/W R/W R/W R/W R/W R/W R/W Publication Release Date: March 2006 Revision 0.7 W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 7.6 BIT 7 Register 5: Watchdog Control (Default: 02h) NAME Reserved PWD DESCRIPTION X Reserved R/W R/W 6 EN_WD 0 Program this bit => 1: Enable Watchdog Timer feature. 0: Disable Watchdog Timer feature. Read-back this bit => During timer count down the bit read back to 1. If count to zero, this bit read back to 0. 5 WD_TIMEOUT 0 Read Back only. Timeout Flag. This bit is Read Only. 1: Watchdog has ever started and counts to zero. 0: Watchdog is restarted and counting. 4 SAF_FREQ [4] 0 3 SAF_FREQ [3] 0 2 SAF_FREQ [2] 0 1 SAF_FREQ [1] 1 0 SAF_FREQ [0] 0 7.7 TYPE R R/W These bits will be reloaded in Reg-0 to select frequency table. As the watchdog is timeout and EN_SAFE_FREQ=1. Register 6: SRC Control (1 = Enable, 0 = Stopped) (Default: FEh) BIT NAME PWD DESCRIPTION TYPE 7 Reserved 1 Reserved R/W 6 33,32 1 SRCT/C 6 outputs control R/W 5 31,30 1 SRCT/C 5 outputs control R/W 4 26,27 1 SRCT/C 4_SATA outputs control R/W 3 24,25 1 SRCT/C 3 outputs control R/W 2 22,23 1 SRCT/C 2 outputs control R/W 1 19,20 1 SRCT/C 1 outputs control R/W 0 Reserved 0 Reserved R/W 7.8 BIT Register 7: Winbond Chip ID (Default: 22h) (Read Only) NAME PWD DESCRIPTION TYPE 7 CHPI_ID [7] 0 Winbond Chip ID. W83195BR/G-101 R 6 CHPI_ID [6] 0 Winbond Chip ID. R 5 CHPI_ID [5] 1 Winbond Chip ID. R - 10 - W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS Register 7: Winbond Chip ID (Default: 22h) (Read Only), continued BIT NAME PWD DESCRIPTION TYPE 4 CHPI_ID [4] 0 Winbond Chip ID. R 3 CHPI_ID [3] 0 Winbond Chip ID. R 2 CHPI_ID [2] 0 Winbond Chip ID. R 1 CHPI_ID [1] 1 Winbond Chip ID. R 0 CHPI_ID [0] 0 Winbond Chip ID. R 7.9 BIT Register 8: M/N Program (Default: D0h) NAME PWD DESCRIPTION TYPE 7 N_DIV [8] 1 Programmable N divisor value. Bit7~0 are defined in the Register 9 R/W 6 N_DIV [9] 1 Programmable N divisor value. Bit7~0 are defined in the Register 9 R/W 5 M_DIV [5] 0 R/W 4 M_DIV [4] 1 R/W 3 M_DIV [3] 0 2 M_DIV [2] 0 1 M_DIV [1] 0 R/W 0 M_DIV [0] 0 R/W R/W Programmable M divisor value. R/W 7.10 Register 9: M/N Program Register (Default: 7Ah) BIT NAME PWD DESCRIPTION TYPE 7 N_DIV [7] 0 R/W 6 N_DIV [6] 1 R/W 5 N_DIV [5] 1 R/W 4 N_DIV [4] 1 3 N_DIV [3] 1 2 N_DIV [2] 0 R/W 1 N_DIV [1] 1 R/W 0 N_DIV [0] 0 R/W Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register 8. - 11 - R/W R/W Publication Release Date: March 2006 Revision 0.7 W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 7.11 Register 10: Reserved (Default: 3Bh) BIT NAME PWD DESCRIPTION TYPE Enable SRC spread spectrum feature,1: Enable, 0: Disable R/W 7 SRC_SPSPEN 0 6 N3VAL<6> 0 R/W 5 N3VAL<5> 1 R/W 4 N3VAL<4> 1 3 N3VAL<3> 1 2 N3VAL<2> 0 R/W 1 N3VAL<1> 1 R/W 0 N3VAL<0> 1 R/W Programmable N3 divisor 6~0 for programmable SATA clock. R/W R/W 7.12 Register 11: Spread Spectrum Programming (Default: 0Bh) BIT NAME PWD 7 SP_UP [3] 0 6 SP_UP [2] 0 5 SP_UP [1] 0 4 SP_UP [0] 0 3 SP_DOWN [3] 1 2 SP_DOWN [2] 0 1 0 SP_DOWN [1] SP_DOWN [0] 1 1 DESCRIPTION TYPE R/W Spread Spectrum Up Counter bit 3 ~ bit 0. R/W R/W R/W Spread Spectrum Down Counter bit 3 ~ bit 0 2's complement representation. Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000 R/W R/W R/W R/W 7.13 Register 12: Divisor Control (Default: 72h) BIT NAME PWD 7 Reserved 0 6 KVAL6 X 5 KVAL5 X 4 KVAL4 X 3 KVAL3 X 2 KVAL2 X 1 KVAL1 X 0 KVAL0 X DESCRIPTION Reserved TYPE R/W R/W Reserved R/W R/W Reserved R/W Define the CPU divider ratio Refer to Table-2 R/W R/W R/W - 12 - W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS Table-2 CPU, SRC, PCI divider ratio selection Table CPU Bit1, 0 LSB MSB Bit2/ Bit4/ Bit6 00 01 10 11 0 Div2 Div3 Div4 Div6 1 Div0 Div0 Div0 Div0 7.14 Register 13: Step-less Enable Control (Default: 0Fh) BIT NAME PWD DESCRIPTION TYPE 7 EN_MN_PROG 0 0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. Once the watchdog timer timeout, the bit will be clear. Then the frequency will be decided by hardware default FS<2:0> or desired frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ (Reg0 - bit 0). 6 N<10> 0 Programmable N divisor bit 10. R/W 5 Reserved 0 Reserved R/W 4 Reserved 0 Reserved R/W 3 IVAL<3> 1 2 IVAL<2> 1 1 IVAL<1> 1 0 IVAL<0> 1 R/W R/W Charge pump current selection R/W R/W R/W - 13 - Publication Release Date: March 2006 Revision 0.7 W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 7.15 Register 14: Control (Default: 10h) BIT NAME PWD DESCRIPTION TYPE CPUT / SRCT / DOT_T output state in during POWER DOWN assertion. 1: Driven (2*Iref), 0: Tristate (Floating) 7 DRI_CONT 0 CPUT / SRCT / DOT_T output state in during STOP Mode assertion. R/W 1: Driven (6*Iref), 0: Tristate (Floating) Complementary parts always tri-state (floating) in power down or stop mode. 6 Reserved 0 Reserved 5 SPCNT [5] 0 R/W 4 SPCNT [4] 1 R/W 3 SPCNT [3] 0 2 SPCNT [2] 0 1 SPCNT [1] 0 R/W 0 SPCNT [0] 0 R/W R/W Spread Spectrum Programmable time, the resolution is 280ns. Default period is 11.8us R/W R/W 7.16 Register 15: Reserved (Default: ECh) 7.17 Register 16: Skew Control (Default: E4h) BIT NAME PWD DESCRIPTION TYPE 7 Reserved 1 Reserved R/W 6 Reserved 1 Reserved R/W 5 Reserved 1 4 Reserved 0 3 Reserved 0 2 PSKEW [2] 1 1 PSKEW [1] 0 0 PSKEW [0] 0 R/W Reserved R/W R/W CPU1 to PCI skew control, Skew resolution is 300ps The decision of skew direction is same as PSKEW [2:0] setting 7.18 Register 17: Reserved (Default: 00h) 7.19 Register 18: Reserved (Default: 00h) - 14 - R/W R/W R/W W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 7.20 Register 19: Reserved (Default: DAh) 7.21 Register 20: Watch dog timer (Default: 88h) BIT NAME PWD DESCRIPTION Reserved TYPE 7 Reserved 1 R/W 6 WD_TIME [6] 0 R/W 5 WD_TIME [5] 0 R/W 4 WD_TIME [4] 0 3 WD_TIME [3] 1 2 WD_TIME [2] 0 1 WD_TIME [1] 0 R/W 0 WD_TIME [0] 0 R/W Setting the down count depth (Failure decision). One bit resolution represents 250ms. Default time depth is 8*250ms = 2.0 second. If the watchdog timer is counting, this register will return present down count value. R/W R/W R/W 7.22 Register21: Control (Default: 4Bh) BIT NAME PWD DESCRIPTION TYPE 7 Tri-state 0 Tri-state all output if set 1 R/W 6 Reserved 1 Reserved R/W 5 Reserved 0 Reserved R/W 4 Reserved 0 Reserved R/W 3 Reserved 1 Reserved R/W 2 Reserved 0 Reserved R/W 1 Reserved 1 Reserved R/W 0 Reserved 1 Reserved R/W - 15 - Publication Release Date: March 2006 Revision 0.7 W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 8. ACCESS INTERFACE The W83195BR/G-101 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83195BR/G-101 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2 C address is defined at 0xD2. Block Read and Block Write Protocol 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 8'h00 8.3 Byte Write protocol 8.4 Byte Read protocol PS: In byte Mode program register Byte number is datasheet register Byte number+1 - 16 - W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 9. SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). 9.2 Parameter Rating Absolute 3.3V Core Supply Voltage -0.5V to +4.6V Absolute 3.3V I/O Supple Voltage - 0.5V to + 4.6V Operating 3.3V Core Supply Voltage 3.135V to 3.465V Operating 3.3V I/O Supple Voltage 3.135V to 3.465V Storage Temperature - 65C to + 150C Ambient Temperature - 55C to + 125C Operating Temperature 0C to + 70C Input ESD protection (Human body model) 2000V General Operating Characteristics VDD= 3.3V 5 %, TA = 0C to +70C, Parameter Symbol Input Low Voltage VIL Input High Voltage VIH Output Low Voltage VOL Output High Voltage VOH Min Max Units 0.8 Vdc 2.0 Vdc 0.4 2.4 Vdc Vdc Operating Supply Current Idd Input pin capacitance Cin 5 pF Cout 6 pF Lin 7 nH Output pin capacitance Input pin inductance Test Conditions 350 mA CPU = 100 to 400 MHz PCI = 33.3 Mhz with load 10pF - 17 - Publication Release Date: March 2006 Revision 0.7 W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 9.3 Skew Group timing clock VDD = 3.3V 5 %, TA = 0C to +70C, Cl=10pF Parameter Max Units CPU pair to CPU pair Skew 125 ps Measure Crossing point SRC pair to SRC pair Skew 125 ps Measure Crossing point PCI to PCI Skew 500 ps Measured at 1.5V 9.4 Min Test Conditions CPU 0.7V Electrical Characteristics VDDC= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Min Max Units Rise Time 175 700 ps Measure Single Ended waveform Fall Time 175 700 ps Measure Single Ended waveform 250 550 mV Measure Single Ended waveform Voltage High 660 850 mV Measure Single Ended waveform Voltage Low -150 mV Measure Single Ended waveform 100 ps Measure Differential waveform 55 % Measure Differential waveform Absolute Voltages crossing point Cycle to Cycle jitter Duty Cycle 9.5 45 Test Conditions SRC 0.7V Electrical Characteristics VDDS= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Rise Time Fall Time Min Max Units Test Conditions 175 700 ps Measure Single Ended waveform 175 700 ps Measure Single Ended waveform 250 550 mV Measure Single Ended waveform Voltage High 660 850 mV Measure Single Ended waveform Voltage Low -150 mV Measure Single Ended waveform 125 ps Measure Differential waveform 55 % Measure Differential waveform Absolute Voltages crossing point Cycle to Cycle jitter Duty Cycle 45 - 18 - W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 9.6 PCIF, PCI Electrical Characteristics VDDP= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, Parameter Min Max Units Rise Time 500 2000 ps Vol=0.4V, Voh=2.4V Fall Time 500 2000 ps Voh=2.4V, Vol=0.4V 250 ps Measured at 1.5V 55 % Measured at 1.5V Cycle to Cycle jitter Duty Cycle 45 Pull-Up Current Min -33 Pull-Up Current Max Pull-Down Current Min -33 30 Pull-Down Current Max 9.7 38 Test Conditions mA Vout=1.0V mA Vout=3.135V mA Vout=1.95V mA Vout=0.4V 48M Electrical Characteristics VDD48= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, Parameter Min Max Units Rise Time 500 2000 ps Vol=0.4V, Voh=2.4V Fall Time 500 2000 ps Voh=2.4V, Vol=0.4V 500 ps Measured at 1.5V 55 % Measured at 1.5V Long term jitter Duty Cycle 45 Pull-Up Current Min -33 Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max -33 30 38 Test Conditions mA Vout=1.0V mA Vout=3.135V mA Vout=1.95V mA Vout=0.4V - 19 - Publication Release Date: March 2006 Revision 0.7 W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 9.8 REF Electrical Characteristics VDD= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, Parameter Min Max Units Rise Time 500 2000 ps Vol=0.4V, Voh=2.4V Fall Time 500 2000 ps Voh=2.4V, Vol=0.4V 1000 ps Measured at 1.5V 55 % Measured at 1.5V Cycle to Cycle jitter Duty Cycle 45 Pull-Up Current Min -29 Pull-Up Current Max -23 Pull-Down Current Min 29 Pull-Down Current Max 9.9 27 Test Conditions mA Vout=1.0V mA Vout=3.135V mA Vout=1.95V mA Vout=0.4V DOT 0.7V Electrical Characteristics VDD= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Min Max Units Rise Time 175 700 ps Measure Single Ended waveform Fall Time 175 700 ps Measure Single Ended waveform 250 550 mV Measure Single Ended waveform Voltage High 660 850 mV Measure Single Ended waveform Voltage Low -150 mV Measure Single Ended waveform 250 ps Measure Differential waveform 55 % Measure Differential waveform Absolute Voltages crossing point Cycle to Cycle jitter Duty Cycle 45 - 20 - Test Conditions W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 10. ORDERING INFORMATION PART NUMBER PACKAGE TYPE PRODUCTION FLOW W83195BR-101 56 PIN SSOP Commercial, 0C to +70C W83195BG-101 56 PIN SSOP(Lead free) Commercial, 0C to +70C 11. HOW TO READ THE TOP MARKING W83195BR-101 28051234 420GAASA W83195BG-101 28051234 420GAASA 1st line: Winbond logo and the type number: Normal part: W83195BR-101, Lead free part: W83195BG-101 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 420 G A A SA 420: packages made in '2004, week 20 G: assembly house ID; O means OSE, G means GR A: Internal use code A: IC revision SA: mask version All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. - 21 - Publication Release Date: March 2006 Revision 0.7 W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS 12. PACKAGE DRAWING AND DIMENSIONS 56 PIN SSOP-300mil .035 .045 SYMBOL .045 .055 0.40/0.50 DIA E END VIEW HE TOP VIEW SEE DETAIL "A" c D A2 A A1 e SIDE VIEW b c 0.13 D HE 18.2 18.42 18.54 910.16 10.31 10.41 E 7.42 0.51 7.52 0.64 7.59 0.76 0.61 0.81 1.40 1.02 e L L1 Y SEATING PLANE A A1 A2 b PARTING LINE Y c L L1 DETAIL"A" - 22 - DIMENSION IN MM DIMENSION IN INCH MIN. NOM MAX. MIN. NOM 0.095 0.101 2.41 2.57 2.79 0.41 0.008 0.012 0.20 0.30 0.088 0.090 2.34 2.24 2.29 0.25 0.20 0.34 0.008 0.010 0 0.25 0.08 8 0.005 0.720 0.400 0.292 0.020 0.024 MAX. 0.110 0.016 0.092 0.0135 0.010 0.725 0.730 0.406 0.410 0.296 0.299 0.025 0.030 0.032 0.040 0.055 0.003 0 8 W83195BR/G-101 STEPLESS FOR INTEL 915/925 CHIPSETS Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 23 - Publication Release Date: March 2006 Revision 0.7