DS90LV027AQ www.ti.com SNLS298D - MAY 2008 - REVISED APRIL 2013 DS90LV027AQ Automotive LVDS Dual Differential Driver Check for Samples: DS90LV027AQ FEATURES DESCRIPTION * * * * * * * * The DS90LV027AQ is a dual LVDS driver device optimized for high data rate and low power applications. The device is designed to support data rates in excess of 600Mbps (300MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90LV027AQ is a current mode driver allowing power dissipation to remain low even at high frequency. In addition, the short circuit fault current is also minimized. 1 2 * * AECQ-100 Grade 1 >600 Mbps (300MHz) Switching Rates 0.3 ns Typical Differential Skew 0.7 ns Maximum Differential Skew 3.3V Power Supply Design Low Power Dissipation (46 mW @ 3.3V Static) Flow-Through Design Simplifies PCB Layout Power Off Protection (Outputs in High Impedance) Conforms to TIA/EIA-644 Standard 8-Lead SOIC Package Saves Space The device is in a 8-lead SOIC package. The DS90LV027AQ has a flow-through design for easy PCB layout. The differential driver outputs provides low EMI with its typical low output swing of 360 mV. It is perfect for high speed transfer of clock and data. The DS90LV027AQ can be paired with its companion dual line receiver, the DS90LV028AQ, or with any of TI's LVDS receivers, to provide a high-speed point-topoint LVDS interface. Connection Diagram Figure 1. Dual-In-Line See Package Number D0008A Functional Diagram 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008-2013, Texas Instruments Incorporated DS90LV027AQ SNLS298D - MAY 2008 - REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) -0.3V to +4V Supply Voltage (VCC) -0.3V to (VCC + 0.3V) Input Voltage (DI) -0.3V to +3.9V Output Voltage (DO) Maximum Package Power Dissipation @ +25C D Package 1068 mW Derate D Package 9.71 mW/C above +25C Package Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC) JA 103.0C/W JC 50.0C/W -65C to +150C Storage Temperature Range Lead Temperature Range Soldering (4 sec.) +260C Maximum Junction Temperature +135C ESD Ratings HBM MM (2) (3) (4) (5) 8kV (4) CDM (1) (3) 250V (5) 1250V Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. JESD22-A114C Machine Model, applicable std. JESD22-A115-A Field Induced Charge Device Model, applicable std. JESD22-C101-C Recommended Operating Conditions Min Typ Max Units Supply Voltage (VCC) 3.0 3.3 3.6 V Temperature (TA) -40 25 +125 C Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1) (2) (3) Symbol Parameter Conditions Pin Min Typ Max Units DO+, DO- 250 360 450 mV 1 35 mV 1.4 1.6 V DIFFERENTIAL DRIVER CHARACTERISTICS VOD Output Differential Voltage VOD VOD Magnitude Change VOH Output High Voltage VOL Output Low Voltage VOS Offset Voltage VOS Offset Magnitude Change IOXD Power-off Leakage IOSD Output Short Circuit Current (1) (2) (3) 2 RL = 100 (Figure 2) 0.9 1.1 1.125 1.2 0 VOUT = VCC or GND, VCC = 0V V 1.375 V mV 3 25 1 10 A -5.7 -8 mA Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD. All typicals are given for: VCC = +3.3V and TA = +25C. The DS90LV027AQ is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers outputs. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: DS90LV027AQ DS90LV027AQ www.ti.com SNLS298D - MAY 2008 - REVISED APRIL 2013 Electrical Characteristics (continued) Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)(2)(3) Symbol Parameter Conditions Pin Min Typ Max Units 2.0 VCC V GND 0.8 V 2 10 A 1 10 A 8 14 mA 14 20 mA Min Typ Max Units DIFFERENTIAL DRIVER CHARACTERISTICS VIH Input High Voltage VIL Input Low Voltage DI IIH Input High Current VIN = 3.3V or 2.4V IIL Input Low Current VIN = GND or 0.5V VCL Input Clamp Voltage ICL = -18 mA ICC Power Supply Current No Load -1.5 VIN = VCC or GND VCC RL = 100 -0.6 V Switching Characteristics Over Supply Voltage and Operating Temperature Ranges, unless otherwise specified. (1) (2) (3) (4) Symbol Parameter Conditions DIFFERENTIAL DRIVER CHARACTERISTICS tPHLD Differential Propagation Delay High to Low RL = 100, CL = 15 pF 0.3 0.8 2.0 ns tPLHD Differential Propagation Delay Low to High (Figure 3 and Figure 4) 0.3 1.1 2.0 ns tSKD1 Differential Pulse Skew |tPHLD - tPLHD| 0 0.3 0.7 ns 0 0.4 (5) (6) tSKD2 Channel to Channel Skew 0.8 ns tSKD3 Differential Part to Part Skew (7) 0 1.0 ns tSKD4 Differential Part to Part Skew (8) 0 1.7 ns tTLH Transition Low to High Time 0.2 0.5 1.0 ns tTHL Transition High to Low Time 0.2 0.5 1.0 fMAX Maximum Operating Frequency (1) (2) (3) (4) (5) (6) (7) (8) (9) (9) 350 ns MHz All typicals are given for: VCC = +3.3V and TA = +25C. These parameters are ensured by design. The limits are based on statistical analysis of the device over PVT (process, voltage, temperature) ranges. CL includes probe and fixture capacitance. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50, tr 1 ns, tf 1 ns (10%-90%). tSKD1, |tPHLD - tPLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. tSKD2 is the Differential Channel to Channel Skew of any event on the same device. tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5C of each other within the operating temperature range. tSKD4, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max - Min| differential propagation delay. fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45%/55%, VOD > 250mV, all channels switching. Parameter Measurement Information Figure 2. Differential Driver DC Test Circuit Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: DS90LV027AQ 3 DS90LV027AQ SNLS298D - MAY 2008 - REVISED APRIL 2013 www.ti.com Parameter Measurement Information (continued) Figure 3. Differential Driver Propagation Delay and Transition Time Test Circuit Figure 4. Differential Driver Propagation Delay and Transition Time Waveforms APPLICATION INFORMATION DEVICE PIN DESCRIPTIONS Pin # 4 Name Description 2, 3 DI TTL/CMOS driver input pins 6, 7 DO+ Non-inverting driver output pin 5, 8 DO- Inverting driver output pin 4 GND Ground pin 1 VCC Positive power supply pin, +3.3V 0.3V Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: DS90LV027AQ DS90LV027AQ www.ti.com SNLS298D - MAY 2008 - REVISED APRIL 2013 Typical Performance Curves Output High Voltage vs Power Supply Voltage Output Low Voltage vs Power Supply Voltage Figure 5. Figure 6. Output Short Circuit Current vs Power Supply Voltage Differential Output Voltage vs Power Supply Voltage Figure 7. Figure 8. Differential Output Voltage vs Load Resistor Offset Voltage vs Power Supply Voltage Figure 9. Figure 10. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: DS90LV027AQ 5 DS90LV027AQ SNLS298D - MAY 2008 - REVISED APRIL 2013 www.ti.com Typical Performance Curves (continued) 6 Power Supply Current vs Frequency Power Supply Current vs Power Supply Voltage Figure 11. Figure 12. Power Supply Current vs Ambient Temperature Differential Propagation Delay vs Power Supply Voltage Figure 13. Figure 14. Differential Propagation Delay vs Ambient Temperature Differential Skew vs Power Supply Voltage Figure 15. Figure 16. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: DS90LV027AQ DS90LV027AQ www.ti.com SNLS298D - MAY 2008 - REVISED APRIL 2013 Typical Performance Curves (continued) Differential Skew vs Ambient Temperature Transition Time vs Power Supply Voltage Figure 17. Figure 18. Transition Time vs Ambient Temperature Figure 19. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: DS90LV027AQ 7 DS90LV027AQ SNLS298D - MAY 2008 - REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision C (April 2013) to Revision D * 8 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 7 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: DS90LV027AQ PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) DS90LV027AQMA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 90LV0 27AQM DS90LV027AQMAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 90LV0 27AQM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS90LV027AQMAX/NOP B Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 5.4 2.0 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90LV027AQMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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