SST39WF800B-70-4C-B3KE - MICROCHIP TECHNOLOGY

Microchip Technology Company

Data Sheet

www.microchip.com

Features

• Organized as 512K x16

• Single Voltage Read and Write Operations

– 1.65-1.95V

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption (typical values at 5 MHz)

– Active Current: 5 mA (typical)

– Standby Current: 5 µA (typical)

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Block-Erase Capability

– Uniform 32 KWord blocks

• Fast Read Access Time

–70ns

• Latched Address and Data

• Fast Erase and Word-Program

– Sector-Erase Time: 36 ms (typical)

– Block-Erase Time: 36 ms (typical)

– Chip-Erase Time: 140 ms (typical)

– Word-Program Time: 28 µs (typical)

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 48-ball TFBGA (6mm x 8mm)

– 48-ball WFBGA (4mm x 6mm) Micro-Package

– 48-ball XFLGA (5mm x 6mm) Micro-Package

– 48-ball XFLGA (4mm x 6mm) Micro-Package

• All devices are RoHS compliant

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

The SST39WF800B is a 512K x16 CMOS Multi-Purpose Flash (MPF) manufac-

tured with proprietary, high-performance CMOS SuperFlash technology. The split-

gate cell design and thick-oxide tunneling injector attain better reliability and man-

ufacturability compared to alternate approaches. The SST39WF800B writes (Pro-

gram or Erase) with a 1.65-1.95V power supply. This device conforms to JEDEC

standard pin assignments for x16 memories

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Product Description

The SST39WF800B is a 512K x16 CMOS Multi-Purpose Flash (MPF) manufactured with SST proprie-

tary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tun-

neling injector attain better reliability and manufacturability compared to alternate approaches. The

SST39WF800B writes (Program or Erase) with a 1.65-1.95V power supply. This device conforms to

JEDEC standard pin assignments for x16 memories.

The SST39WF800B features high-performance Word-Programming which provides a typical Word-

Program time of 28 µsec. It uses Toggle Bit or Data# Polling to detect the completion of the Program or

Erase operation. On-chip hardware and software data protection schemes protects against inadvertent

writes. Designed, manufactured, and tested for a wide spectrum of applications, the SST39WF800B is

offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than

100 years.

The SST39WF800B is suited for applications that require convenient and economical updating of pro-

gram, configuration, or data memory. It significantly improves performance and reliability of all system

applications while lowering power consumption. It inherently uses less energy during Erase and Pro-

gram than alternative flash technologies. When programming a flash device, the total energy con-

sumed is a function of the applied voltage, current, and time of application. For any given voltage

range, SuperFlash technology uses less current to program and has a shorter erase time; therefore,

the total energy consumed during any Erase or Program operation is less than alternative flash tech-

nologies. These devices also improve flexibility while lowering the cost for program, data, and configu-

ration storage applications.

SuperFlash technology provides fixed Erase and Program times independent of the number of Erase/

Program cycles that have occurred. Consequently, the system software or hardware does not have to

be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program

times increase with accumulated Erase/Program cycles.

To meet surface mount requirements, the SST39WF800B is offered in 48-ball TFBGA, 48-ball

WFBGA, and a 48-ball XFLGA packages. See Figures 2 and 3 for pin assignments and Table 1 for pin

descriptions.

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Block Diagram

Figure 1: Functional Block Diagram

Y-Decoder

I/O Buffers and Data Latches

1344 B1.0

Address Buffer Latches

X-Decoder

DQ15 -DQ

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Pin Assignments

Figure 2: Pin Assignments for 48-Ball WFBGA and 48-Ball XFLGA

Figure 3: Pin Assignments for 48-ball TFBGA

CE#

VSS

DQ8

OE#

DQ0

A18

DQ10

DQ9

DQ1

A17

DQ2

DQ3

VDD

WE#

DQ12

DQ13

A10

DQ4

DQ5

DQ14

A11

A13

A12

DQ11

DQ6

DQ15

A14

A15

A16

DQ7

VSS

TOP VIEW (balls facing down)

AB C D E F G H J K L

1344 48-wfbga M2Q P02.0

SST39WF800B

1344 48-tfbga P01.0

SST39WF800B

TOP VIEW (balls facing down)

ABCDEFGH

A13

WE#

A12

A17

A14

A10

A18

A15

A11

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Table 1: Pin Description

Symbol Pin Name Functions

AMS1-A0

1. AMS = Most significant address

AMS =A

18 for SST39WF800B

Address Inputs To provide memory addresses. During Sector-Erase AMS-A11 address lines will

select the sector. During Block-Erase AMS-A15 address lines will select the

block.

DQ15-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide power supply voltage: 1.65-1.95V for SST39WF800B

VSS Ground

NC No Connection Unconnected pins.

T1.0 25031

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Device Operation

Commands, which are used to initiate the memory operation functions of the device, are written to the

device using standard microprocessor write sequences. A command is written by asserting WE# low

while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever

occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST39WF800B is controlled by CE# and OE#; both have to be low for the

system to obtain data from the outputs.

CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is

consumed.

OE# is the output control and is used to gate data from the output pins. The data bus is in high imped-

ance state when either CE# or OE# is high. See Figure 5.

Word-Program Operation

The SST39WF800B is programmed on a word-by-word basis. The sector where the word exists must

be fully erased before programming.

Programming is accomplished in three steps:

1. Load the three-byte sequence for Software Data Protection.

2. Load word address and word data. During the Word-Program operation, the addresses

are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is

latched on the rising edge of either CE# or WE#, whichever occurs first.

3. Initiate the internal Program operation after the rising edge of the fourth WE# or CE#,

whichever occurs first. Once initiated, the Program operation will be completed within 40

µs. See Figures 6 and 7 for WE# and CE# controlled Program operation timing diagrams

and Figure 17 for flowcharts.

During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the inter-

nal Program operation, the host is free to perform additional tasks. Any commands issued during the

internal Program operation are ignored.

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Sector-/Block-Erase Operation

The SST39WF800B offers both Sector-Erase and Block-Erase modes which allow the system to erase

the device on a sector-by-sector, or block-by-block, basis.

The sector architecture is based on uniform sector size of 2 KWord. Initiate the Sector-Erase operation

by executing a six-byte command sequence with Sector-Erase command (30H) and sector address

(SA) in the last bus cycle.

The Block-Erase mode is based on uniform block size of 32 KWord. Initiate the Block-Erase operation

by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA)

in the last bus cycle.

The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command

(30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins

after the sixth WE# pulse.

The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See

Figures 10 and 11 for timing waveforms. Any commands issued during the Sector- or Block-Erase

operation are ignored.

Chip-Erase Operation

The SST39WF800B provides a Chip-Erase operation, which allows the user to erase the entire mem-

ory array to the ‘1’ state. This is useful when the entire device must be quickly erased.

Initiate the Chip-Erase operation by executing a six-byte command sequence with Chip-Erase com-

mand (10H) at address 5555H in the last byte sequence.

The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. Dur-

ing the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command

sequence, Figure 9 for the timing diagram, and Figure 20 for the flowchart. Any commands issued dur-

ing the Chip-Erase operation are ignored.

Write Operation Status Detection

To optimize the system write cycle time, the SST39WF800B provides two software means to detect the

completion of a Program or Erase write cycle. The software detection includes two status bits—Data#

Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge

of WE#, which initiates the internal Program or Erase operation.

The completion of the nonvolatile Write is asynchronous with the system; therefore, either a Data#

Polling or Toggle Bit read may occur simultaneously with the completion of the Write cycle. If this

occurs, the system may get an erroneous result, i.e., valid data may appear to conflict with either DQ7

or DQ6. To prevent spurious rejection in the event of an erroneous result, the software routine must

include a loop to read the accessed location an additional two (2) times. If both Reads are valid, then

the device has completed the Write cycle, otherwise the rejection is valid.

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Data# Polling (DQ7)

When the SST39WF800B is in the internal Program operation, any attempt to read DQ7will produce

the complement of the true data. Once the Program operation is complete, DQ7will produce true data.

Although DQ7may have valid data immediately following the completion of an internal Write operation,

the remaining data outputs may still be invalid. Valid data on the entire data bus will appear in subse-

quent successive Read cycles after an interval of 1 µs.During an internal Erase operation, any attempt

to read DQ7will produce a ‘0’. Once the internal Erase operation is complete, DQ7will produce a ‘1’.

The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For

Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#)

pulse. See Figure 8 for Data# Polling timing diagram and Figure 18 for a flowchart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ6will produce

alternating ‘1’s and ‘0’s, i.e., toggling between ‘1’ and ‘0’.

When the Program or Erase operation is complete, the DQ6bit will stop toggling and the device is

ready for the next operation.

The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For

Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse.

See Figure 0-1 for Toggle Bit timing diagram and Figure 18 for a flowchart.

Data Protection

The SST39WF800B provides both hardware and software features to protect nonvolatile data from

inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.0V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-

vents inadvertent writes during power-up or power-down.

Software Data Protection (SDP)

The SST39WF800B provides the JEDEC approved Software Data Protection scheme for all data alter-

ation operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-

byte sequence. The three-byte load sequence is used to initiate the Program operation, providing opti-

mal protection from inadvertent Write operations, e.g., during the system power-up or power-down.

Any Erase operation requires the inclusion of six-byte sequence. This group of devices are shipped

with the Software Data Protection permanently enabled. See Table 4 for the specific software com-

mand codes. During SDP command sequence, invalid commands will abort the device to Read mode

within TRC. The contents of DQ15-DQ8can be VIL or VIH, but no other value, during any SDP command

sequence.

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Common Flash Memory Interface (CFI)

The SST39WF800A contains the CFI information that describes the characteristics of the device, and

supports both the original SST CFI Query mode implementation for compatibility with existing SST

devices, as well as the general CFI Query mode.

To enter the SST CFI Query mode, the system must write the three-byte sequence, same as the Prod-

uct ID Entry command, with 98H (CFI Query command) to address 5555H in the last byte sequence.

To enter the general CFI Query mode, the system must write a one-byte sequence using the Entry

command with 98H to address 55H.

Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in

Tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI

Query mode.

Product Identification

The Product Identification mode identifies the device as the SST39WF800B and manufacturer as SST.

This mode is accessed by software operations. Use Software Product Identification operation to iden-

tify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For

details, see Table 4 for software operation, Figure 12 for the Software ID Entry and Read timing dia-

gram, and Figure 19 for the Software ID Entry command sequence flowchart.

Product Identification Mode Exit/CFI Mode Exit

To return to the standard Read mode, exit the Software Product Identification mode. Issue the Soft-

ware ID Exit command sequence which returns the device to the Read mode.

The Software ID Exit command may also be used to reset the device to the Read mode after any inad-

vertent transient condition that causes the device to behave abnormally, e.g., not read correctly.

The Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See

Table 4 for software command codes, Figure 14 for timing waveform, and Figure 19 for a flowchart.

Table 2: Product Identification Table

Address Data

Manufacturer’s ID 0000H 00BFH

Device ID

SST39WF800B 0001H 273EH

T2.0 25031

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Operations

Table 3: Operation Modes Selection

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1

1. X can be VIL or VIH, but no other value.

Sector or Block address,

XXH for Chip-Erase

Standby VIH X X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Product Identification

Software Mode VIL VIL VIH See Table 4

T3.0 25031

Table 4: Software Command Sequence

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1

1. Address format A14-A0(Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence.

AMS = Most significant address

AMS =A

18 for SST39WF800B

Data2

2. DQ15-DQ8can be VIL or VIH, but no other value, for the Command sequence

Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Word-Program

5555H AAH 2AAAH 55H 5555H A0H WA

3. WA = Program word address

Data

Sector-Erase

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA

4. SAXfor Sector-Erase; uses AMS-A11 address lines

BAXfor Block-Erase; uses AMS-A15 address lines

30H

Block-Erase

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BA

50H

Chip-Erase

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID Entry5,6

5. The device does not remain in Software Product ID mode if powered down.

6. With AMS-A1= 0; SST Manufacturer’s ID = 00BFH, is read with A0=0,

SST39WF800B Device ID = 273EH, is read with A0=1.

5555H AAH 2AAAH 55H 5555H 90H

SST CFI Query

Entry5

5555H AAH 2AAAH 55H 5555H 98H

General CFI Query

Mode

55H 98H

Software ID Exit7/

CFI Exit

7. Both Software ID Exit operations are equivalent

XXH F0H

Software ID Exit7/

CFI Exit

5555H AAH 2AAAH 55H 5555H F0H

T4.0 25031

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Table 5: CFI Query Identification String1for SST39WF800B

Address Data Data

10H 0051H Query Unique ASCII string “QRY”

11H 0052H

12H 0059H

13H 0001H Primary OEM command set

14H 0007H

15H 0000H Address for Primary Extended Table

16H 0000H

17H 0000H Alternate OEM command set (00H = none exists)

18H 0000H

19H 0000H Address for Alternate OEM extended Table (00H = none exits)

1AH 0000H

T5.0 25031

1. Refer to CFI publication 100 for more details.

Table 6: System Interface Information for SST39WF800B

Address Data Data

1BH 0016H VDD Min (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH 0020H VDD Max (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH 0000H VPP min (00H = no VPP pin)

1EH 0000H VPP max (00H = no VPP pin)

1FH 0005H Typical time out for Word-Program 2Nµs (25=32µs)

20H 0000H Typical time out for min size buffer program 2Nµs (00H = not supported)

21H 0005H Typical time out for individual Sector/Block-Erase 2Nms (25=32ms)

22H 0007H Typical time out for Chip-Erase 2Nms (27= 128 ms)

23H 0001H Maximum time out for Word-Program 2Ntimes typical (21x2

5=64µs)

24H 0000H Maximum time out for buffer program 2Ntimes typical

25H 0001H Maximum time out for individual Sector/Block-Erase 2Ntimes typical (21x2

5=64ms)

26H 0001H Maximum time out for Chip-Erase 2Ntimes typical (21x2

7= 256 ms)

T6.0 25031

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Table 7: Device Geometry Information for SST39WF800B

Address Data Data

27H 0014H Device size = 2NByte (14H = 20; 220 = 1 MByte)

28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface

29H 0000H

2AH 0000H Maximum number of byte in multi-byte write = 2N(00H = not supported)

2BH 0000H

2CH 0002H Number of Erase Sector/Block sizes supported by device

2DH 00FFH Sector Information (y+1=Number of sectors; z x 256B = sector size)

2EH 0000H y = 255+1=256sectors (00FFH = 255)

2FH 0010H

30H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)

31H 000FH Block Information (y+1=Number of blocks; z x 256B = block size)

32H 0000H y = 15+1=16blocks(000FH = 15)

33H 0000H

34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

T7.0 25031

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Electrical Specifications

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute

Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these conditions or conditions greater than those defined in the

operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con-

ditions may affect device reliability.)

Temperature Under Bias ............................................. -55°C to +125°C

Storage Temperature ................................................ -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential ............................-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential ..................-2.0V to VDD+2.0V

Voltage on A9Pin to Ground Potential ...................................... -0.5V to 11V

Package Power Dissipation Capability (TA= 25°C) .................................. 1.0W

Surface Mount Solder Reflow Temperature1...........................260°C for 10 seconds

1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.

Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest

information.

Output Short Circuit Current2.................................................. 50mA

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

Table 8: Operating Range

Range Ambient Temp VDD

Commercial 0°C to +70°C 1.65-1.95V

Industrial -40°C to +85°C 1.65-1.95V

T8.1 25031

Table 9: AC Conditions of Test1

1. See Figures 15 and 16

Input Rise/Fall Time Output Load

5ns CL=30pF

T9.1 25031

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Power-Up Specifications

All functionalities and DC specifications are specified for a VDD ramp rate faster than 1V per 100 ms

(0V to 1.8V in less than 180 ms). In addition, a VDD ramp rate slower than 1V per 20 µs is recom-

mended. See Table 10 and Figure 4 for more information.

Figure 4:Power-Up Reset Diagram

Table 10:Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

VDD Min to Read Operation 100 µs

TPU-WRITE1VDD Min to Write Operation 100 µs

T10.0 25031

1344 F37.1

VDD

CE#

TPU-READ

VDD min

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

DC Characteristics

Table 11:DC Operating Characteristics, VDD = 1.65-1.95V1

1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C

(room temperature), and VDD = 1.8V. Not 100% tested.

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT, at f=5 MHz, VDD=VDD Max

Read 15 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

Program and Erase 20 mA CE#=WE#=VIL, OE#=VIH

ISB Standby VDD Current2

2. 40 µA is the maximum ISB for all SST39WF800B commercial grade devices. 40 µA is the maximum ISB for all

39WF800A industrial grade devices. For all SST39WF800B commercial and industrial devices, ISB typical is under 5

µA.

40 µA CE#=VDD,V

DD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD,V

DD=VDD Max

ILO Output Leakage Current 1 µA VOUT=GND to VDD,V

DD=VDD Max

VIL Input Low Voltage 0.2VDD VDD=VDD Min

VIH Input High Voltage 0.8VDD VV

DD=VDD Max

VOL Output Low Voltage 0.1 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.1 V IOH=-100 µA, VDD=VDD Min

T11.0 25031

Table 12:Capacitance (TA= 25°C, f=1 MHz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

I/O Pin Capacitance VI/O =0V 12pF

CIN1Input Capacitance VIN =0V 6pF

T12.0 25031

Table 13:Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1,2

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would

result in a higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T13.0 25031

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

AC Characteristics

Table 14:Read Cycle Timing Parameters

Symbol Parameter

70 ns

UnitsMin Max

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

CE# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1CE# High to High-Z Output 40 ns

TOHZ1OE# High to High-Z Output 40 ns

TOH1Output Hold from Address Change 0 ns

T14.0 25031

Table 15:Program/Erase Cycle Timing Parameters

Symbol Parameter Min Max Units

TBP Word-Program Time 40 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 50 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 50 ns

TWP WE# Pulse Width 50 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 50 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 50 ms

TBE Block-Erase 50 ms

TSCE Chip-Erase 200 ms

T15.0 25031

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Figure 5: Read Cycle Timing Diagram

Figure 6: WE# Controlled Program Cycle Timing Diagram

1344 F03.0

ADDRESS AMS-0

DQ15-0

WE#

OE#

CE#

TCE

TRC TAA

TOE

TOLZ

VIH

HIGH-Z

TCLZ TOH TCHZ

HIGH-Z

DATA VA L I DDATA VA L I D

TOHZ

Note: AMS = Most significant address

AMS =A

18 for SST39WF800B

1344 F04.0

ADDRESS AMS-0

DQ15-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

WE#

TBP

Note: AMS = Most significant address

AMS =A

18 for SST39WF800B

X can be VIL or VIH, but no other value.

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Figure 7: CE# Controlled Program Cycle Timing Diagram

Figure 8: Data# Polling Timing Diagram

1344 F05.0

ADDRESS AMS-0

DQ15-0

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

CE#

TBP

Note: AMS = Most significant address

AMS =A

18 for SST39WF800B

X can be VIL or VIH, but no other value.

1344 F06.0

ADDRESS AMS-0

DQ7DATA DATA # DATA # DATA

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

Note: AMS = Most significant address

AMS =A

18 for SST39WF800B

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

FIGURE 0-1: TOGGLE BIT TIMING DIAGRAM

Figure 9: WE# Controlled Chip-Erase Timing Diagram

1344 F07.0

ADDRESS AMS-0

DQ6

WE#

OE#

CE#

TOE

TOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note: AMS = Most significant address

AMS =A

18 for SST39WF800B

1344 F08.0

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX10XX55XXAA XX80 XXAA

5555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are inter-

changeable as long as minimum timings are met. (See Table 15)

AMS = Most significant address

AMS =A

18 for SST39WF800B

X can be VIL or VIH, but no other value.

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Figure 10:WE# Controlled Block-Erase Timing Diagram

Figure 11:WE# Controlled Sector-Erase Timing Diagram

1344 F09.0

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX50XX55XXAA XX80 XXAA

BAX

OE#

CE#

SIX-BYTE CODE FOR BLOCK-ERASE

TBE

TWP

Note: This device also supports CE# controlled Block-Erase operation The WE# and CE# signals are

interchangeable as long as minimum timings are met. (See Table 15)

AMS = Most significant address

AMS =A

18 for SST39WF800B

X can be VIL or VIH, but no other value.

1344 F10.0

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX30XX55XXAA XX80 XXAA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

Note: This device also supports CE# controlled Sector-Erase operation The WE# and CE# signals

are interchangeable as long as minimum timings are met. (See Table 15)

AMS = Most significant address

AMS =A

18 for SST39WF800B

X can be VIL or VIH, but no other value.

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Figure 12:Software ID Entry and Read

Figure 13:SST CFI Query Entry and Read

1344 F11.0

ADDRESS A14-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2

5555 2AAA 5555 0000 0001

OE#

CE#

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

TWP

TWPH

TAA

00BF

Device ID

XX55XXAA XX90

Note: Device ID = 273FH for SST39WF800B

X can be VIL or VIH, but no other value.

1344 F12.0

ADDRESS A14-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2

5555 2AAA 5555

OE#

CE#

THREE-BYTE SEQUENCE FOR

SST CFI QUERY ENTRY

TWP

TWPH TAA

XX55XXAA XX98

Note: X can be VIL or VIH, but no other value.

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Figure 14:Software ID Exit/CFI Exit

Figure 15:AC Input/Output Reference Waveforms

1344 F13.0

ADDRESS A

14-0

15-0

IDA

WHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

XXAA XX55 XXF0

Note: X can be VIL or VIH, but no other value.

1344 F14.0

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (VDD) for a logic ‘1’ and VILT (VSS) for a logic ‘0’.

Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input

rise and fall times are (10% 90%) <5 ns.

Note: VIT -V

INPUT Test

VOT -V

OUTPUT Test

VIHT -V

INPUT HIGH Test

VILT -V

INPUT LOW Test

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Figure 16:A Test Load Example

1344 F15.0

TO TESTER

TO DUT

VDD

25K

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Figure 17:Word-Program Algorithm

1344 F16.0

Start

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXA0H

Address: 5555H

Load Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

Note: X can be VIL or VIH, but no other value.

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Figure 18:Wait Options

1344 F17.0

Wait TBP,

TSCE, TSE

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7=

true data

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Figure 19:Software ID/CFI Command Flowcharts

1344 F18.0

Load data: XXAAH

Address: 5555H

Software ID Entry

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX90H

Address: 5555H

Wait TIDA

Read Software ID

Load data: XXAAH

Address: 5555H

CFI Query Entry

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX98H

Address: 5555H

Wait TIDA

Read CFI data

Load data: XXAAH

Address: 5555H

Software ID Exit/CFI Exit

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XXF0H

Address: 5555H

Load data: XXF0H

Address: XXH

Return to normal

operation

Wait TIDA

Return to normal

operation

Note: X can be VIL or VIH, but no other value.

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Figure 20:Erase Command Sequence

1344 F19.0

Load data: XXAAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Load data: XXAAH

Address: 5555H

Wait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX30H

Address: SAX

Load data: XXAAH

Address: 5555H

Wait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 5555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX50H

Address: BAX

Load data: XXAAH

Address: 5555H

Wait TBE

Block erased

to FFFFH

Note: X can be VIL or VIH, but no other value.

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Product Ordering Information

Valid combinations for SST39WF800B

SST39WF800B-70-4C-B3KE SST39WF800B-70-4I-B3KE

SST39WF800B-70-4C-C2QE SST39WF800B-70-4I-C2QE

SST39WF800B-70-4C-MAQE SST39WF800B-70-4I-MAQE

SST39WF800B-70-4C-CAQE SST39WF800B-70-4I-CAQE

Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST

sales representative to confirm availability of valid combinations and to determine availability of new combi-

nations.

SST 39 WF 800B - 70 - 4C - B3KE

XX XX XXXX - XX - XX -XXXX

Environmental Attribute

E1= non-Pb

Package Modifier

K = 48 balls

Q = 48 balls (66 possible positions)

Package Type

B3 = TFBGA (0.8mm pitch, 6mm x 8mm)

C2 = XFLGA (0.5mm pitch, 5mm x 6mm)

MA= WFBGA (0.5mm pitch, 4mm x 6mm)

CA = XFLGA (0.5mm pitch, 4mm x 6mm)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

Device Density

800 = 8 Mbit

Voltage

W = 1.65-1.95V

Product Series

39 = Multi-Purpose Flash

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Packaging Diagrams

Figure 21:48-Ball Thin-Profile, Fine-Pitch Ball Grid Array (TFBGA) 6mm x 8mm

SST Package Code: B3K

A1 CORNER

HGFEDCBA

ABCDEFGH

BOTTOM VIEWTOP VIEW

SIDE VIEW

SEATING PLANE

0.35 0.05

1.10 0.10

0.12

6.00 0.10

0.45 0.05

(48X)

A1 CORNER

8.00 0.10

0.80

4.00

0.80

5.60

48-tfbga-B3K-6x8-450mic-5

Note: 1. Complies with JEDEC Publication 95, MO-210, variant AB-1 , although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm ( 0.05 mm)

1mm

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Figure 22: 48-Ball Extremely Thin-Profile, Fine-Pitch Land Grid Array (XFLGA) 5mm x 6mm

SST Package Code: C2Q

LKJHGFEDCBA

ABCDEFGHJKL

0.50

BOTTOM VIEW

5.00 0.08

0.29 0.05

(48X)

A1 INDICATOR4

6.00 0.08

2.50

5.00

A1 CORNER

TOP VIEW

48-xflga-C2Q-5x6-29mic-NR

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-222, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. For low-profile mounting on PCB, SST recommends underfill for best solder joint reliability.

4. Coplanarity: 0.08 mm

5. No bump is present in position A1; a gold-colored indicator is present.

1mm

DETAIL SIDE VIEW

SEATING PLANE

0.04 + 0.025/ - 0.015

0.52 max.

0.473 nom.

0.08

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Figure 23:48-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) 4mm x 6mm

SST Package Code: MAQ

LKJHGFEDCBA

ABCDEFGHJKL

0.50

BOTTOM VIEW

4.00

0.08

0.32 0.05

(48X)

6.00

0.08

2.50

5.00

A1 CORNER

TOP VIEW

48-wfbga-MAQ-4x6-32mic-2.0

Note: 1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger

and bottom side A1 indicator is triangle at corner.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.08 mm

4. Ball opening size is 0.29 mm ( 0.05 mm)

1mm

DETAIL SIDE VIEW

SEATING PLANE

0.20 0.06

0.73 max.

0.636 nom.

0.08

A1 INDICATOR

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Figure 24: 48-Ball Extremely Thin-Profile, Fine-Pitch Land Grid Array (XFLGA) 4mm x 6mm

SST Package Code: CAQ

LKJHGFEDCBA

ABCDEFGHJKL

0.50

BOTTOM VIEW

4.00

0.08

0.29

0.05

(48X)

6.00

0.08

2.50

5.00

A1 CORNER

TOP VIEW

48-xflga-CAQ-4x6-29mic-6.0

Note: 1. Complies with JEDEC Publication 95, MO-207, variant CZB-4, dimensions except the bump height

is much less, and the A1 indicator is different.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.08 mm.

4. For low-profile mounting on PCB, SST recommends underfill for best solder joint reliability.

1mm

DETAIL SIDE VIEW

SEATING PLANE

0.04

+0.025/-0.015

0.52 max.

0.473 nom.

0.08

A1 INDICATOR

8 Mbit (x16) Multi-Purpose Flash

SST39WF800B

Data Sheet

Microchip Technology Company

Table 16:Revision History

Number Description Date

00 •Initial release of data sheet Feb 2007

01 •Added “Power-Up Specifications” on page 14

•Removed the M2QE and MBQE packages

•Added Y1QE package information

Jul 2007

02 •EOL of all Y1QE parts. Replacement parts are MAQE parts listed in

this document.

•Added information for the MAQE and CAQE packages.

Dec 2009

A•Applied new document format

•Released document under letter revision system

•Updated spec number from S71344 to DS25031

Aug 2011

SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Tech-

nology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and

registered trademarks mentioned herein are the property of their respective owners.

Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current

package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.

Memory sizes denote raw storage capacity; actual usable capacity may be less.

SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of

Sale.

For sales office(s) location and information, please see www.microchip.com.

Silicon Storage Technology, Inc.

A Microchip Technology Company

www.microchip.com

ISBN:978-1-61341-405-7