2 A, Low VIN, Low Dropout Linear Regulator ADP1740/ADP1741 FEATURES TYPICAL APPLICATION CIRCUITS VIN = 1.8V 4.7F 4.7F 16 VIN 13 14 15 VIN VOUT VOUT 1 VIN 100k VOUT 12 ADP1740 2 VIN TOP VIEW (Not to Scale) 3 VIN PG 4 EN VOUT 11 VOUT 10 SENSE 9 NC 8 PG GND SS 7 5 6 07081-001 10nF Figure 1. ADP1740 with Fixed Output Voltage, 1.5 V VIN = 1.8V VOUT = 0.5V(1 + R1/R2) 4.7F 4.7F 16 VIN 13 14 15 VIN VOUT VOUT VOUT 12 1 VIN 100k APPLICATIONS Server computers Memory components Telecommunications equipment Network equipment DSP/FPGA/microprocessor supplies Instrumentation equipment/data acquisition systems VOUT = 1.5V 2 VIN 3 VIN PG ADP1741 TOP VIEW (Not to Scale) 4 EN VOUT 11 VOUT 10 R1 ADJ 9 PG GND SS 7 5 6 NC 8 R2 10nF 07081-002 Maximum output current: 2 A Input voltage range: 1.6 V to 3.6 V Low shutdown current: 2 A Low dropout voltage: 160 mV @ 2 A load Initial accuracy: 1% Accuracy over line, load, and temperature: 2% 7 fixed output voltage options with soft start: 0.75 V to 2.5 V (ADP1740) Adjustable output voltage options with soft start: 0.75 V to 3.0 V (ADP1741) High PSRR 65 dB @ 1 kHz 65 dB @ 10 kHz 54 dB @ 100 kHz 23 V rms at 0.75 V output Stable with small 4.7 F ceramic output capacitor Excellent load and line transient response Current-limit and thermal overload protection Power-good indicator Logic-controlled enable Reverse current protection Figure 2. ADP1741 with Adjustable Output Voltage, 0.75 V to 3.0 V GENERAL DESCRIPTION The ADP1740/ADP1741 are low dropout (LDO) CMOS linear regulators that operate from 1.6 V to 3.6 V and provide up to 2 A of output current. These low VIN/VOUT LDOs are ideal for regulation of nanometer FPGA geometries operating from 2.5 V down to 1.8 V I/O rails, and for powering core voltages down to 0.75 V. Using an advanced, proprietary architecture, the ADP1740/ ADP1741 provide high power supply rejection ratio (PSRR) and low noise, and achieve excellent line and load transient response with only a small 4.7 F ceramic output capacitor. The ADP1740 is available in seven fixed output voltage options. The ADP1741 is an adjustable version that allows output voltages ranging from 0.75 V to 3.0 V via an external divider. The ADP1740/ADP1741 allow an external soft start capacitor to be connected to program the startup. A digital power-good output allows power system monitors to check the health of the output voltage. The ADP1740/ADP1741 are available in a 16-lead, 4 mm x 4 mm LFCSP, making them not only very compact solutions, but also providing excellent thermal performance for applications that require up to 2 A of output current in a small, low profile footprint. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008-2010 Analog Devices, Inc. All rights reserved. ADP1740/ADP1741 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 11 Applications ....................................................................................... 1 Soft Start Function ..................................................................... 11 Typical Application Circuits............................................................ 1 Adjustable Output Voltage (ADP1741) ................................... 12 General Description ......................................................................... 1 Enable Feature ............................................................................ 12 Revision History ............................................................................... 2 Power-Good Feature .................................................................. 12 Specifications..................................................................................... 3 Reverse Current Protection Feature ........................................ 13 Input and Output Capacitor, Recommended Specifications .. 4 Applications Information .............................................................. 14 Absolute Maximum Ratings............................................................ 5 Capacitor Selection .................................................................... 14 Thermal Data ................................................................................ 5 Undervoltage Lockout ............................................................... 15 Thermal Resistance ...................................................................... 5 Current-Limit and Thermal Overload Protection ................. 15 ESD Caution .................................................................................. 5 Thermal Considerations............................................................ 15 Pin Configurations and Function Descriptions ........................... 6 PCB Layout Considerations ...................................................... 17 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19 REVISION HISTORY 2/10--Rev. A to Rev. B Changes to Table 4 ............................................................................ 5 Changes to Ordering Guide .......................................................... 19 10/08--Revision 0: Initial Version 4/09--Rev. 0 to Rev. A Changes to Table 3 ............................................................................ 5 Rev. B | Page 2 of 20 ADP1740/ADP1741 SPECIFICATIONS VIN = (VOUT + 0.4 V) or 1.6 V (whichever is greater), IOUT = 100 mA, CIN = COUT = 4.7 F, TA = 25C, unless otherwise noted. Table 1. Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT 1 Symbol VIN IGND SHUTDOWN CURRENT IGND-SD OUTPUT VOLTAGE ACCURACY Fixed Output Voltage Accuracy (ADP1740) VOUT Adjustable Output Voltage Accuracy (ADP1741) 2 LINE REGULATION LOAD REGULATION 3 DROPOUT VOLTAGE 4 VADJ VOUT/VIN VOUT/IOUT VDROPOUT START-UP TIME 5 tSTART-UP CURRENT-LIMIT THRESHOLD 6 THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis ILIMIT PG OUTPUT LOGIC LEVEL PG Output Logic High PG Output Logic Low PG Output Delay from EN Transition, Low to High PG OUTPUT THRESHOLD Output Voltage Falling Output Voltage Rising EN INPUT EN Input Logic High EN Input Logic Low EN Input Leakage Current UNDERVOLTAGE LOCKOUT Input Voltage Rising Input Voltage Falling Hysteresis SOFT START CURRENT ADJ INPUT BIAS CURRENT (ADP1741) Test Conditions/Comments TJ = -40C to +125C IOUT = 500 A IOUT = 100 mA IOUT = 100 mA, TJ = -40C to +125C IOUT = 2 A IOUT = 2 A, TJ = -40C to +125C EN = GND, VIN = 3.6 V EN = GND, VIN = 1.6 V, TJ = -40C to +85C EN = GND, VIN = 3.6 V, TJ = -40C to +85C Min 1.6 IOUT = 100 mA IOUT = 10 mA to 2 A 10 mA < IOUT < 2 A, TJ = -40C to +125C IOUT = 100 mA IOUT = 10 mA to 2 A 10 mA < IOUT < 2 A, TJ = -40C to +125C VIN = (VOUT + 0.4 V) to 3.6 V, TJ = -40C to +125C IOUT = 10 mA to 2 A, TJ = -40C to +125C IOUT = 100 mA, VOUT 1.8 V IOUT = 100 mA, VOUT 1.8 V, TJ = -40C to +125C IOUT = 2 A, VOUT 1.8 V IOUT = 2 A, VOUT 1.8 V, TJ = -40C to +125C CSS = 0 nF, IOUT = 10 mA CSS = 10 nF, IOUT = 10 mA -1 -1.5 -2 0.495 0.492 0.490 -0.3 TJ rising PGHIGH PGLOW 1.6 V VIN 3.6 V, IOH < 1 A 1.6 V VIN 3.6 V, IOL < 2 mA 1.6 V VIN 3.6 V, CSS = 10 nF Max 3.6 90 400 800 1.5 2 0.5 1.8 6 30 100 +1 +1.5 +2 0.505 0.508 0.510 +0.3 0.5 10 18 160 280 2.4 TSSD TSSD-HYS Typ 200 5.2 3 5 1.6 V VIN 3.6 V 1.6 V VIN 3.6 V VIH VIL VI-LEAKAGE UVLO UVLORISE UVLOFALL UVLOHYS ISS ADJI-BIAS 1.6 V VIN 3.6 V 1.6 V VIN 3.6 V EN = VIN or GND 1.0 5.5 V V ms -10 -6.5 % % 0.4 1.2 0.1 0.4 1 1.58 1.25 1.6 V VIN 3.6 V 1.6 V VIN 3.6 V, TJ = -40C to +125C Rev. B | Page 3 of 20 0.6 % % % V V V %/V %/A mV mV mV mV s ms A C C 150 15 PGFALL PGRISE Unit V A A A mA mA A A A 100 0.9 10 1.2 150 V V A V V mV A nA ADP1740/ADP1741 Parameter SENSE INPUT BIAS CURRENT (ADP1740) OUTPUT NOISE Symbol SNSI-BIAS Test Conditions/Comments 1.6 V VIN 3.6 V OUTNOISE POWER SUPPLY REJECTION RATIO PSRR 10 Hz to 100 kHz, VOUT = 0.75 V 10 Hz to 100 kHz, VOUT = 2.5 V VIN = VOUT + 1 V, IOUT = 10 mA 1 kHz, VOUT = 0.75 V 1 kHz, VOUT = 2.5 V 10 kHz, VOUT = 0.75 V 10 kHz, VOUT = 2.5 V 100 kHz, VOUT = 0.75 V 100 kHz, VOUT = 2.5 V Min Typ 10 Max Unit A 23 65 V rms V rms 65 56 65 56 54 51 dB dB dB dB dB dB 1 Minimum output load current is 500 A. Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of the resistors used. 3 Based on an endpoint calculation using 10 mA and 2 A loads. See Figure 6 for typical load regulation performance. 4 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages above 1.6 V. 5 Start-up time is defined as the time between the rising edge of EN to VOUT being at 95% of its nominal value. 6 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V. 2 INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter MINIMUM INPUT AND OUTPUT CAPACITANCE 1 CAPACITOR ESR 1 Symbol CMIN RESR Test Conditions/Comments TA = -40C to +125C TA = -40C to +125C Min 3.3 0.001 Typ Max 0.1 Unit F The minimum input and output capacitance should be greater than 3.3 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during capacitor selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with this LDO. Rev. B | Page 4 of 20 ADP1740/ADP1741 ABSOLUTE MAXIMUM RATINGS board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. The specified values of JA are based on a 4-layer, 4 in x 3 in circuit board. Refer to JEDEC JESD51-7 for detailed information about board construction. For more information, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. Table 3. Parameter VIN to GND VOUT to GND EN to GND SS to GND PG to GND SENSE/ADJ to GND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +3.6 V -65C to +150C -40C to +125C JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL DATA Absolute maximum ratings apply only individually, not in combination. The ADP1740/ADP1741 may be damaged when junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature is within the specified temperature limits. In applications with high power dissipation and poor PCB thermal resistance, the maximum ambient temperature may need to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (JA). TJ is calculated using the following formula: JB is the junction-to-board thermal characterization parameter with units of C/W. JB of the package is based on modeling and calculation using a 4-layer board. The JEDEC JESD51-12 document, Guidelines for Reporting and Using Electronic Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. JB measures the component power flowing through multiple thermal paths rather than through a single path, as in thermal resistance (JB). Therefore, JB thermal paths include convection from the top of the package, as well as radiation from the package, factors that make JB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and the power dissipation (PD) using the following formula: TJ = TB + (PD x JB) Refer to the JEDEC JESD51-8 and JESD51-12 documents for more detailed information about JB. THERMAL RESISTANCE JA and JB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 16-Lead LFCSP with Exposed Pad ESD CAUTION TJ = TA + (PD x JA) The junction-to-ambient thermal resistance (JA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal Rev. B | Page 5 of 20 JA 42 JB 25.5 Unit C/W ADP1740/ADP1741 12 VOUT VIN 1 14 VOUT 13 VOUT 15 VIN PIN 1 INDICATOR 12 VOUT 11 VOUT VIN 3 TOP VIEW (Not to Scale) 10 VOUT VIN 3 10 VOUT 9 SENSE EN 4 TOP VIEW (Not to Scale) 9 ADJ NC 8 PG 5 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD BE CONNECTED TO THE GROUND PLANE ON THE BOARD. 07081-003 PG 5 EN 4 SS 7 ADP1741 GND 6 VIN 2 NC 8 11 VOUT SS 7 ADP1740 GND 6 VIN 2 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD BE CONNECTED TO THE GROUND PLANE ON THE BOARD. Figure 3. ADP1740 Pin Configuration 07081-004 PIN 1 INDICATOR VIN 1 16 VIN 14 VOUT 13 VOUT 15 VIN 16 VIN PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. ADP1741 Pin Configuration Table 5. Pin Function Descriptions Pin No. ADP1740 ADP1741 1, 2, 3, 15, 16 1, 2, 3, 15, 16 Mnemonic VIN 4 4 EN 5 5 PG 6 7 8 9 6 7 8 GND SS NC SENSE 9 10, 11, 12, 13, 14 EP ADJ VOUT 10, 11, 12, 13, 14 EP Exposed pad Description Regulator Input Supply. Bypass VIN to GND with a 4.7 F or greater capacitor. Note that all five VIN pins must be connected to the source supply. Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For automatic startup, connect EN to VIN. Power-Good Output. This open-drain output requires an external pull-up resistor to VIN. If the part is in shutdown mode, current-limit mode, or thermal shutdown, or if it falls below 90% of the nominal output voltage, the PG pin immediately transitions low. Ground. Soft Start Pin. A capacitor connected to this pin determines the soft start time. Not Connected. No internal connection. Sense Input. This pin measures the actual output voltage at the load and feeds it to the error amplifier. Connect the SENSE pin as close to the load as possible to minimize the effect of IR drop between the regulator output and the load. Adjust Pin. A resistor divider from VOUT to ADJ sets the output voltage. Regulated Output Voltage. Bypass VOUT to GND with a 4.7 F or greater capacitor. Note that all five VOUT pins must be connected to the load. The exposed pad on the bottom of the LFCSP enhances thermal performance and is electrically connected to GND inside the package. It is recommended that the exposed pad be connected to the ground plane on the board. Rev. B | Page 6 of 20 ADP1740/ADP1741 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 1.9 V, VOUT = 1.5 V, IOUT = 100 mA, CIN = COUT = 4.7 F, TA = 25C, unless otherwise noted. 1.520 1600 1.505 1.500 1.495 1.490 1.485 1200 LOAD = 800mA 800 LOAD = 400mA 600 LOAD = 100mA 400 LOAD = 10mA 200 -40 -5 25 85 0 07081-005 1.480 125 JUNCTION TEMPERATURE (C) -40 25 85 125 Figure 8. Ground Current vs. Junction Temperature 1600 1.515 1400 1.510 1200 GROUND CURRENT (A) 1.520 1.505 1.500 1.495 1.490 1000 800 600 400 100 1k 10k LOAD CURRENT (mA) 0 10 07081-006 1.480 10 100 1k 10k LOAD CURRENT (mA) Figure 6. Output Voltage vs. Load Current 07081-009 200 1.485 Figure 9. Ground Current vs. Load Current 1.520 1600 LOAD = 10mA LOAD = 100mA LOAD = 400mA LOAD = 800mA LOAD = 1.2A LOAD = 2A 1.510 1400 LOAD = 2A GROUND CURRENT (A) 1.515 1.505 1.500 1.495 1.490 1200 LOAD = 1.2A 1000 800 LOAD = 800mA 600 LOAD = 400mA 400 LOAD = 100mA 1.485 200 2.0 2.2 2.4 2.6 2.8 3.0 3.2 INPUT VOLTAGE (V) 3.4 3.6 Figure 7. Output Voltage vs. Input Voltage 0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 INPUT VOLTAGE (V) Figure 10. Ground Current vs. Input Voltage Rev. B | Page 7 of 20 3.4 3.6 07081-010 LOAD = 10mA 1.480 1.8 07081-007 OUTPUT VOLTAGE (V) -5 JUNCTION TEMPERATURE (C) Figure 5. Output Voltage vs. Junction Temperature OUTPUT VOLTAGE (V) LOAD = 1.2A 1000 07081-008 1.510 1400 GROUND CURRENT (A) 1.515 OUTPUT VOLTAGE (V) LOAD = 2A LOAD = 10mA LOAD = 100mA LOAD = 400mA LOAD = 800mA LOAD = 1.2A LOAD = 2A ADP1740/ADP1741 100 4500 1.9V 2.0V 2.4V 2.6V 3.0V 3.6V 70 3500 60 50 40 30 3000 2500 2000 1500 1000 20 500 0 -40 -15 10 35 60 85 TEMPERATURE (C) 0 2.3 07081-011 10 Figure 11. Shutdown Current vs. Temperature at Various Input Voltages 2.4 2.5 2.6 2.7 2.8 INPUT VOLTAGE (V) Figure 14. Ground Current vs. Input Voltage (in Dropout), VOUT = 2.5 V 0.25 T ILOAD DROPOUT VOLTAGE (V) 0.20 1 0.15 1mA TO 2A LOAD STEP, 2.5A/s, 1A/DIV 1.6V VOUT 0.10 2 2.5V 50mV/DIV 0.05 10 100 1k 10k LOAD CURRENT (mA) CH1 1.0 A BW CH2 50mV 07081-012 1 B W M10s A CH1 380mA T 10.40% 07081-015 VIN = 3.6V VOUT = 1.5V 0 Figure 15. Load Transient Response, CIN = 4.7 F, COUT = 4.7 F Figure 12. Dropout Voltage vs. Load Current, VOUT = 1.6 V, 2.5 V 2.50 T ILOAD 2.40 1 1mA TO 2A LOAD STEP, 2.5A/s, 1A/DIV 2.30 LOAD = 10mA LOAD = 100mA LOAD = 400mA LOAD = 800mA LOAD = 1.2A LOAD = 2A 2.15 2.4 2.5 2.6 INPUT VOLTAGE (V) 2.7 50mV/DIV VIN = 3.6V VOUT = 1.5V 2.8 Figure 13. Output Voltage vs. Input Voltage (in Dropout), VOUT = 2.5 V CH1 1.0 A BW CH2 50mV B W M10s A CH1 880mA T 10.20% Figure 16. Load Transient Response, CIN = 22 F, COUT = 22 F Rev. B | Page 8 of 20 07081-016 2.20 2.10 2.3 VOUT 2 2.25 07081-013 OUTPUT VOLTAGE (V) 2.45 2.35 07081-014 SHUTDOWN CURRENT (A) 80 LOAD = 10mA LOAD = 100mA LOAD = 400mA LOAD = 800mA LOAD = 1.2A LOAD = 2A 4000 GROUND CURRENT (A) 90 ADP1740/ADP1741 0 T VIN LOAD = 2A LOAD = 1.2A LOAD = 800mA LOAD = 400mA LOAD = 100mA LOAD = 10mA -10 -20 3V TO 3.5V INPUT VOLTAGE STEP, 2V/s PSRR (dB) -30 VOUT 2 5mV/DIV -40 -50 -60 -70 -80 VOUT = 1.5V CIN = COUT = 4.7F B W M10s A CH4 T 9.40% 800mV -100 10 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 17. Line Transient Response, Load Current = 2 A Figure 20. Power Supply Rejection Ratio vs. Frequency, VOUT = 0.75 V, VIN = 1.75 V 70 0 LOAD = 2A LOAD = 1.2A LOAD = 800mA LOAD = 400mA LOAD = 100mA LOAD = 10mA -10 2.5V 60 -20 50 -30 40 PSRR (dB) NOISE (V rms) 100 07081-020 CH1 500mV BW CH2 5mV -90 07081-017 1 1.5V 30 -50 -60 -70 0.75V 20 -40 -80 10 0.01 0.1 1 10 LOAD CURRENT (A) 07081-018 0.001 -100 10 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 18. Noise vs. Load Current and Output Voltage Figure 21. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.5 V, VIN = 2.5 V 10 0 LOAD = 2A LOAD = 1.2A LOAD = 800mA LOAD = 400mA LOAD = 100mA LOAD = 10mA -10 -20 -30 PSRR (dB) 1 1.5V 2.5V 0.1 -40 -50 -60 -70 -80 0.75V 0.01 10 100 1k 10k 100k FREQUENCY (Hz) Figure 19. Noise Spectral Density vs. Output Voltage, ILOAD = 10 mA -100 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 22. Power Supply Rejection Ratio vs. Frequency, VOUT = 2.5 V, VIN = 3.5 V Rev. B | Page 9 of 20 10M 07081-022 -90 07081-019 NOISE SPECTRAL DENSITY (V/ Hz) 100 07081-021 -90 0 0.0001 ADP1740/ADP1741 0 -10 PSRR (dB) -20 -30 1.5V/2A 2.5V/10mA 0.75V/2A 2.5V/2A 0.75V/10mA 1.5V/10mA -40 -50 -60 -80 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 07081-048 -70 Figure 23. Power Supply Rejection Ratio vs. Frequency and Output Voltage Rev. B | Page 10 of 20 ADP1740/ADP1741 THEORY OF OPERATION The ADP1740/ADP1741 are low dropout linear regulators that use an advanced, proprietary architecture to provide high power supply rejection ratio (PSRR) and excellent line and load transient response with only a small 4.7 F ceramic output capacitor. Both devices operate from a 1.6 V to 3.6 V input rail and provide up to 2 A of output current. Supply current in shutdown mode is typically 2 A. The ADP1740 is available in seven fixed output voltage options from 0.75 V to 2.5 V. The ADP1740 allows for connection of an external soft start capacitor, which controls the output voltage ramp during startup. The ADP1741 is an adjustable version with an output voltage that can be set to a value from 0.75 V to 3.0 V by an external voltage divider. Both devices are controlled by an enable pin (EN). SOFT START FUNCTION ADP1740 REVERSE POLARITY PROTECTION VIN For applications that require a controlled startup, the ADP1740/ ADP1741 provide a programmable soft start function. The programmable soft start is useful for reducing inrush current upon startup and for providing voltage sequencing. To implement soft start, connect a small ceramic capacitor from SS to GND. Upon startup, a 0.9 A current source charges this capacitor. The ADP1740/ADP1741 start-up output voltage is limited by the voltage at SS, providing a smooth ramp-up to the nominal output voltage. The soft start time is calculated as follows: VOUT UVLO GND SHORT-CIRCUIT AND THERMAL PROTECTION SENSE R1 0.5V REF EN R2 tSS = VREF x (CSS/ISS) PG DETECT 0.9A SS SHUTDOWN 07081-023 PG Figure 24. ADP1740 Internal Block Diagram ADP1741 where: tSS is the soft start period. VREF is the 0.5 V reference voltage. CSS is the soft start capacitance from SS to GND. ISS is the current sourced from SS (0.9 A). When the ADP1740/ADP1741 are disabled (using the EN pin), the soft start capacitor is discharged to GND through an internal 100 resistor. REVERSE POLARITY PROTECTION VIN (1) VOUT 2.50 UVLO 2.25 EN ADJ 0.9A SHUTDOWN 1nF 1.50 1.25 4.7nF 1.00 10nF 0.75 SS Figure 25. ADP1741 Internal Block Diagram 0.50 0.25 0 Internally, the ADP1740/ADP1741 consist of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass transistor, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. Rev. B | Page 11 of 20 0 2 4 6 8 TIME (ms) Figure 26. VOUT Ramp-Up with External Soft Start Capacitor 10 07081-025 PG DETECT VOLTAGE (V) 1.75 0.5V REF PG EN 2.00 SHORT-CIRCUIT AND THERMAL PROTECTION 07081-024 GND ADP1740/ADP1741 T The EN pin active/inactive thresholds are derived from the VIN voltage. Therefore, these thresholds vary with changing input voltage. Figure 29 shows typical EN active/inactive thresholds when the input voltage varies from 1.6 V to 3.6 V. EN 1 1.1 1.0 500mV/DIV CH1 2.0V BW VOUT = 1.5V CIN = COUT = 4.7F CH2 500mV BW M40s T 9.8% A CH1 920mV 07081-026 2 EN THRESHOLD (V) VOUT Figure 27. VOUT Ramp-Up with Internal Soft Start 0.9 EN ACTIVE 0.8 EN INACTIVE 0.7 0.6 The output voltage of the ADP1741 can be set over a 0.75 V to 3.0 V range. The output voltage is set by connecting a resistive voltage divider from VOUT to ADJ. The output voltage is calculated using the following equation: VOUT = 0.5 V x (1 + R1/R2) (2) where: R1 is the resistor from VOUT to ADJ. R2 is the resistor from ADJ to GND. The maximum bias current into ADJ is 150 nA, so to achieve less than 0.5% error due to the bias current, use values less than 60 k for R2. ENABLE FEATURE The ADP1740/ADP1741 use the EN pin to enable and disable the VOUT pins under normal operating conditions. As shown in Figure 28, when a rising voltage on EN crosses the active threshold, VOUT turns on. When a falling voltage on EN crosses the inactive threshold, VOUT turns off. T EN 0.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 INPUT VOLTAGE (V) Figure 29. Typical EN Pin Thresholds vs. Input Voltage POWER-GOOD FEATURE The ADP1740/ADP1741 provide a power-good pin, PG, to indicate the status of the output. This open-drain output requires an external pull-up resistor to VIN. If the part is in shutdown mode, current-limit mode, or thermal shutdown, or if it falls below 90% of the nominal output voltage, the powergood pin (PG) immediately transitions low. During soft start, the rising threshold of the power-good signal is 93.5% of the nominal output voltage. The open-drain output is held low when the ADP1740/ADP1741 have sufficient input voltage to turn on the internal PG transistor. An optional soft start delay can be detected. The PG transistor is terminated via a pull-up resistor to VOUT or VIN. Power-good accuracy is 93.5% of the nominal regulator output voltage when this voltage is rising, with a 90% trip point when this voltage is falling. Regulator input voltage brownouts or glitches trigger power no-good if VOUT falls below 90%. A normal power-down triggers power no-good when VOUT drops below 90%. VOUT 1 2 VOUT = 1.5V CIN = COUT = 4.7F CH1 500mV BW CH2 500mV BW M2.0ms T 29.6% A CH1 1.05V 07081-027 500mV/DIV 07081-028 ADJUSTABLE OUTPUT VOLTAGE (ADP1741) Figure 28. Typical EN Pin Operation As shown in Figure 28, the EN pin has hysteresis built in. This hysteresis prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. Rev. B | Page 12 of 20 ADP1740/ADP1741 REVERSE CURRENT PROTECTION FEATURE T VIN 1V/DIV 1 VOUT 500mV/DIV PG 1V/DIV 2 CH1 1.0V BW CH3 1.0V BW CH2 500mV BW M40.0s A CH3 T 50.40% 900mV 07081-029 VOUT = 1.5V CIN = COUT = 4.7F Figure 30. Typical PG Behavior vs. VOUT, VIN Rising (VOUT = 1.5 V) The ADP1740/ADP1741 have additional circuitry to protect against reverse current flow from VOUT to VIN. For a typical LDO with a PMOS pass device, there is an intrinsic body diode between VIN and VOUT. When VIN is greater than VOUT, this diode is reverse-biased. If VOUT is greater than VIN, the intrinsic diode becomes forward-biased and conducts current from VOUT to VIN, potentially causing destructive power dissipation. The reverse current protection circuitry detects when VOUT is greater than VIN and reverses the direction of the intrinsic diode connection, reverse-biasing the diode. The gate of the PMOS pass device is also connected to VOUT, keeping the device off. Figure 32 shows a plot of the reverse current vs. the VOUT to VIN differential. 4000 3500 T CH2 500mV BW M40.0s A CH3 T 50.40% 2000 1500 1000 0 VOUT = 1.5V CIN = COUT = 4.7F CH1 1.0V BW CH3 1.0V BW 2500 500 PG 1V/DIV 0 900mV 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VOUT - VIN (V) 07081-030 2 VOUT 500mV/DIV 3000 Figure 32. Reverse Current vs. VOUT - VIN Figure 31. Typical PG Behavior vs. VOUT, VIN Falling (VOUT = 1.5 V) Rev. B | Page 13 of 20 3.0 3.3 3.6 07081-132 1 REVERSE CURRENT (A) VIN 1V/DIV ADP1740/ADP1741 APPLICATIONS INFORMATION CAPACITOR SELECTION Input Bypass Capacitor Output Capacitor Connecting a 4.7 F capacitor from the VIN pin to GND reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or high source impedance are encountered. If output capacitance greater than 4.7 F is required, it is recommended that the input capacitor be increased to match it. The ADP1740/ADP1741 are designed for operation with small, space-saving ceramic capacitors, but they function with most commonly used capacitors as long as care is taken with regard to the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 3.3 F capacitance with an ESR of 100 m or less is recommended to ensure the stability of the ADP1740/ADP1741. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP1740/ADP1741 to large changes in load current. Figure 33 and Figure 34 show the transient responses for output capacitance values of 4.7 F and 22 F, respectively. T ILOAD 1A/DIV 1mA TO 2A LOAD STEP, 2.5A/s 1 VOUT 50mV/DIV 2 CH1 1.0A BW CH2 50.0mV B M1.0s W A CH1 380mA T 10.80% 07081-032 VIN = 3.6V, VOUT = 1.5V CIN = COUT = 4.7F Input and Output Capacitor Properties Any good quality ceramic capacitors can be used with the ADP1740/ADP1741, as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. Figure 35 shows the capacitance vs. voltage bias characteristics of an 0805 case, 4.7 F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or with a higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is approximately 15% over the -40C to +85C temperature range and is not a function of package size or voltage rating. 5 MURATA P/N GRM219R61A475KE34 Figure 33. Output Transient Response, COUT = 4.7 F T CAPACITANCE (F) 4 ILOAD 1A/DIV 1mA TO 2A LOAD STEP, 2.5A/s 1 3 2 1 0 2 4 6 8 10 VOLTAGE BIAS (V) Figure 35. Capacitance vs. Voltage Bias Characteristics VIN = 3.6V, VOUT = 1.5V CIN = COUT = 22F CH1 1.0A BW CH2 50.0mV B M1.0s W A CH1 880mA T 11.80% Figure 34. Output Transient Response, COUT = 22 F 07081-133 0 07081-033 2 VOUT 50mV/DIV Use Equation 3 to determine the worst-case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = COUT x (1 - TEMPCO) x (1 - TOL) where: CEFF is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. Rev. B | Page 14 of 20 (3) ADP1740/ADP1741 In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and COUT = 4.46 F at 1.8 V, as shown in Figure 35. Substituting these values in Equation 3 yields CEFF = 4.46 F x (1 - 0.15) x (1 - 0.1) = 3.41 F Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP1740/ADP1741, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. THERMAL CONSIDERATIONS To guarantee reliable operation, the junction temperature of the ADP1740/ADP1741 must not exceed 125C. To ensure that the junction temperature stays below this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistance between the junction and ambient air (JA). The JA value is dependent on the package assembly compounds used and the amount of copper to which the GND pin and the exposed pad (EP) of the package are soldered on the PCB. Table 6 shows typical JA values for the 16-lead LFCSP for various PCB copper sizes. Table 7 shows typical JB values for the 16-lead LFCSP. Table 6. Typical JA Values UNDERVOLTAGE LOCKOUT The ADP1740/ADP1741 have an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage is less than approximately 1.58 V. This ensures that the ADP1740/ADP1741 inputs and the output behave in a predictable manner during power-up. CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION Copper Size (mm2) 01 100 500 1000 6400 1 The ADP1740/ADP1741 are protected against damage due to excessive power dissipation by current-limit and thermal overload protection circuits. The ADP1740/ADP1741 are designed to reach current limit when the output load reaches 3 A (typical). When the output load exceeds 3 A, the output voltage is reduced to maintain a constant current limit. Thermal overload protection is included, which limits the junction temperature to a maximum of 150C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature begins to rise above 150C, the output is turned off, reducing the output current to zero. When the junction temperature drops below 135C (typical), the output is turned on again and output current is restored to its nominal value. Consider the case where a hard short from VOUT to ground occurs. At first, the ADP1740/ADP1741 reach current limit so that only 3 A is conducted into the short. If self-heating of the junction becomes great enough to cause its temperature to rise above 150C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 135C, the output turns on and conducts 3 A into the short, again causing the junction temperature to rise above 150C. This thermal oscillation between 135C and 150C causes a current oscillation between 3 A and 0 A that continues as long as the short remains at the output. Current-limit and thermal overload protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation should be externally limited so that junction temperatures do not exceed 125C. JA (C/W), LFCSP 130 80 69 54 42 Device soldered to minimum size pin traces. Table 7. Typical JB Values Copper Size (mm2) 100 500 1000 JB (C/W) @ 1 W 32.7 31.5 25.5 The junction temperature of the ADP1740/ADP1741 can be calculated from the following equation: TJ = TA + (PD x JA) (4) where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = [(VIN - VOUT) x ILOAD] + (VIN x IGND) (5) where: VIN and VOUT are the input and output voltages, respectively. ILOAD is the load current. IGND is the ground current. Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation can be simplified as follows: TJ = TA + {[(VIN - VOUT) x ILOAD] x JA} (6) As shown in Equation 6, for a given ambient temperature, inputto-output voltage differential, and continuous load current, a minimum copper size requirement exists for the PCB to ensure that the junction temperature does not rise above 125C. Figure 36 through Figure 41 show junction temperature calculations for different ambient temperatures, load currents, VIN to VOUT differentials, and areas of PCB copper. Rev. B | Page 15 of 20 ADP1740/ADP1741 140 JUNCTION TEMPERATURE, TJ (C) 120 LOAD = 2A 100 LOAD = 1A 80 LOAD = 500mA 60 LOAD = 250mA LOAD = 100mA LOAD = 10mA 0 0.5 1.0 1.5 2.0 2.5 3.0 VIN - VOUT (V) LOAD = 1A 60 40 20 JUNCTION TEMPERATURE, TJ (C) LOAD = 250mA 60 LOAD = 100mA 40 LOAD = 10mA 0 0.5 1.0 1.5 2.0 2.5 3.0 VIN - VOUT (V) JUNCTION TEMPERATURE, TJ (C) LOAD = 250mA 80 60 LOAD = 100mA 40 LOAD = 10mA 1.5 2.0 2.5 VIN - VOUT (V) 3.0 07081-036 JUNCTION TEMPERATURE, TJ (C) 100 1.0 3.0 MAX JUNCTION TEMPERATURE LOAD = 500mA LOAD = 1A 100 LOAD = 250mA 80 LOAD = 100mA 60 LOAD = 10mA 40 20 140 LOAD = 1A 0 0.5 2.5 1.0 1.5 2.0 2.5 3.0 3.0 Figure 40. 500 mm2 of PCB Copper, TA = 50C, LFCSP 120 20 2.0 VIN - VOUT (V) MAX JUNCTION TEMPERATURE LOAD = 500mA 1.5 120 Figure 37. 500 mm2 of PCB Copper, TA = 25C, LFCSP 140 LOAD = 2A 0 0.5 07081-035 JUNCTION TEMPERATURE, TJ (C) LOAD = 1A 20 1.0 VIN - VOUT (V) 140 LOAD = 2A LOAD = 500mA LOAD = 10mA Figure 39. 6400 mm2 of PCB Copper, TA = 50C, LFCSP 120 80 LOAD = 100mA 0 0.5 MAX JUNCTION TEMPERATURE 100 LOAD = 250mA 80 Figure 36. 6400 mm2 of PCB Copper, TA = 25C, LFCSP 140 LOAD = 500mA 07081-038 20 LOAD = 2A 100 07081-039 40 MAX JUNCTION TEMPERATURE 120 07081-037 MAX JUNCTION TEMPERATURE 07081-034 JUNCTION TEMPERATURE, TJ (C) 140 Figure 38. 0 mm2 of PCB Copper, TA = 25C, LFCSP LOAD = 1A MAX JUNCTION TEMPERATURE 120 LOAD = 500mA 100 LOAD = 250mA 80 LOAD = 100mA 60 LOAD = 10mA 40 20 0 0.5 1.0 1.5 2.0 2.5 VIN - VOUT (V) Figure 41. 0 mm2 of PCB Copper, TA = 50C, LFCSP Rev. B | Page 16 of 20 ADP1740/ADP1741 140 (7) Figure 42 through Figure 45 show junction temperature calculations for different board temperatures, load currents, VIN to VOUT differentials, and areas of PCB copper. MAX JUNCTION TEMPERATURE 100 LOAD = 2A LOAD = 2A LOAD = 500mA 60 LOAD = 250mA 40 20 0.75 140 60 LOAD = 250mA 40 20 LOAD = 10mA 1.75 2.25 2.75 07081-040 1.25 VIN - VOUT (V) Figure 42. 500 mm2 of PCB Copper, TB = 25C, LFCSP MAX JUNCTION TEMPERATURE LOAD = 2A LOAD = 500mA 80 LOAD = 250mA 60 40 LOAD = 100mA 20 0.75 1.25 1.75 2.25 Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP1740/ ADP1741. However, as shown in Table 6, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. LOAD = 10mA LOAD = 100mA 2.25 VIN - VOUT (V) Figure 43. 500 mm2 of PCB Copper, TB = 50C, LFCSP 2.75 07081-041 20 1.75 2.75 PCB LAYOUT CONSIDERATIONS LOAD = 250mA 60 1.25 LOAD = 10mA Figure 45. 1000 mm2 of PCB Copper, TB = 50C, LFCSP LOAD = 500mA 80 40 LOAD = 1A LOAD = 2A 100 VIN - VOUT (V) LOAD = 1A 0.75 120 0 0.25 120 0 0.25 2.75 MAX JUNCTION TEMPERATURE LOAD = 500mA 100 2.25 07081-043 80 140 1.75 Figure 44. 1000 mm2 of PCB Copper, TB = 25C, LFCSP LOAD = 1A 0.75 1.25 LOAD = 10mA VIN - VOUT (V) 100 0 0.25 LOAD = 1A 80 0 0.25 120 LOAD = 100mA JUNCTION TEMPERATURE, TJ (C) 120 LOAD = 100mA JUNCTION TEMPERATURE, TJ (C) JUNCTION TEMPERATURE, TJ (C) 140 MAX JUNCTION TEMPERATURE 07081-042 TJ = TB + (PD x JB) JUNCTION TEMPERATURE, TJ (C) In cases where the board temperature is known, the thermal characterization parameter, JB, can be used to estimate the junction temperature rise. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and the power dissipation (PD) using the following formula: Here are a few general tips when designing PCBs: * * * * Place the input capacitor as close as possible to the VIN and GND pins. Place the output capacitor as close as possible to the VOUT and GND pins. Place the soft start capacitor close to the SS pin. Connect the load as close as possible to the VOUT and SENSE pins (ADP1740) or to the VOUT and ADJ pins (ADP1741). Use of 0603 or 0805 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. Rev. B | Page 17 of 20 Figure 46. Evaluation Board 07081-046 07081-044 ADP1740/ADP1741 07081-045 Figure 48. Typical Board Layout, Bottom Side Figure 47. Typical Board Layout, Top Side Rev. B | Page 18 of 20 ADP1740/ADP1741 OUTLINE DIMENSIONS 4.00 BSC SQ 12 MAX 1.00 0.85 0.80 0.65 BSC TOP VIEW 3.75 BSC SQ 0.75 0.60 0.50 0.80 MAX 0.65 TYP 0.35 0.30 0.25 16 13 12 9 PIN 1 INDICATOR 1 2.25 2.10 SQ 1.95 8 5 4 0.25 MIN 1.95 BSC 0.05 MAX 0.02 NOM SEATING PLANE (BOTTOM VIEW) 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 072808-A PIN 1 INDICATOR 0.60 MAX 0.60 MAX COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP1740ACPZ-0.75-R7 ADP1740ACPZ-1.0-R7 ADP1740ACPZ-1.1-R7 ADP1740ACPZ-1.2-R7 ADP1740ACPZ-1.5-R7 ADP1740ACPZ-1.8-R7 ADP1740ACPZ-2.5-R7 ADP1741ACPZ-R7 ADP1741ACPZ ADP1740-1.5-EVALZ ADP1741-EVALZ ADP1740-BL1-EVZ ADP1741-BL1-EVZ 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Output Voltage (V) 0.75 1.0 1.1 1.2 1.5 1.8 2.5 Adjustable, 0.75 V to 3.0 V Adjustable, 0.75 V to 3.0 V 1.5 Adjustable Z = RoHS Compliant Part. Rev. B | Page 19 of 20 Package Description 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ Evaluation Board Evaluation Board Blank Evaluation Board Blank Evaluation Board Package Option CP-16-4 CP-16-4 CP-16-4 CP-16-4 CP-16-4 CP-16-4 CP-16-4 CP-16-4 CP-16-4 ADP1740/ADP1741 NOTES (c)2008-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07081-0-2/10(B) Rev. B | Page 20 of 20