Ultralow Distortion, Wide Bandwidth
Voltage Feedback Op Amps
Data Sheet AD9631/AD9632
Rev. D Document Feedback
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FEATURES
Wide bandwidth
AD9631, G = +1
AD9632, G = +2
Small signal
AD9631, 320 MHz
AD9632, 250 MHz
Large signal (4 V p-p)
AD9631, 175 MHz
AD9632, 180 MHz
Ultralow distortion (SFDR), low noise
−113 dBc typical @ 1 MHz
−95 dBc typical @ 5 MHz
−72 dBc typical @ 20 MHz
46 dBm third-order intercept @ 25 MHz
7.0 nV/√Hz spectral noise density
High speed
Slew rate: 1300 V/μs
Settling time to 0.01%, 2 V step: 16 ns
±3 V to ±5 V supply operation
17 mA supply current
APPLICATIONS
ADC input driver
Differential amplifiers
IF/RF amplifiers
Pulse amplifiers
Professional video
DAC current to voltage
Baseband and video communications
Pin diode receivers
Active filters/integrators/log amps
GENERAL DESCRIPTION
The AD9631/AD9632 are very high speed and wide bandwidth
amplifiers. The AD9631 is unity gain stable. The AD9632 is
stable at gains of 2 or greater. Using a voltage feedback
architecture, the exceptional settling time, bandwidth, and low
distortion of the AD9631/AD9632 meet the requirements of
many applications that previously depended on current feed-
back amplifiers. Its classical op amp structure works much more
predictably in many designs.
PIN CONFIGURATION
Figure 1. 8-Lead PDIP (N) and SOIC (R) Packages
A proprietary design architecture has produced an amplifier
that combines many of the best characteristics of both current
feedback and voltage feedback amplifiers. The AD9631/AD9632
exhibit exceptionally fast and accurate pulse response (16 ns to
0.01%) as well as extremely wide small signal and large signal
bandwidth and ultralow distortion. The AD9631 achieves
−72 dBc at 20 MHz, 320 MHz small signal bandwidth, and
175 MHz large signal bandwidths.
These characteristics position the AD9631/AD9632 ideally for
driving flash as well as high resolution ADCs. Additionally, the
balanced high impedance inputs of the voltage feedback archi-
tecture allow maximum flexibility when designing active filters.
The AD9631/AD9632 are offered in the industrial (−40°C to
+85°C) temperature range. They are available in PDIP and SOIC.
Figure 2. AD9631 Harmonic Distortion vs. Frequency, G = +1
1
2
3
4
NC
–INPUT
+INPU
T
–V
S
8
7
6
5
NC
AD9631/
AD9632
TOP VIEW
(Not to Scale)
+V
S
OUTPUT
NC
NOTES
1. NC = NO CONNECT.
00601-001
–
30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
10k 100k 1M 10M 100M
HARMONIC DISTORTION (dBc)
FREQUENCY (Hz)
THIRD HARMONIC
SECOND HARMONIC
VS = ±5V
RL = 500Ω
VOUT = 2V p-p
00601-002
AD9631/AD9632 Data Sheet
Rev. D | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Configuration ............................................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 5
Metallization Photo ...................................................................... 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 15
General......................................................................................... 15
Feedback Resistor Choice.......................................................... 15
Pulse Response ........................................................................... 16
Large Signal Performance ......................................................... 16
Power Supply Bypassing ............................................................ 16
Driving Capacitive Loads .......................................................... 16
Applications Information .............................................................. 17
Operation as a Video Line Driver ............................................ 17
Active Filters ............................................................................... 17
Analog-to-Digital Converter (ADC) Driver .......................... 18
Layout Considerations ............................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
2/14—Rev. C to Rev. D
Changes to Figure 33 ...................................................................... 10
Changes to Analog-to-Digital Converter (ADC) Driver Section
and Figure 66 ................................................................................... 18
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
7/03—Rev. B to Rev. C
Deleted Evaluation Boards information .......................... Universal
Deleted military CERDIP version .................................... Universal
Change to Absolute Maximum Ratings ......................................... 3
Change to TPC 4 ............................................................................... 4
Change to TPC 10............................................................................. 5
Change to Figure 6 ......................................................................... 14
Updated Outline Dimensions ....................................................... 17
1/03—Rev. A to Rev. B
Deleted DIP (N) Inverter, SOIC (R) Inverter, and DIP (N)
Noninverter Evaluation Boards in Figures 12–14 ...................... 17
Updated Outline Dimensions ....................................................... 18
Data Sheet AD9631/AD9632
Rev. D | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
±VS = ±5 V; RLOAD = 100 Ω; AV = 1 (AD9631); AV = 2 (AD9632), unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments
AD9631 AD9632
Unit Min Typ Max Min Typ Max
DYNAMIC PERFORMANCE
Bandwidth (–3 dB)
Small Signal VOUT ≤ 0.4 V p-p 220 320 180 250 MHz
Large Signal1 VOUT = 4 V p-p 150 175 155 180 MHz
Bandwidth for 0.1 dB Flatness VOUT = 300 mV p-p
RF = 140 Ω (AD9631);
RF = 425 Ω (AD9632)
130 130 MHz
Slew Rate, Average ± VOUT = 4 V step 1000 1300 1200 1500 V/μs
Rise/Fall Time VOUT = 0.5 V step 1.2 1.4 ns
V
OUT
= 4 V step
2.5
ns
Settling Time
To 0.1% VOUT = 2 V step 11 11 ns
To 0.01% VOUT = 2 V step 16 16 ns
HARMONIC/NOISE PERFORMANCE
Second Harmonic Distortion 2 V p-p; 20 MHz, RL = 100 Ω −64 −57 −54 −47 dBc
RL = 500 Ω −72 −65 −72 −65 dBc
Third Harmonic Distortion 2 V p-p; 20 MHz, RL = 100 Ω −76 −69 −74 −67 dBc
RL = 500 Ω −81 −74 −81 −74 dBc
Third-Order Intercept
25 MHz
46
dBm
Noise Figure RS = 50 Ω 18 14 dB
Input Voltage Noise 1 MHz to 200 MHz 7.0 4.3 nA/√Hz
Input Current Noise 1 MHz to 200 MHz 2.5 2.0 pA/√Hz
Average Equivalent Integrated
Input Noise Voltage
0.1 MHz to 200 MHz 100 60 μV rms
Differential Gain Error (3.58 MHz) RL = 150 Ω 0.03 0.06 0.02 0.04 %
Differential Phase Error (3.58 MHz) RL = 150 Ω 0.02 0.04 0.02 0.04 Degree
Phase Nonlinearity DC to 100 MHz 1.1 1.1 Degree
DC PERFORMANCE2 RL = 150 Ω
Input Offset Voltage3 3 10 2 5 mV
TMIN − TMAX 13 8 mV
Offset Voltage Drift ±10 ±10 µV/°C
Input Bias Current 2 7 2 7 µA
TMIN − TMAX 10 10 µA
Input Offset Current 0.1 3 0.1 3 µA
TMIN − TMAX 5 5 µA
Common-Mode Rejection Ratio VCM = ± 2.5 V 70 90 70 90 dB
Open-Loop Gain VOUT = ± 2.5 V 46 52 46 52 dB
TMIN − TMAX 40 40 dB
INPUT CHARACTERISTICS
Input Resistance 500 500 kΩ
Input Capacitance
1.2
pF
Input Common-Mode Voltage Range ±3.4 ±3.4 V
AD9631/AD9632 Data Sheet
Rev. D | Page 4 of 20
Parameter Test Conditions/Comments
AD9631 AD9632
Unit Min Typ Max Min Typ Max
OUTPUT CHARACTERISTICS
Output Voltage Range RL = 150 Ω ±3.2 ±3.9 ±3.2 ±3.9 V
Output Current 70 70 mA
Output Resistance 0.3 0.3 Ω
Short Circuit Current 240 240 mA
POWER SUPPLY
Operating Range ±3.0 ±5.0 ±6.0 ±3.0 ±5.0 ±6.0 V
Quiescent Current 17 18 16 17 mA
T
MIN
− T
MAX
21
20
mA
Power Supply Rejection Ratio TMIN − TMAX 50 60 56 66 dB
1 See the Absolute Maximum Ratings and Theory of Operation sections of this data sheet.
2 Measured at AV = 50.
3 Measured with respect to the inverting input.
Data Sheet AD9631/AD9632
Rev. D | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage (+VS to −VS) 12.6 V
Voltage Swing × Bandwidth Product 550 V × MHz
Internal Power Dissipation
PDIP (N) 1.3 W
SOIC (R) 0.9 W
Input Voltage (Common Mode) ±VS
Differential Input Voltage ±1.2 V
Output Short Circuit Duration Observe Power
Derating Curves
Storage Temperature Range −65°C to +125°C
Operating Temperature Range (A Grade) −40°C to +85°C
Lead Temperature Range (Soldering 10 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
METALLIZATION PHOTO
Figure 3. Dimensions shown in inches and (millimeters) Connect Substrate to −VS
THERMAL RESISTANCE
Table 3.
Package Type1 θ
JA Unit
8-Lead PDIP (N) 90 °C/W
8-Lead SOIC (R) 140 °C/W
1 For device in free air.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by these
devices is limited by the associated rise in junction temperature.
The maximum safe junction temperature for plastic encapsu-
lated devices is determined by the glass transition temperature
of the plastic, approximately 150°C. Exceeding this limit tempo-
rarily may cause a shift in parametric performance due to a
change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure.
While the AD9631 and AD9632 are internally short circuit
protected, this may not be sufficient to guarantee that the max-
imum junction temperature (150°C) is not exceeded under all
conditions. To ensure proper operation, it is necessary to
observe the maximum power derating curves.
Figure 4. Maximum Power Dissipation vs. Temperature
ESD CAUTION
AD9631
AD9632
–IN
–IN
2+VS
7
6
OUT
2+VS
7
6
OUT
3
+IN 4
–VS
3
+IN 4
–VS
0.046
(1.17)
0.050 (1. 27)
0.046
(1.17)
00601-003
2.0
0
0.5
1.0
1.5
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
MAXIMUM POWER DISSIPATIO N (W)
AMBIENT TEMP ERATU RE (°C)
8-LEAD SOIC PACKAGE
8-LEAD PDIP PACKAGE T
J
= 150°C
00601-004
AD9631/AD9632 Data Sheet
Rev. D | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5. AD9631 Noninverting Configuration, G = +1
Figure 6. AD9631 Large Signal Transient Response; VOUT = 4 V p-p,
G = +1, RF = 250 Ω
Figure 7. AD9631 Small Signal Transient Response; VOUT = 400 mV p-p,
G = +1, RF = 140 Ω
Figure 8. AD9631 Inverting Configuration, G = −1
Figure 9. AD9631 Large Signal Transient Response; VOUT = 4 V p-p, G = −1,
RF = RIN = 267 Ω
Figure 10. AD9631 Small Signal Transient Response; VOUT = 400 mV p-p,
G = −1, RF = RIN = 267 Ω
AD9631
+V
S
0.1µF
0.1µF
10µF
10µF
–V
S
R
F
130Ω
V
IN
R
L
= 100Ω
V
OUT
PULSE
GENERATOR
T
R
/T
F
= 350ps
R
T
49.9Ω
00601-005
1V 5ns
00601-006
100mV 5ns
00601-007
AD9631
0.1µF
0.1µF
10µF
10µF
+VS
–VS
RF
RL = 100Ω
VOUT
PULSE
GENERATOR
TR/TF = 350ps
RT
49.9Ω
267Ω
VIN
100Ω
00601-008
1V 5ns
00601-009
100mV 5ns
00601-010
Data Sheet AD9631/AD9632
Rev. D | Page 7 of 20
Figure 11. AD9632 Noninverting Configuration, G = +2
Figure 12. AD9632 Large Signal Transient Response; VOUT = 4 V p-p, G = +2,
RF = RIN = 422 Ω
Figure 13. AD9632 Small Signal Transient Response; VOUT = 400 mV p-p,
G = +2, RF = RIN = 274 Ω
Figure 14. AD9632 Inverting Configuration, G = −1
Figure 15. AD9632 Large Signal Transient Response; VOUT = 4 V p-p, G = −1,
RF = RIN = 422 Ω, RT = 56.2 Ω
Figure 16. AD9632 Small Signal Transient Response; VOUT = 400 mV p-p,
G = −1, RF = RIN = 267 Ω, RT = 61.9 Ω
PULSE
GENERATOR
T
R
/T
F
= 350ps
R
T
49.9Ω
R
IN
AD9632
+V
S
0.1µF
0.1µF
10µF
10µF
–V
S
R
F
130Ω
V
IN
R
L
= 100Ω
V
OUT
00601-011
1V 5ns
00601-012
100mV 5ns
00601-013
PULSE
GENERATOR
T
R
/T
F
= 350ps
R
T
49.9Ω
R
IN
100Ω
V
IN
AD9632
+V
S
0.1µF
0.1µF
10µF
10µF
–V
S
R
F
R
L
= 100Ω
V
OUT
00601-014
1V 5ns
00601-015
100mV 5ns
00601-016
AD9631/AD9632 Data Sheet
Rev. D | Page 8 of 20
Figure 17. AD9631 Small Signal Frequency Response, G = +1
Figure 18. AD9631 0.1 dB Flatness, N Package (for R Package Add 20 Ω to RF)
Figure 19. AD9631 Open-Loop Gain and Phase Margin vs. Frequency,
RL = 100 Ω
Figure 20. AD9631 Small Signal −3 dB Bandwidth vs. RF
Figure 21. AD9631 Large Signal Frequency Response, G = +1
Figure 22. AD9631 Small Signal Frequency Response, G = −1
1
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1M 10M 100M 1G
GAIN (d B)
FRE QUENCY ( Hz )
V
S
= ±5V
R
L
= 100Ω
V
OUT
= 300mV p - p
R
F
= 200Ω
R
F
= 100Ω
R
F
= 50Ω
R
F
= 150Ω
00601-017
0.1
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
1M 10M 100M 500M
GAIN (d B)
FRE QUENCY ( Hz )
V
S
= ±5V
R
L
= 100Ω
G = +1
V
OUT
= 300mV p - p
R
F
= 150Ω
R
F
= 140Ω
R
F
= 100Ω
R
F
= 120Ω
00601-018
90
80
–20
–10
0
10
20
30
40
50
60
70
100
80
–120
–100
–80
–60
–40
–20
0
20
40
60
10k 100k 1M 10M 100M 1G
GAIN (d B)
PHASE M ARGIN ( Degrees)
FRE QUENCY ( Hz )
PHASE
GAIN
00601-019
450
250
300
350
400
475
275
358
375
425
20 40 60 80 100 120 140 160 180 200 220 240
–3dB BANDWIDTH (M Hz )
VAL UE OF FEE DBACK RE S IST OR, R
F
(Ω)
V
S
= ±5V
R
L
= 100Ω
G = +1
N PACKAG E
R PACKAG E
R
F
R
L
130Ω AD9631
00601-020
1
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1M 10M 100M 500M
OUTPUT (dB)
FRE QUENCY ( Hz )
V
S
= ±5V
R
L
= 100Ω
V
OUT
= 4V p-p
R
F
= 250Ω
R
F
= 50Ω TO 250Ω
BY 50Ω
00601-021
1
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1M 10M 100M 1G
GAIN (d B)
FRE QUENCY ( Hz )
V
S
= ±5V
R
L
= 100Ω
V
OUT
= 300mV p - p
R
F
= 267Ω
00601-022
Data Sheet AD9631/AD9632
Rev. D | Page 9 of 20
Figure 23. AD9631 Harmonic Distortion vs. Frequency, RL = 500 Ω
Figure 24. AD9631 Harmonic Distortion vs. Frequency, RL = 100 Ω
Figure 25. AD9631 Third Order Intercept vs. Frequency
Figure 26. AD9631 Differential Gain and Phase Error, G = +2, RL = 150 Ω
Figure 27. AD9631 Short-Term Settling Time, 2 V Step, RL = 100 Ω
Figure 28. AD9631 Long-Term Settling Time, 2 V Step, RL = 100 Ω
–30
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
10k 100k 1M 100M10M
HARMO NIC DIS TO RTION (dBc)
FRE QUENCY ( Hz )
V
S
= ±5V
R
L
= 500Ω
G = +1
V
OUT
= 2V p-p
SECOND
HARMONIC
THIRD
HARMONIC
00601-023
–30
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
10k 100k 1M 100M10M
HARMO NIC DIS TO RTION (dBc)
FRE QUENCY ( Hz )
V
S
= ±5V
R
L
= 100Ω
G = +1
V
OUT
= 2V p-p
SECOND
HARMONIC
THIRD
HARMONIC
00601-024
60
20
25
30
35
40
45
50
55
10 100
INTERCEP T (dBm)
FREQUENCY (MHz)
00601-025
–0.10
–0.05
0
0.05
0.10
–0.10
–0.05
0
0.05
0.10
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 11TH10TH
DIFFERENTIAL GAIN
(%)
DIFFE RE NTI AL PHASE
(Degrees)
00601-026
0.3
–0.3
–0.2
–0.1
0
0.1
0.2
010 20 30 40 50 60 70 80
ERRO R ( %)
SETTLING TIME (ns)
00601-027
0.3
–0.2
–0.1
0
0.1
0.2
0123456 8 107 9
ERRO R ( %)
SETTLING TIME (µs)
00601-028
AD9631/AD9632 Data Sheet
Rev. D | Page 10 of 20
Figure 29. AD9632 Small Signal Frequency Response, G = +2
Figure 30. AD9632 0.1 dB Flatness, N Package (for R Package Add 20 Ω to RF)
Figure 31. AD9632 Open-Loop Gain and Phase Margin vs. Frequency,
RL = 100 Ω
Figure 32. AD9632 Small Signal −3 dB Bandwidth vs. RF, RIN
Figure 33. AD9632 Large Signal Frequency Response, G = +2
Figure 34. AD9632 Small Signal Frequency Response, G = −1
7
–3
–2
–1
0
1
2
3
4
5
6
1M 10M 100M 1G
GAIN (d B)
FRE QUENCY ( Hz )
V
S
= ±5V
R
L
= 100Ω
V
OUT
= 300mV p - p
R
F
= 425Ω
R
F
= 225Ω
R
F
= 125Ω
R
F
= 325Ω
00601-029
0.1
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
1M 10M 100M
OUTPUT (dB)
FRE QUENCY ( Hz )
VS = ±5V
RL = 100Ω
G = +2
VOUT = 300mV p-p
RF = 275Ω
RF = 325Ω
RF = 375Ω
RF = 425Ω
00601-030
65
–15
–10
–5
0
5
10
15
20
25
30
35
40
45
50
55
60 100
150
50
0
–50
–100
–150
–200
–250
10k 100k 1M 10M 100M 1G
A
OL
(d B)
PHASE M ARGIN ( Degrees)
FRE QUENCY ( Hz )
PHASE
GAIN
00601-031
375
350
325
300
275
250
225
200
175
150
12550 100 150 200 250 300 350 400 450 500 550 600
–3dB BANDWIDTH (M Hz )
VALUE OF RF, RIN (Ω)
VS = ±5V
RL = 100Ω
G = +2
N PACKAG E
R PACKAG E
AD9632
RF
RL
100Ω
49.9Ω
RIN
00601-032
7
–3
–2
–1
0
1
2
3
4
5
6
1M 10M 100M 500M
OUTPUT (dB)
FRE QUENCY ( Hz )
V
S
= ±5V
R
L
= 100Ω
V
OUT
= 4V p-p
R
F
= 425Ω
R
F
= 125Ω TO 425Ω
BY 100Ω
00601-033
1
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1M 10M 100M 1G
GAIN (d B)
FRE QUENCY ( Hz )
V
S
= ±5V
R
L
= 100Ω
V
OUT
= 300mV p - p
R
F
, R
IN
= 267Ω
00601-034
Data Sheet AD9631/AD9632
Rev. D | Page 11 of 20
Figure 35. AD9632 Harmonic Distortion vs. Frequency, RL = 500 Ω
Figure 36. AD9632 Harmonic Distortion vs. Frequency, RL = 100 Ω
Figure 37. AD9632 Third Order Intercept vs. Frequency
Figure 38. AD9632 Differential Gain and Phase Error G = +2, RL = 150 Ω
Figure 39. AD9632 Short-Term Settling Time, 2 V Step, RL = 100 Ω
Figure 40. AD9632 Long-Term Settling Time, 2 V Step, RL = 100 Ω
–30
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
10k 100k 1M 100M10M
HARMO NIC DIS TO RTION (dBc)
FRE QUENCY ( Hz )
V
S
= ±5V
R
L
= 500Ω
G = +2
V
OUT
= 2V p-p
SECOND
HARMONIC
THIRD
HARMONIC
00601-035
–30
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
10k 100k 1M 100M10M
HARMO NIC DIS TO RTION (dBc)
FRE QUENCY ( Hz )
V
S
= ±5V
R
L
= 100Ω
G = +2
V
OUT
= 2V p-p
SECOND
HARMONIC
THIRD
HARMONIC
00601-036
50
10
15
20
25
30
35
40
45
10 100
INTERCEP T (dBm)
FREQUENCY (MHz)
00601-037
–0.04
–0.02
0
0.02
0.04
–0.04
–0.02
0
0.02
0.04
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 11TH10TH
DIFFERENTIAL GAIN
(%)
DIFFE RE NTI AL PHASE
(Degrees)
00601-038
0.2
–0.3
–0.2
–0.1
0
0.1
010 20 30 40 50 60 70 80
ERRO R ( %)
SETTLING TIME (ns)
00601-039
0.3
–0.2
–0.1
0
0.1
0.2
0123456 8 107 9
ERRO R ( %)
SETTLING TIME (µs)
00601-040
AD9631/AD9632 Data Sheet
Rev. D | Page 12 of 20
Figure 41. AD9631 Noise vs. Frequency
Figure 42. AD9631 PSRR vs. Frequency
Figure 43. AD9631 CMRR vs. Frequency
Figure 44. AD9632 Noise vs. Frequency
Figure 45. AD9632 PSRR vs. Frequency
Figure 46. AD9632 CMRR vs. Frequency
24
3
6
9
12
15
18
21
10 100 1k 100k10k
INPUT NOISE VOLTAGE (nV√Hz)
FRE QUENCY ( Hz )
V
S
= ±5V
00601-041
80
75
70
65
0
5
10
15
20
25
30
35
40
45
50
55
60
10k 100k 1M 10M 100M 1G
PSRR ( dB)
FRE QUENCY ( Hz )
–PSRR
+PSRR
00601-042
100
90
20
30
40
50
60
70
80
100k 1M 10M 1G100M
CMRR (dB)
FRE QUENCY ( Hz )
V
S
= ±5V
ΔV
CM
= 1V
R
L
= 100Ω
00601-043
17
3
5
7
9
11
13
15
10 100 1k 100k10k
INPUT NOISE VOLTAGE (nV√Hz)
FRE QUENCY ( Hz )
V
S
= ±5V
00601-044
80
75
70
65
0
5
10
15
20
25
30
35
40
45
50
55
60
10k 100k 1M 10M 100M 1G
PSRR ( dB)
FRE QUENCY ( Hz )
–PSRR
+PSRR
00601-045
100
90
20
30
40
50
60
70
80
100k 1M 10M 1G100M
CMRR (dB)
FRE QUENCY ( Hz )
V
S
= ±5V
ΔV
CM
= 1V
R
L
= 100Ω
00601-046
Data Sheet AD9631/AD9632
Rev. D | Page 13 of 20
Figure 47. AD9631 Output Resistance vs. Frequency
Figure 48. AD9632 Output Resistance vs. Frequency
Figure 49. Output Swing vs. Temperature
Figure 50. Open-Loop Gain vs. Temperature
Figure 51. PSRR vs. Temperature
Figure 52. CMRR vs. Temperature
1k
0.01
0.1
1
10
100
10k 100k 1M 10M 100M
R
OUT
(Ω)
FRE QUENCY ( Hz )
V
S
= ±5V
G = +1
00601-047
1k
0.01
0.1
1
10
100
10k 100k 1M 10M 100M
R
OUT
(Ω)
FRE QUENCY ( Hz )
V
S
= ±5V
G = +1
00601-048
4.1
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
–60 –40 –20 020 40 60 80 100 120 140
OUTPUT SWING (V)
JUNCTION TEM P E RATURE (°C)
VS = ±5V +VOUT
RL = 150Ω
RL = 50Ω
+VOUT
|–VOUT|
|–VOUT|
00601-049
1350
350
450
550
650
750
850
950
1050
1150
1250
–60 –40 –20 020 40 60 80 100 120 140
OPEN-LOO P G AIN (V/V)
JUNCTION TEM P E RATURE (°C)
+AOL
AD9632
AD9631 +AOL
–AOL
–AOL
00601-050
76
56
58
60
62
64
66
68
70
72
74
–60 –40 –20 020 40 60 80 100 120 140
PSRR ( dB)
JUNCTION TEM P E RATURE (°C)
AD9632
AD9632
AD9631
AD9631
+PSRR
+PSRR
–PSRR
–PSRR
00601-051
98
96
94
92
90
88
86
–60 –40 –20 020 40 60 80 100 120 140
CMRR (dB)
JUNCTION TEM P E RATURE (°C)
–CMRR
+CMRR
00601-052
AD9631/AD9632 Data Sheet
Rev. D | Page 14 of 20
Figure 53. Supply Current vs. Temperature
Figure 54. Input Offset Voltage vs. Temperature
Figure 55. AD9631 Input Offset Voltage Distribution
Figure 56. Short Circuit Current vs. Temperature
Figure 57. Input Bias Current vs. Temperature
Figure 58. AD9632 Input Offset Voltage Distribution
21
20
19
18
17
16
15
14
–60 –40 –20 020 40 60 80 100 120 140
SUPP LY CURRENT (mA)
JUNCTION TEM P E RATURE (°C)
±6V
±6V
±5V
±5V
AD9631
AD9631
AD9632
AD9632
00601-053
–1.0
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–60 –40 –20 020 40 60 80 100 120 140
INPUT OFFSET VOLTAGE (mV)
JUNCTION TEM P E RATURE (°C)
AD9631
AD9632
VS = ±5V
VS = ±5V
VS = ±6V
VS = ±6V
00601-054
220
0
20
40
60
80
100
120
140
160
180
200
100
0
10
20
30
40
50
60
70
80
90
–7 –6 –5 –4 –3 –2 –1 01234567
COUNT
PERCENT
INPUT OFFSET VOLTAGE (mV)
CUMULATIVE
FREQUENCY
DISTRIBUTION
3 WAFER LOTS
COUNT = 1373
00601-055
250
180
190
200
210
220
230
240
–60 –40 –20 020 40 60 80 100 120 140
SHO RT CIRCUIT CURRE NT (mA)
JUNCTION TEM P E RATURE (°C)
AD9631
AD9632
SINK
SINK
SOURCE
SOURCE
00601-056
2.0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–60 –40 –20 020 40 60 80 100 120 140
INP UT BIAS CURRE NT (µ A)
JUNCTION TEM P E RATURE (°C)
AD9631 AD9632
+IB
+IB
–IB
–IB
00601-057
180
0
20
40
60
80
100
120
140
160
100
0
10
20
30
40
50
60
70
80
90
–7 –6 –5 –4 –3 –2 –1 01234567
COUNT
PERCENT
INPUT OFFSET VOLTAGE (mV)
CUMULATIVE
FREQUENCY
DISTRIBUTION
3 WAFER LOTS
COUNT = 573
00601-058
Data Sheet AD9631/AD9632
Rev. D | Page 15 of 20
THEORY OF OPERATION
GENERAL
The AD9631/AD9632 are wide bandwidth, voltage feedback
amplifiers. Because their open-loop frequency response follows
the conventional 6 dB/octave roll-off, their gain bandwidth
product is basically constant. Increasing their closed-loop gain
results in a corresponding decrease in small signal bandwidth.
This can be observed by noting the bandwidth specification
between the AD9631 (gain of +1) and AD9632 (gain of +2). The
AD9631/AD9632 typically maintain 65° of phase margin. This
high margin minimizes the effects of signal and noise peaking.
FEEDBACK RESISTOR CHOICE
The value of the feedback resistor is critical for optimum per-
formance on the AD9631 (gain of +1) and less critical as the
gain increases. Therefore, this section is specifically targeted
at the AD9631.
At the minimum stable gain (+1), the AD9631 provides opti-
mum dynamic performance with RF = 140 Ω. This resistor acts
as a parasitic suppressor only against damped RF oscillations
that can occur due to lead (input, feedback) inductance and
parasitic capacitance. This value of RF provides the best combi-
nation of wide bandwidth, low parasitic peaking, and fast
settling time.
In fact, for the same reasons, place a 100 Ω to 130 Ω resistor in
series with the positive input for other AD9631 noninverting
and all AD9631 inverting configurations. The correct connec-
tion is shown in Figure 59 and Figure 60.
Figure 59. Noninverting Operation
Figure 60. Inverting Operation
When the AD9631 is used in the transimpedance (I to V)
mode, such as in photodiode detection, the value of RF and
diode capacitance (CI) are usually known. Generally, the value
of RF selected will be in the kΩ range, and a shunt capacitor (CF)
across RF will be required to maintain good amplifier stability.
The value of CF required to maintain optimal flatness (<1 dB
peaking) and settling time can be estimated by
( )
[ ]
2
1
22
/12 F
O
FI
O
FRRCC
ωω
−≅
where:
ωO is equal to the unity gain bandwidth product of the amplifier
in rad/sec.
CI is the equivalent total input capacitance at the inverting input.
Typically ωO = 800 × 106 rad/sec (see Figure 19).
As an example, choosing RF = 10 kΩ and CI = 5 pF requires CF
to be 1.1 pF (Note that CI includes both source and parasitic
circuit capacitance). The bandwidth of the amplifier can be
estimated using CF:
FF
3dB CR
f
π
2
6.1
≅
Figure 61. Transimpedance Configuration
For general voltage gain applications, the amplifier bandwidth
can be closely estimated as
( )
G
F
O
3dB
RR
f/12 +
≅
π
ω
This estimation loses accuracy for gains of +2/−1 or lower due
to the damping factor of the amplifier. For these low gain cases,
the bandwidth will actually extend beyond the calculated value
(see Figure 17 and Figure 29).
As a general rule, Capacitor CF will not be required if
( )
O
I
G
F
NG
CRR
ω
4
≤×
where NG is the noise gain (1 + RF/RG) of the circuit. For most
voltage gain applications, this should be the case.
+VS
0.1µF
0.1µF
10µF
10µF
–VS
100Ω TO
130Ω
RIN
RTERM
VIN
VOUT
RF
RG
RF
RG
G = 1 +
AD9631/
AD9632
00601-059
+VS
0.1µF
0.1µF
10µF
10µF
–VS
RTERM
VIN
VOUT
RF
RG
RF
RG
G = 1 –
AD9631/
AD9632
100Ω TO
130Ω
RIN
00601-060
V
OUT
R
F
C
F
C
I
I
I
AD9631
00601-061
AD9631/AD9632 Data Sheet
Rev. D | Page 16 of 20
PULSE RESPONSE
Unlike a traditional voltage feedback amplifier, where the slew
speed is dictated by its front end dc quiescent current and gain
bandwidth product, the AD9631/AD9632 provide on-demand
current that increases proportionally to the input step signal
amplitude. This results in slew rates (1300 V/µs) comparable
to wideband current feedback designs. This, combined with
relatively low input noise current (2.0 pA/√Hz), gives the
AD9631/AD9632 the best attributes of both voltage and
current feedback amplifiers.
LARGE SIGNAL PERFORMANCE
The outstanding large signal operation of the AD9631 and
AD9632 is due to a unique, proprietary design architecture. To
maintain this level of performance, the maximum 550 V × MHz
product must be observed (for example, @ 100 MHz, VOUT ≤
5.5 V p-p).
POWER SUPPLY BYPASSING
Adequate power supply bypassing can be critical when optimiz-
ing the performance of a high frequency circuit. Inductance in
the power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors
(typically greater than 1 µF) will be required to provide the best
settling time and lowest distortion. A parallel combination of at
least 4.7 µF, and between 0.1 µF and 0.01 µF, is recommended.
Some brands of electrolytic capacitors will require a small series
damping resistor ≈4.7 Ω for optimum results.
DRIVING CAPACITIVE LOADS
The AD9631/AD9632 were designed primarily to drive non-
reactive loads. If driving loads with a capacitive component is
desired, the best frequency response is obtained by the addition
of a small series resistance as shown in Figure 62. Figure 63
shows the optimum value for RSERIES vs. capacitive load. It is
worth noting that the frequency response of the circuit when
driving large capacitive loads will be dominated by the passive
roll-off of RSERIES and CL.
Figure 62. Driving Capacitive Loads
Figure 63. Recommended RSERIES vs. Capacitive Load
RF
RSERIES
RIN
RIN
CL
RL
1kΩ
AD9631/
AD9632
00601-062
40
30
20
10 010 20515 25
RSERIES (Ω)
CL (pF)
00601-063
Data Sheet AD9631/AD9632
Rev. D | Page 17 of 20
APPLICATIONS INFORMATION
The AD9631/AD9632 are voltage feedback amplifiers well
suited for applications such as photodetectors, active filters,
and log amplifiers. The wide bandwidth (320 MHz), phase
margin (65°), low current noise (2.0 pA/√Hz), and slew rate
(1300 V/µs) of the devices give higher performance capabilities
to these applications over previous voltage feedback designs.
With a settling time of 16 ns to 0.01% and 11 ns to 0.1%, the
devices are an excellent choice for DAC I/V conversion. The
same characteristics along with low harmonic distortion make
them a good choice for ADC buffering/amplification. With
superb linearity at relatively high signal frequencies, the
AD9631/AD9632 are ideal drivers for ADCs up to 12 bits.
OPERATION AS A VIDEO LINE DRIVER
The AD9631/AD9632 have been designed to offer outstanding
performance as video line drivers. The important specifications
of differential gain (0.02%) and differential phase (0.02°) meet
the most exacting HDTV demands for driving video loads.
Figure 64. Video Line Driver
ACTIVE FILTERS
The wide bandwidth and low distortion of the AD9631/
AD9632 are ideal for the realization of higher bandwidth active
filters. These characteristics, while being more common in
many current feedback op amps, are offered in the AD9631/
AD9632 in a voltage feedback configuration. Many active
filter configurations are not realizable with current feedback
amplifiers.
A multiple feedback active filter requires a voltage feedback
amplifier and is more demanding of op amp performance than
other active filter configurations, such as the Sallen-Key. In
general, the amplifier should have a bandwidth that is at least
10 times the bandwidth of the filter if problems due to phase
shift of the amplifier are to be avoided.
Figure 65 is an example of a 20 MHz low-pass multiple feedback
active filter using an AD9632.
Figure 65. Active Filter Circuit
Choose
FO = cutoff frequency = 20 MHz
α = damping ratio = 1/Q = 2
H = absolute value of circuit gain =
1
1
4=
−
R
R
Then
12 CFk
O
π
=
2
)1(14
α
+
=HC
C2
HK
R1 2
α
=
)1(2 +
=HK
R3
α
)1(RHR4 =
+V
S
0.1µF
0.1µF
10µF
10µF
–V
S
V
OUT
V
IN
AD9631/
AD9632
75Ω
75Ω
75Ω
274Ω 274Ω
75Ω
CABLE
75Ω
CABLE
00601-064
0.1µF
10µF
0.1µF
10µF
V
OUT
V
IN
+5V
–5V
AD9632
100Ω
C1
50pF
R3
78.7Ω
R4
154Ω
R1
154Ω
C2
100pF
00601-065
AD9631/AD9632 Data Sheet
Rev. D | Page 18 of 20
ANALOG-TO-DIGITAL CONVERTER (ADC) DRIVER
As ADCs move toward higher speeds with higher resolutions,
there becomes a need for high performance drivers that will not
degrade the analog signal to the converter. It is desirable from a
system’s standpoint that the ADC be the element in the signal
chain that ultimately limits overall distortion. Figure 66 is such
an example.
Figure 66. AD9631 Used as Driver for an ADC Signal Chain
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD9631/AD9632
requires careful attention to board layout and component
selection. Proper RF design techniques and low-pass parasitic
component selection are mandatory.
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance path. Remove the ground plane from the area near
the input pins to reduce stray capacitance.
Use chip capacitors for supply bypassing (see Figure 59 and
Figure 60). Connect one end to the ground plane, and the other
within 1/8 inch of each power pin. Connect an additional large
(0.47 μF to 10 μF) tantalum electrolytic capacitor in parallel,
though not necessarily so close, to supply current for fast, large
signal changes at the output.
The feedback resistor should be located close to the inverting
input pin to keep the stray capacitance at this node to a mini-
mum. Capacitance variations of less than 1 pF at the inverting
input will significantly affect high speed performance.
Use stripline design techniques for long signal traces (greater
than about 1 inch). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly
terminated at each end.
00601-066
+5V
–5V
130Ω
140Ω
ANALOG IN
AD9631 ADC
Data Sheet AD9631/AD9632
Rev. D | Page 19 of 20
OUTLINE DIMENSIONS
Figure 67. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
Figure 68. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDE C S TANDARDS MS-001
CONTROLLING DIMENSIONSARE IN INCHES; MIL L I MET ER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED- OFF I NCH E QUIVALENTS FOR
REF E RE NCE ONLY AND ARE NO T APPROPRIATE FOR USE IN DESIGN.
CORNE R LEADS MAY BE CONF IG URE D AS WHOLE OR HAL F LE ADS .
070606-A
0.022 ( 0.56)
0.018 ( 0.46)
0.014 ( 0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 ( 5.33)
MAX
0.150 ( 3.81)
0.130 ( 3.30)
0.115 (2.92)
0.070 ( 1.78)
0.060 ( 1.52)
0.045 ( 1.14)
8
14
5
0.280 ( 7.11)
0.250 ( 6.35)
0.240 ( 6.10)
0.100 ( 2.54)
BSC
0.400 ( 10.16)
0.365 ( 9.27)
0.355 ( 9.02)
0.060 ( 1.52)
MAX
0.430 ( 10.92)
MAX
0.014 ( 0.36)
0.010 ( 0.25)
0.008 ( 0.20)
0.325 ( 8.26)
0.310 ( 7.87)
0.300 ( 7.62)
0.195 ( 4.95)
0.130 ( 3.30)
0.115 (2.92)
0.015 ( 0.38)
GAUGE
PLANE
0.005 ( 0.13)
MIN
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
AD9631/AD9632 Data Sheet
Rev. D | Page 20 of 20
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9631ANZ –40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
AD9631AR –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD9631AR-REEL –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD9631AR-REEL7 –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD9631ARZ –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD9631ARZ-REEL –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD9631ARZ-REEL7 –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD9631AR-EBZ AD9631 Evaluation Board
AD9631ACHIPS Die
AD9632ANZ –40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
AD9632AR –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD9632ARZ –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD9632ARZ-REEL –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD9632ARZ-REEL7 –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD9632AR-EBZ AD9632 Evaluation Board
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D00601-0-2/14(D)
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