MCP25050-I/P - MICROCHIP - Datasheet.Directory

MCP2502X/5X

Features

• Implements CAN V2.0B

- Programmable bit rate up to 1 Mb/s

- One programmable mask

- Two programmable filters

- Three auto-transmit buffers

- Two message reception buffers

- Does not require sync hro niz ati on or

configuration message s

• Hardware Features

- Non-volatile memory for user configuration

- User configuration automatically loaded on

power-up

- Eight general-purpose I/O lines individually

selectable as inputs or outputs

- Individually selectable transmit-on-pin-

change for each input

- Four 10-bit, analog input channels wit h

programmab le conversi on clock and VREF

sources (MCP2505X devices only)

- Message sc heduling cap a b ili ty

- Two 10-bit PWM outputs with independently

progra mmab le frequenci es

- Devic e configu rati on can be modified via

CAN bus messages

- In-Circuit Serial Programming™ (ICSP™) of

default configuration memory

- Optional 1-wire CAN bus operation

• Low-power CMOS technology

- Operates from 2.7V to 5.5V

- 10 mA active current, typical

- 30 µA standby current (CAN Sleep mode)

• 14-pin PDIP (300 mil) and SOIC (150 mil)

packages

• Available temperature ranges:

- Industrial (I): -40°C to +85°C

- Extended (E): -40°C to +125°C

Description

The MCP2502X/5X devices operate as I/O expanders

for a Controller Area Network (CAN) system,

supporting CAN V2.0B active, with bus rates up to

1 Mb/s. The MCP2502X/5X allows a simple CAN node

to be implemented without the need for a

microcontroller.

The devices are identical, with the following

exceptions:

The MCP2502X/5X devices feature a number of

peripherals, including digital I/Os, four-channel 10-bit

A/D (MCP2505X) and PWM outputs with automatic

message transmission on change-of-input state. This

includes an analog input excee ding a preset thre shold.

One mask and two acceptance filters are provided to

give maximum flexibility during system design with

respect to identifiers that the device will respond to.

The device can also be configured to automatically

transmit a unique message whenever any of several

error conditions occur.

The device is pre-programmed in non-volatile memory

so that the part defaults to a specific configuration at

power-up.

Device A/D One Wire

Digital

CANbus

MCP25020 No No

MCP25025 No Yes

MCP25050 Yes No

MCP25055 Yes Yes

CAN I/O Expander Family

MCP2502X/5X

Package Types

Definition of Terms

The following terms are used throughout this

document:

I/O Expander - refers to the integrated circuit (IC)

device being described (MCP2502X/5X).

Input Message - term given to messages that are

received by the MCP2502X/5X and cause the internal

has been performed, the MCP2502X/5X transmits a

Command Acknowledge message to indicate that the

comma nd was rec eiv ed and proce ss ed.

Command Ackn owledge Message - term given to the

message that is automatically transmitted by the

MCP2502X/5X after receiving and processing an input

message.

Information Request Message - term given to

Remote Request messages that are received by the

MCP2502X/5X that subsequently generate an output

message (data frame) in response.

Output Message - term given to the mes sage that the

MCP2502X/5X sends in response to an Information

Request message.

On Bus Message - term given to the message t hat the

MCP2502X/5X transmits after completing the pow er-on/

self-configuration sequence at timed intervals, if

enabled.

Self-Configuration - term used to describe the

process of transferring the contents of the EPROM

memory array to the SRAM memory array.

On Bus - term us ed to desc ribe the cond ition when the

MCP2502X/5X is fully-configured and ready to

transmi t, or receiv e, on the bus. Th is is the o nly st ate in

which the MCP2502X/5X can transmit on the bus.

Edge Detection - refers to the MCP2502X/5X’s ability

to automatically transmit a message based upon the

occurance of a predefined edge on any digital input.

Threshold Detection - refers to the MCP2502X/5X’s

ability to automatically transmit a message when a

predefined analog threshold is reached.

GP0/AN0

GP1/AN1

VDD

TXCAN/TXRXCAN

RXCAN/NC*

GP5/VREF+

GP4/VREF-GP6/CLKOUT

GP3/AN3/PWM2

OSC1/CLKIN

GP2/AN2/PWM1

9OSC2

VSS

GP7/RST/VPP

PDIP/SOIC

* One-wire option available on MCP250X5 devices.

MCP2502X/5X

1.0 DEVICE OVERVIEW

This document contains device-specific information on

the M CP 2502 X/5 X f amil y of CAN I/O ex pande rs. The

CAN protocol is not discussed in depth in this

docume nt. Additional inform ati on on the CA N prot oco l

can be found in the CAN specification, as defined by

Robert Bos ch GmbH .

Figure 1-1 is the block diagram of the MCP2502X/5X

and Tab le 1-1 is the pinout desc ript ion .

The following sections detail the modules as listed in

Figure 1-1.

FIGURE 1-1: MCP2502X/5X BLOCK DIAGRAM

TABLE 1-1: PINOUT DESCRIPTION

GPIO

GP4/VREF-

GP3/AN3/PWM2

GP2/AN2/PWM1

GP1/AN1

GP0/AN0

GP5/VREF+

GP6/CLKOUT

GP7RST/VPP

User

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT CAN

Protocol

Engine RXCAN

TXCAN/

A/DPWM1PWM2

Memory

TXRXCAN

* Only the MCP2505X devices have the A/D module.

State Machine

and

Control Logic

Name Pin

Number Standard

Function Alternate

Function Programming

Mode Function

GP0/AN0 *1 Bidirectional I/O pin, TTL input buffer Analog input channel None

GP1/AN1 *2 Bidirectional I/O pin, TTL input buffer Analog input channel None

GP2/AN2/PWM2 *3 Bidi rectional I/O pin, TTL input buffer Analog input/PWM output None

GP3/AN3/PWM3 *4 Bidi rectional I/O pin, TTL input buffer Analog input/PWM output None

GP4/VREF- 5 Bidirectional I/O pin, TTL input buffer External VREF-Data

GP5/VREF+ 6 Bidirectional I/O pin, TTL input buffer External VREF input Clock

VSS 7 Ground None Ground

OSC1/CLKIN 8 External oscillator input External clock input None

OSC2 9 External oscillator output None None

GP6/CLKOUT 10 Bidirectional I/O pin, TTL input buffer CLKOUT output None

GP7/RST/VPP 11 Input pin, TTL input buffer External Reset input Vpp

RXCAN 12 CAN data receive input Not connected for 1-wire None

TXCAN/TXRXCAN 13 CAN data transmit output CAN TX and RX for 1-wire

operation (MCP250X5) None

VDD 14 Power None Power

* Only the MCP2505X devices have the A/D module.

MCP2502X/5X

NOTES:

MCP2502X/5X

2.0 CAN MODULE

The CAN module is a protocol controller that converts

between raw digital data and CAN message packets.

The main functi onal bl ock of th e CAN modul e is sh own

in Figure 2-1 and consists of:

• CAN protocol engine

• Buff ers, masks and filt ers

The modul e feat ures include:

• Implementation of the CAN protocol

• Doubl e-bu f f e red receiver wi th two separate

rece ive buffers

• One full-acceptance mask (standard and

extended)

• Two full-acceptance filters (standard and

extended)

• One filter for each receive buffer

• Three prioritized transmit buffers for transmitting

predefined message types

• Automatic wake-up on bus traffic function

• Error management logic for transmit and receive

error states

• Low -power SLEEP mode

FIGURE 2-1: CAN MODULE

Acceptance Filter

RXF1

Identifier

Data Field Data Field

Identifier

Accep tance Mask

RXM

Acceptance Filter

RXF0

TXREQ

TXB2

ABTF

MLOA

TXERR

MESSAGE

Message

Queue

Control Transmit Byte Sequencer

TXREQ

TXB0

ABTF

MLOA

TXERR

MESSAGE

CRC<14:0>

Comparator

Receive<7:0>Transmit<7:0>

Receive

Error

Transmit

Error

Protocol

REC

TEC

ErrPas

BusOf

Finite

State

Machine

Counter

Shift<14:0>

{Trans mi t<5: 0>, Re ce iv e<8 :0>}

Transmit

Logic Bit

Timing

Logic

TXCAN/TXRXCAN RXCAN Configuration

Registers

Clock

Generator

PROTOCOL

ENGINE

BUFFERS

TXREQ

TXB1

ABTF

MLOA

TXERR

MESSAGE

MCP2502X/5X

2.1 CAN Protocol F ini te State Machine

The heart of the engine is the Finite State Machine

(FSM). This state machine sequences through

messages on a bit-by-bit basis, changing states as the

fields of the various frame types are transmitted or

received. The FSM is a sequencer controlling the

sequential data stream between the TX/RX Shift

also controls the Error Management Logic (EML) and

the parallel data stream between the TX/RX Shift

cesses o f re ception, arbi trati on , tra ns mis sion and error

signal ing are perform ed according to t he CAN protoco l.

The automatic retransmission of messages on the bus

line is also handled.

2.2 Cyclic Redundancy Check (CRC)

The Cyclic Redundancy Check register generates the

Cyclic Redundancy Check (CRC) code that is

transmitted after either the Control field (for messages

with 0 data bytes) or the Dat a fiel d and is us ed to ch eck

the CRC field of incoming messages.

2.3 Error Management Logi c

The error managem ent lo gic is respo nsible fo r the fau lt

confinement of the CAN device. Its two counters (the

Receive Error Counter (REC) and the Transmit Error

Counter (TEC)) are incremented and decremented by

commands from the Bit S tream processor . According to

the values of the error counters, the MCP2502X/5X is

set into t he stat es error-act ive, error-p assive or bus-of f.

Error-active: Both error counters are below the error-

passive limit of 128.

Error-passive: At leas t one of the error counters (TEC

or REC) equals or exceeds 128.

Bus-off: The transmit error counter (TEC) equals or

exceed s the bus -off limit of 25 6. The dev ic e remains in

this state until the bus-off recovery sequence is

received. The bus-off recovery sequence consists of

128 occurrences of 11 consecutive recessive bits.

FIGURE 2-2: ERROR MODES STATE DIAGRAM

Note: The MCP2502X/5X, after going bus-off,

will recover back to error-active

automatically if the bus remains idle for

128 x 11 bits. OPTREG2.ERRE must be

set to force the MCP2502X/5X to enter

Liste n-onl y mode in stead of Normal mode

during bus recovery. The current error

mode (except for bus-off) of the

MCP2502X/5X can be determined by

reading the EFLG register via the Read

CAN error message.

Bus-Off

Error-Active

Error-Passive

RE C < 127 or

TEC < 127

REC > 127 or

TEC > 127

TEC > 255

RESET

128 occurrences of

11 consecutive

“recessive” bits

MCP2502X/5X

FIGURE 2-3: BIT TIME PARTITIONING

2.4 Bit T iming Logic

The Bit Timing Logic (BTL) monitors the bus line input

and handles the bus-related bit timing based on the

CAN protocol. The BTL synchronizes on a recessive-

to-dominant bus transition at Start-of-Frame (hard

synchronization) and on any further recessive-to-

dominant bus line transition if the CAN controller itself

does not transmit a dominant bit (resynchronization).

The BTL also provides programmable time segments

to compensate for the propagation delay time, phase

shifts and to define the position of the sample point

within the bit t im e. Th es e pro gram m abl e s egments a re

made up of integer units called Time Quanta (TQ). The

nominal bit time is calculated by programming the TQ

length and the number of TQ in each time segment, as

discussed below.

2.4.1 TIME QUANTUM (TQ)

Time Quantum is a fixed unit of time derived from the

oscillator period. There is a programmable baud rate

prescaler (BRP) (with integral values ranging from 1 to

64) as well as a fixed division by two for clock

generation.

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

bit 7 bit 0

bit 7-0 TEC7:TEC0: Transmit Error Counter bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

bit 7 bit 0

bit 7-0 REC7:REC0: Receive Error Counter bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Input Signal

Sync Prop

Segment Phase

Segment 1 Phase

Segment 2

Sample Point

MCP2502X/5X

The base TQ is defined as twice the oscillator period.

Adding the BRP into the equation yields:

By definition, the nominal bit time is programmable

from a minimum of 8 TQ to 25 TQ. Also, the minimum

nominal bit time is 1 µ s, which corresponds to 1 Mb/s.

2.4.2 TIME SEGMENTS

Time segments make up the nominal bit time. The

nomina l bit time c an be thoug ht of as being d ivided in to

separate non-overlapping time segments. These

segments are shown in Figure 2-3.

• Synchron iz ati on Segm en t (SyncSeg)

• Prop ag ation Segm en t (PropSeg )

• Pha se Bu ffer Segment 1 (PS1)

• Pha se Bu ffer Segment 2 (PS2)

Rules for Programming the Segments

There are a few rules to follow when programming the

time segments:

• PropSeg + PS1 ≥ PS2

• PS2 > Sync Jump Width

• PS2 ≥ Information Processing Time

2.4.2.1 Synchronization Segment

This part of the bit time is used to synchronize the

various CAN nodes on the bus. The edge of the input

signal is expected to occur during the SyncSeg. The

duration is fixed at 1TQ.

2.4.2.2 Propagation Segment

This part of the bit time is used to compensate for

physical delay times within the network. These delay

times c ons is t of th e si gnal prop a gati on time on th e bu s

line an d the in ternal d elay time o f the no des. Th e dela y

is calculated as being the round-trip time from

transmitter to receiver (twice the signal's propagation

time on the bus line), the input comparator delay and

the output driver delay. The length of the Propagation

Segment can be programmed from 1TQ to 8 TQ by

setting the PRSEG2:PRSEG0 bits of the CNF2

2.4.2.3 Phase Buffer Segments

The Phase Buffer Segments are used to optimally

locate the sampling point of the received bit within the

nominal bit time. The sampling point occurs between

PS1 and PS2. These segments can be automatically

lengthened or shortened by the resynchronization

process. Thus, the variation of the values of the phase

buffe r segments represent the DPLL functionality.

Phase Segment 1 (PS1): The end of PS1 determines

the samp ling point with in a bit time. PS1 is program ma-

ble from 1TQ - 8 TQ in duration.

Phase Segment 2 (PS2): PS2 provides delay before

the next transmitted data transition and is also pro-

grammable from 1TQ - 8 TQ in duratio n. H owe ver, due

to IPT requirements, the actual minimum length of

phase segment 2 is 2 TQ. It m ay al so b e de f in ed to be

equal to the greate r of PS1 or the inf orm ati on p roc ess -

ing time (IPT).

2.4.3 SAMPLE POINT

The sample point is the point of time at which the bus

level is read and the value of the received bit is

determined. The sampling point occurs at the end of

PS1. If desired, it is possible to specify multiple

sampli ng of the bus l ine at the sample po int. The v alu e

of the received bit is determined to be the value of the

majority decision of three values. The three samples

are ta ken at the sample point, and twice before, with a

time of TQ/2 between each sample.

2.4.4 INFORMATION PROCESSING TIME

The Information Processing Time (IPT) is the time

segment (starting at the sample point) that is reserved

for calculation of the subsequent bit level. The CAN

specification defines this time to be less than or equal

to 2 TQ. The MCP2502X/5X defines this time to be

Q. Thus, PS2 must be at least 2 TQ long.

2.4.5 SYNCHRONIZATION JUMP WIDTH

To compensate for phase shifts and oscillator

tolerances between the nodes in the system, each

CAN controller must be able to synchronize to the

relevant signal edge of the incoming signal. When a

recessive-to-dominant edge in the transmitted data is

detected , the logic will compare the location of the edge

to the expected time (SyncSeg). The circuit will then

adjust th e value s of PS1 and PS2, as nece ssary, using

the programmed Synchronization Jump Width (SJW).

This adj ustment is made for resyn chroniza tion during a

message and not hard synchronization, which occurs

only at the message Start-of-Frame (SOF).

TQ2*TOSC*BRP 1+()=

where BRP =binary value represented by

CNF1.BRP<5:0>

Nominal Bit Time TQ* Sync_Seg PropSeg

Phase_Seg1 Phase_Seg2

(

)

MCP2502X/5X

As a result of resynchronization, PS1 may be

lengthened or PS2 may be shortened. The amount of

lengthe ning or shortening of the phase buf fer segment s

has an upper-bound given by the SJW. The SJW is

programmable between 1TQ and 4 TQ. The value of

the SJW wil l be added to PS1 (or s ubtracted from PS2)

dependi ng on the phase er ror (e) of the edge in rel ation

to the receiver’s SyncSeg. The phase error is defined

as follows:

• e = 0 if the edge lies within SYNCESEG

- No resynchronization is required.

• e > 0 if the edge lies before the sample point

- PS1 will be lengthened by the amount of the

SJW.

• e < 0 if the edge lies after the sample point of the

previous bit and before the SyncSeg of the

current bit

- PS2 will be shortened by the amount of the

SJW.

2.4.6 CONFIGURATION REGISTERS

There are three registers (in the configuration register

module) associated with the CAN bit timing logic that

controls the bit timing for the CAN bus interface.

2.4.6.1 CNF1

The BRP<5:0> bits control the baud rate prescaler.

These bits set the length of TQ relative to the OSC1

input frequency, with the minimum length of TQ being

OSC in length (when BRP<5:0> are set to 000000).

The SJW<1:0> bits select the synchronization jump

width in terms of number of TQ’s.

2.4.6.2 CNF2

The PRSEG<2:0> bits set the length (in TQ’s) of the

propagation segment. The PS1<2:0> bits set the length

(in TQ’s) of phase segment 1. The SAM bi t controls how

many times the RXCAN pin is sampled. Setting this bit

to a ‘1’ causes the bus to be sampled three times.

Twice at TQ/2 be f ore t he sa mp le po i nt a nd once at t he

normal sample point (which is at the end of PS1). The

value of the bus is determined to be the value read

during at least two of the samples. If the SAM bit is set

to a ‘0’, the RXCAN pin is sampled only once at the

sample point. The BTLMODE bit controls how the

length o f PS2 is de termin ed. If th is bi t is set to a ‘ 1’, the

length of PS2 is determined by the PS2<2:0> bits of

CNF3. If th e BTLMO DE bit is set to a ‘0’ then the leng th

of PS2 is the greater of PS1 and the information

processing time (which is fixed at 2 TQ for the

MCP2502X/5X).

2.4.6.3 CNF3

The PS2<2:0> bi ts set the length, in TQ’ s, of PS2, if the

CNF2.BTLMOD E bi t is set to a ‘1’. If th e BTL MODE b it

is set to a ‘0’, the PS2<2:0> bits have no effect.

Additionally, the wake-up filter (CNF3.WAKFIL) is

implemented in the CNF3 register. This filter is a low-

pass filter that can be used to prevent the MCP2502X/

5X from waking up due to short glitches on the CAN

bus.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0

bit 7 bit 0

bit 7-6 SJW1:SJW0: Synchronized Jump Width bits

11 = Length = 4 x TQ

10 = Length = 3 x TQ

01 = Length = 2 x TQ

00 = Length = 1 x TQ

bit 5-0 BRP5:BRP0: Baud Rate Prescaler bits

111111 =TQ = 2 x 64 x 1/FOSC

000000 =TQ = 2 x 1 x 1/FOSC

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BTLMODE SAM PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEG1 PRSEG0

bit 7 bit 0

bit 7 BTL MODE: Length determination of PHSEG2 bit

1 = Length of Phase_Seg2 determined by bits 2:0 of CNF3

0 = Length of Phase_Se g2 is the greater of Phase_Se g1 or IPT(2Tq)

bit 6 SAM: Sample of the CAN bus line bit

1 = Bus line is sampled three times at the sample point

0 = Bus line is sampled once at the sample point

bit 5-3 PHSEG12:PHSEG10: Phase Buffer Segment1 bits

111 = length = 8 x TQ

000 = length = 1 x TQ

bit 2-0 PRSEG2:PRSEG0: Propagation Time Segment bits

111 = length = 8 x TQ

000 = length = 1 x TΘ

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— WAKFIL — — — PHSEG22 PHSEG21 PHSEG20

bit 7 bit 0

bit 7 Unimplemented: (Reads as 0)

bit 6 WAKFIL: Wak e-up filter bit

1 = Wake-up filter enabled

0 = Wake-up filter disabled

bit 5-3 Unimplemented: (Reads as 0)

bit 2-0 PHSEG22:PHSEG20: Phase Buffer Segment2 bits

111 = length = 8 x TQ

001 = length = 2 x TQ

000 = Invalid

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

2.5 Buffers, Masks, and Filters

This p art o f t he CAN mo dul e su ppo rts the tra ns mi ttin g,

receiving and acceptance of CAN messages.

Three transmit buffers are used for the three transmit

message IDs, as discussed later in this section. Two

receive buffers store the CAN message’s arbitration

field, control field and the data field.

One m ask defi nes w hic h bit s a re to b e app lied to eith er

filter. The mask can be regarded as defining “don’t

care” bits for the filter.

Each of the two filters define a bit pattern that will be

compared to all incoming messages. All filter bits that

have not been defined as “don’t care” by the mask are

applied to the message.

2.5.1 TRANSMIT MESSAGE ID’S

The MCP2502X/5X device contains three separate

transmit message ID’s: TXID0, TXID1 and TXID2. The

data length code is predefined for each of the various

output messages, with the data that is transmitted

coming directly from the contents of the device’s

peripheral registers.

2.5.1.1 Transmit Message ID0 (TXID0)

TXID0 contains the identifier that is used when trans-

mitting the On Bus message. If enabled

(STCON.STEN = 1), the On Bus message will be

transmitted at predefined intervals. Depending on the

message-select bit (STCON.STMS = 1), the CAN

messa ge will send GPIO and A/D data.

Transmit Message ID0 will not automatically be sent

when the device is brought out of sleep.

2.5.1.2 Transmit Message ID1 (TXID1)

TXID1 contains the identifier that is used when the

MCP2502X/5X sends the Command Acknowledge

message, the Receive Overflow message and/or the

Error Condition message. All message types use the

same identifier.

The CAEN bit, in the OPTREG2 register, selects

between the Command Acknowledge and Receive

Overflo w operation. These mes sage type s have a DLC

of 0 and do not contain any data. The Error Condition

message can occur anytime, has a DLC of 3 and

contains the EFLG, TEC and REC data values.

Command Acknowledge: TXID1 sends a Command

Acknowledge message when the MCP2502X/5X

receives an Input Message and processes the

instruction (and OPTREG2.CAEN = 1). This message

is used as a hand shake for the node requesting the

modification of the MCP2502X/5X. There is no data

associated with this message.

Receive Overflow: TXID1 sends a Receive Overflow

message if there is a Receive Overflow condition (and

OPTREG2.CAEN = 0). This only occurs if the device

has received a valid message before processing the

previous valid message from the same receive buffer.

There is no data associated with this message.

Error Condition: An Error Condition message is

transmitted if the TEC or REC counters reach error

warning (> 95) or error passive (> 127). This message

contains the TXID1 identifier and the TEC, REC and

EFLG counters.

A hysteresis is implemented in hardware that prevents

messages from repeatedly being transmitted due to

error counts changing by one or two bits. Once a

message is sent for an error warning (TEC or REC >

95), the message will not trigger again until the error

counter ≤ 79 and bac k to > 95 (hyste resis = 17 cou nts).

Similarly, an error passive message is sent at TEC or

REC > 12 7 a nd is n ot s en t a gai n until t he error counter

≤ 111 and back to >127 (hysteresis = 17 counts).

2.5.1.3 Transmit Message ID2 (TXID2)

Transmit ID2 contains the identifier that is used when

transmitting auto-conversion-initiated messages,

including digital input edge detection and/or analog

input exceeding a threshold. This message will also be

sent when the device wakes up from sleep due to a

digital input change-of-state condition (i.e., change-of-

state occurs on input configured to transmit on

change-of-state).

2.6 Receive Buffers

The MCP2505X contains two receive buffers, each

with thei r own filter . There is also a Message Ass embly

Buffer (MAB) that acts as a third receive buffer (see

Figure 2-1).

The two receive buffers, combined with the MAB help,

insure that rece iv ed me ss ag es w il l be proc es se d w hil e

minimizing the chances of receive buf fer overrun due to

maximum bus loading of messages destined for the

MCP2502X/5X.

Note: A zero data lengt h On Bus messa ge will be

transmitted once after power-up,

regardless of scheduled transmission-

enable st a tus . Note: The receive buffers are used by the

MCP2502X/5 X to implement the command

messages and are not externally

accessible.

MCP2502X/5X

2.7 Acceptance Mask

The acceptance mask is used to define which bits in the

CAN ID are to be co mp ared aga inst th e program mabl e

filter s. Individual bit s within the mask correspo nd to bits

in the CAN ID that, in turn, correspond to bits in the

accept ance filters . Any bit in the mask that is set to a ‘1’

will cause the corresponding CAN ID bit to be

comp ared agains t the associ ated filter bit. Any bit in the

mask tha t is set to a ‘0’ i s no t c om p a r ed an d effectively

sets the associated CAN ID bit to ‘d on’t care ’.

2.7.1 MASKS AND STANDARD/

EXTENDED IDS

To insure proper operation of the information request

and input mess age s, som e m as k bi t s (as c onfigured in

the mask registers) may be ignored as explained:

Message with a standard ID - the three least

significant bits of a standard identifier

(RXMSIDL.SID2:SID0) are ‘don’t care’ for the mask

registers and effecti v ely become ‘0’.

Message with an extended ID - the three least

significant bits of the standard identifier

(RXMSIDL.SID2:SID0) are configurable and the three

least significant bits of the extended identifier

(RXMEID0.EID2:EID0) are always ‘don’t cares’ and

ef fe cti ve ly bec om es ‘0’.

2.8 Acceptance Filters

There are two separate acceptance filters defined for

the MCP2502X/5X: RXF0 and RXF1. RXF0 is used for

Information Request messages and RXF1 is used for

input messages (see T able 4-2 and Table 4-3). Each bit

in the filters corresponds to a bit in the CAN ID. Every

bit in the CAN ID, for whi ch the corr espon ding M ask bit

is set, must match the associated filter bit in order for

the message to be accepted. Messages that fail to

meet the mask/fIlter criteria are ignored.

Note: The EXIDE bit in the Mask register

(RXMSIDL) can be used to mask the IDE

bit in the corresponding Receive buffer

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3

bit 7 bit 0

bit 7-0 SID10:SID3: Standard Identifier bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x

SID2 SID1 SID0 — EXIDE —EID17EID16

bit 7 bit 0

bit 7-5 SID2:SID0: Standard Identifier bits

bit 4 Unimplemented: Read as '0’

bit 3 EXIDE: Extended Identifier Enable bit

1 = Message will transmit extended identifier

0 = Message will transmit standard identifier

bit 2 Unimplemented: Read as '0’

bit 1-0 EID17:EID16: Extended Identifier bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8

bit 7 bit 0

bit 7-0 EID15:EID8: Extended Identifier bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0

bit 7 bit 0

bit 7-0 EID7:EID0: Extended Identifier bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3*

bit 7 bit 0

bit 7-0 SID10:SID3: Standard Identifier bits

* If OPTREG2.MTYPE = 1, then SID3 is forced to zero.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x

SID2 SID1 SID0 — EXIDE —EID17EID16

bit 7 bit 0

bit 7-5 SID2:SID0: Standard Identifier bits

Standard mess age s, bits = b’000’

Extended messages, bits = SID2:SID0

bit 4 Unimplemented: Read as '0’

bit 3 EXIDE: Extended Identifier Enable bit

1 = Apply filter to RXFnSIDL.EXIDE (filter applies to standard or extended message frames

depending on filter bit)

0 = Do not apply filter to RXFnSIDL.EXIDE (filter will be applied to both st andard and extended

message frames)

bit 2 Unimplemented: Read as '0’

bit 1-0 EID17:EID16: Extended Identifier bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8

bit 7 bit 0

bit 7-0 EID15:EID8: Extended Identifier bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0

bit 7 bit 0

bit 7-3 EID7:EID3: Extended Identifier bits

bit 2-0 EID2:EID0: Extended Identifier bits (always reads as ‘0’)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3*

bit 7 bit 0

bit 7-0 SID10:SID3: Standard Identifier bits

* If OPTREG2.MTYPE = 1, then SID3 = X

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x

SID2 SID1 SID0 — EXIDE —EID17EID16

bit 7 bit 0

bit 7-5 SID2:SID0: Standard Identifier bits

1 = When EXIDE = 1, SID2:SID0 = b’xxx’

0 = When EXIDE = 0, SID2:SID0 = as configured

bit 4 Unimplemented: Read as ‘0’

bit 3 EXIDE: Extended Identifier Enable bit

1 = Filter will apply to extended identifier

0 = Filter will apply to standard identifier

bit 2 Unimplemented: Read as ‘0’

bit 1-0 EID17:EID16: Extended Identifier bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8

bit 7 bit 0

bit 7-0 EID15:EID8: Extended Identifier Bit

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0

bit 7 bit 0

bit 7-0 EID7:EID0: Extended Identifier Bit (always = b’xxx’)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

ESCF RBO TXBO TXEP RXEP TXWAR RXWAR EWARN

bit 7 bit 0

bit 7 ESCF: Error State Change (for sending Error state message)

1 = An error state change occurred

0 = No error state change

bit 6 RBO: Receive Buffer Overflow

1 = Overflow occurred

0 = No overflow occurred

bit 5 TXBO: Transmitter in Bus Off Error State bit

1 = TEC reaches 256

0 = Indicates a successful bus recovery sequence

bit 4 TXEP: Transmitter in Error Passive State bit

1 = TEC is equal to or greater than 128

0 = TEC is less than 128

bit 3 RXEP: Receiver in Error Passive State bit

1 = REC is equal to or greater than 128

0 = REC is less than 128

bit 2 TXWAR: Transmitter in Error Warning State bit

1 = TEC is equal to or greater than 96

0 = TEC is less than 96

bit 1 RXWAR: Receiver in Error Warning State bit

1 = REC is equal to or greater than 96

0 = REC is less than 96

bit 0 EWARN; Either th e Recei ve Error c ounter o r T rans mit erro r count er has re ached or exce eded

96 errors

1 = TEC or REC is equal to or greater than 96 (TXWAR or RXWAR = 1)

0 = Both REC and TEC are less than 96

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

NOTES:

MCP2502X/5X

3.0 USER REGISTERS

3.1 Description

The MCP2502X/5X allows the user to pre-program

registers pertaining to CAN module and device

configuration into non-volatile EPROM memory. In this

way, the device is initialized to a default state after

power-up. The user registers are transferred to SRAM

during the power-up sequence and many of the

the device establishes a connection with the bus.

Additionally, there are 16 user-defined registers that

can be used to store information about the part (e.g.,

serial number, node identifier, etc.). The registers are

summa riz ed in Tab le 3-1.

Note 1: When transferred to RAM, the register

addresses are offset by 1Ch. Accessing

individual registers using the “Write

requires use of the offset address. Also,

see Table 3-2 for information on

accessible registers not contained in user

EPROM.

2: Do not address locations outside of the

user memory map or unexpected results

may occur.

TABLE 3-1: USER MEMORY MAP

Address Name Description Address Name Description

00h IOINTEN Enable inputs for Transmit-On-Change

feature

1Bh RXF0EID0 Acceptance Filter 0, Extended ID

LSB

01h IOINTPO Defines polarity for I/O or greater than/

less than operator for A/D Transmit-On-

Change inputs

1Ch RXF1SIDH Acceptance Filter 1, Standard ID

MSB

02h GPLAT General Purpose I/O (GPIO) Register 1Dh RXF1SI DL Acceptance Filter 1, Standard ID

LSB, Extended ID USB, and

Extended ID enable

03h 0xFF Reserved 1Eh RXF1EID8 Acceptance Filter 1, Extended ID

MSB

04h OPTREG1 Configuration options, including GPIO

pull-up enable, clockout enable and

prescaler

1Fh RXF1EID0 Acceptance Filter 1, Extended ID

LSB

05h T1CON PWM1 Timer Control Register; contains

enable bit, clock prescale and DC LSBs

20h TXID0SIDH Transmit Buffer 0, Standard ID MSB

06h T2CON PWM2 Timer Control Register; contains

enable bits, clock prescale and DC LSBs

21h TXID0SIDL Transmit Buff er 0, S t andard ID LSB,

Extended ID USB, and Extended ID

enable

07h PR1 PWM1 Period Register 22h TXID0EID8 Transmit Buf fer 0, Extended I D MSB

08h PR2 PWM2 Period Register 23h TXID0EID0 Transmit Buffer 0, Extended ID LSB

09h PWM1DCH PWM1 Duty Cycle (DC) MSBs 24h TXID1SIDH Transmit Buffer 1, Standard ID MSB

0Ah PWM2DCH PWM2 Duty Cycle (DC) MSBs 25h TXID1SIDL Transmit Buff er 1, S t andard ID LSB,

Extended ID USB, and Extended ID

enable

0Bh CNF1 3CAN module register configures

synchronization jump width and baud rate

prescaler

26h TXID1EID8 Transmit Buf fer 1, Extended I D MSB

0Ch CNF2 3CAN module register configures

propagation segment, phase segment 1,

and determines number of sample points

27h TXID1EID0 Transmit Buffer 1, Extended ID LSB

0Dh CNF3 3CAN module register configures phase

buffer segment 2, Sleep mode

28h TXID2SIDH Transmit Buffer 2, Standard ID MSB

Note 1: GPDDR is mapped to 1Fh is SRAM and not offset by 1Ch.

2: User memory (35h-44h) is not transferred to RAM on power-up and can only be accessed via “Read User Mem”

commands.

3: Cannot be modified from initial programmed values.

4: Unimplemented on MCP2502X devices and read 0x00 (exception, ADCON1 = 0x0F).

MCP2502X/5X

0Eh ADCON04A/D Control Register; contains enable,

conversion rate, channel select bits

29h TXID2SIDL Transmit Buff er 2, S t andard ID LSB,

Extended ID USB, and Extended ID

enable

0Fh ADCON14A/D Control Register; contains voltage

reference source, conversion rate and

A/D input enable bits

2Ah TXID2EID8 Transmit Buf fer 2, Extended ID MSB

10h STCON S cheduled Transmission Control Register 2Bh TXID2EID0 Transmit Buffer 2, Extended ID LSB

11h OPTREG2 Configurat ion options, including Sleep

mode, RTR message and error recovery

enables

2Ch ADCMP3H4Analog Channel 3 Compare Value

MSB

12h — Reserved 2Dh ADCMP3L4Analog Channel 3 Compare Value

LSb’s

13h — Reserved 2Eh ADCMP2H4Analog Channel 2 Compare Value

MSB

14h RXMSIDH Acceptance Filter Mask, Standard ID MSB 2Fh ADCMP2L4Analog Channel 2 Compare Valu e

LSb’s

15h RXMSIDL Acceptance Filter Mask, Standard ID LSB

and Extended ID USB

30h ADCMP1H4Analog Channel 1 Compare Value

MSB

16h RXMEID 8 Acceptance Filter Mask, Extended ID

MSB

31h ADCMP1L4Analog Channel 1 Compare Valu e

LSb’s

17h RXMEID 0 Acceptance Filter Mask, Extended ID LSB 32h ADCMP0H4Analog Channel 0 Compare Value

MSB

18h RXF0SIDH Acceptance Filter 0, S tandard ID MSB 33h ADCMP0L4Analog Channel 0 Compare Value

LSb’s

19h RXF0SIDL Acceptance Filter 0, Standard ID LSB,

Extended ID USB, and Extended ID

enable

34h GPDDR1General Purpose I/O Data Direction

1Ah RXF0EID8 Acceptance Filter 0, Extended ID MSB 35-44h USER[0:F]2User Defined Bytes (0-15)

TABLE 3-1: USER MEMORY MAP (CONTINUED)

Address Name Description Address Name Description

Note 1: GPDDR is mapped to 1Fh is SRAM and not offset by 1Ch.

2: User memory (35h-44h) is not transferred to RAM on power-up and can only be accessed via “Read User Mem”

commands.

3: Cannot be modified from initial programmed values.

4: Unimplemented on MCP2502X devices and read 0x00 (exception, ADCON1 = 0x0F).

TABLE 3-2: ACCESSIBLE RAM REGISTERS NOT IN THE EPROM MAP

Addr* Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Va lue o n

POR Value on

RST

1Fh** GPDDR — DDR6 DDR4 DDR4 DDR3 DDR2 DDR1 DDR0 -111 1111 -111 1111

18h EFLG ESCF RBO TXEP TXEP RXEP TXWAR RXWAR EWARN 0000 0000 0000 0000

19h TEC Transmit Error Counters 0000 0000 0000 0000

1Ah REC Receive Error Counters 0000 0000 0000 0000

50h ADRES3H AN3.9 AN3.8 AN3.6 AN3.6 AN3.5 AN3.4 AN3.3 AN3.2 xxxx xxxx uuuu uuuu

51h ADRES3L AN3.1 AN3.0 — — — — — — xx-- ---- uu-- ----

52h ADRES2H AN2.9 AN2.8 AN2.6 AN2.6 AN2.5 AN2.4 AN2.3 AN2.2 xxxx xxxx uuuu uuuu

53h ADRES2L AN2.1 AN2.0 — — — — — — xx-- ---- uu-- ----

54h ADRES1H AN1.9 AN1.8 AN1.6 AN1.6 AN1.5 AN1.4 AN1.3 AN1.2 xxxx xxxx uuuu uuuu

55h ADRES1L AN1.1 AN1.0 — — — — — — xx-- ---- uu-- ----

56h ADRES0H AN0.9 AN0.8 AN0.6 AN0.6 AN0.5 AN0.4 AN0.3 AN0.2 xxxx xxxx uuuu uuuu

57h ADRES0L AN0.1 AN0.0 — — — — — — xx-- ---- uu-- ----

* These addresses are used when using the “Write Register” or “Read Register” command

** The GPDDR register is not offset to RAM the same as the other registers in the EPROM

MCP2502X/5X

4.0 DEVICE OPERATION

4.1 Power-Up Sequence

The following sections describe the events/actions of

the MCP2502X/5X during normal power-up and

operation.

4.1.1 POWER-ON RESET

The MCP2502X/5X goes through a se quence of event s

at power-on reset (POR) in order to load the

programmed configuration and insure that errors are

not introduced on the bus. During this time, the device

is prevented from generating a low condition on the

TXCAN pin. The TXCAN pin must remain high from

power-on until the device goes on bus.

Operational Mode at Power-On

The MCP2 502 X/5X in iti all y po we rs up in Confi guration

mode. While in this mode, the MCP2502X/5X will be

prevented from sending or receiving messages via the

CAN interface. The ADC and PWM peripherals are

disabled while in this mode.

Self-Configuration

Once th e MCP2 502X/5 X is ou t of res et, it will pe rform

a self-configuration. This is accomplished by

transferring the contents of the EPROM array to the

corresponding locations within the SRAM array. In

additio n, the check sum of the da ta written to SRAM will

be compared to a pre-programmed value as a test of

valid data.

Going On Bus

Once the self-configuration cycle has successfully

completed, the MCP2502X/5X switches to Listen-only

mode. It will rema in in this mode until an error-free C AN

message is detected. This is done to ensure that the

device is at the correct bus rate for the system.

Once the device detects an error-free message, it wait s

for CAN bus idle before switching t o Normal mode. This

prevents it from going on bus in the middle of another

node’s transmission and generating an error frame.

Alternately, the MCP2505X may directly enter Normal

mode (without first entering Listen-only Mode) after

completing its self-configuration. This is configured by

the user via a control bit (OPTREG2.PUNRM).

Once the MCP2502X/5X enters Normal mode, it is

ready to send/receiv e messages vi a the CAN inter face.

At this point the ADC and PWM peripherals are

operational, if enabled.

Scheduled Transmissions

Once the MCP2502X/5X has gone on bus it will

transmit the On Bus message once, regardless of

whether enabled or not. This message notifies the

network o f the M CP2502X/5X’ s p res enc e. Th e On Bus

message will (if enabled STCON.STEN) repeat at a

frequency determined by the STCON register

(Register 4-1).

This message can also be configured to send the

“Read A/D Register” data bytes along with the

predefined identifier in TXID2 by setting

STCON.STMS = 1.

4.2 Message Functions

The MCP2502X/5X uses the global mask (RXMASK),

two filters (RXF0 and RXF1) and two receive buffers

(RB0 and RB1) to determine if a received message

should be acted upon. There are 16 functions that can

be per formed by the M CP2502X/5X bas ed on receive d

messages (see Table 4-1).These functions allow the

device to not only be accessed for Information

Request/Input/Output operations, but also to be

reconfigured via the CAN bus, if necessary.

4.3 Message Types

There are three types of messages that are used to

implement the functions of Table 4-1.

1. Information Request Messages (IRM)

- Received by the MCP2502X/5X.

2. Output Messages - Transmitted from the

MCP2502X/5X as a response to IRMs.

3. Input Messages - Received by the MCP2502X/

5X and used to modify registers.

Note: The first On Bus message sent after

power-up will NOT send the “Read A/D

STCON.STMS value.

Note: If the M CP250 2X/5X ente rs SLEEP mod e,

the scheduled transmissions will cease

until the device wakes up again. This

implie s tha t SLEEP mode ha s pri orit y ov er

scheduled transmissions.

Note: Information Request Messages (IRMs)

and Input messages are both input

messages to th e MCP25 02X/5X. IRMs are

received into receive buffer 0 and input

messages are received into receive buffer

1. This must be taken into account while

configuring the acceptance filters.

MCP2502X/5X

4.3.1 INFORMATION REQUEST

MESSAGES

Information Request Messages (IRM) are messages

that the MCP2502X/5X receives into Receive Buffer 0

(matche s Filte r 0) and t hen res ponds to b y trans mitting

a message (output m essage) c ont aining the reque sted

data.

IRMs can b e implemente d as either a Rem ote T ransfer

Request (RTR) or a Data Frame message by

configuring the MTYPE bit in the OPTREG2 register.

TABLE 4-1: MESSAGE FUNCTION

4.3.1.1 RTR Message Type

When RTR message types are selected

(OPTREG2.MTYPE) and a node in the system wants

information from the MCP2502X/5X, it has to send a

remote frame on the bus. The identifier for the remote

frame must be such that it will be accepted through the

MCP2502X/5 X’s mask/filter process (using RXF0). The

RTR message type (remote frames) is the default

configuration (MTYPE bit = 0).

Information Request “RTR” messages must not only

meet the RXMASK/RXF0 criteria but must also have

the RTR bit of the CAN ID set (since the filter registers

do not co ntain an exp licit RTR bit). If a message p asses

the mask/filter process and the RTR bit is a ‘0’, that

message will be ignored.

Once t he MCP2 502X/5X has re ceive d a re mote f rame,

it will determine the function to be performed based

upon the three LSb’s (RXB0SIDL.SID2:SID0 for

standard messages and RXB0EID0.EID2:EID0 for

extended messages) of the received remote frame.

Additionally, a predefined Data Length Code (DLC)

must be sent to signify the number of data bytes that

the MCP2502X/5X must return in it’s output message

(see Table 4-2 and Table 4-3).

4.3.1.2 Data Frame Mess age Ty pe

When a non-RTR (or data frame) message type is

selected and a node in the system wants information

from the MCP2502X/5X, it sends an Information

Request in the form of a data frame. The identifier for

this request must be such that it will be accepted

through the MCP2502X/5X’ s mask/filte r process (using

RXF0).

Informati on reques t message s in the dat a f rame format

must not only meet the RXMASK/RXF0 criteria, but

must also have the RTR bit of the CAN ID cleared

(since the filter registe rs do not con t ain an expl icit R TR

bit). If a message passes the mask/filter process and

the RTR bit is a ‘1’, that message will be ignored.

Once the MCP2502X/5X has received a data frame

information request, it will determine the function to be

performed based upon the three LSb’s

(RXB0SIDL.SID2:SID0 for standard messages and

RXB0EID0.EID2:EID0 for extended messages) of the

received data frame. Also, Bit 3 of the received

message ID must be set to a ‘1’.

In addition, the data length code (DLC) must be set to

a zero. Refer to Table 4-2 and Table 4-3 for more

information.

Regardless of the message format, all messages

except the Read Register message can use either

standard or extended identifiers. The Read Register

messa ge has one addition al requirem ent; it mu st be an

extended identifier. This is discussed in more detail in

Table 4-1 and Table 4-3 for more information.

Name Description

Read A/D

Registers T ransmits a single message containing

the current state of the analog and I/O

registers, including the configuration

Read Control

Registers T ransmits several control registers not

included in other messages

Read Configura-

tion Registers Transmits the contents of many of the

configuration registers

Read CAN

error states Transmits the error flag register and

the error counts

Read PWM

Configuration T ransmits the registers associated with

the PWM modules

Read User

Registers 1 Transmits the values in bytes 0 - 7 of

the user memory

Read User

Registers 2 Transmits the values in bytes 8 -15 of

the user memory

Read Register*Transmits a single byte containing the

value in an addressed user memory

Write Register Uses a mask to write a value to an

addressed register

Write TX Message

ID0 (T XI D 0) Writes the identifiers to a specified

value

Write TX Message

ID1 (T XI D 1) Writes the identifiers to a specified

value

Write TX Message

ID2 (T XI D 2) Writes the identifiers to a specified

value

Write I/O

Configuration

Registers

Writes specified values to the three

IOCON registers

Write RX Mask Changes the receive mask to the

specified value

Write RX Filter0 Changes the specified filter to the

specified value

Write RX Filter1 Changes the specified filter to the

specified value

* The Read Register command is available when using

extended message format only. Not available with

standard message format.

MCP2502X/5X

4.3.2 OUTPUT MESSAGES

The data frame sent in response to the information

request mess age is defin ed as an output mes sage.

If the dat a fame is in respo nse to a remote frame, it wil l

have the same identifier (standard or extended) and

cont ain the same n umber of dat a bytes spec ified by the

DLC of the remote frame (per the CAN 2.0B

specification).

If the output message is in response to a data frame,

the lower-three LSb’s of the identifier (standard or

extende d) must be the same as the rec eived me ssage,

as well as the upper-seven MSb’s in the case of a

stan dard identifie r , or the upper 2 5 MSb’s in the ca se of

an extended identifier. Bit 3 of a standard or extended

identifier of the output message will differ from the

receive d informat ion requ est message in that t he value

equals ‘1’ for an IRM and equals ‘0’ for the resulting

output message.

Output messages contain the requested data (in the

data field). Example: The information request

messa ge Read CAN erro r is a remote tran smit req uest

received by the MCP2502X/5X with a DLC of 3. The

responding output message will return a data frame

that contains the same identifier (standard or extended)

as the receive messag e. The accompany ing data bytes

will conta in the v alues o f the pred efined GP IO registe rs

and related control/status registers, as shown in

Table 4-2 and 4-3.

4.3.3 INPUT MESSAGES

Input messages are received into receive buffer 1 and

are used to change the values of the pre-defined

groups of registers. There is also an input message

that can change a single register’s contents. The

primary purpose of input messages are to reconfigure

MCP2502X/5X parameters (if needed) while in an

operating CAN system and are, therefore, optional in

system implementation. These messages are in the

form of standard (or extended) data frames (per the

CAN 2.0B specification) that have identifiers which

pass the MCP2502X/5X’s mask/filter process (using

RXF1). After passing the mask and filter, the lower-

three bits of the standard identifier

(RXF1SIDL.SID2:SID0) will indicate which register(s)

are to be written. The values for the register(s) are

contained in the data byte registers as defined in

Table 4-2.

4.4 Dynamic Message Handling

The design insures that transmit and receive messages

are handled properly for variable bus-loading

conditi ons a nd diffe r en t tra ns mi t/receive c om bin ati ons .

4.4.1 MESSAGE ACCEPTANCE/

REJECTION

Messages received that meet the Mask/RXFn criteria

are then compared to the requirements for input

messages or IRMs, as determined by the filter used to

accept the message. If the message meets the

requirements of one of the associated input or

information request m essag es, th e approp riate acti ons

for that message function are taken.

4.4.2 RECEIVING MULTIPLE MESSAGES

The MCP2502X/5X can only receive and process one

message at a time. While the MCP2502X/5X should

have ample time to process any received message

before another is completely received, a second

message received before the first message is finished

processing will be lost.

However , the MCP25 02X/5X has the abi lity to notify th e

network if a message is lost. TXID1 can be configured

to transmit a message if a receive overflow occurs

(OPTREG2.CAEN = 0).

Note: If the DLC of the incoming remote frame

differs from the message definitions

summarized in Table 4-2 and Table 4-3, the

resultin g outp ut mess age will limit it sel f to the

erroneous DLC that was received (to

maintain compliance with the Bosch CAN

specification). The output message will

concatenate the number of data bytes for an

erroneous DLC that is less than the defined

number. For an erroneous DLC that is

greater than the defined number, the

MCP2502X/5X will extend the number of

data bytes, with the data value of the last

defined data byte being repeated in the extra

bytes in the data field.

Note: If using more than one controlling node, the

MCP2502X/5X must be set up to accept

input messages with different identifiers in

order to a vo id pos s ibl e m es sa ge co lli sions i n

the DLC or data bytes if transmitted at the

same time.

Note 1: IRMs can theoretically be sent by more

than one controlling node because the

message is a predefined constant and

destructive collisions will not occur.

2: The number of data bytes in an input

messa ge must match the DLC n umber as

defined in Table 4-2 and Table 4-3. If the

user specifies and transmits an input

message with a DLC that is less than the

required number of data bytes, the

MCP25020 will operate on co rrupted data

for the bytes that it did not receive and

unknown results will occur.

MCP2502X/5X

4.4.3 TRANSMIT MESSAGE PRIORITY

There is a priority for all transmit messages, including

TXIDn and all “Output” messages.

The transmit message priority is as follows:

1. Output messages have the highest priority.

Prioritization of the individual output message

types is determined by the three bits that

determine message type, with the lowest value

having the highe st priori ty (e.g., Read A/D Reg s

is a higher priority than Read Control Regs).

2. TXID2 (T ransmit auto-converted messages) has

the second-highest priority.

3. TXID1 (Command acknowledge) has the third-

highest priority.

4. TXID0 (On Bus message) has the lowest

priority.

In the event two or more messages are pending

transmission, transmit-message-prioritization will occur

and the highest message type will be sent first.

Messages that are currently transmitting will not be

prioritized.

MCP2502X/5X

TABLE 4-2: COMMAND MESSAGES (STANDARD IDENTIFIER)

Information Request Messages (to MCP2502X/5X)

Standard ID Data Bytes

09876543210 R

EDLC

Read A/D Regs xxxxxxx* 0 0 0 1* 0 1000 8* n/a n/a n/a n/a n/a n/a n/a n/a

Read Control Regs xxxxxxx* 0 0 1 1* 0 0111 7* n/a n/a n/a n/a n/a n/a n/a n/a

Read Config Regs xxxxxxx* 0 1 0 1* 0 0101 5* n/a n/a n/a n/a n/a n/a n/a n/a

Read CAN Error xxxxxxx* 0 1 1 1* 0 0011 3* n/a n/a n/a n/a n/a n/a n/a n/a

Read PWM Config xxxxxxx* 1 0 0 1* 0 0110 6* n/a n/a n/a n/a n/a n/a n/a n/a

Read User Mem (bank1) xxxxxxx* 1 0 1 1* 0 1000 8* n/a n/a n/a n/a n/a n/a n/a n/a

Read User Mem (bank 2) xxxxxxx* 1 1 0 1* 0 1000 8* n/a n/a n/a n/a n/a n/a n/a n/a

Output Messages (from MCP 2502X/ 5X)

Standard ID Data Bytes

09876543210R

EDLC

Read A/D Regs x x x x x x x * 0 0 0 001 0 0 0 8 IOINTFL GPIO AN0H AN1H AN10L AN2H AN3H AN32L

Read Control Regs x x x x x x x * 0 0 1 000 1 1 1 7 ADCON0 ADCON1 OPTREG OPTREG STCON IOINTEN IOINTPO n/a

Read Config Regs x x x x x x x * 0 1 0 000 1 0 1 5 DDR GPIO CNF1 CNF2 CNF3 n/a n/a n/a

Read CAN Error x x x x x x x * 0 1 1 000 0 1 1 3EFLG TEC REC n/a n/a n/a n/a n/a

Read PWM Config x x x x x x x * 1 0 0 000 1 1 0 6 PR1 PR2 T1CON T2CON PWM1DC PWM2DC n/a n/a

Read User Mem (bank1) x x x x x x x * 1 0 1 001 0 0 0 8 USERID0 USERID1 USERID2 USERID3 USERID4 USERID5 USERID6 USERID7

Read User Mem (bank 2) x x x x x x x * 1 1 0 001 0 0 0 8 USERID8 USERID9 USERID1 USERID1 USERID1 USERID1 USERID1 USERID1

Input Messages** (to MCP2502X /5X )

Standard ID Data Bytes

09876543210R

EDLC

Write Register x x x x x x x x 000000 0 1 1 3 addr mask value n/a n/a n/a n/a n/a

Write TX Message ID 0 x x x x x x x x 001000 1 0 0 4 TX0SIDH TX0SIDL TX0EID8 TX0EID0 n/a n/a n/a n/a

Write TX Message ID 1 x x x x x x x x 010000 1 0 0 4 TX1SIDH TX1SIDL TX1EID8 TX1EID0 n/a n/a n/a n/a

Write TX Message ID 2 x x x x x x x x 011000 1 0 0 4 TX2SIDH TX2SIDL TX2EID8 TX2EID0 n/a n/a n/a n/a

Write I/O Configuration x x x x x x x x 100000 1 0 1 5 IOINTEN IOINTPO DDR OPTREG ADCON1 n/a n/a n/a

Write RX Mask xxxxxxxx101000 1 0 0 4 RXMSIDH RXMSIDL RXMEID8 RXMEID0 n/a n/a n/a n/a

Write RX Filter0 x x x x x x x x 110000 1 0 0 4 RXF0SID RXF0SID RXF0EID RXF0EID n/a n/a n/a n/a

Write RX Filter1 x x x x x x x x 111000 1 0 0 4 RXF1SID RXF1SID RXF1EID RXF1EID n/a n/a n/a n/a

* If using non-RTR messages for information request messages (IRM), the RTR bit = 0, DLC bit field = 0, and bit 3 of the IRM ID = 1. Also, bit 3 of the output message ID = 0.

If using RTR messages for IRMs, the RTR bit = 1, DLC bit field = number of bytes in corresponding output message, and bit three of the IRM ID = x (don’t care), also, bit 3 of the

output message = x (don’t care).

** User-defined IRM IDs must be different from input message IDs to avoid message contention between the corresponding output message and the input message.

MCP2502X/5X

TABLE 4-3: COMMAND MESSAGES (EXTENDED IDENTIFIER)

Information Request Messages (to MCP2502X/ 5X)

Standard ID Extended ID Data Bytes

09876543210R

DLC 1

6RXBEID8

(8 bits) RXBEID0

(8 bits)

Read A/D Regs x x xxxxxxxxx111 0 0 0 8* x x xxxx xxxx xxxx *000 n/a n/a n/a n/a n/a n/a n/a n/a

Read Control Regs x x xxxxxxxxx110 1 1 1 7* x x xxxx xxxx xxxx *001 n/a n/a n/a n/a n/a n/a n/a n/a

Read Config Regs x x xxxxxxxxx110 1 0 1 5* x x xx xx xxxx xxxx *010 n/a n/a n/a n/a n/a n/a n/a n/a

Read CAN Error x x xxxxxxxxx110 0 1 1 3* x x xxxx xxxx xxxx *011 n/a n/a n/a n/a n/a n/a n/a n/a

Read PWM Config x x xxxxxxxxx110 1 1 0 6* x x xxxx xxxx xxxx *100 n/a n/a n/a n/a n/a n/a n/a n/a

Read User Mem x x xxxxxxxxx111 0 0 0 8* x x xxxx xxxx xxxx *101 n/a n/a n/a n/a n/a n/a n/a n/a

Read User Mem x x xxxxxxxxx111 0 0 0 8* x x xxxx xxxx xxxx *110 n/a n/a n/a n/a n/a n/a n/a n/a

Read Register x x xxxxxxxxx1 1 0 0 0 0 1* x x addr xxxx *111 n/a n/a n/a n/a n/a n/a n/a n/a

Output Messages (from MCP 2502X/5 X)

Standard ID Extended ID Data Bytes

09876543210R

DLC 1

6RXBEID8

(8 bits) RXBEID0

(8 bits)

Read A/D Regs x xxxxxxxxxx011000 8 x x xxxx xxx x xxxx *000 IOINTFL GPIO AN0H AN1H AN10L AN2H AN3H AN32L

Read Control Regs x xxxxxxxxxx010111 7 x x xxxx xxxx xxxx *001 ADCON0 ADCON1 OPTREG OPTREG STCON IOINTEN IOINTPO n/a

Read Config Regs x xxxxxxxxxx010101 5 x x xxxx xxxx xxxx *010 DDR GPIO CNF1 CNF2 CNF3 n/a n/a n/a

Read CAN Error x xxxxxxxxxx010011 3 x x xx xx xxxx xxxx *011 EF LG T EC REC n/a n/a n/a n/a n/a

Read PWM Config x xxxxxxxxxx010110 6 x x xxxx xxx x xxxx *100 PR1 PR2 T1CON T2CON PWM1D PWM2D n/a n/a

Read User Mem x xxxxxxxxxx011000 8 x x xx xx xxxx xxxx *101 USERID0 USERID1 USERID 2 USERID3 USERID4 USERID5 USERID6 USERID7

Read User Mem x xxxxxxxxxx011000 8 x x xx xx xxxx xxxx *110 USERID8 USERID9 USERID1 USERID1 USERID1 USERID1 USERID1 U SER ID1

Read Register x xxxxxxxxxx0 10000 1xx addr xxxx *111 value n/a n/a n/a n/a n/a n/a n/a

Input Messages (to MCP2502X /5X)

Standard ID Extended ID Data Bytes

09876543210R

DLC 1

6RXBEID8

(8 bits) RXBEID0

(8 bits)

Write Register xxxxxxxxxxx010011 3 x x xxxx xxxx xxxx x000 addr mask value n/a n/a n/a n/a n/a

Write TX Message x xxxxxxxxxx010100 4 x x xxxx xxx x xxxx x001 TX0SIDH TX0SIDL TX0EID8 TX0EID0 n/a n/a n/a n/a

Write TX Message x xxxxxxxxxx010100 4 x x xxxx xxx x xxxx x010 TX1SIDH TX1SIDL TX1EID8 TX1EID0 n/a n/a n/a n/a

Write TX Message x xxxxxxxxxx010100 4 x x xxxx xxx x xxxx x011 TX2SID H TX2SIDL TX2EID8 TX2EID0 n/a n/a n/a n/a

Write I/O Configura- xxxxxxxxxxx010101 5 x x xxxx xxxx xxxx x100 IOINTEN IOINTPO DDR OPTREG ADCON1 n/a n/a n/a

Write RX Mask xxxxxxxxxxx010100 4 x x xxxx xxxx xxxx x101 RXM- RXMSIDL RXMEID8 RXMEID0 n/a n/a n/a n/a

Write RX Filter0 x xxxxxxxxxx010100 4 x x xxxx xxx x xxxx x110 RXF 0 SI D RXF 0SI D R X F0EID R XF 0EI D n/a n/a n/a n/a

Write RX Filter1 x xxxxxxxxxx010100 4 x x xxxx xxx x xxxx x111 RXF1SID RXF1SID RXF1EID RXF1EID n/a n/a n/a n/a

* If using non-RTR messages for information request messages (IRM), the RTR bit = 0, DLC bit field = 0, and bit 3 of the IRM ID = 1. Also, bit 3 of the output message ID = 0.

If using RTR messages for IRMs, the RTR bit = 1, DLC bit field = number of bytes in corresponding output message, and bit three of the IRM ID = x (don’t care), also, bit 3 of the

output message = x (don’t care).

** User-defined IRM IDs must be different from input message IDs to avoid message contention between the corresponding output message and the input message.

MCP2502X/5X

4.5 Automatic Transmission

The MCP2502X/5X can automatically initiate four

different message types to indicate the following

situations:

• Edge detected on a digital input (TXID2).

• Threshold exceeded on an analog input (TXID2).

• Error condition (Read Error output message).

• Scheduled transmissions (TXID0).

The buffers have an implied transmit priority, where

buffer 2 is the highest and buffer 0 is the lowest.

Therefore, multiple message buffers can be requested

for transmission and each one will be sent in order of

priority.

4.5.1 DIGITAL INPUT EDGE DETECTION

Each GPIO pin configured as a digital input can be

individually configured to automatically transmit a

message when a defined edge occurs, as explained in

the GPIO module section. When transmitting this

message, the MCP2502X/5X uses TXID2. The DLC is

set to two and the first two bytes of the Read A/D

registers (IOINTFL and GPIO) are sent.

4.5.2 ANALOG INPUT THRESHOLD

DETECTION

Each GPIO pin that has been configured as an analog

input can be individually configured to automatically

transmit a message when a threshold is exceeded as

described in the Analog-to-Digital Converter Module

section. The MCP2502X/5X sends TXID2 when

transmitting this message. The DLC is set to eight and

the eight bytes of the ‘Read A/D Registers’ are sent.

4.5.2.1 Hysteresis Function

This fun ction is au tomatic and will ins ure that an an alog

value that is on the compare edge (i.e., toggling LSb)

does not fi ll the CAN bus wit h continuous A/D m essage

transmissions.

The hysteresis uses the two LSb’s of the compare

configurable by the user. They will be forced to either

b’00’ or b’11’, de pending on the com pare polari ty . If

configured for A/D result > compare register, the

automatic transmission will occur when the A/D value

is greater than or equal to b’nnnn nnnn 11’ and

reset when less than or equal to b’nnnn nnnn 00’.

The opposite conditions must occur if the compare

polarity is set for A/D result < compare register.

A hysteresis example:

• The user sets the upper-eight bits of the 10-bit

compare register (ADCMP0H). The lower-two bits

of the compare register are no t configurable by

the user and are forced to either b’11’ or b’00’

depending on the polarity of the compare

threshold (i.e., transmit is triggered above or

below the compare value via the IOINTPO

• The user sets the polarity of the compare

threshold (IOINTPO). In this example, the

threshold is set for triggering a message on an

A/D > c omp a r e re gis te r. The two L S b’s are forc ed

to b’11’.

• When the A/D conversion exceeds the compare

tran smission will occur once.

• In order for the automatic transmission to occur

again, the A/D value must first drop below the

compare register b’nnnn nnnn 00’ and then

back above the compare register

b’nnnn nnnn 11’.

FIGURE 4-1: HYSTERESIS

FUNCTION

4.5.3 ERROR CONDITION

The MCP2 502 X/5X ca n be c onf igu r ed to autom ati ca ll y

transmit a message whenever one or more of the

following error conditions occur:

• Receiver has entered error-warning state

• Receiver has entered error-passive state

• Transmitter has entered error-warning state

• Transmitter has entered error-passive state

• A Receive buffer h as ov erflowed

Note: The GPIO register that is sent with the

message (data byte 2) can be ignored if

there are no digital inputs enabled for

change-of-state, as it contains no useful

information for the Analog Input Threshold

Detect f unction.

LSbs = b’11’

Set to Trigger when A/D>Compare Register

LSbs = b’00’

LSbs = b’11’

LSbs = b’00’

Set to Trigger when A/D<Compare Register

A/D above compare,

Message sent A/D above compare,

Message sent

A/D below compare,

Reset

A/D below compare,

Message sent A/D below compare

Message sent

A/D above compare,

Reset

MCP2502X/5X

If the Error Condition message is enabled

(OPTREG2.TXONE = 1) and one of the above

conditions occur, the MCP2502X/5X sends TXID1

identifier with output message Read CAN Error States

data field (three data bytes).

4.5.4 SCH EDULED TRANSMIS SION S

The MCP2502X/5X has the capability of sending

scheduled transmissions (On Bus message), if

enabled.

The scheduled transmission control register (STCON)

enables and configures the occurrence of the

scheduled message. Setting the STEN bit in the

STCON register enables the scheduled message. The

STBF1:STBF0 and STM3:STM0 bits allow a scheduled

tran smissi on to be init iated f rom a m inimum o f 256 µ s

to a maximum of 16.8 seconds (using a 16 MHz FOSC)

and the following equation:

Message Type - The message sent for scheduled

transmissions consists of either TXID0 with zero data

bytes or TXID0 with eight data bytes containing the

Read A/D Regs message, depending on STMS bit in

the STCON register.

Note: The actual scheduled transmission

intervals may vary slightly due to the

internal event que of the control module.

Scheduled Transmission

= STBF1:STBF0(STM3:STM0)

R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

STEN STMS STBF1 STBF0 STM3 STM2 STM1 STM0

bit 7 bit 0

bit 7 STEN: Scheduled Transmission Enable bits

1 = Enabled

0 =Disabled

bit 6 STMS: Scheduled Transmission Message Select

1 = Sends Transmit ID 0 (TXID0) with the “Read A/D Regs” data (DLC = 8)

0 = Sends Transmit ID 0 (TXID0) with no data (DLC = 0)

bit 5-4 STBF1:STBF0: Base Transmission Frequency bits

00 = 4096TOSC

01 = 16•(4096TOSC)

10 = 256•(4096TOSC)

10 = 4096•(4096TOSC)

(e.g., STBF1:STBF0 => 00 => 256 µs for a 16 MHz FOSC)

bit 3-0 STM3:STM0: Scheduled Transmission Multiplier bits

0000 = 1

0001 = 2

1110 = 15

1111 = 16

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

TABLE 4-4: REGISTERS ASSOCIATED WITH THE CAN MODULE

Addr Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Va lue o n

POR Value on

RST

0Bh CNF1 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 xxxx xxxx uuuu uuuu

0Ch CNF2 BTLM-

ODE SAM PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEG1 PRSEG0 xxxx xxxx uuuu uuuu

0Dh CNF3 — WAKF — — — PHSE G22 PHSEG 21 PHSEG20 -x-- xxxx -u-- uuuu

10h STCON STEM STMS STBF1 STBF0 STM3 STM2 STM1 STM0 0xxx xxxx 0uuu uuuu

11h OPTREG2 CAEN ERRE TXONE SLPEN MTYPE PDEFEN PUSLP PUNRM 0000 0000 uuuu uuuu

14h RXMSIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu

15h RXMSIDL SID2 SID1 SID0 — — — EID17 EID16 xxx- --xx uuu- --uu

16h RXMEID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu

17h RXMEID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu

18h RXF0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu

19h RXF0SIDL SID2 SID1 SID0 — — — EID17 EID16 xxx- --xx uuu- --uu

1Ah RXF0EID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu

1Bh RXF0EID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu

1Ch RXF1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu

1Dh RXF1SIDL SID2 SID1 SID0 — — — EID17 EID16 xxx- --xx uuu- --uu

1Eh RXF1EID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu

1Fh RXF1EID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu

20h TXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu

21h TXB0SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx uuu- u-uu

22h TXB0EID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu

23h TXB0EID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu

24h TXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu

25h TXB1SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx uuu- u-uu

26h TXB1EID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu

27h TXB1EID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu

28h TXB2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx uuuu uuuu

29h TXB2SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx uuu- u-uu

2Ah TXB2EID8 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx uuuu uuuu

2Bh TXB2EID0 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx uuuu uuuu

MCP2502X/5X

NOTES:

MCP2502X/5X

5.0 GPIO MODULE

5.1 Description

The MCP2502X/5X has eight general-purpose input/

output pins (GP0 to GP7), collectively lab eled GPIO. All

GPIO port pins have TTL input levels and full CMOS

output driv ers, with the exceptio n of GP7, which is input

only. Pins GP6:GP0 can be individually configured as

input or output via the GPDDR register.

Each of the GPIO pins has a weak internal pull-up

resistor. A single control bit (OPTREG.GPPU) can turn

on/off all the pull-ups. The weak pull-up is automatically

turned off when the port pin is configured as an output.

The pull-ups are disabled during a Power-on Reset.

All pins are multiplexed with an alternate function,

including analog-to-digital conversion on up to four of

the GPIO pins, analog V REF inputs up to two pins, PWM

outputs up to two pins, clock-out function and external

reset. Th e operatio n of each pin is selecte d by clearing,

or setti ng, control bits in various cont rol registers . GPIO

pin functions are summarized in Table 5-1.

TABLE 5-1: GPIO FUNCTIONS

5.2 Digital Input Edge Detection

All GPIO pins have a digital input edge detection

feature that will automatically transmit a message when

an edge with the proper polarity occurs on any of the

digital inputs. Only pins configured as inputs and

enabled for this function via control register IOINTPO

will perform thi s operation.

Three control registers are associated with this

function. An enable pin for each GPIO pin resides in the

IOINTEN register. When a bit is set to a '1', the

corresponding GPIO pin is enabled to generate a

transmit-on-change message (TXID2) whe n an edge of

specified polarity occurs.

The digital edge detection function on a GPIO pin

configu r ed a s a digi tal inpu t is edg e trig gere d. A ris in g-

edge will generate a transmission if the corresponding

bit in the IOINTPO register is set. A falling-edge will

generate a transmission if the bit is cleared. When a

valid edge appears on the enabled GPIO pin, CAN

message TXID2 is initiated.

The edge-detection function on any given GPIO pin

(configured as a digital input) can wake up the

processor from SLEEP if the corresponding interrupt

enable bit in the IOINTEN register was set prior to

going into SLEEP mode. If a wake-up from SLEEP is

caused in this manner, the device will immediately

initiate a transmit message (TXID2).

Note: The G PDDR re gis ter c ont rols the d irec tio n

of the GPIO pins, even when they are

being used as analog inputs. The user

must ensure that the bits in the GPDDR

using them as analog inputs.

Name Bit

#Function

GP0/AN0 bit0 I/O or analog input

GP1/AN1 bit1 I/O or analog input

GP2/AN2/PWM2 bit2 I/O, analog input

or PWM out

GP3/AN3/PWM3 bit3 I/O, analog input

or PWM out

GP4/VREF- bit4 I/O or analog voltage

reference

GP5/VREF+ bit5 I/O or analog voltage

reference

GP6/CLKOUT bit6 I/O or Clock output

GP7/nRST/VPP bit7 Input, external reset input

or programming voltage

input

Note: Refer to Section 7.4 “A/D Threshold

Detection” for information regarding A/D

channels.

MCP2502X/5X

U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0 ’

bit 6-0 DDR6:DDR0: Data Direction Register* bits

1 = corresponding GPIO pin is configured as an input

0 = corresponding GPIO pin is configured as an output

* must bet set if corres pon din g anal og cha nn el is ena ble d (see ADCON1 )

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— GP6 GP5 GP4 GP3 GP2 GP1 GP0

bit 7 bit 0

bit 7 Unimplemented: Read as '0’

bit 6-0 GP6:GP0: GPIO Bits

1 = corresponding GPIO pin output latch is a ‘1’

0 = corresponding GPIO pin output latch is a ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GP7TXC GP6TXC GP5TXC GP4TXC GP3TXC GP2TXC GP1TXC GP0TXC

bit 7 bit 0

bit 7-0 GP7TXC:GP0TXC: Transmit-on-change Enable bits

1 = Enable Transmit-On-Change/Compare For Corresponding GPIO/AN Channel

0 = Disable Transmit-On-Change/Compare For Corresponding GPIO/AN Channel

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GP7POL GP6POL GP5POL GP4POL GP3POL GP2POL GP1POL GP0POL

bit 7 bit 0

bit 7-0 GP7POL:GP0POL: Transmit-on-change Polarity bits

1 = Digital Inputs: Low-to-High Transition On Corresponding GPIO Input Pin Generates a

transmit message

Analog Inputs: A/D result above compare value generates a transmit message

0 = Digital Inputs: High-to-Low Transition On Corresponding GPIO Input Generates transmit

message

Analog Inputs: A/D result below compare value generates a transmit message

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

GP7TXF GP6TXF GP5TXF GP4TXF GP3TXF GP2TXF GP1TXF GP0TXF

bit 7 bit 0

bit 7-0 GP7TXF:GP0TXF: Transmit-on-change Polarity bits

1 = Digital Inputs: A valid edge has occurred on the digital input

Analog Inputs: A/D result does exceed the compare threshold

0 = Digital Inputs: A valid edge has not occurred on the digital input

Analog Inputs: A/D result does not exceed the compare threshold

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-0 R/W-0 R/W-0

GPPU CLKEN CLKPS1 CLKPS0 — CMREQ AQT1 AQT0

bit 7 bit 0

bit 7 GPPU: W e ak pul l-u p enab led

1 = Weak pull-ups disabled

0 = Weak pull-ups enabled (GP7:GP0)

bit 6 CLKEN:

1 = Clock Out Function disabled

0 = Clock Out Function enabled

bit 5-4 CLKPS1:CLKPS0: CLKOUT Prescaler bits

00 = FOSC/1

01 = FOSC/2

10 = FOSC/4

11 = FOSC/8

bit 3 Reserved:

bit 2 CMREQ: Requests mode of operation (allows mode changes via the CAN bus)

1 = Request s L is ten -onl y mode

0 = Requests Normal mode *

* CMREQ m us t be cleared a s defa ul t to avoid de vic e ente ring L ist en-o nly m od e on first “Inpu t”

message.

bit 1-0 AQT1:AQT0: Analog Acquisition Time bits

00 = 64TOSC

01 = 2•(64TOSC)

10 = 4•(64TOSC)

11 = 8•(64TOSC)

(e.g., AQT1:AQT0 => 00 => 2.56 µs for a 25 MHz FOSC)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO MODULE

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CAEN ERREN TXONEN SLPEN MTYPE PDEFEN PUSLP PUNRM

bit 7 bit 0

bit 7 CAEN: Command Acknowledge Enable bit

1 = Enables the command acknowledge message (TXID1)

0 = Enables the receive overflow message (TXID1)

bit 6 ERREN: Error Recovery Enable bit

1 = MCP2502X/5X will recover into Listen-only mode from bus off

0 = MCP2502X/5X will recover into Normal mode from bus-off

bit 5 TXONEN: Transmit on Error Condition bit(REC or TEC)

1 = Enable, will send message if error counter(s) go high enough

0 = Disable, will NOT send message regardless of error counter values

bit 4 SLPEN: Low power SLEEP mode enable/disable

1 = Device will enter Sleep if bus is idle for at least 1408 bit times

0 = SLEEP mode is disabled

bit 3 MTYPE: Determines if information request messages use RTR or not

1 = RTR is NOT used for IRM (Data Frame)

0 = RTR is used for IRM (Remote Frame)

bit 2 PDEFEN: Enables PWM outputs to retur n to POR default values when CAN bu s communication

is lost

1 = Enables PWM output default values

0 = Disables PWM out put default values

bit 1 PUSLP: Allows device to enter SLEEP while in Listen-only mode during power-up sequence

1 = Enables SLEEP when in Listen-only mode during power-up sequence

0 = Disables SLEEP when in Listen-only mode during power-up sequence

bit 0 PUNRM: Enters Normal mode after co mp leti ng self-c onfigurati on duri ng pow e r-up se que nc e

1 = Enters “Normal” mode after completing self-configuration during power-up sequence

0 = Enables “Listen-only” mode after completing self-configuration during power-up sequence

and waits for an error-free message before switching to Normal mode

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Addr Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Value on

POR Value on

RST

Bank 0

34h GPDDR — DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 -111 1111 -111 1111

00h IOINTEN GP7TXC GP6TXC GP5TXC GP4TXC GP3TXC GP2TXC GP1TXC GP0TXC 0000 0000 0000 0000

01h IOINTPO GP7POL GP6POL GP5POL GP4POL GP3POL GP2POL GP1POL GP0POL 0000 0000 0000 0000

04h OPTREG1 GPPU CLKEN CLKPS1 CLKPS0 —CMREQ AQT1 AQT0 0000 ---- 0000 ----

Legend: x = unknown, U = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by module.

MCP2502X/5X

NOTES:

MCP2502X/5X

6.0 PWM MODULE

6.1 Description

There are tw o Pulse Width Modulation (PWM) m odules

(PWM1 and PWM2) that generate up to a 10-bit

resoluti on output signa l on G P2 and G P3, res pecti vely.

Each of these outputs can be separately enabled, with

each having its own associated timer, duty cycle and

period registers for controlling the PWM output shape.

Each PW M module co ntai ns a se t of mas ter/sl ave dut y

cycle registers, pro viding up to a 10 -bit resolutio n PWM

outp ut . F ig u re 6 -1 sh ows a s im pl if ie d b l oc k diag r a m of

the PWM module. A PWM output has a time base

(period) and a time that the output stays high (duty

cycle), as shown in Figure 6-2. The frequency of the

PWM is the inverse of the period (1/period).

At power-on, the PWM outputs are not enabled until

after the self-configuration sequence has been

completed (i.e., all SRAM registers have been loaded

with their d efault valu es) t o prev ent i nvali d sig nals from

occurring on the PWM outputs.

FIGURE 6-1: SIMPLI FIED BLOCK

DIAGRAM

The PWM outputs can be forced to their default POR

conditions if CAN bus communication is lost and is

enabled via OPTR EG2.PDEFEN. The system design er

must im plement a hand-shaking protocol, such that th e

MCP25 05X will rec eive a vali d messa ge into o ne of the

receive buffers before four successive scheduled

transmi ssions occu r . If a valid messa ge is not received,

the PWM outputs GP2 and GP3 will automatically

reconfig ure to t heir default conditions. This includ es the

PWM mod ul e i tself bei ng disable d a nd the GPIO b ein g

forced low, high or tri-state.

FIGURE 6-2: PWM OUTPUT

6.2 PWM Timer Modules

There are two 8-bit timers supporting the two PWM

outputs. Both timers have a prescaler only. The timers

are readable and writable and are cleared on any

device reset or when the timer is turned off.

The input clock (FOSC/4) has a prescale option of 1:1,

1:4 or 1:16, selected by control bits TnCKPS[1:0] in

appropriate timer).

Each timer module has an 8-bit period register, PRn.

PRn is a readable and writable register. The timer

module increments from 00h until it matches PRn and

then resets to 00h on the next increment cycle. The

PRn register is set when the device is reset.

Each timer can be shut off by clearing control bit

TMRnON (TnCON<7>).

6.2.1 TIMER MODULE PRESCALER

The pr escaler co unt ers are c lea red when a w rit e to the

TnCON or TMRn register or any device reset (RST

reset or Power-on reset) occurs.

6.3 PWM Modules

Each PW M module con tai ns a se t of mast er/sla ve dut y

cycle registers, pro viding up to a 10-bit resolu tion PWM

outp ut . F i gu re 6 -2 sh ow s a s im pl i fie d bl oc k di a gra m o f

the PWM module.

6.3.1 PW M PE RIO D

The PWM period is specified by writing to the PRn

following formula:

When TMRn is equal to PRn, the following two events

occur on the next cycle:

•TMRn is cleared

• The PWM duty cycle is latched from PWMnDCH

into PWMnDBH

PWMnDCH

PWMnDBH

TMRn

Prn

Note

Comparator

DDR<Y>

GP<Y>

(PWMn)

Comparator

TnCON

(2 LSB)

Duty cycle

registers

Note 1: 8-bit timer is concatenated with 2-bit interna

Q clock or 2 bits of the prescaler to create

10-bit time base

TMRn = PRn

Period

Duty Cycle TMRn = PRn

TMRn=Duty Cycle

PWM period PRn

()1+[]*4TOSC* TM Rn prescale value()=

PWM frequency 1 PWM period()⁄=

MCP2502X/5X

6.3.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

PWMnDCH and TnCON registers. Up to 10-bit

resolution is available. The PWMnDCH contains the

eight M Sb’s, w hile the TnCO N register contain s the two

LSb’s. This 10-bit value is represented by

PWM1DCH:T1CON<1:0> for PWM Module 1 and

PWM2DCH:T2CON<1:0> for PWM Module 2.

The following equation is used to calculate the PMW

duty cycle:

PWMnDCH can be written to at any time, but the duty

cycle value is not latched into PWMnDBH until after a

match b etwee n PR n a nd TMRn oc curs (i.e., t he p erio d

is co mplete).

The PWMnDBH register and 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM

operation.

When the PWMnDBH and 2-bit latch match TMRn

concatenated with an internal 2-bit Q clock or 2 bits of

the TMRn prescaler, the PWM output pin is cleared.

Maximum PWM resolution (bits) for a given PWM

frequenc y is equ al to:

In order to achieve higher resolution, the PWM

frequency must be decreased. In order to achieve

higher PWM frequency, the resolution must be

decreased. Table 6-1 lists example PWM frequencies

and resolutions for FOSC = 20 MHz. TMRn prescaler

and PRn values are also shown.

TABLE 6-1: PWM FREQUENCIES AND RESOLUTIONS AT 20 MHZ

PWMDC PWMnDC()=*T

OSC*TMRn (prescale)

Note: If the PWM duty cycle value is longer than

the PWM period (PWM duty cycle

= 100%), the PWM output pin will not be

cleared.

log FOSC

()Fpwm()⁄()log 2()bits()⁄

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.30 kHz 208.30 kHz

Timer Prescaler (1, 4, 16) 1641111

PRn Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 5.5

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

DC1B9 DC1B8 DC1B7 DC1B6 DC1B5 DC1B4 DC1B3 DC1B2

bit 7 bit 0

bit 7-0 DC1B9:DC1B2: Most Significant PWM0 Duty Cycle bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

DC2B9 DC2B8 DC2B7 DC2B6 DC2B5 DC2B4 DC2B3 DC2B2

bit 7 bit 0

bit 7-0 DC2B9:DC2B2: Most Significant PWM2 Duty Cycle bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-x R/W-x

TMR1ON — T1CKPS1 T1CKPS0 —— DC1B1 DC1B0

bit 7 bit 0

bit 7 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Disables Timer1

bit 6 Unimplemented: Read as '0'

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Clock Prescale Sele ct bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

bit 3-2 Unimplemented: Read as '0'

bit 1-0 DC1B1:DC1B0: Least Significant PWM1 Duty Cycle bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-x R/W-x

TMR2ON — T2CKPS1 T2CKPS0 —— DC2B1 DC2B0

bit 7 bit 0

bit 7 TMR2ON: Timer2 On bit

1 = Enables Timer2

0 = Disables Timer2

bit 6 Unimplemented: Read as '0'

bit 5-4 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Sele ct bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

bit 3-2 Unimplemented: Read as '0'

bit 1-0 DC2B1:DC2B0: Least Significant PWM2 Duty Cycle bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

TABLE 6-2: REGISTERS ASSOCIATED WITH THE PWM MODULE

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

PR1B7 PR1B6 PR1B5 PR1B4 PR1B3 PR1B2 PR1B1 PR1B0

bit 7 bit 0

bit 7-0 PR1B7:PR1B0: PWM1 Period Register bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

PR2B7 PR2B6 PR2B5 PR2B4 PR2B3 PR2B2 PR2B1 PR2B0

bit 7 bit 0

bit 7-0 PR2B7:PR2B0: PWM2 Period Register bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Addr Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Va lue on

POR Value on

RST

34h GPDDR —DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 -111 1111 -111 1111

05h T1CON TMR1ON — T1CKPS1 T1CKPS0 —— DC1B1 DC1B0 0-00 --xx 0-00 --uu

06h T2CON TMR2ON — T2CKPS1 T2CKPS0 —— DC2B1 DC2B0 0-00 --xx 0-00 --uu

07h PR1 T imer 1 Module’s Period Register 1111 1111 1111 1111

08h PR2 T imer 2 Module’s Period Register 1111 1111 1111 1111

09h PWM1DCH DC1B9 DC1B8 DC1B7 DC1B6 DC1B5 DC1B4 DC1B3 DC1B2 xxxx xxxx uuuu uuuu

0Ah PWM2DCH DC2B9 DC2B8 DC2B7 DC2B6 DC2B5 DC2B4 DC2B3 DC2B2 xxxx xxxx uuuu uuuu

Legend: x = unknown, U = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by module.

MCP2502X/5X

7.0 ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

7.1 Description

The Analog-to-Digital (A/D) module is a four-channel,

10-b it succes sive appr oximati on type o f A/D. The A/ D

allows conversion of an analog input signal to a

corresponding 10-bit number. The four channels are

multiplexed on the GP[3:0] pins. The converter is

turned off/on via the ADCON0 register and each

channe l is indivi dually enabled vi a the ADCON1 control

select able as in ternal or externa l. Each chann el can be

set to one of two conversion modes:

1. Auto-conversion

2. Convert-on-request.

7.2 A/D Module Registers

The A/D module itself has several registers. The

registers are:

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

• Transmit-on-Change Register (IOINTEN)

• Compare an d Polarity Register (ADCMPnL)

• A/D Result Registers (ADRESnL, ADRESnH)

The ADCON0 register controls the operation of the

A/D mod ule, including auto-conv ersion rate and en able

bit. The ADCON 1 register enables the A/D fu nction on

port pins GP3:GP0, A/D conversion rate and selects

the voltage reference source. The IOINTEN register’s

four least significant bits enable/disable the transmit-

on-change function. The ADCMPnL.ADPOL bit sets

the polari ty (above or belo w threshold) for th e transmit-

on-chan ge func tio n.

The result of an A/D conversion is made available to

the use r wi thin th e dat a fi eld o f th e Read A/D Re giste rs

output message via the CAN bus. This message can

be directly requested by another CAN node or be

automatically transmitted (TXIDO), as has been

described previously.

Addit ionally, the individual channel res ults ma y be read

using the “Read Register” command as described in

Section 4.3.1 “Information Request Messa ges ” and

as shown in Table 3-2 by addressing the appropriate

A/D result register (ADRESnL and ADRESnH).

7.3 A/D Conversion Modes

There are two modes of conversion that can be

individually selected for each analog channel that has

been enabled. These are auto-conversion and

conversion-on-request.

7.3.1 AUTO-CONVERSION MODE

If t he Auto- conver sion mo de is sel ected (STCON ), an

A/D conversion is performed sequentially for each

channel that has been set to Analog Input mode and

has been configured for Auto-conversion mode.

Conversion starts with AN0 and is immediately

followed by AN1, etc. Once the conversion has

completed, the value is stored in the analog channel

registers for the respective channel.

The rate of the auto-conversion is determined by a

timer and prescaler. The formula for determining

conversion rates is:

Typical conversion rates with a 20 MHz oscillator input

are shown in Table 7-1.

TABLE 7-1: AUTO-CONVERSION RATES

FOR GIVEN PRESCALE

RATES AT 20 MHZ

The time r is turned on if one of the G PnTXC bits ar e set

in the IOINTEN register and configured as analog

input.

The prescaler counter is cleared when the device is

reset (RST reset or Power-on reset).

Note: The G PDDR re gis ter c ont rols the d irec tio n

of the GPIO pins, even when they are

being used as analog inputs. The user

must ensure that the bits in the GPDDR

using them as analog inputs.

TOPS[2:0] Prescale

Rate Auto-Conversion

Rate

000 1:1 51 µs

001 1:8 410 µs

010 1:32 2 ms

011 1:128 7 ms

100 1:512 26 ms

101 1:1024 52 ms

110 1:2048 105 ms

111 1:4096 210 ms

TOSC

()1024()Prescaler rate()

MCP2502X/5X

7.3.2 CONVERSION-ON-REQUEST

MODE

If the Conversion-on-request mode is selected, the

device performs an A/D conversion only after receiving

a Read A/D Registers or Read Register Receive

message (IRM). In th e c as e o f t he Read A/D R e gis te rs

command, all of the GPIO pins that have been

configured as analog input channels will have an A/D

convers ion done before the dat a frame is sent. Whe n a

Read Regi ster Receiv e me ss age is ini t ia ted (exte nde d

message format only), the A/D conversion is performed

when t he MSB of t he analog channel is reques ted, with

the MSB re sult being tra nsferred. A subseque nt read of

the LSB will transmit the value latched when the MSB

was requested (it is recommended that the Read A/D

Registers receive message is used to obtain complete

analog channel values in one message).

7.4 A/D Threshold Detection

Once an A/D auto -conversion has been c ompleted, the

A/D channel result(s) can be compared to a value

stored in the associated A/D channel comparator

registers.

If the value in the analog channel result registers (i.e.,

AN0L and AN10H registers for analog channel 0) is

lower or higher than the value in the A/D comparator

registers (as specified by a corresponding polarity bit),

a transmit-on-change message will be sent (TXID2).

The threshold-detection function for all analog

channels is bit-selectable.

If the A/D channel has been con figured for transmit-o n-

change mode, the MCP2505 will send a transmit

message with the appropriate data. It is possible that

more than one A/D channel has a change-of-state

condition. This does not pose a problem since all

analog channel data is provided in the transmit

message.

R-x R-x R-x R-x R-x R-x R-x R-x

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

bit 7 bit 0

bit 7-0 AD9:AD2: Most Significant A/D Result bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R-x R-x U-0 U-0 U-0 U-0 U-0 U-0

AD1 AD0 — — — — — —

bit 7 bit 0

bit 7-6 AD1:AD0: Least significa nt A/D Result b its

bit 5-0 Unimplemented: Reads as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

ANnCMP9 ANnCMP8 ANnCMP7 ANnCMP6 ANnCMP5 ANnCMP4 ANnCMP3 ANnCMP2

bit 7 bit 0

bit 7-0 ANnCMP9:ANnCMP2: Most Significant A/D Compare bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x U-0 U-0 U-0 U-0 U-0 U-0

ANnCMP1 ANnCMP0 — — — — — —

bit 7 bit 0

bit 7-6 ANnCMP1:ANnCMP0: Least Signifi ca nt A/D Compare bits

bit 5-0 Unimplemented: Reads as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-0 R/W-0 R/W-0 R/W-0 U-x U-0 U-x U-x

ADON T0PS2 T0PS1 T0PS0 — — — —

bit 7 bit 0

bit 7 ADON: A/D On Bit

1 = A/D converter module is operating

0 = A/D converter module is shut off and consumes no operating current

bit 6-4 T0PS2:T0PS0: Timer0 Prescaler Rate Select bits (used for auto-conversions)

000 = 1:1 Prescaller Rate

001 = 1:8 Prescaller Rate

010 = 1:32 Prescaller Rate

011 = 1:128 Prescaller Rate

100 = 1:512 Prescaller Rate

101 = 1:1024 Prescaller Rate

110 = 1:2048 Prescaller Rate

111 = 1:4096 Prescaller Rate

Formula: (TOSC)(1024) (Prescaler Rate)

bit 3 Reserved

bit 2 Unimplemented: Reads as ‘0’

bit 1-0 Reserved

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCS1 ADCS0 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

bit 7 bit 0

bit 7-6 ADCS1:ADCS0: A/D Conversion Select bits

00 = FOSC/2

01 = FOSC/8

10 = FOSC/32

11 = Reserved

bit 5-4 VCFG1:VCFG0: Voltage Referen ce Confi gu r ati on bit s

bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits*

1 = Corresponding GPIO pin configured as Digital I/O

0 = Corresponding GPIO pin configured as A/D Input

* corresponding data direction bit (GPDDR register) must be set for each enabled analog

channel.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

VCFG1:VCFG0 A/D VREF+ A/D VREF-

00 VDD VSS

01 External VREF+VSS

10 VDD External VREF-

11 External VREF+ External VREF-

MCP2502X/5X

7.5 Read A/D Registers Output

Message

When the MCP2502X/5X responds to a Read A/D Regs

IRM with an OM, the analog values are contained in

R-x R-x R-x R-x R-x R-x R-x R-x

ANnR9 ANnR8 ANnR7 ANnR6 ANnR5 ANnR4 ANnR3 ANnR2

bit 7 bit 0

bit 7-0 ANnR9:ANnR2: Bits 9-2 of channel ‘n’ results

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R-x R-x U-x U-x R-x R-x U-x U-x

AN3R.1 AN3R.0 —— AN2R.1 AN2R.0 — —

bit 7 bit 0

bit 7-6 AN3R.1:AN3R.0: A/D Channel 3, bits 1:0 results

bit 5-4 Unimplemented: Reads as ‘0’

bit 3-2 AN2R.1:AN2R.0: A/D Channel 2, bits 1:0 results

bit 1-0 Unimplemented: Reads as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

TABLE 7-2: REGISTERS ASSOCIATED WITH THE A/D MODULE

R-x R-x U-x U-x R-x R-x U-x U-x

AN1R.1 AN1R.0 —— AN0R.1 AN0R.0 — —

bit 7 bit 0

bit 7-6 AN1R.1:AN1R.0: A/D Channel 1, bits 1:0 results

bit 5-4 Unimplemented: Reads as ‘0’

bit 3-2 AN0R.1:AN0R.0: A/D Channel 0, bits 1:0 results

bit 1-0 Unimplemented: Reads as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Addr Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Value on

POR Value on

RST

1Eh GPPIN GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000 0000 0000

34h GPDDR * —DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 -111 1111 -111 1111

00h IOINTEN GP7TXC GP6TXC GP5TXC GP4TXC GP3TXC GP2TXC GP1TXC GP0TXC 0000 0000 0000 0000

01h IOINTPO GP7POL GP6POL GP5POL GP4POL GP3POL GP2POL GP1POL GP0POL 0000 0000 0000 0000

0Eh ADCON0 ADON T0PS2 T0PS1 T0PS0 GO/DONE — CHS1 CHS0 0000 0-00 0000 0-00

0Fh ADCON1 ADCS1 ADCS0 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000

2Ch ADCMP3 AN3CM AN3CMP. AN3CMP. AN3CMP. AN3CMP.5 AN3CMP.4 AN3CMP. AN3CMP2 xxxx xxxx uuuu uuuu

2Dh ADCMP3 AN3CM AN3CMP. ——ReservedADPOLxx-- ---- uu-- ----

2Eh ADCMP2 AN2CM AN2CMP. AN2CMP. AN2CMP. AN2CMP.5 AN2CMP.4 AN2CMP. AN2CMP2 xxxx xxxx uuuu uuuu

2Fh ADCMP2 AN2CM AN2CMP. ——ReservedADPOLxx-- ---- uu-- ----

30h ADCMP1 AN1CM AN1CMP. AN1CMP. AN1CMP. AN1CMP.5 AN1CMP.4 AN1CMP. AN1CMP2 xxxx xxxx uuuu uuuu

31h ADCMP1 AN1CM AN1CMP. ——ReservedADPOLxx-- ---- uu-- ----

32h ADCMP0 AN0CM AN0CMP. AN0CMP. AN0CMP. AN0CMP.5 AN0CMP.4 AN0CMP. AN0CMP2 xxxx xxxx uuuu uuuu

33h ADCMP0 AN0CM AN0CMP. —— Reserved —xx-- ---- uu-- ----

10h STCON STEM STMS STBF1 STBF0 STM3 STM2 STM1 STM0 0xxx xxxx 0uuu uuuu

*The GPDDR register controls the direction of the GPIO pins, even when they are being used as analog inputs. The user must ensure

that the bits in the GPDDR register are maintained set (input) when using t hem as analog inputs.

MCP2502X/5X

8.0 SPECIAL FEATURES OF THE

MCP2502X/5X

8.1 Description

There are a number of special circuits in the

MCP2502X/5X that deal with the needs of real-time

applications. These features are intended to maximize

system reliability, minimize cost through elimination of

external components and provide power-saving

operating modes. These are:

• Oscillator selection

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

• SLEEP

• In-Circuit Serial Programming

Several oscillator options are offered to allow the

device to fit the application. XT and HS modes allow

the device to support a wide range of crystal

freq uencies while the LP crystal option saves power.

Two timers are implemented to offer necessary delays

on power-up. One is the Oscillator Start-up Timer

(OST), intended to keep the device in reset until the

crystal oscillator is stable. The other is the Power-up

Timer (PWRT), which provides a fixed delay of 72 ms

(nominal) on power-up only, designed to keep the part

in reset while the power supply stabilizes. With these

two tim ers on -ch ip, mo st applicati on s n eed no external

reset circuitry.

SLEEP mode is designed to offer a very low current

power-down mode. The user can wake-up from SLEEP

through e xternal reset, transmit-on-chan ge or CAN bus

activity.

A set of configuration bits are used to select various

options.

FIGURE 8-1: CRY STAL/CERAMIC

RESONATOR

OPERATION

FIGURE 8-2: EXTERNAL CLOCK INPUT

OPERATION

8.2 Configuration Bits

The co nfiguratio n b its can be eit her p r o gram m ed (rea d

as ‘0’) or unprogrammed (read as ‘1’) to select various

device configurations. These bits are mapped in

program memory location 2007h. The configuration

belongs to the special test/co nfiguration memory sp ace

(2000h-3FFFh) that can be accessed only during

programming.

8.3 Oscillator Configurations

Four different oscillator modes may be selected. The

user can program two configuration bits

(FOSC1:FOSC0) in the CO NFIG registe r to select one of

these modes:

• LP = Low-Power Crystal

• XT = Crystal/Resonator

• HS = High-spee d Crystal Resonator

In all modes, a crystal or ceramic resonator is

connected to the OSC1/CLKIN and OSC2/CLKOUT

pins to establish oscillation (Figure 8-1). The oscillator

design requires the use of a parallel-cut crystal. The

device can also have an external clock source to drive

the OSC1/CLKIN pin (Figure 8-2).

The device will default to HS mode if the CONFIG

SLEEP

TO INTERNA L

LOGIC

OSC1

OSC2

XTAL RF

MCP2505X

OSC1

MCP2505X

Open

Clock from

ext. System

OSC2

MCP2502X/5X

8.4 Reset

The MCP2 502X/5X dif ferentiate s between two kinds of

reset:

• Power-on Reset (POR)

•External RST

reset

Some r egi st e rs a r e n ot aff ec ted in an y re se t con dit i on .

Their st atus is unknow n on POR and uncha nged in any

other reset. Most other registers are reset to a reset

state on Power-on Reset (POR), on RST and on RST

during SLEEP. They are not affected by a wake-up from

SLEEP, which is viewed as the resumption of normal

operation. A simplified block diagram of the on-chip

reset circ uit is shown in Figure 8-3. The MCP25 02X/5X

has a R ST noise filter in the RST reset path. The filter

will detect and ignore small pulses.

8.4.1 POWER-ON RESET

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.5V to 2.1V). If the

RST input on the GP7 pin is sel ected, the RS T pin may

be tied thro ugh a seri es resisto r to VDD, e lim in ati ng the

need for external RC components usually required for

a Power-on Reset. A maximum rise time for VDD is

specified in Section 9.0 “Electrical Characteristics”

of this document.

When the device starts normal operation (exits the

reset condi tion), de vice o per ating p aram eters (v olt ag e,

frequency, temperature, etc.) must be met to ensure

proper operation. For additional information, refer to

AN607, “Power-up Troubleshooting”, DS00607).

U-0 U-0 R/W-x R/W-x R/W-x R/W-x

——RRRR

bit 13 bi t 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W R/W R/W

R R R R R RSTEN FOSC1 FOSC0

bit 7 bit 0

bit 13-11 Unimplemented: Read as '0'

bit 10-3 Reserved: do not attempt to modif y

bit 2 RSTEN: Enable RST input on GP7

1 =RST

input Enabled

0 =RST

input Disabled

bit 1-0 FOSC1:FOSC0: Oscillator Selection bits

11 = HS oscillator

10 = Reserved for Test (EC oscillator)

01 = XT oscillator

00 = LP oscillator

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2502X/5X

FIGURE 8-3: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

8.4.2 POWER-UP TIMER

The Power-up Timer (PWRT) provides a fixed, 72 ms

nominal time-out, on power-up only , from the POR. The

Power-up Timer operates on an internal RC oscillator,

with the device being kept in reset a s long as the PWRT

is active. The PWRT's time delay allows VDD to rise to

an acceptable level. The power-up time delay will vary

from device to device due to VDD, temperature and

process variation. For more information, please see

Section 9.2 “DC Characteristics”.

8.5 Oscillator Start-up Timer

The Oscillator Start-up Timer (OST) provides a 512

oscillator cycle (TOSC) delay after the PWRT delay is

complete. This ensures that the crystal oscillator has

started and stabilized and must be less than the total

time it takes (704 oscillator cycles or 44 TQ) for the

minimum standard data frame or remote transmit

message to be completed on the CAN bus once a

wake-up from SLEEP occurs. The OST time-out is

invoked only on Power-on Reset or wake-up from

SLEEP.

8.6 Power-down Mode (SLEEP)

Power-down mode (or SLEEP) is enabled via the

SLPEN bit in the OPTREG2 register. When enabled,

the MCP2502 X/5X will enter SLEEP once the CAN bus

has been idle for a minimum 1408 bit times while in

Normal mode.

Additionally, the device may be configured to enter

SLEEP while in Listen-only mode immediately after

power-up if there is no activity on the CAN bus.

Subsequent CAN bus activity will wake the device up

from SLEEP an d th e NEXT mes sage wi ll b e c onfi rme d

as a valid message before en tering Normal mode. This

feature is enabled via the PUSLP bit in the OPTREG2

While in SLEEP, the I/O ports maintain the status they

had before the SLEEP instruction was executed

(driving high, low or hi-impedance).

The following operations will not function while the

device is in SLEEP:

• A/D Module data conversion

• Auto-conversion mode

• Auto-messaging

• PWM module and outputs

• Clock output

8.6.1 WAKE-UP FROM SLEEP

The MCP2502X/5X can wake-up from SLEEP through

one of the following events:

• External reset input on RST pin

• Transmit-on-change due to edge detected on

GPIO pin

• Activity detected on CAN bus

For the device to wake-up due to a GPIO transmit-on-

change, the c orrespo nding interru pt ena ble bi t must be

set (enabled). Wake-up occurs regardless of the state

of the GIE bit.

If a wake-up from SLEEP is caused by activity on the

CAN bus, the message that caused the wake-up will not

be received or acknowledged by the MCP2502X/5X.

RST

VDD

OSC1

VDD Rise

Detect Power-on Reset

OST

10-bit Ripple Counter

PWRT

On-chip

RC OSC

Enable PWRT

Enable OST

QChip Reset

MCP2502X/5X

8.7 In-Circuit Serial Programmi ng

The MCP2502X/5X can be serially programmed while

in the end application circuit. This is simply done with

two lines for clock and data, and three other lines for

power, ground and the programming voltage. This

allows customers to manufacture boards with

unprogrammed devices and then program the device

just before shipping the product, also allowing the

most recent firmware (or a custom firmware) to be

programmed.

The device is placed into a program/verify mode by

holding the GP4 and GP5 pins low while raising GP7

(VPP) pin from VIL to VIH (see the MCP2502X/5X

programming specification, “MCP250XX In-Circuit

Serial Programming™ (ICSP)”, DS20072, for more

informati on). GP4 become s the pr ogrammin g data an d

GP5 becomes the programming clock. Both GP4 and

GP5 are Schmitt Tr igger inputs in this mode. The signal

definitions are summarized in Table 8-1

TABLE 8-1: IN-CIRCUIT SERIAL

PROGRAMMING PIN

FUNCTIONS

Pin Name Pin

Number Programming Mode

Function

VSS 7 Ground

GP4 5 Data

GP5 6 Clock

GP7 11 VPP

VDD 14 Power

MCP2502X/5X

9.0 ELECTRICAL CHARACTERISTICS

9.1 Absolute Maximum Ratings†

Ambient temperature under bias.............................................................................................................-55°C to +125°C

Storage temperature...............................................................................................................................-65°C to +150°C

Voltage on any pin with respect to Vss (except VDD and RST).......................................................-0.3V to (VDD + 0.6V)

VDD................................................................................................................................................................... 0V to 7.0V

Volta ge on RST with respect to Vss............................................................................................................. ..... 0V to 14V

Total power dissipati on (Note 1) ..............................................................................................................................1.0 W

Maximum source current out of VSS pin ...............................................................................................................300 mA

Maximum sink current into VDD pin............... ..... ...... ................. ...... ................ ...... ...... ................ ...... ................. ...250 mA

Input clamp current, Iik (Vi < 0 or Vi > VDD)..........................................................................................................±20 mA

Output clamp current, Iok (VO < 0 or VO > VDD)....................................................................................................±20 mA

Maximum current sunk by any I/O pin.....................................................................................................................25 mA

Maximum current sourced by any input pin ............................................................................................................25 mA

Maximum current sunk by GPIO port....................................................................................................................200 mA

Maximum current sourced by GPIO port ..............................................................................................................200 mA

Soldering temperature of leads (10 seconds).......................................................................................................+300°C

ESD protection on all pins.................................................................................................................................................. ≥ 3.5 kV

Note 1: Power diss ipation is calculated as follow s : Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)

FIGURE 9-1: MCP2505X VOLTAGE-FREQUENCY GRAPH

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . T his is a stres s rati ng onl y and functi onal o peratio n of th e d evice a t those or any ot her co nditio ns ab ove thos e

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Frequency

Voltage

6.0V

5.5V

4.5V

4.0V

2.0V

25 MHz

5.0V

3.5V

3.0V

2.7V

Fmax = (9.44 MHz/V) (VDDAPPMIN - 2.7V) + 8 MHz

Note: VDDAPPMIN is the minimum voltage of the MCP2505X device in the application.

8MHz

4.5V

MCP2505X

Characterized and no t 100% tested.

MCP2502X/5X

9.2 DC Characteristics

DC Characteristics Industrial (I): TAMB = -40°C to +85°C VCC = 2.7V to 5.5V

Automotive (E): TAMB = -40°C to +125°C VCC = 4.5V to 5.5V

Param.

No. Sym Characteristics Min Max Units Test Conditions

VDD Supply Voltage 2.7

4.5 5.5

5.5 V

VXT and LP OSC configuration

HS OSC config urat ion (Note 2)

SVDD VDD Rise Rate to ensure

internal power-on reset signal 0.05 — V/ms (Note 3)

High-level input voltage

VIH GPIO pins 2 VDD+0.3 V

VIH RXCAN (Schmitt Trigger) .7 VDD VDD V

OSC1 .85 VDD VDD V

Low-level input voltage —

VIL RXCAN (Schmitt Trigger) VSS 0.2 VDD V

VIL GPIO pins -0.3 0.5V V

OSC1 VSS 0.2 VDD V

Low-level outpu t voltage

VOL TXCAN GPIO pins — 0.6 V IOL = 8.5 mA, VDD = 4.5V

High-level output voltage V

VOH TXCAN, GPIO pins VDD -0.7 — V IOH =-3.0 mA, VDD = 4.5V,

I-temp

Input leakage current

ILI All I/O except OSC1, GP7 -1 +1 µA

OSC1, GP7 pin -5 +5 µA

CINT Internal Capacitance

(all inputs and outputs, except

GP7)

—7pFTAMB = 25°C, fC = 1.0 MHz,

VDD = 5.0V (Note 3)

GP7 — 15 pF

IDD Operat ing Current — 20 mA XT OSC VDD = 5.5V;

FOSC =25MHz

IDDS Standby Current

(CAN Sleep Mode) — 30 µA Inputs tied to VDD or VSS

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: Refer to Figure 9-1.

3: This parameter is periodically sampled and not 100% tested.

© 2007 Microchip Technology Inc. DS21664D-page 53
MCP2502X/5X
9.3 AC Characteristics
AC Characteristics Industrial (I): TAMB = -40°C to +85°C  VCC = 2.7V t o 5. 5V
Automotive (E): TAMB = -40°C to +125°C  VCC = 4.5V to 5. 5V
Param.
No. Sym Characte r istic s Min Max Units Test Conditions
FOS CLKIN Frequency DC 4 MHz XT osc mode
DC 25 MHz HS osc mode (Note 3)
DC 200 kHz LP osc mode
FOS Oscillator Frequency  0.1 4 MHz XT osc mode 
4 25 MHz HS osc mode (Note 3)
5 200 kHz LP osc mode
1T
OSC CLKIN Period 250 — ns XT osc mode
40 — ns HS osc mode
5 — µs LP osc mode
Oscillator Period 0.25 10 µs XT osc mode
40 250 ns HS osc mode
5 — µs LP osc mode
3T
OSL CLKIN High or Low Time 100 — ns XT osc mode
TOSH 15 — ns HS osc mode
2.5 — µs LP osc mode
4 Tosr CLKIN Rise or Fall Time — 25 ns XT osc mode (Note 1)
— 50 ns HS osc mode (Note 1)
— 15 ns LP osc mode (Note 1)
10 TDCLKOUT CLKOUT Propagation Delay — 60 ns VDD = 4.5 V (Note 2)
12 TCKR CLKOUT Rise Time — 100 ns Note 2
13 TCKR CLKOUT Fall Time — 200 ns Note 2
20 TIOR Port output rise time — 40 ns Note 1
21 TIOF Port output fall time — 40 ns Note 1
30 TMCL RST Pulse Low 2 — µs VDD = 5V
32 TOST Oscillation Start-up Timer 512 — Tosc TOSC = OSC1 period
33 TPWRT Power-up Timer 28 132 ms VDD = 5V
34 TIOZ I/O Hi-impedance from RST 
low —2.1µsNote 1
TPWMR PWM output rise time — 25 ns Note 1
TPWMF PWM output fall time — 25 ns Note 1
TAD A/D clock period 1.6 — µs VREFΔ ≥ 2.5V
3.0 — µs VREF full range
TCNV Conversion Time (not 
including acquisition time) —13TAD
Note 1: This parameter is periodically sampled and not 100% tested.
2: Measurements are taken with CLKOUT output configured as 4 x TOSC.
3: Refer to Figure 9-1.

MCP2502X/5X

FIGURE 9-2: I/O TIMING

FIGURE 9-3: RESET, OST AND POWER-UP-TIMER

OSC1

I/O Pin

(input)

I/O Pin

(output)

20, 21

Old Value New Value

Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins.

13 12

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

RESET

I/O Pins

MCP2502X/5X

9.4 A/D Converter Characteristics

AC Converter Characteristics Industrial (I): TAMB = -40°C to +85°C VCC = 2.7V to 5.5V

Automotive (E): TAMB = -40°C to +125°C VCC = 4.5V to 5.5V

Param.

No. Sym Characteristics Min Max Units Test Conditions

NRA/D resolu tion — 10- bits VREF = VDD = 5.12V, VSS ≤ in

≤VREF

NINT A/D Integral error — less than

±1 LSb VREF+ = VDD = 5.12V,

VSS- = VSS = 0 V (I TEMP)

NDIF A/D Differential error — less than

±1 LSb VREF+ = VDD = 5.12V,

VSS- = VSS = 0 V (I TEMP)

NGA/D Gain error — less than

±1 LSb VREF+ = VDD = 5.12V,

VSS- = VSS = 0 V

NOFF A/D Offset error — less than

±2 LSb VREF+ = VDD = 5.12V,

VSS- = VSS = 0 V

Monotonicity — — VSS ≤ in ≤VREF

VREF Refer ence Voltage 4.096 VDD+0.3 V Absolute minimum to ensure

10-bit accuracy.

VREF+ Reference V high VREF-VDD+0.3 V Minimum resolutio n for A/D is

1mV.

VREF- Reference V low VSS-0.3 VREF+ V Mini mum r esolu tion for A/D is

1mV.

VAIN Analog input V VREF-VREF+V

ZAIN Recom m end ed im ped anc e

of analog voltage source —2.5kΩNote

IREF VREF input current — 10 µA

NHYS Analog Transmit-on-change

Hysteresis — 2 LSb Specified by design (see

Section 4.5.2.1 “Hysteres is

Function”)

Note: Design guidance only

MCP2502X/5X

NOTES:

MCP2502X/5X

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

14-Lead PDIP (300 mil) Example:

14-Lead SOIC (208 mil) Example:

XXXXXXXXXXXXXX

YYWWNNN

XXXXXXXXXXX

YYWWNNN

XXXXXXXXXXX

MCP25050

XXXXXXXXXXXXXX

0725NNN

MCP25055

0737NNN

XXXXXXXXXXX

Legend: XX...X Customer-spec if ic information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the eve nt the full Microc hip p ar t number cannot be marked on one li ne, it wi

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

MCP2502X/5X

14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

otes:

. Pin 1 visual index feature may vary, but must be located with the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 14

Pitch e .100 BSC

Top to Seating Plane A – – .210

Molded Package Thickness A2 .115 .130 .195

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .325

Molded Package Width E1 .240 .250 .280

Overall Length D .735 .750 .775

Tip to Seating Plane L .115 . 130 .150

Lead Thickness c .008 . 010 .015

Upper Lead Width b1 .045 .060 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

123

Microchip Technology Drawing C04-005

MCP2502X/5X

14-Lead Plastic Small Outli ne (SL) – Narrow, 3.90 mm Body [SOIC]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 14

Pitch e 1.27 BSC

Overall Height A – – 1.75

Molded Package Thickness A2 1.25 – –

Standoff § A1 0.10 – 0.25

Overall Width E 6.00 BSC

Molded Package Width E1 3.90 BSC

Overall Length D 8.65 BSC

Chamfer (optional) h 0.25 – 0.50

Foot Length L 0.40 – 1.27

Footprint L1 1.04 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.17 – 0.25

Lead Width b 0.31 – 0.51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

123

hα

Microchip Technology Drawing C04-065

MCP2502X/5X

NOTES:

MCP2502X/5X

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX

PackageTemperature

Range

Device

Device: MCP25020: CAN I/O Expander

MCP25020T: CAN I/O Expander (Tape and Reel)

MCP25025: CAN I/O Expander

MCP25025T: CAN I/O Expander (Tape and Reel)

MCP25050: Mixed Signal CAN I/O Expander

MCP25050T: Mixed Signal CAN I/O Expander

(Ta pe and Ree l)

MCP25055: Mixed Signal CAN I/O Expander

MCP25055T: Mixed Signal CAN I/O Expander

(Ta pe and Ree l)

Temperatu re R ang e: I = -40°C to +85°C

E = -40°C to +1 25°C (not ava ila ble on MC P25 02 5

or MCP25055 devices)

Package: P = Plastic DIP (300 mil Body), 14-lead

SL = Plastic SOIC (150 mil Body), 14-lead

Examples:

a) MCP250 20– I/P : In dustrial tem per atu re ,

PDIP package.

b) MCP250 25– I/S L: Industrial tem per atu re ,

SOIC package.

c) MCP250 50T-E/SL: Tape and Reel ,

Extended temperature,

SOIC package.

d) MCP250 55- I/S L: Indus trial tem per atu re

SOIC package.

MCP2502X/5X

NOTES:

MCP2502X/5X

APPENDIX A: REVISION HISTORY

Revision D (January 2007)

This revision includes updates to the packaging

diagrams.

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is pro vid ed only fo r yo ur c onvenien ce

and may be supers eded by updates. It is y our resp o ns i bil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART ,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PIC kit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInf o, PowerMate, PowerTool, REAL ICE , rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporat ed in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of t he most secure families of its kind on t he market t oday, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microchip are commit ted to continuously improving the code protect ion f eatures of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

T empe, Arizona, Gresham, Oregon and Mountain View , California. The

Company’s quality system processes and procedures are for its PIC®

MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

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12/08/06