KL05 Sub-Family Reference Manual Supports: MKL05Z8VFK4, MKL05Z16VFK4, MKL05Z32VFK4, MKL05Z8VLC4, MKL05Z16VLC4, MKL05Z32VLC4, MKL05Z8VFM4, MKL05Z16VFM4, MKL05Z32VFM4, MKL05Z16VLF4, and MKL05Z32VLF4 Document Number: KL05P48M48SF1RM Rev. 3.1, November 2012 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 2 Freescale Semiconductor, Inc. Contents Section number Title Page Chapter 1 About This Document 1.1 1.2 Overview.......................................................................................................................................................................31 1.1.1 Purpose.........................................................................................................................................................31 1.1.2 Audience......................................................................................................................................................31 Conventions..................................................................................................................................................................31 1.2.1 Numbering systems......................................................................................................................................31 1.2.2 Typographic notation...................................................................................................................................32 1.2.3 Special terms................................................................................................................................................32 Chapter 2 Introduction 2.1 Overview.......................................................................................................................................................................33 2.2 Kinetis L Series.............................................................................................................................................................33 2.3 KL05 Sub-Family Introduction.....................................................................................................................................36 2.4 Module functional categories........................................................................................................................................37 2.5 2.4.1 ARM(R) CortexTM-M0+ Core Modules.........................................................................................................37 2.4.2 System Modules...........................................................................................................................................38 2.4.3 Memories and Memory Interfaces...............................................................................................................39 2.4.4 Clocks...........................................................................................................................................................39 2.4.5 Security and Integrity modules....................................................................................................................39 2.4.6 Analog modules...........................................................................................................................................40 2.4.7 Timer modules.............................................................................................................................................40 2.4.8 Communication interfaces...........................................................................................................................41 2.4.9 Human-machine interfaces..........................................................................................................................41 Orderable part numbers.................................................................................................................................................42 Chapter 3 Chip Configuration 3.1 Introduction...................................................................................................................................................................43 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 3 Section number 3.2 3.3 3.4 3.5 3.6 Title Page Module to Module Interconnects..................................................................................................................................43 3.2.1 Module to Module Interconnects.................................................................................................................43 3.2.2 Analog reference options.............................................................................................................................45 Core Modules................................................................................................................................................................46 3.3.1 ARM Cortex-M0+ Core Configuration.......................................................................................................46 3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................48 3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................52 System Modules............................................................................................................................................................53 3.4.1 SIM Configuration.......................................................................................................................................53 3.4.2 System Mode Controller (SMC) Configuration...........................................................................................54 3.4.3 PMC Configuration......................................................................................................................................54 3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................55 3.4.5 MCM Configuration....................................................................................................................................57 3.4.6 Crossbar-Light Switch Configuration..........................................................................................................58 3.4.7 Peripheral Bridge Configuration..................................................................................................................59 3.4.8 DMA request multiplexer configuration......................................................................................................60 3.4.9 DMA Controller Configuration...................................................................................................................63 3.4.10 Computer Operating Properly (COP) Watchdog Configuration..................................................................63 Clock Modules..............................................................................................................................................................66 3.5.1 MCG Configuration.....................................................................................................................................66 3.5.2 OSC Configuration......................................................................................................................................67 Memories and Memory Interfaces................................................................................................................................68 3.6.1 Flash Memory Configuration.......................................................................................................................68 3.6.2 Flash Memory Controller Configuration.....................................................................................................70 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 4 Freescale Semiconductor, Inc. Section number 3.6.3 3.7 3.8 3.9 3.10 Title Page SRAM Configuration...................................................................................................................................71 Analog...........................................................................................................................................................................73 3.7.1 12-bit SAR ADC Configuration..................................................................................................................73 3.7.2 CMP Configuration......................................................................................................................................77 3.7.3 12-bit DAC Configuration...........................................................................................................................79 Timers...........................................................................................................................................................................80 3.8.1 Timer/PWM Module Configuration............................................................................................................80 3.8.2 PIT Configuration........................................................................................................................................83 3.8.3 Low-power timer configuration...................................................................................................................84 3.8.4 RTC configuration.......................................................................................................................................86 Communication interfaces............................................................................................................................................87 3.9.1 SPI configuration.........................................................................................................................................87 3.9.2 I2C Configuration........................................................................................................................................88 3.9.3 UART Configuration...................................................................................................................................89 Human-machine interfaces (HMI)................................................................................................................................91 3.10.1 GPIO Configuration.....................................................................................................................................91 3.10.2 TSI Configuration........................................................................................................................................93 Chapter 4 Memory Map 4.1 Introduction...................................................................................................................................................................95 4.2 System memory map.....................................................................................................................................................95 4.3 Flash Memory Map.......................................................................................................................................................96 4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................96 4.4 SRAM memory map.....................................................................................................................................................97 4.5 Bit Manipulation Engine...............................................................................................................................................97 4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................98 4.6.1 Read-after-write sequence and required serialization of memory operations..............................................98 4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map..............................................................................................99 4.6.3 Modules Restricted Access in User Mode...................................................................................................102 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 5 Section number 4.7 Title Page Private Peripheral Bus (PPB) memory map..................................................................................................................102 Chapter 5 Clock Distribution 5.1 Introduction...................................................................................................................................................................105 5.2 Programming model......................................................................................................................................................105 5.3 High-Level device clocking diagram............................................................................................................................105 5.4 Clock definitions...........................................................................................................................................................106 5.4.1 5.5 Device clock summary.................................................................................................................................107 Internal clocking requirements.....................................................................................................................................109 5.5.1 Clock divider values after reset....................................................................................................................109 5.5.2 VLPR mode clocking...................................................................................................................................110 5.6 Clock Gating.................................................................................................................................................................110 5.7 Module clocks...............................................................................................................................................................110 5.7.1 PMC 1-kHz LPO clock................................................................................................................................112 5.7.2 COP clocking...............................................................................................................................................112 5.7.3 RTC clocking...............................................................................................................................................112 5.7.4 LPTMR clocking..........................................................................................................................................113 5.7.5 TPM clocking...............................................................................................................................................113 5.7.6 UART clocking............................................................................................................................................114 Chapter 6 Reset and Boot 6.1 Introduction...................................................................................................................................................................115 6.2 Reset..............................................................................................................................................................................115 6.2.1 Power-on reset (POR)..................................................................................................................................116 6.2.2 System reset sources....................................................................................................................................116 6.2.3 MCU Resets.................................................................................................................................................119 6.2.4 Reset Pin .....................................................................................................................................................120 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 6 Freescale Semiconductor, Inc. Section number 6.2.5 6.3 Title Page Debug resets.................................................................................................................................................121 Boot...............................................................................................................................................................................122 6.3.1 Boot sources.................................................................................................................................................122 6.3.2 FOPT boot options.......................................................................................................................................122 6.3.3 Boot sequence..............................................................................................................................................123 Chapter 7 Power Management 7.1 Introduction...................................................................................................................................................................125 7.2 Clocking Modes............................................................................................................................................................125 7.2.1 Partial Stop...................................................................................................................................................125 7.2.2 DMA Wakeup..............................................................................................................................................126 7.2.3 Compute Operation......................................................................................................................................127 7.2.4 Peripheral Doze............................................................................................................................................128 7.2.5 Clock Gating................................................................................................................................................129 7.3 Power modes.................................................................................................................................................................129 7.4 Entering and exiting power modes...............................................................................................................................131 7.5 Module Operation in Low Power Modes......................................................................................................................131 Chapter 8 Security 8.1 Introduction...................................................................................................................................................................135 8.2 Flash Security...............................................................................................................................................................135 8.3 Security Interactions with other Modules.....................................................................................................................135 8.3.1 Security Interactions with Debug.................................................................................................................136 Chapter 9 Debug 9.1 Introduction...................................................................................................................................................................137 9.2 Debug Port Pin Descriptions.........................................................................................................................................137 9.3 SWD status and control registers..................................................................................................................................138 9.3.1 MDM-AP Control Register..........................................................................................................................139 9.3.2 MDM-AP Status Register............................................................................................................................140 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 7 Section number Title Page 9.4 Debug Resets................................................................................................................................................................142 9.5 Micro Trace Buffer (MTB)...........................................................................................................................................143 9.6 Debug in Low Power Modes........................................................................................................................................143 9.7 Debug & Security.........................................................................................................................................................143 Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction...................................................................................................................................................................145 10.2 Signal Multiplexing Integration....................................................................................................................................145 10.3 10.4 10.2.1 Port control and interrupt module features..................................................................................................146 10.2.2 Clock gating.................................................................................................................................................147 10.2.3 Signal multiplexing constraints....................................................................................................................147 Pinout............................................................................................................................................................................147 10.3.1 KL05 signal multiplexing and pin assignments...........................................................................................147 10.3.2 KL05 Pinouts...............................................................................................................................................149 Module Signal Description Tables................................................................................................................................153 10.4.1 Core Modules...............................................................................................................................................153 10.4.2 System Modules...........................................................................................................................................154 10.4.3 Clock Modules.............................................................................................................................................154 10.4.4 Memories and Memory Interfaces...............................................................................................................154 10.4.5 Analog..........................................................................................................................................................154 10.4.6 Timer Modules.............................................................................................................................................155 10.4.7 Communication Interfaces...........................................................................................................................156 10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................156 Chapter 11 Port control and interrupts (PORT) 11.1 Introduction...................................................................................................................................................................159 11.2 Overview.......................................................................................................................................................................159 11.2.1 Features........................................................................................................................................................159 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 8 Freescale Semiconductor, Inc. Section number 11.2.2 Title Page Modes of operation......................................................................................................................................160 11.3 External signal description............................................................................................................................................160 11.4 Detailed signal description............................................................................................................................................161 11.5 Memory map and register definition.............................................................................................................................161 11.6 11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................164 11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................166 11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................167 11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................167 Functional description...................................................................................................................................................168 11.6.1 Pin control....................................................................................................................................................168 11.6.2 Global pin control........................................................................................................................................169 11.6.3 External interrupts........................................................................................................................................169 Chapter 12 System integration module (SIM) 12.1 Introduction...................................................................................................................................................................171 12.1.1 12.2 Features........................................................................................................................................................171 Memory map and register definition.............................................................................................................................171 12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................173 12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................173 12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................174 12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................176 12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................177 12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................178 12.2.7 System Device Identification Register (SIM_SDID)...................................................................................180 12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................182 12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................183 12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................185 12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................186 12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................187 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 9 Section number 12.3 Title Page 12.2.13 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................189 12.2.14 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................190 12.2.15 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................191 12.2.16 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................191 12.2.17 Unique Identification Register Low (SIM_UIDL)......................................................................................192 12.2.18 COP Control Register (SIM_COPC)...........................................................................................................192 12.2.19 Service COP Register (SIM_SRVCOP)......................................................................................................193 Functional description...................................................................................................................................................194 Chapter 13 System Mode Controller (SMC) 13.1 Introduction...................................................................................................................................................................195 13.2 Modes of operation.......................................................................................................................................................195 13.3 Memory map and register descriptions.........................................................................................................................197 13.4 13.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................197 13.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................199 13.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................200 13.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................201 Functional description...................................................................................................................................................202 13.4.1 Power mode transitions................................................................................................................................202 13.4.2 Power mode entry/exit sequencing..............................................................................................................205 13.4.3 Run modes....................................................................................................................................................207 13.4.4 Wait modes..................................................................................................................................................209 13.4.5 Stop modes...................................................................................................................................................210 13.4.6 Debug in low power modes.........................................................................................................................213 Chapter 14 Power Management Controller (PMC) 14.1 Introduction...................................................................................................................................................................215 14.2 Features.........................................................................................................................................................................215 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 10 Freescale Semiconductor, Inc. Section number 14.3 Title Page Low-voltage detect (LVD) system................................................................................................................................215 14.3.1 LVD reset operation.....................................................................................................................................216 14.3.2 LVD interrupt operation...............................................................................................................................216 14.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................216 14.4 I/O retention..................................................................................................................................................................217 14.5 Memory map and register descriptions.........................................................................................................................217 14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................218 14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................219 14.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................220 Chapter 15 Low-Leakage Wakeup Unit (LLWU) 15.1 Introduction...................................................................................................................................................................223 15.1.1 Features........................................................................................................................................................223 15.1.2 Modes of operation......................................................................................................................................224 15.1.3 Block diagram..............................................................................................................................................225 15.2 LLWU signal descriptions............................................................................................................................................226 15.3 Memory map/register definition...................................................................................................................................226 15.4 15.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................227 15.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................228 15.3.3 LLWU Module Enable register (LLWU_ME)............................................................................................229 15.3.4 LLWU Flag 1 register (LLWU_F1).............................................................................................................231 15.3.5 LLWU Flag 3 register (LLWU_F3).............................................................................................................232 15.3.6 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................234 15.3.7 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................235 Functional description...................................................................................................................................................236 15.4.1 LLS mode.....................................................................................................................................................237 15.4.2 VLLS modes................................................................................................................................................237 15.4.3 Initialization.................................................................................................................................................237 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 11 Section number Title Page Chapter 16 Reset Control Module (RCM) 16.1 Introduction...................................................................................................................................................................239 16.2 Reset memory map and register descriptions...............................................................................................................239 16.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................239 16.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................241 16.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................242 16.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................243 Chapter 17 Bit Manipulation Engine (BME) 17.1 Introduction...................................................................................................................................................................245 17.1.1 Overview......................................................................................................................................................246 17.1.2 Features........................................................................................................................................................246 17.1.3 Modes of Operation.....................................................................................................................................247 17.2 External Signal Description..........................................................................................................................................247 17.3 Memory Map and Register Definition..........................................................................................................................248 17.4 Functional Description..................................................................................................................................................248 17.5 17.4.1 BME Decorated Stores.................................................................................................................................248 17.4.2 BME Decorated Loads.................................................................................................................................254 17.4.3 Additional Details on Decorated Addresses and GPIO Accesses................................................................261 Application Information................................................................................................................................................262 Chapter 18 Miscellaneous Control Module (MCM) 18.1 Introduction...................................................................................................................................................................265 18.1.1 18.2 Features........................................................................................................................................................265 Memory map/register descriptions...............................................................................................................................265 18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................266 18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................267 18.2.3 Platform Control Register (MCM_PLACR)................................................................................................267 18.2.4 Compute Operation Control Register (MCM_CPO)...................................................................................270 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 12 Freescale Semiconductor, Inc. Section number Title Page Chapter 19 Micro Trace Buffer (MTB) 19.1 Introduction...................................................................................................................................................................273 19.1.1 Overview......................................................................................................................................................273 19.1.2 Features........................................................................................................................................................276 19.1.3 Modes of Operation.....................................................................................................................................277 19.2 External Signal Description..........................................................................................................................................277 19.3 Memory Map and Register Definition..........................................................................................................................278 19.3.1 MTB_RAM Memory Map...........................................................................................................................278 19.3.2 MTB_DWT Memory Map...........................................................................................................................291 19.3.3 System ROM Memory Map.........................................................................................................................301 Chapter 20 Crossbar Switch Lite (AXBS-Lite) 20.1 Introduction...................................................................................................................................................................307 20.1.1 Features........................................................................................................................................................307 20.2 Memory Map / Register Definition...............................................................................................................................307 20.3 Functional Description..................................................................................................................................................308 20.4 20.3.1 General operation.........................................................................................................................................308 20.3.2 Arbitration....................................................................................................................................................309 Initialization/application information...........................................................................................................................310 Chapter 21 Peripheral Bridge (AIPS-Lite) 21.1 21.2 Introduction...................................................................................................................................................................311 21.1.1 Features........................................................................................................................................................311 21.1.2 General operation.........................................................................................................................................311 Functional description...................................................................................................................................................312 21.2.1 Access support.............................................................................................................................................312 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 13 Section number Title Page Chapter 22 Direct Memory Access Multiplexer (DMAMUX) 22.1 Introduction...................................................................................................................................................................313 22.1.1 Overview......................................................................................................................................................313 22.1.2 Features........................................................................................................................................................314 22.1.3 Modes of operation......................................................................................................................................314 22.2 External signal description............................................................................................................................................315 22.3 Memory map/register definition...................................................................................................................................315 22.3.1 22.4 22.5 Channel Configuration register (DMAMUXx_CHCFGn)..........................................................................315 Functional description...................................................................................................................................................316 22.4.1 DMA channels with periodic triggering capability......................................................................................317 22.4.2 DMA channels with no triggering capability...............................................................................................319 22.4.3 Always-enabled DMA sources....................................................................................................................319 Initialization/application information...........................................................................................................................320 22.5.1 Reset.............................................................................................................................................................320 22.5.2 Enabling and configuring sources................................................................................................................320 Chapter 23 DMA Controller Module 23.1 Introduction...................................................................................................................................................................325 23.1.1 Overview......................................................................................................................................................325 23.1.2 Features........................................................................................................................................................326 23.2 DMA Transfer Overview..............................................................................................................................................327 23.3 Memory Map and Registers..........................................................................................................................................328 23.4 23.3.1 Source Address Register (DMA_SARn).....................................................................................................329 23.3.2 Destination Address Register (DMA_DARn).............................................................................................330 23.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn).............................................................331 23.3.4 DMA Control Register (DMA_DCRn)........................................................................................................333 Functional Description..................................................................................................................................................337 23.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)............................................................................337 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 14 Freescale Semiconductor, Inc. Section number Title Page 23.4.2 Channel Initialization and Startup................................................................................................................337 23.4.3 Dual-Address Data Transfer Mode..............................................................................................................339 23.4.4 Advanced Data Transfer Controls: Auto-Alignment...................................................................................340 23.4.5 Termination..................................................................................................................................................341 Chapter 24 Multipurpose Clock Generator (MCG) 24.1 Introduction...................................................................................................................................................................343 24.1.1 Features........................................................................................................................................................343 24.1.2 Modes of Operation.....................................................................................................................................345 24.2 External Signal Description..........................................................................................................................................346 24.3 Memory Map/Register Definition.................................................................................................................................346 24.4 24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................346 24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................348 24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................349 24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................349 24.3.5 MCG Control 6 Register (MCG_C6)...........................................................................................................351 24.3.6 MCG Status Register (MCG_S)..................................................................................................................351 24.3.7 MCG Status and Control Register (MCG_SC)............................................................................................352 24.3.8 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................354 24.3.9 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................354 Functional Description..................................................................................................................................................354 24.4.1 MCG mode state diagram............................................................................................................................354 24.4.2 Low Power Bit Usage..................................................................................................................................358 24.4.3 MCG Internal Reference Clocks..................................................................................................................358 24.4.4 External Reference Clock............................................................................................................................359 24.4.5 MCG Fixed frequency clock .......................................................................................................................359 24.4.6 MCG Auto TRIM (ATM)............................................................................................................................359 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 15 Section number 24.5 Title Page Initialization / Application information........................................................................................................................361 24.5.1 MCG module initialization sequence...........................................................................................................361 24.5.2 Using a 32.768 kHz reference......................................................................................................................363 24.5.3 MCG mode switching..................................................................................................................................364 Chapter 25 Oscillator (OSC) 25.1 Introduction...................................................................................................................................................................371 25.2 Features and Modes......................................................................................................................................................371 25.3 Block Diagram..............................................................................................................................................................372 25.4 OSC Signal Descriptions..............................................................................................................................................372 25.5 External Crystal / Resonator Connections....................................................................................................................373 25.6 External Clock Connections.........................................................................................................................................374 25.7 Memory Map/Register Definitions...............................................................................................................................375 25.7.1 25.8 25.9 OSC Memory Map/Register Definition.......................................................................................................375 Functional Description..................................................................................................................................................376 25.8.1 OSC Module States......................................................................................................................................376 25.8.2 OSC Module Modes.....................................................................................................................................378 25.8.3 Counter.........................................................................................................................................................379 25.8.4 Reference Clock Pin Requirements.............................................................................................................379 Reset..............................................................................................................................................................................380 25.10 Low Power Modes Operation.......................................................................................................................................380 25.11 Interrupts.......................................................................................................................................................................380 Chapter 26 Flash Memory Controller (FMC) 26.1 Introduction...................................................................................................................................................................381 26.1.1 Overview......................................................................................................................................................381 26.1.2 Features........................................................................................................................................................381 26.2 Modes of operation.......................................................................................................................................................382 26.3 External signal description............................................................................................................................................382 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 16 Freescale Semiconductor, Inc. Section number Title Page 26.4 Memory map and register descriptions.........................................................................................................................382 26.5 Functional description...................................................................................................................................................382 Chapter 27 Flash Memory Module (FTFA) 27.1 Introduction...................................................................................................................................................................385 27.1.1 Features........................................................................................................................................................386 27.1.2 Block Diagram.............................................................................................................................................386 27.1.3 Glossary.......................................................................................................................................................387 27.2 External Signal Description..........................................................................................................................................388 27.3 Memory Map and Registers..........................................................................................................................................388 27.4 27.3.1 Flash Configuration Field Description.........................................................................................................388 27.3.2 Program Flash IFR Map...............................................................................................................................389 27.3.3 Register Descriptions...................................................................................................................................390 Functional Description..................................................................................................................................................398 27.4.1 Flash Protection............................................................................................................................................399 27.4.2 Interrupts......................................................................................................................................................399 27.4.3 Flash Operation in Low-Power Modes........................................................................................................400 27.4.4 Functional Modes of Operation...................................................................................................................400 27.4.5 Flash Reads and Ignored Writes..................................................................................................................400 27.4.6 Read While Write (RWW)...........................................................................................................................401 27.4.7 Flash Program and Erase..............................................................................................................................401 27.4.8 Flash Command Operations.........................................................................................................................401 27.4.9 Margin Read Commands.............................................................................................................................406 27.4.10 Flash Command Description........................................................................................................................407 27.4.11 Security........................................................................................................................................................420 27.4.12 Reset Sequence............................................................................................................................................422 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 17 Section number Title Page Chapter 28 Analog-to-Digital Converter (ADC) 28.1 28.2 28.3 28.4 Introduction...................................................................................................................................................................423 28.1.1 Features........................................................................................................................................................423 28.1.2 Block diagram..............................................................................................................................................424 ADC Signal Descriptions..............................................................................................................................................425 28.2.1 Analog Power (VDDA)...............................................................................................................................426 28.2.2 Analog Ground (VSSA)...............................................................................................................................426 28.2.3 Voltage Reference Select.............................................................................................................................426 28.2.4 Analog Channel Inputs (ADx).....................................................................................................................427 Register definition.........................................................................................................................................................427 28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................428 28.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................431 28.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................433 28.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................434 28.3.5 Compare Value Registers (ADCx_CVn).....................................................................................................435 28.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................436 28.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................438 28.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................439 28.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................440 28.3.10 ADC Plus-Side General Calibration Value Register (ADCx_CLPD).........................................................440 28.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................441 28.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)..........................................................441 28.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)..........................................................442 28.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)..........................................................442 28.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)..........................................................443 28.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)..........................................................443 Functional description...................................................................................................................................................444 28.4.1 Clock select and divide control....................................................................................................................444 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 18 Freescale Semiconductor, Inc. Section number 28.5 Page 28.4.2 Voltage reference selection..........................................................................................................................445 28.4.3 Hardware trigger and channel selects..........................................................................................................445 28.4.4 Conversion control.......................................................................................................................................446 28.4.5 Automatic compare function........................................................................................................................453 28.4.6 Calibration function.....................................................................................................................................455 28.4.7 User-defined offset function........................................................................................................................456 28.4.8 Temperature sensor......................................................................................................................................457 28.4.9 MCU wait mode operation...........................................................................................................................458 28.4.10 MCU Normal Stop mode operation.............................................................................................................458 28.4.11 MCU Low-Power Stop mode operation......................................................................................................459 Initialization information..............................................................................................................................................460 28.5.1 28.6 Title ADC module initialization example............................................................................................................460 Application information................................................................................................................................................462 28.6.1 External pins and routing.............................................................................................................................462 28.6.2 Sources of error............................................................................................................................................464 Chapter 29 Comparator (CMP) 29.1 Introduction...................................................................................................................................................................469 29.2 CMP features................................................................................................................................................................469 29.3 6-bit DAC key features.................................................................................................................................................470 29.4 ANMUX key features...................................................................................................................................................471 29.5 CMP, DAC and ANMUX diagram...............................................................................................................................471 29.6 CMP block diagram......................................................................................................................................................472 29.7 Memory map/register definitions..................................................................................................................................474 29.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................474 29.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................475 29.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................477 29.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................477 29.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................478 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 19 Section number 29.7.6 29.8 29.9 Title Page MUX Control Register (CMPx_MUXCR)..................................................................................................479 Functional description...................................................................................................................................................480 29.8.1 CMP functional modes.................................................................................................................................480 29.8.2 Power modes................................................................................................................................................489 29.8.3 Startup and operation...................................................................................................................................490 29.8.4 Low-pass filter.............................................................................................................................................490 CMP interrupts..............................................................................................................................................................493 29.10 DMA support................................................................................................................................................................493 29.11 CMP Asyncrhonous DMA support...............................................................................................................................493 29.12 Digital-to-analog converter...........................................................................................................................................494 29.13 DAC functional description..........................................................................................................................................494 29.13.1 Voltage reference source select....................................................................................................................494 29.14 DAC resets....................................................................................................................................................................495 29.15 DAC clocks...................................................................................................................................................................495 29.16 DAC interrupts..............................................................................................................................................................495 29.17 CMP Trigger Mode.......................................................................................................................................................495 Chapter 30 12-bit Digital-to-Analog Converter (DAC) 30.1 Introduction...................................................................................................................................................................497 30.2 Features.........................................................................................................................................................................497 30.3 Block diagram...............................................................................................................................................................497 30.4 Memory map/register definition...................................................................................................................................498 30.4.1 DAC Data Low Register (DACx_DATnL).................................................................................................499 30.4.2 DAC Data High Register (DACx_DATnH)................................................................................................499 30.4.3 DAC Status Register (DACx_SR)...............................................................................................................500 30.4.4 DAC Control Register (DACx_C0).............................................................................................................500 30.4.5 DAC Control Register 1 (DACx_C1)..........................................................................................................502 30.4.6 DAC Control Register 2 (DACx_C2)..........................................................................................................502 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 20 Freescale Semiconductor, Inc. Section number 30.5 Title Page Functional description...................................................................................................................................................503 30.5.1 DAC data buffer operation...........................................................................................................................503 30.5.2 DMA operation............................................................................................................................................504 30.5.3 Resets...........................................................................................................................................................504 30.5.4 Low-Power mode operation.........................................................................................................................504 Chapter 31 Timer/PWM Module (TPM) 31.1 31.2 31.3 31.4 Introduction...................................................................................................................................................................507 31.1.1 TPM Philosophy..........................................................................................................................................507 31.1.2 Features........................................................................................................................................................507 31.1.3 Modes of Operation.....................................................................................................................................508 31.1.4 Block Diagram.............................................................................................................................................508 TPM Signal Descriptions..............................................................................................................................................509 31.2.1 TPM_EXTCLK -- TPM External Clock....................................................................................................509 31.2.2 TPM_CHn -- TPM Channel (n) I/O Pin.....................................................................................................510 Memory Map and Register Definition..........................................................................................................................510 31.3.1 Status and Control (TPMx_SC)...................................................................................................................512 31.3.2 Counter (TPMx_CNT).................................................................................................................................513 31.3.3 Modulo (TPMx_MOD)................................................................................................................................514 31.3.4 Channel (n) Status and Control (TPMx_CnSC)...........................................................................................515 31.3.5 Channel (n) Value (TPMx_CnV).................................................................................................................517 31.3.6 Capture and Compare Status (TPMx_STATUS).........................................................................................517 31.3.7 Configuration (TPMx_CONF).....................................................................................................................519 Functional Description..................................................................................................................................................521 31.4.1 Clock Domains.............................................................................................................................................521 31.4.2 Prescaler.......................................................................................................................................................522 31.4.3 Counter.........................................................................................................................................................522 31.4.4 Input Capture Mode.....................................................................................................................................524 31.4.5 Output Compare Mode.................................................................................................................................525 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 21 Section number Title Page 31.4.6 Edge-Aligned PWM (EPWM) Mode...........................................................................................................526 31.4.7 Center-Aligned PWM (CPWM) Mode........................................................................................................528 31.4.8 Registers Updated from Write Buffers........................................................................................................530 31.4.9 DMA............................................................................................................................................................530 31.4.10 Reset Overview............................................................................................................................................531 31.4.11 TPM Interrupts.............................................................................................................................................531 Chapter 32 Periodic Interrupt Timer (PIT-RTI) 32.1 Introduction...................................................................................................................................................................533 32.1.1 Block diagram..............................................................................................................................................533 32.1.2 Features........................................................................................................................................................534 32.2 Signal description..........................................................................................................................................................534 32.3 Memory map/register description.................................................................................................................................535 32.4 32.3.1 PIT Module Control Register (PIT_MCR)..................................................................................................535 32.3.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)...............................................................................537 32.3.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)...............................................................................537 32.3.4 Timer Load Value Register (PIT_LDVALn)...............................................................................................538 32.3.5 Current Timer Value Register (PIT_CVALn).............................................................................................538 32.3.6 Timer Control Register (PIT_TCTRLn)......................................................................................................539 32.3.7 Timer Flag Register (PIT_TFLGn)..............................................................................................................540 Functional description...................................................................................................................................................540 32.4.1 General operation.........................................................................................................................................540 32.4.2 Interrupts......................................................................................................................................................542 32.4.3 Chained timers.............................................................................................................................................542 32.5 Initialization and application information.....................................................................................................................542 32.6 Example configuration for chained timers....................................................................................................................543 32.7 Example configuration for the lifetime timer...............................................................................................................544 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 22 Freescale Semiconductor, Inc. Section number Title Page Chapter 33 Low-Power Timer (LPTMR) 33.1 33.2 Introduction...................................................................................................................................................................547 33.1.1 Features........................................................................................................................................................547 33.1.2 Modes of operation......................................................................................................................................547 LPTMR signal descriptions..........................................................................................................................................548 33.2.1 33.3 33.4 Detailed signal descriptions.........................................................................................................................548 Memory map and register definition.............................................................................................................................548 33.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)......................................................................549 33.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)................................................................................550 33.3.3 Low Power Timer Compare Register (LPTMRx_CMR).............................................................................552 33.3.4 Low Power Timer Counter Register (LPTMRx_CNR)...............................................................................552 Functional description...................................................................................................................................................553 33.4.1 LPTMR power and reset..............................................................................................................................553 33.4.2 LPTMR clocking..........................................................................................................................................553 33.4.3 LPTMR prescaler/glitch filter......................................................................................................................553 33.4.4 LPTMR compare..........................................................................................................................................555 33.4.5 LPTMR counter...........................................................................................................................................555 33.4.6 LPTMR hardware trigger.............................................................................................................................556 33.4.7 LPTMR interrupt..........................................................................................................................................556 Chapter 34 Real Time Clock (RTC) 34.1 34.2 Introduction...................................................................................................................................................................557 34.1.1 Features........................................................................................................................................................557 34.1.2 Modes of operation......................................................................................................................................557 34.1.3 RTC Signal Descriptions.............................................................................................................................557 Register definition.........................................................................................................................................................558 34.2.1 RTC Time Seconds Register (RTC_TSR)...................................................................................................559 34.2.2 RTC Time Prescaler Register (RTC_TPR)..................................................................................................559 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 23 Section number 34.3 Title Page 34.2.3 RTC Time Alarm Register (RTC_TAR).....................................................................................................560 34.2.4 RTC Time Compensation Register (RTC_TCR).........................................................................................560 34.2.5 RTC Control Register (RTC_CR)................................................................................................................561 34.2.6 RTC Status Register (RTC_SR)..................................................................................................................563 34.2.7 RTC Lock Register (RTC_LR)....................................................................................................................564 34.2.8 RTC Interrupt Enable Register (RTC_IER).................................................................................................565 Functional description...................................................................................................................................................566 34.3.1 Power, clocking, and reset...........................................................................................................................566 34.3.2 Time counter................................................................................................................................................567 34.3.3 Compensation...............................................................................................................................................567 34.3.4 Time alarm...................................................................................................................................................568 34.3.5 Update mode................................................................................................................................................568 34.3.6 Register lock................................................................................................................................................569 34.3.7 Interrupt........................................................................................................................................................569 Chapter 35 Serial Peripheral Interface (SPI) 35.1 35.2 35.3 Introduction...................................................................................................................................................................571 35.1.1 Features........................................................................................................................................................571 35.1.2 Modes of Operation.....................................................................................................................................572 35.1.3 Block Diagrams............................................................................................................................................573 External Signal Description..........................................................................................................................................575 35.2.1 SPSCK -- SPI Serial Clock.........................................................................................................................575 35.2.2 MOSI -- Master Data Out, Slave Data In...................................................................................................576 35.2.3 MISO -- Master Data In, Slave Data Out...................................................................................................576 35.2.4 SS -- Slave Select........................................................................................................................................576 Memory Map and Register Descriptions......................................................................................................................577 35.3.1 SPI control register 1 (SPIx_C1)..................................................................................................................577 35.3.2 SPI control register 2 (SPIx_C2)..................................................................................................................579 35.3.3 SPI baud rate register (SPIx_BR).................................................................................................................580 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 24 Freescale Semiconductor, Inc. Section number 35.4 35.5 Title Page 35.3.4 SPI status register (SPIx_S).........................................................................................................................581 35.3.5 SPI data register (SPIx_D)...........................................................................................................................582 35.3.6 SPI match register (SPIx_M).......................................................................................................................583 Functional Description..................................................................................................................................................584 35.4.1 General.........................................................................................................................................................584 35.4.2 Master Mode................................................................................................................................................584 35.4.3 Slave Mode..................................................................................................................................................586 35.4.4 SPI Transmission by DMA..........................................................................................................................587 35.4.5 SPI Clock Formats.......................................................................................................................................589 35.4.6 SPI Baud Rate Generation...........................................................................................................................592 35.4.7 Special Features...........................................................................................................................................592 35.4.8 Error Conditions...........................................................................................................................................594 35.4.9 Low Power Mode Options...........................................................................................................................595 35.4.10 Reset.............................................................................................................................................................596 35.4.11 Interrupts......................................................................................................................................................597 Initialization/Application Information..........................................................................................................................598 35.5.1 Initialization Sequence.................................................................................................................................598 35.5.2 Pseudo-Code Example.................................................................................................................................599 Chapter 36 Inter-Integrated Circuit (I2C) 36.1 Introduction...................................................................................................................................................................603 36.1.1 Features........................................................................................................................................................603 36.1.2 Modes of operation......................................................................................................................................604 36.1.3 Block diagram..............................................................................................................................................604 36.2 I2C signal descriptions..................................................................................................................................................605 36.3 Memory map and register descriptions.........................................................................................................................605 36.3.1 I2C Address Register 1 (I2Cx_A1)..............................................................................................................606 36.3.2 I2C Frequency Divider register (I2Cx_F)....................................................................................................607 36.3.3 I2C Control Register 1 (I2Cx_C1)...............................................................................................................608 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 25 Section number 36.4 36.5 Title Page 36.3.4 I2C Status register (I2Cx_S)........................................................................................................................609 36.3.5 I2C Data I/O register (I2Cx_D)...................................................................................................................611 36.3.6 I2C Control Register 2 (I2Cx_C2)...............................................................................................................612 36.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT).......................................................................613 36.3.8 I2C Range Address register (I2Cx_RA)......................................................................................................614 36.3.9 I2C SMBus Control and Status register (I2Cx_SMB).................................................................................615 36.3.10 I2C Address Register 2 (I2Cx_A2)..............................................................................................................616 36.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................617 36.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................617 Functional description...................................................................................................................................................617 36.4.1 I2C protocol.................................................................................................................................................617 36.4.2 10-bit address...............................................................................................................................................623 36.4.3 Address matching.........................................................................................................................................624 36.4.4 System management bus specification........................................................................................................625 36.4.5 Resets...........................................................................................................................................................628 36.4.6 Interrupts......................................................................................................................................................628 36.4.7 Programmable input glitch filter..................................................................................................................630 36.4.8 Address matching wakeup...........................................................................................................................631 36.4.9 DMA support...............................................................................................................................................631 Initialization/application information...........................................................................................................................632 Chapter 37 Universal Asynchronous Receiver/Transmitter (UART0) 37.1 37.2 Introduction...................................................................................................................................................................635 37.1.1 Features........................................................................................................................................................635 37.1.2 Modes of operation......................................................................................................................................636 37.1.3 Block diagram..............................................................................................................................................636 Register definition.........................................................................................................................................................638 37.2.1 UART Baud Rate Register High (UARTx_BDH).......................................................................................639 37.2.2 UART Baud Rate Register Low (UARTx_BDL)........................................................................................640 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 26 Freescale Semiconductor, Inc. Section number 37.3 Title Page 37.2.3 UART Control Register 1 (UARTx_C1).....................................................................................................640 37.2.4 UART Control Register 2 (UARTx_C2).....................................................................................................642 37.2.5 UART Status Register 1 (UARTx_S1)........................................................................................................643 37.2.6 UART Status Register 2 (UARTx_S2)........................................................................................................645 37.2.7 UART Control Register 3 (UARTx_C3).....................................................................................................647 37.2.8 UART Data Register (UARTx_D)...............................................................................................................648 37.2.9 UART Match Address Registers 1 (UARTx_MA1)....................................................................................649 37.2.10 UART Match Address Registers 2 (UARTx_MA2)....................................................................................650 37.2.11 UART Control Register 4 (UARTx_C4).....................................................................................................650 37.2.12 UART Control Register 5 (UARTx_C5).....................................................................................................651 Functional description...................................................................................................................................................652 37.3.1 Baud rate generation....................................................................................................................................652 37.3.2 Transmitter functional description...............................................................................................................652 37.3.3 Receiver functional description...................................................................................................................654 37.3.4 Additional UART functions.........................................................................................................................657 37.3.5 Interrupts and status flags............................................................................................................................659 Chapter 38 General-Purpose Input/Output (GPIO) 38.1 38.2 Introduction...................................................................................................................................................................661 38.1.1 Features........................................................................................................................................................661 38.1.2 Modes of operation......................................................................................................................................661 38.1.3 GPIO signal descriptions.............................................................................................................................662 Memory map and register definition.............................................................................................................................663 38.2.1 Port Data Output Register (GPIOx_PDOR).................................................................................................664 38.2.2 Port Set Output Register (GPIOx_PSOR)....................................................................................................665 38.2.3 Port Clear Output Register (GPIOx_PCOR)................................................................................................665 38.2.4 Port Toggle Output Register (GPIOx_PTOR).............................................................................................666 38.2.5 Port Data Input Register (GPIOx_PDIR).....................................................................................................666 38.2.6 Port Data Direction Register (GPIOx_PDDR).............................................................................................667 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 27 Section number 38.3 38.4 Title Page FGPIO memory map and register definition................................................................................................................667 38.3.1 Port Data Output Register (FGPIOx_PDOR)..............................................................................................668 38.3.2 Port Set Output Register (FGPIOx_PSOR).................................................................................................668 38.3.3 Port Clear Output Register (FGPIOx_PCOR).............................................................................................669 38.3.4 Port Toggle Output Register (FGPIOx_PTOR)...........................................................................................669 38.3.5 Port Data Input Register (FGPIOx_PDIR)...................................................................................................670 38.3.6 Port Data Direction Register (FGPIOx_PDDR)..........................................................................................670 Functional description...................................................................................................................................................671 38.4.1 General-purpose input..................................................................................................................................671 38.4.2 General-purpose output................................................................................................................................671 38.4.3 IOPORT.......................................................................................................................................................671 Chapter 39 Touch Sensing Input (TSI) 39.1 39.2 Introduction...................................................................................................................................................................673 39.1.1 Features........................................................................................................................................................673 39.1.2 Modes of operation......................................................................................................................................673 39.1.3 Block diagram..............................................................................................................................................674 External signal description............................................................................................................................................675 39.2.1 39.3 39.4 TSI[15:0]......................................................................................................................................................675 Register definition.........................................................................................................................................................675 39.3.1 TSI General Control and Status Register (TSIx_GENCS)..........................................................................675 39.3.2 TSI DATA Register (TSIx_DATA).............................................................................................................680 39.3.3 TSI Threshold Register (TSIx_TSHD)........................................................................................................681 Functional description...................................................................................................................................................681 39.4.1 Capacitance measurement............................................................................................................................682 39.4.2 TSI measurement result...............................................................................................................................685 39.4.3 Enable TSI module.......................................................................................................................................685 39.4.4 Software and hardware trigger.....................................................................................................................685 39.4.5 Scan times....................................................................................................................................................686 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 28 Freescale Semiconductor, Inc. Section number Title Page 39.4.6 Clock setting................................................................................................................................................686 39.4.7 Reference voltage.........................................................................................................................................686 39.4.8 Current source..............................................................................................................................................687 39.4.9 End of scan...................................................................................................................................................687 39.4.10 Out-of-range interrupt..................................................................................................................................687 39.4.11 Wake up MCU from low power modes.......................................................................................................688 39.4.12 DMA function support.................................................................................................................................688 39.4.13 Noise detection mode...................................................................................................................................688 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 29 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 30 Freescale Semiconductor, Inc. Chapter 1 About This Document 1.1 Overview 1.1.1 Purpose This document describes the features, architecture, and programming model of the Freescale KL05 microcontroller. 1.1.2 Audience This document is primarily for system architects and software application developers who are using or considering using the KL05 microcontroller in a system. 1.2 Conventions 1.2.1 Numbering systems The following suffixes identify different numbering systems: This suffix Identifies a b Binary number. For example, the binary equivalent of the number 5 is written 101b. In some cases, binary numbers are shown with the prefix 0b. d Decimal number. Decimal numbers are followed by this suffix only when the possibility of confusion exists. In general, decimal numbers are shown without a suffix. h Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 31 Conventions 1.2.2 Typographic notation The following typographic notation is used throughout this document: Example Description placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers. code Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type is also used for example code. Instruction mnemonics and directives in text and tables are shown in all caps; for example, BSR. SR[SCM] A mnemonic in brackets represents a named field in a register. This example refers to the Scaling Mode (SCM) field in the Status Register (SR). REVNO[6:4], XAD[7:0] Numbers in brackets and separated by a colon represent either: * A subset of a register's named field For example, REVNO[6:4] refers to bits 6-4 that are part of the COREREV field that occupies bits 6-0 of the REVNO register. * A continuous range of individual signals of a bus For example, XAD[7:0] refers to signals 7-0 of the XAD bus. 1.2.3 Special terms The following terms have special meanings: Term Meaning asserted Refers to the state of a signal as follows: * An active-high signal is asserted when high (1). * An active-low signal is asserted when low (0). deasserted Refers to the state of a signal as follows: * An active-high signal is deasserted when low (0). * An active-low signal is deasserted when high (1). In some cases, deasserted signals are described as negated. reserved Refers to a memory space, register, or field that is either reserved for future use or for which, when written to, the module or chip behavior is unpredictable. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 32 Freescale Semiconductor, Inc. Chapter 2 Introduction 2.1 Overview This chapter provides an overview of the Kinetis L series of ARM(R) CortexTM-M0+ MCUs and KL05 product family. It also presents high-level descriptions of the modules available on the devices covered by this document. 2.2 Kinetis L Series The Kinetis L series is the most scalable portfolio of ultra low-power, mixed-signal ARM Cortex-M0+ MCUs in the industry. The portfolio includes 5 MCU families that offer a broad range of memory, peripheral and package options. Kinetis L Series families share common peripherals and pin-counts allowing developers to migrate easily within an MCU family or between MCU families to take advantage of more memory or feature integration. This scalability allows developers to standardize on the Kinetis L Series for their end product platforms, maximising hardware and software reuse and reducing timeto-market. Features common to all Kinetis L series families include: * 48 MHz ARM Cortex-M0+ core * High-speed 12/16-bit analog-to-digital converters * 12-bit digital-to-analog converters for all series except for KLx4/KLx2 family * High-speed analog comparators * Low-power touch sensing with wake-up on touch from reduced power states for all series except for KLx4/KLx2 family * Powerful timers for a broad range of applications including motor control * Low power focused serial communication interfaces such as low power UART, SPI, I2C etc. * Single power supply: 1.71V - 3.6V with multiple low-power modes support single operation temperature: -40 ~ 105 C (exclude CSP package) KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 33 Kinetis L Series Kinetis L series MCU families combine the latest low-power innovations with precision mixed-signal capability and a broad range of communication, connectivity, and humanmachine interface peripherals. Each MCU family is supported by a market-leading enablement bundle from Freescale and numerous ARM 3rd party ecosystem partners. The KL0x family is the entry-point to the Kinetis L series and is pin compatible with the 8-bit S08PT family. The KL1x/2x/3x/4x families are compatible with each other and their equivalent ARM Cortex-M4 Kinetis K series families - K10/20/30/40. Family Program Flash Packages KL4x Family 128-256KB 64-121pin KL3x Family 64-256KB 64-121pin KL2x Family 32-256KB 32-121pin KL1x Family 32-256KB 32-80pin KL0x Family 16-48pin 8-32KB Low power Mixed signal Key Features USB Segment LCD Figure 2-1. Kinetis L series families of MCU portfolio All Kinetis L series families include a powerful array of analog, communication and timing and control peripherals with the level of feature integration increasing with flash memory size and the pin count. Features within the Kinetis L series families include: * Core and Architecture: * ARM Cortex-M0+ Core running up to 48 MHz with zero wait state execution from memories * Single-cycle access to I/O: Up to 50 percent faster than standard I/O, improves reaction time to external events allowing bit banging and software protocol emulation * Two-stage pipeline: Reduced number of cycles per instruction (CPI), enabling faster branch instruction and ISR entry, and reducing power consumption * Excellent code density vs. 8-bit and 16-bit MCUs - reduces flash size, system cost and power consumption KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 34 Freescale Semiconductor, Inc. Chapter 2 Introduction * * * * * Optimized access to program memory: Accesses on alternate cycles reduces power consumption * 100 percent compatible with ARM Cortex-M0 and a subset ARM CortexM3/M4: Reuse existing compilers and debug tools * Simplified architecture: 56 instructions and 17 registers enables easy programming and efficient packaging of 8/16/32-bit data in memory * Linear 4 GB address space removes the need for paging/banking, reducing software complexity * ARM third-party ecosystem support: Software and tools to help minimize development time/cost * Micro Trace Buffer: Lightweight trace solution allows fast bug identification and correction * BME: Bit manipulation engine reduces code size and cycles for bit oriented operations to peripheral registers eliminating traditional methods where the core would need to perform read-modify-write operations. * Up to 4-channel DMA for peripheral and memory servicing with minimal CPU intervention (feature not available on KL02 family) Ultra low-power: * Extreme dynamic efficiency: 32-bit ARM Cortex-M0+ core combined with Freescale 90 nm thin film storage flash technology delivers 50% energy savings per Coremark versus the closest 8/16-bit competitive solution * Multiple flexible low-power modes, including new operation clocking option which reduces dynamic power by shutting off bus and system clocks for lowest power core processing. Peripherals with an alternate asynchronous clock source can continue operation. * UART, SPI, I2C, ADC, DAC, TPM, LPT, and DMA support low-power mode operation without waking up the core Memory: * Scalable memory footprints from 8 KB flash / 1 KB SRAM to 256 KB flash / 32 KB SRAM * Embedded 64 B cache memory for optimizing bus bandwidth and flash execution performance (32 B cache on KL02 family) Mixed-signal analog: * Fast, high precision 16-, or 12-bit ADC with optional differential pairs, 12-bit DAC, high speed comparators. Powerful signal conditioning, conversion and analysis capability with reduced system cost (12-bit DAC not available on KL02 family) Human Machine Interface (HMI): * Optional capacitive Touch Sensing Interface with full low-power support and minimal current adder when enabled * Segment LCD controller KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 35 KL05 Sub-Family Introduction * Connectivity and Communications: * Up to three UARTs, all UARTs support DMA transfers, and can trigger when data on bus is detected, UART0 supports 4x to 32x over sampling ratio. Asynchronous transmit and receive operation for operating in STOP/VLPS modes. * Up to two SPIs * Up to two I2Cs * Full-speed USB OTG controller with on-chip transceiver * 5 V to 3.3 V USB on-chip regulator * Up to one I2S * Reliability, Safety and Security: * Internal watchdog with independent clock source * Timing and Control: * Powerful timer modules which support general purpose, PWM, and motor control functions * Periodic Interrupt Timer for RTOS task scheduler time base or trigger source for ADC conversion and timer modules * System: * GPIO with pin interrupt functionality * Wide operating voltage range from 1.71 V to 3.6 V with flash programmable down to 1.71 V with fully functional flash and analog peripherals * Ambient operating temperature ranges from -40 C to 105 C 2.3 KL05 Sub-Family Introduction The device is highly-integrated, market leading ultra low power 32-bit microcontroller based on the enhanced Cortex-M0+ (CM0+) core platform. The family derivatives feature: * Core platform clock up to 48 MHz, bus clock up to 24 MHz * Memory option is up to 32 KB Flash and 4 KB RAM * Wide operating voltage ranges from 1.71V to 3.6V with full functional Flash program/erase/read operations * Multiple package options from 24-pin to 48-pin * Ambient operating temperature ranges from -40 C to 105 C The family acts as an ultra low power, cost effective microcontroller to provide developers an appropriate entry-level 32-bit solution. The family is next generation MCU solution for low cost, low power, high performance devices applications. It's valuable for cost-sensitive, portable applications requiring long battery life-time. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 36 Freescale Semiconductor, Inc. Chapter 2 Introduction 2.4 Module functional categories The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail. Table 2-1. Module functional categories Module category Description ARM Cortex-M0+ core * 32-bit MCU core from ARM's Cortex-M class, 1.77 CoreMark(R)/MHz from single-cycle access memories, 48 MHz CPU frequency System * System integration module * Power management and mode controllers * Multiple power modes available based on run, wait, stop, and powerdown modes * Miscellaneous control module * Low-leakage wakeup unit * Peripheral bridge * Direct memory access (DMA) controller with multiplexer to increase available DMA requests * COP watchdog Memories * Internal memories include: * Up to 32 KB flash memory * up to 4 KB SRAM Clocks * Multiple clock generation options available from internally- and externallygenerated clocks * MCG module with FLL for systems and CPU clock sources * Low power 1 kHz RC oscillator for RTC and COP watchdog * System oscillator to provide clock source for the MCU Security * COP watchdog timer (COP) Analog * 12-bit analog-to-digital converters with DMA supported * Comparator (CMP) with internal 6-bit digital-to-analog converter (DAC) * 12-bit DAC with DMA support and two 16-bit data buffer Timers * * * * * * Communications * One8-bit serial peripheral interface * One inter-integrated circuit (I2C) module * One low power UART module Human-Machine Interfaces (HMI) * General purpose input/output controller * Capacitive touch sense input interface enabled in hardware One 6-channel TPM One 2-channel TPM 2-channel periodic interrupt timer Real time clock Low-power timer System tick timer 2.4.1 ARM(R) CortexTM-M0+ Core Modules The following core modules are available on this device. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 37 Module functional categories Table 2-2. Core modules Module Description ARM(R) CortexTM-M0+ The ARM(R) CortexTM-M0+ is the newest member of the Cortex M Series of processors targeting microcontroller applications focused on very cost sensitive, deterministic, interrupt driven environments. The Cortex M0+ processor is based on the ARMv6 Architecture and Thumb(R)-2 ISA and is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4 cores. NVIC The ARMv6-M exception model and nested-vectored interrupt controller (NVIC) implement a relocatable vector table supporting many external interrupts, a single non-maskable interrupt (NMI), and priority levels. The NVIC replaces shadow registers with equivalent system and simplified programmability. The NVIC contains the address of the function to execute for a particular handler. The address is fetched via the instruction port allowing parallel register stacking and look-up. The first sixteen entries are allocated to ARM internal sources with the others mapping to MCU-defined interrupts. AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is to detect asynchronous wake-up events in stop modes and signal to clock control logic to resume system clocking. After clock restart, the NVIC observes the pending interrupt and performs the normal interrupt or event processing. Single-cycle I/O Port For high-speed, single-cycle access to peripherals, the Cortex-M0+ processor implements a dedicated single-cycle I/O port. Debug interfaces Most of this device's debug is based on the ARM CoreSightTM architecture. One debug interface is supported: * Serial Wire Debug (SWD) 2.4.2 System Modules The following system modules are available on this device. Table 2-3. System modules Module Description System integration module (SIM) The SIM includes integration logic and several module configuration settings. System mode controller The SMC provides control and protection on entry and exit to each power mode, control for the Power management controller (PMC), and reset entry and exit for the complete MCU. Power management controller (PMC) The PMC provides the user with multiple power options. Multiple modes are supported that allow the user to optimize power consumption for the level of functionality needed. Includes power-on-reset (POR) and integrated low voltage detect (LVD) with reset (brownout) capability and selectable LVD trip points. Miscellaneous control module (MCM) The MCM includes integration logic and details. Crossbar switch (XBS) The XBS connects bus masters and bus slaves, allowing all bus masters to access different bus slaves simultaneously and providing arbitration among the bus masters when they access the same slave. Low-leakage wakeup unit (LLWU) The LLWU module allows the device to wake from low leakage power modes (LLS and VLLS) through various internal peripheral and external pin sources. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 38 Freescale Semiconductor, Inc. Chapter 2 Introduction Table 2-3. System modules (continued) Module Description Peripheral bridge The peripheral bridge converts the crossbar switch interface to an interface to access a majority of peripherals on the device. DMA multiplexer (DMAMUX) The DMA multiplexer selects from many DMA requests down to 4 for the DMA controller. Direct memory access (DMA) controller The DMA controller provides programmable channels with transfer control descriptors for data movement via dual-address transfers for 8-, 16- and 32-bit data values. Computer operating properly watchdog (WDOG) The WDOG monitors internal system operation and forces a reset in case of failure. It can run from an independent 1 kHz low power oscillator with a programmable refresh window to detect deviations in program flow or system frequency. 2.4.3 Memories and Memory Interfaces The following memories and memory interfaces are available on this device. Table 2-4. Memories and memory interfaces Module Description Flash memory Program flash memory -- up to 32 KB of the non-volatile flash memory that can execute program code Flash memory controller Manages the interface between the device and the on-chip flash memory. SRAM Up to 4 KB internal system RAM. 2.4.4 Clocks The following clock modules are available on this device. Table 2-5. Clock modules Module Description Multipurpose Clock Generator (MCG) MCG module containing a frequency-locked-loop (FLL) controlled by internal or external reference oscillator. System oscillator The system oscillator, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 2.4.5 Security and Integrity modules The following security and integrity modules are available on this device: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 39 Module functional categories Table 2-6. Security and integrity modules Module Description Watchdog Timer (WDOG) Watchdog Timer keeps a watch on the system functioning and resets it in case of its failure. 2.4.6 Analog modules The following analog modules are available on this device: Table 2-7. Analog modules Module Description Analog-to-digital converters (ADC) 12-bit successive-approximation ADC module. Analog comparators One comparator that compares two analog input voltages across the full range of the supply voltage and can trigger an ADC acquisition, TPM update, or CPU interrupt. 6-bit digital-to-analog converters (DAC) 64-tap resistor ladder network which provides a selectable voltage reference for comparator. 12-bit digital-to-analog converters (DAC) Low-power general-purpose DAC, whose output can be placed on an external pin or set as one of the inputs to the analog comparator or ADC. 2.4.7 Timer modules The following timer modules are available on this device: Table 2-8. Timer modules Module Description Timer/PWM module (TPM) * Selectable TPM clock mode * Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 * 16-bit free-running counter or modulo counter with counting be up or updown * Six configurable channels for input capture, output compare, or edge-aligned PWM mode * Support the generation of an interrupt and/or DMA request per channel * Support the generation of an interrupt and/or DMA request when the counter overflows * Support selectable trigger input to optionally reset or cause the counter to start incrementing. * Support the generation of hardware triggers when the counter overflows and per channel Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 40 Freescale Semiconductor, Inc. Chapter 2 Introduction Table 2-8. Timer modules (continued) Module Description Periodic interrupt timers (PIT) * * * * * One general purpose interrupt timer Interrupt timers for triggering ADC conversions 32-bit counter resolution Clocked by bus clock frequency DMA support Low power timer (LPTMR) * 16-bit time counter or pulse counter with compare * Configurable clock source for prescaler/glitch filter * Configurable input source for pulse counter Real-time counter (RTC) * 16-bit up-counter * 16-bit modulo match limit * Software controllable periodic interrupt on match * Software selectable clock sources for input to prescaler with programmable 16-bit prescaler * XOSC 32.678 kHz nominal * LPO (~1 kHz) * External RTC_CLKIN 2.4.8 Communication interfaces The following communication interfaces are available on this device: Table 2-9. Communication modules Module Description Serial peripheral interface (SPI) Synchronous serial bus for communication to an external device Inter-integrated circuit (I2C) Allows communication between a number of devices. Also supports the System Management Bus (SMBus) Specification, version 2. Universal asynchronous receiver/ transmitters (UART) One low power UART module that retains functional in stop modes. 2.4.9 Human-machine interfaces The following human-machine interfaces (HMI) are available on this device: Table 2-10. HMI modules Module Description General purpose input/output (GPIO) Some general purpose input or output (GPIO) pins are capable of interrupt and DMA request generation. Capacitive touch sense input (TSI) Contains up to 12 channel inputs for capacitive touch sensing applications. Operation is available in low-power modes via interrupts. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 41 Orderable part numbers 2.5 Orderable part numbers The following table summarizes the part numbers of the devices covered by this document. Table 2-11. Orderable part numbers summary Freescale part number CPU frequency Pin count Package Total flash memory RAM Temperature range MKL05Z8VFK4 48 MHz 24 QFN 8 KB 1 KB -40 to 105 C MKL05Z16VFK4 48 MHz 24 QFN 16 KB 2 KB -40 to 105 C MKL05Z32VFK4 48 MHz 24 QFN 32 KB 4 KB -40 to 105 C MKL05Z8VLC4 48 MHz 32 LQFP 8 KB 1 KB -40 to 105 C MKL05Z16VLC4 48 MHz 32 LQFP 16 KB 2 KB -40 to 105 C MKL05Z32VLC4 48 MHz 32 LQFP 32 KB 4 KB -40 to 105 C MKL05Z8VFM4 48 MHz 32 QFN 8 KB 1 KB -40 to 105 C MKL05Z16VFM4 48 MHz 32 QFN 16 KB 2 KB -40 to 105 C MKL05Z32VFM4 48 MHz 32 QFN 32 KB 4 KB -40 to 105 C MKL05Z16VLF4 48 MHz 48 LQFP 16 KB 2 KB -40 to 105 C MKL05Z32VLF4 48 MHz 48 LQFP 32 KB 4 KB -40 to 105 C KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 42 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.1 Introduction This chapter provides details on the individual modules of the microcontroller. It includes: * Module block diagrams showing immediate connections within the device * Specific module-to-module interactions not necessarily discussed in the individual module chapters * Links for more information 3.2 Module to Module Interconnects 3.2.1 Module to Module Interconnects The below table captures the module to module interconnections for this device. Table 3-1. Module to Module Interconnects Peripheral Signal -- to Peripheral TPM1 CH0F, CH1F to ADC (Trigger) Use Case Control ADC Triggering SOPT7_ADCAL (A AND B) TTRGEN = 0 Comment Ch0 is A, and Ch1 is B, selecting this ADC trigger is for supporting A and B triggering. In Stop and VLPS modes, the second trigger must be set to >10us after the first trigger Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 43 Module to Module Interconnects Table 3-1. Module to Module Interconnects (continued) Peripheral Signal -- to Peripheral Use Case Control Comment LPTMR Hardware trigger to ADC (Trigger) ADC Triggering SOPT7_ADC0T (A or B) RGSEL (4 bit field), ADC0PRETRG SEL to select A or B -- TPMx TOF to ADC (Trigger) ADC Triggering SOPT7_ADC0T (A or B) RGSEL (4 bit field), SOPT7_ADC0P RETRGSEL to select A or B -- PIT CHx TIF0, TIF1 to ADC (Trigger) ADC Triggering SOPT7_ADC0T (A or B) RGSEL (4 bit field), ADC0PRETRG SEL to select A or B -- RTC ALARM or SECONDS to ADC (Trigger) ADC Triggering SOPT7_ADC0T (A or B) RGSEL (4 bit field) ADC0PRETRG SEL to select A or B -- EXTRG_IN EXTRG_IN to ADC (Trigger) ADC Triggering SOPT7_ADC0T (A or B) RGSEL (4 bit field) ADC0PRETRG SEL to select A or B -- CMP0 CMP0_OUT to ADC (Trigger) ADC Triggering SOPT7_ADC0T (Aor B) RGSEL (4 bit field) ADC0PRETRG SEL to select A or B -- CMP0 CMP0_OUT to LPTMR_ALT0 Count CMP events LPTMR_CSR[T PS] -- CMP0 CMP0_OUT to TPM1 CH0 Input capture SOPT4_TPM1C H0SRC -- CMP0 CMP0_OUT to UART0_RX IR interface SOPT5_UART0 RXSRC -- LPTMR Hardware trigger to CMPx Low power CMP_CR1[TRIG triggering of the M] comparator -- LPTMR Hardware trigger to TPMx TPM Trigger input TPMx_CONF[T RGSEL] (4 bit field) -- TPMx TOF to TPMx TPM Trigger input TPMx_CONF[T RGSEL] (4 bit field) -- Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 44 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-1. Module to Module Interconnects (continued) Peripheral Signal -- to Peripheral Use Case Control Comment TPM1 Timebase to TPMx TPM Global timebase input TPMx_CONF[G TBEEN] -- PIT CHx TIF0, TIF1 to TPMx TPM Trigger input TPMx_CONF[T RGSEL] (4 bit field) If PIT is triggering the TPM, the TPM clock must be faster than Bus clock. RTC ALARM or SECONDS to TPMx TPM Trigger input TPMx_CONF[T RGSEL] (4 bit field) -- EXTRG_IN EXTRG_IN to TPMx TPM Trigger input TPMx_CONF[T RGSEL] (4 bit field) -- CMP0 CMP0_OUT to TPMx TPM Trigger input TPMx_CONF[T RGSEL] (4 bit field) -- LPTMR Hardware trigger to TSI TSI triggering TSI selects HW trigger -- UART0 UART0_TX to Modulated by TPM1 CH0 UART modulation SOPT5_UART0 TXSRC -- PIT TIF0 to DAC Advance DAC FIFO DAC HWTRG Select -- PIT TIF0 to DMA CH0 DMA HW Trigger DMA MUX register option -- PIT TIF1 to DMA CH1 DMA HW Trigger DMA MUX register option -- 3.2.2 Analog reference options Several analog blocks have selectable reference voltages as shown in the below table. These options allow analog peripherals to share or have separate analog references. Care should be taken when selecting analog references to avoid cross talk noise. Table 3-2. Analog reference options Module Reference option Comment/ Reference selection 12-bit SAR ADC 1 - VREFH Selected by ADCx_SC2[REFSEL] bits 2 - VDDA 3 - Reserved 12-bit DAC 1 - VREFH 2- CMP with 6-bit DAC Selected by DACx_C0[DACRFS] bit VDDA1 Vin1 - VREFH Vin2 - Selected by CMPx_DACCR[VRSEL] bit VDD1 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 45 Core Modules 1. Use this option for the best ADC operation. 3.3 Core Modules 3.3.1 ARM Cortex-M0+ Core Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at www.arm.com. Debug Crossbar switch Interrupts ARM Cortex-M0+ Core Figure 3-1. Core configuration Table 3-3. Reference links to related information Topic Related module Reference Full description ARM Cortex-M0+ core, r0p0 ARM Cortex-M0+ Technical Reference Manual, r0p0 System memory map System memory map Clocking Clock distribution Power management Power management System/instruction/data bus module Crossbar switch Crossbar switch Debug Serial Wire Debug (SWD) Debug Interrupts Nested Vectored Interrupt Controller (NVIC) NVIC Miscellaneous Control Module (MCM) MCM 3.3.1.1 ARM Cortex M0+ Core The ARM Cortex M0+ parameter settings are as follows: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 46 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-4. ARM Cortex-M0+ parameter settings Parameter Verilog Name Value Description Arch Clock Gating ACG 1 = Present DAP Slave Port Support AHBSLV 1 DAP ROM Table Base BASEADDR 0xF000_2003 Endianess BE 0 Little endian control for data transfers Breakpoints BKPT 2 Implements 2 breakpoints Implements architectural clock gating Support any AHB debug access port (like the CM4 DAP) Base address for DAP ROM table Debug Support DBG 1 = Present Halt Event Support HALTEV 1 = Present I/O Port IOP 1 = Present Implements single-cycle ld/st accesses to special address space IRQ Mask Enable IRQDIS 0x00000000 Assume (for now) all 32 IRQs are used (set if IRQ is disabled) Debug Port Protocol JTAGnSW 0 = SWD Core Memory Protection MPU 0 = Absent SWD protocol, not JTAG Number of IRQs NUMIRQ 32 Reset all regs RAR 0 = Standard Do not force all registers to be async reset Multiplier SMUL 0 = Fast Mul Implements single-cycle multiplier Multi-drop Support SWMD 0 = Absent Do not include serial wire support for multidrop System Tick Timer SYST 1 = Present Implements system tick timer (for CM4 compatibility) DAP Target ID TARGETID 0 User/Privileged USER 1 = Present Implements processor operating modes Vector Table Offset Register VTOR 1 = Present Implements relocation of exception vector table Implements WIC interface No MPU Assume full NVIC request vector WIC Support WIC 1 = Present WIC Requests WICLINES 34 Exact number of wakeup IRQs is 34 Watchpoints WPT 2 Implements 2 watchpoints For details on the ARM Cortex-M0+ processor core, see the ARM website: www.arm.com. 3.3.1.2 Buses, Interconnects, and Interfaces The ARM Cortex-M0+ core has two bus interfaces: * single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system memory, which includes flash and RAM. * single 32-bit I/O port bus interfacing to the GPIO with 1-cycle loads and stores. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 47 Core Modules 3.3.1.3 System Tick Timer The CLKSOURCE bit in SysTick Control and Status register selects either the core clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock (when CLKSOURCE = 0). Because the timing reference is a variable frequency, the TENMS bit in the SysTick Calibration Value Register is always zero. 3.3.1.4 Debug Facilities This device supports standard ARM 2-pin SWD debug port. 3.3.1.5 Core Privilege Levels The Core on this device is implemented with both Privileged and Unprivileged levels. The ARM documentation uses different terms than this document to distinguish between privilege levels. If you see this term... it also means this term... Privileged Supervisor Unprivileged or user User 3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration ARM Cortex-M0+ core This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at www.arm.com. Interrupts Module Nested Vectored Interrupt Controller (NVIC) PPB Module Module Figure 3-2. NVIC configuration Table 3-5. Reference links to related information Topic Related module Reference Full description Nested Vectored Interrupt Controller (NVIC) ARM Cortex-M0+ Technical Reference Manual System memory map System memory map Clocking Clock distribution Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 48 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-5. Reference links to related information (continued) Topic Related module Reference Power management Power management Private Peripheral Bus (PPB) ARM Cortex-M0+ core ARM Cortex-M0+ core 3.3.2.1 Interrupt priority levels This device supports 4 priority levels for interrupts. Therefore, in the NVIC each source in the IPR registers contains 2 bits. For example, IPR0 is shown below: 31 R W 30 IRQ3 29 28 27 26 25 24 0 0 0 0 0 0 23 22 IRQ2 21 20 19 18 17 16 0 0 0 0 0 0 15 14 IRQ1 13 12 11 10 9 8 0 0 0 0 0 0 7 6 IRQ0 5 4 3 2 1 0 0 0 0 0 0 0 3.3.2.2 Non-maskable interrupt The non-maskable interrupt request to the NVIC is controlled by the external NMI signal. The pin the NMI signal is multiplexed on, must be configured for the NMI function to generate the non-maskable interrupt request. 3.3.2.3 Interrupt channel assignments The interrupt vector assignments are defined in the following table. * Vector number -- the value stored on the stack when an interrupt is serviced. * IRQ number -- non-core interrupt source count, which is the vector number minus 16. The IRQ number is used within ARM's NVIC documentation. Table 3-7. Interrupt vector assignments Address IRQ1 Vector NVIC IPR register number2 Source module Source description ARM Core System Handler Vectors 0x0000_0000 0 -- -- ARM core Initial Stack Pointer 0x0000_0004 1 -- -- ARM core Initial Program Counter Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 49 Core Modules Table 3-7. Interrupt vector assignments (continued) Address IRQ1 Vector NVIC IPR register number2 Source module Source description 0x0000_0008 2 -- -- ARM core Non-maskable Interrupt (NMI) 0x0000_000C 3 -- -- ARM core Hard Fault 0x0000_0010 4 -- -- -- -- 0x0000_0014 5 -- -- -- -- 0x0000_0018 6 -- -- -- -- 0x0000_001C 7 -- -- -- -- 0x0000_0020 8 -- -- -- -- 0x0000_0024 9 -- -- -- -- 0x0000_0028 10 -- -- -- -- 0x0000_002C 11 -- -- ARM core Supervisor call (SVCall) 0x0000_0030 12 -- -- -- -- 0x0000_0034 13 -- -- -- -- 0x0000_0038 14 -- -- ARM core Pendable request for system service (PendableSrvReq) 0x0000_003C 15 -- -- ARM core System tick timer (SysTick) 0x0000_0040 16 0 0 DMA DMA channel 0 transfer complete and error 0x0000_0044 17 1 0 DMA DMA channel 1 transfer complete and error 0x0000_0048 18 2 0 DMA DMA channel 2 transfer complete and error 0x0000_004C 19 3 0 DMA DMA channel 3 transfer complete and error 0x0000_0050 20 4 1 -- -- 0x0000_0054 21 5 1 FTFA Command complete and read collision 0x0000_0058 22 6 1 PMC Low-voltage detect, low-voltage warning 0x0000_005C 23 7 1 LLWU Low Leakage Wakeup 0x0000_0060 24 8 2 I2C0 0x0000_0064 25 9 2 -- 0x0000_0068 26 10 2 SPI0 0x0000_006C 27 11 2 -- 0x0000_0070 28 12 3 UART0 0x0000_0074 29 13 3 -- 0x0000_0078 30 14 3 -- 0x0000_007C 31 15 3 ADC0 0x0000_0080 32 16 4 CMP0 0x0000_0084 33 17 4 TPM0 0x0000_0088 34 18 4 TPM1 0x0000_008C 35 19 4 -- 0x0000_0090 36 20 5 RTC Alarm interrupt 0x0000_0094 37 21 5 RTC Seconds interrupt Non-Core Vectors Single interrupt vector for all sources Status and error Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 50 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-7. Interrupt vector assignments (continued) Address IRQ1 Vector NVIC IPR register number2 Source module Source description 0x0000_0098 38 22 5 PIT Single interrupt vector for all channels 0x0000_009C 39 23 5 -- -- 0x0000_00A0 40 24 6 -- 0x0000_00A4 41 25 6 DAC0 0x0000_00A8 42 26 6 TSI0 0x0000_00AC 43 27 6 MCG 0x0000_00B0 44 28 7 LPTMR0 0x0000_00B4 45 29 7 -- 0x0000_00B8 46 30 7 Port control module Pin detect (Port A) 0x0000_00BC 47 31 7 Port control module Pin detect (Port B ) 1. Indicates the NVIC's interrupt source number. 2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4 3.3.2.3.1 Determining the bitfield and register location for configuring a particular interrupt Suppose you need to configure the SPI0 interrupt. The following table is an excerpt of the SPI0 row from Interrupt priority levels. Table 3-8. Interrupt vector assignments Address 0x0000_0068 IRQ1 Vector 26 10 NVIC IPR register number2 2 Source module SPI0 Source description Single interrupt vector for all sources 1. Indicates the NVIC's interrupt source number. 2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4. * The NVIC registers you would use to configure the interrupt are: * NVICIPR2 * To determine the particular IRQ's bitfield location within these particular registers: * NVICIPR2 bitfield starting location = 8 * (IRQ mod 4) + 6 = 22 Since the NVICIPR bitfields are 2-bit wide (4 priority levels), the NVICIPR2 bitfield range is 22-23 Therefore, the following bitfield locations are used to configure the SPI0 interrupts: * NVICIPR2[23:22] KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 51 Core Modules 3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at www.arm.com. Clock logic Nested vectored interrupt controller (NVIC) Wake-up requests Asynchronous Wake-up Interrupt Controller (AWIC) Module Module Figure 3-3. Asynchronous wake-up interrupt controller configuration Table 3-9. Reference links to related information Topic Related module Reference System memory map System memory map Clocking Clock distribution Power management Power management Nested vectored interrupt controller (NVIC) Wake-up requests NVIC AWIC wake-up sources 3.3.3.1 Wake-up sources The device uses the following internal and external inputs to the AWIC module. Table 3-10. AWIC stop wake-up sources Wake-up source Description Available system resets RESET pin when LPO is its clock source Low-voltage detect Power management controller - functional in Stop mode Low-voltage warning Power management controller - functional in Stop mode Pin interrupts Port control module - any enabled pin interrupt is capable of waking the system ADC The ADC is functional when using internal clock source CMP0 Interrupt in normal or trigger mode Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 52 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-10. AWIC stop wake-up sources (continued) Wake-up source Description I2Cx Address match wakeup UART0 Any interrupt provided clock remains enabled RTC Alarm or seconds interrupt TSI Any interrupt NMI NMI pin TPMx Any interrupt provided clock remains enabled LPTMR Any interrupt provided clock remains enabled SPI Slave mode interrupt 3.4 System Modules 3.4.1 SIM Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access System integration module (SIM) Figure 3-4. SIM configuration Table 3-11. Reference links to related information Topic Related module Reference Full description SIM SIM System memory map System memory map Clocking Clock distribution Power management Power management KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 53 System Modules 3.4.2 System Mode Controller (SMC) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Resets System Mode Controller (SMC) Power Management Controller (PMC) Register access Figure 3-5. System Mode Controller configuration Table 3-12. Reference links to related information Topic Related module Reference Full description System Mode Controller (SMC) SMC System memory map System memory map Power management Power management Power management controller (PMC) PMC Low-Leakage Wakeup Unit (LLWU) LLWU Reset Control Module (RCM) Reset 3.4.2.1 VLLS2 not supported VLLS2 power mode is not supported on this device. 3.4.3 PMC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 54 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Peripheral bridge Module signals Power Management Controller (PMC) Module signals System Mode Controller (SMC) Low-Leakage Wakeup Unit Register access Figure 3-6. PMC configuration Table 3-13. Reference links to related information Topic Related module Reference Full description PMC PMC System memory map System memory map Power management Power management Full description System Mode Controller (SMC) System Mode Controller Low-Leakage Wakeup Unit (LLWU) LLWU Reset Control Module (RCM) Reset 3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 55 System Modules Peripheral bridge 0 Power Management Controller (PMC) Register access Wake-up requests Low-Leakage Wake-up Unit (LLWU) Module Module Figure 3-7. Low-Leakage Wake-up Unit configuration Table 3-14. Reference links to related information Topic Related module Reference Full description LLWU LLWU System memory map System memory map Clocking Clock distribution Power management Power management chapter Power Management Controller (PMC) Power Management Controller (PMC) System Mode Controller (SMC) System Mode Controller Wake-up requests LLWU wake-up sources 3.4.4.1 LLWU interrupt NOTE Do not mask the LLWU interrupt when in LLS mode. Masking the interrupt prevents the device from exiting stop mode when a wakeup is detected. 3.4.4.2 Wake-up Sources The device uses the following internal peripheral and external pin inputs as wakeup sources to the LLWU module. LLWU_Px are external pin inputs, and LLWU_M0IFM7IF are connections to the internal peripheral interrupt flags. NOTE In addition to the LLWU wakeup sources, the device also wakes from low power modes when NMI or RESET pins are enabled and the respective pin is asserted. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 56 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-15. LLWU Wakeup Sources IRQ Module source or pin name LLWU_P0 PTA4 LLWU_P1 PTA5 LLWU_P2 PTA6 LLWU_P3 PTA7 LLWU_P4 PTB0 LLWU_P5 PTB2 LLWU_P6 PTB4 LLWU_P7 PTA0 LLWU_M0IF LPTMR0 LLWU_M1IF CMP0 LLWU_M2IF Reserved LLWU_M3IF Reserved LLWU_M4IF TSI0 LLWU_M5IF RTC Alarm LLWU_M6IF Reserved LLWU_M7IF RTC Seconds 3.4.5 MCM Configuration Miscellaneous Control Module (MCM) Transfers Transfers Flash Memory Controller ARM Cortex-M0+ core This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Figure 3-8. MCM configuration Table 3-16. Reference links to related information Topic Related module Reference Full description Miscellaneous control module (MCM) MCM System memory map System memory map Clocking Clock distribution Power management Power management Private Peripheral Bus (PPB) ARM Cortex-M0+ core ARM Cortex-M0+ core Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 57 System Modules Table 3-16. Reference links to related information (continued) Topic Related module Reference Transfer Flash memory controller Flash memory controller 3.4.6 Crossbar-Light Switch Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. GPIO controller Crossbar Switch S0 Flash controller M0 ARM core unified bus M2 S1 SRAML DMA Master Modules BME S2 SRAMU Peripheral bridge 0 Peripherals Slave Modules Figure 3-9. Crossbar-Light switch integration Table 3-17. Reference links to related information Topic Related module Reference Full description Crossbar switch Crossbar Switch System memory map System memory map Clocking Clock Distribution Crossbar switch master ARM Cortex-M0+ core ARM Cortex-M0+ core Crossbar switch master DMA controller DMA controller Crossbar switch slave Flash memory controller Flash memory controller Crossbar switch slave SRAM controller SRAM configuration Crossbar switch slave Peripheral bridge Peripheral bridge 2-ported peripheral GPIO controller GPIO controleer KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 58 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.4.6.1 Crossbar-Light Switch Master Assignments The masters connected to the crossbar switch are assigned as follows: Master module Master port number ARM core unified bus 0 DMA 2 3.4.6.2 Crossbar Switch Slave Assignments This device contains 3 slaves connected to the crossbar switch. The slave assignment is as follows: Slave module Slave port number Flash memory controller 0 SRAM controller 1 Peripheral bridge 0 2 3.4.7 Peripheral Bridge Configuration Transfers AIPS-Lite peripheral bridge Transfers Peripherals Crossbar switch This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Figure 3-10. Peripheral bridge configuration Table 3-18. Reference links to related information Topic Related module Reference Full description Peripheral bridge (AIPS-Lite) Peripheral bridge (AIPS-Lite) System memory map System memory map Clocking Clock Distribution Crossbar switch Crossbar switch Crossbar switch KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 59 System Modules 3.4.7.1 Number of peripheral bridges This device contains one peripheral bridge. 3.4.7.2 Memory maps The peripheral bridges are used to access the registers of most of the modules on this device. See AIPS0 Memory Map for the memory slot assignment for each module. 3.4.8 DMA request multiplexer configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge 0 Register access DMA controller Requests Channel request DMA Request Multiplexer Module Module Module Figure 3-11. DMA request multiplexer configuration Table 3-19. Reference links to related information Topic Related module Reference Full description DMA request multiplexer DMA Mux System memory map System memory map Clocking Clock distribution Power management Channel request Requests Power management DMA controller DMA Controller DMA request sources KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 60 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.4.8.1 DMA MUX Request Sources This device includes a DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 4 DMA channels. Because of the mux there is no hard correlation between any of the DMA request sources and a specific DMA channel. Some of the modules support Asynchronous DMA operation as indicated by the last column in the following DMA source assignment table. Table 3-20. DMA request sources - MUX 0 Source number Source module Source description Async DMA capable 0 -- Channel disabled1 1 Reserved Not used 2 UART0 Receive Yes 3 UART0 Transmit Yes 4 Reserved -- 5 Reserved -- 6 Reserved -- 7 Reserved -- 8 Reserved -- 9 Reserved -- 10 Reserved -- 11 Reserved -- 12 Reserved -- 13 Reserved -- 14 Reserved -- 15 Reserved -- 16 SPI0 Receive 17 SPI0 Transmit 18 Reserved -- 19 Reserved -- 20 Reserved -- 21 Reserved -- 22 I2C0 -- 23 Reserved -- 24 TPM0 Channel 0 Yes 25 TPM0 Channel 1 Yes 26 TPM0 Channel 2 Yes 27 TPM0 Channel 3 Yes 28 TPM0 Channel 4 Yes 29 TPM0 Channel 5 Yes 30 Reserved -- Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 61 System Modules Table 3-20. DMA request sources - MUX 0 (continued) Source number Source module Source description Async DMA capable 31 Reserved -- 32 TPM1 Channel 0 Yes 33 TPM1 Channel 1 Yes 34 Reserved -- 35 Reserved -- 36 Reserved -- 37 Reserved -- 38 Reserved -- 39 Reserved -- 40 ADC0 -- 41 Reserved -- 42 CMP0 -- 43 Reserved -- 44 Reserved -- 45 DAC0 -- 46 Reserved -- 47 Reserved -- 48 Reserved -- 49 Port control module Port A Yes 50 Port control module Port B Yes 51 Reserved -- 52 Reserved -- 53 Reserved -- 54 TPM0 Overflow Yes 55 TPM1 Overflow Yes 56 Reserved -- 57 TSI -- 58 Reserved -- 59 Reserved -- 60 DMA MUX Always enabled 61 DMA MUX Always enabled 62 DMA MUX Always enabled 63 DMA MUX Always enabled Yes Yes Yes 1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 62 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.4.8.2 DMA transfers via PIT trigger The PIT module can trigger a DMA transfer on the first two DMA channels. The assignments are detailed at PIT/DMA Periodic Trigger Assignments . 3.4.9 DMA Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge 0 Transfers DMA Controller Requests DMA Multiplexer Crossbar switch Register access Figure 3-12. DMA Controller configuration Table 3-21. Reference links to related information Topic Related module Reference Full description DMA controller DMA controller System memory map System memory map Clocking Clock distribution Power management Crossbar switch Power management Crossbar switch Requests Crossbar switch DMA request sources 3.4.10 Computer Operating Properly (COP) Watchdog Configuration This section summarizes how the module has been configured in the chip. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 63 System Modules Peripheral bridge 0 Mode Controller Register access WDOG Figure 3-13. COP watchdog configuration Table 3-22. Reference links to related information Topic Related module Reference Clocking Clock distribution Power management Power management Programming model System Integration Module (SIM) SIM 3.4.10.1 COP clocks The two clock inputs for the COP are the 1 kHz clock and the bus clock. 3.4.10.2 COP watchdog operation The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter before it times out, a system reset is generated to force the system back to a known starting point. After any reset, the COP watchdog is enabled. If the COP watchdog is not used in an application, it can be disabled by clearing COPCTRL[COPT] in the SIM. The COP counter is reset by writing 0x55 and 0xAA (in that order) to the address of the SIM's Service COP (SRVCOP) register during the selected timeout period. Writes do not affect the data in the SRVCOP register. As soon as the write sequence is complete, the COP timeout period is restarted. If the program fails to perform this restart during the timeout period, the microcontroller resets. Also, if any value other than 0x55 or 0xAA is written to the SRVCOP register, the microcontroller immediately resets. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 64 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration The SIM's COPCTRL[COPCLKS] field selects the clock source used for the COP timer. The clock source options are either the bus clock or an internal 1 kHz clock source. With each clock source, there are three associated timeouts controlled by COPCTRL[COPT]. The following table summarizes the control functions of the COPCLKS and COPT bits. The COP watchdog defaults to operation from the 1 kHz clock source and the longest timeout for that clock source (210 cycles). Table 3-23. COP configuration options Control Bits Clock Source COP Window Opens COP Overflow Count COPCTRL[COPCLKS] COPCTRL[COPT] N/A 00 N/A N/A COP is disabled 0 01 1 kHz N/A 25 cycles (32 ms) 0 10 1 kHz N/A 28 cycles (256 ms) 0 11 1 kHz N/A 210 cycles (1024 ms) 1 01 Bus 6,144 cycles 213 cycles 1 10 Bus 49,152 cycles 216 cycles 1 11 Bus 196,608 cycles 218 cycles (COPCTRL[COPW]=1) After the bus clock source is selected, windowed COP operation is available by setting COPCTRL[COPW] in the SIM. In this mode, writes to the SRVCOP register to clear the COP timer must occur in the last 25% of the selected timeout period. A premature write immediately resets the chip. When the 1 kHz clock source is selected, windowed COP operation is not available. The COP counter is initialized by the first writes to the SIM's COPCTRL register and after any system reset. Subsequent writes to the SIM's COPCTRL register have no effect on COP operation. Even if an application uses the reset default settings of the COPT, COPCLKS, and COPW bits, the user should write to the write-once COPCTRL register during reset initialization to lock in the settings. This approach prevents accidental changes if the application program becomes lost. The write to the SRVCOP register that services (clears) the COP counter should not be placed in an interrupt service routine (ISR) because the ISR could continue to be executed periodically even if the main application program fails. If the bus clock source is selected, the COP counter does not increment while the microcontroller is in debug mode or while the system is in stop (including VLPS or LLS) mode. The COP counter resumes when the microcontroller exits debug mode or stop mode. If the 1 kHz clock source is selected, the COP counter is re-initialized to zero upon entry to either debug mode or stop (including VLPS or LLS) mode. The counter begins from zero upon exit from debug mode or stop mode. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 65 Clock Modules Regardless of the clock selected, the COP is disabled when the chip enters a VLLSx mode. Upon a reset that wakes the chip from the VLLSx mode, the COP is re-initialized and enabled as for any reset. 3.4.10.3 Clock Gating This family of devices includes clock gating control for each peripheral, that is, the clock to each peripheral can explicitly be gated on or off, using clock-gate control bits in the SIM module. 3.5 Clock Modules 3.5.1 MCG Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge System integration module (SIM) System oscillator Register access Multipurpose Clock Generator (MCG) Figure 3-14. MCG configuration Table 3-24. Reference links to related information Topic Related module Reference Full description MCG MCG System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 66 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.5.1.1 MCG FLL modes On L-series devices the MCGFLLCLK frequency is limited to 48 MHz max. The DCO is limited to the two lowest range settings (MCG_C4[DRST_DRS] must be set to either 0b00 or 0b01). 3.5.2 OSC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Module signals RTC System oscillator Signal multiplexing MCG Register access Figure 3-15. OSC configuration Table 3-25. Reference links to related information Topic Related module Reference Full description OSC OSC System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing Full description MCG MCG 3.5.2.1 OSC modes of operation with MCG and RTC The most common method of controlling the OSC block is through MCG clock source selection MCG_C1[CLKS] and the MCG_C2 register bits to configure the oscillator frequency range, gain-mode, and for crystal or external clock operation. The OSC_CR also provides control for enabling the OSC and configuring internal load capacitors for the EXTAL and XTAL pins. See the OSC and MCG chapters for more details. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 67 Memories and Memory Interfaces The RTC_CR[OSCE] bit has overriding control over the MCG and OSC_CR enable functions. When RTC_CR[OSCE] is set, the OSC is configured for low frequency, low power and the RTC_CR[SCxP] bits override the OSC_CR[SCxP] bits to control the internal capacitance configuration. See the RTC chapter for more details. 3.6 Memories and Memory Interfaces 3.6.1 Flash Memory Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bus controller 0 Flash memory controller Register access Transfers Flash memory Figure 3-16. Flash memory configuration Table 3-26. Reference links to related information Topic Related module Reference Full description Flash memory Flash memory System memory map System memory map Clocking Clock Distribution Transfers Flash memory controller Flash memory controller Register access Peripheral bridge Peripheral bridge 3.6.1.1 Flash Memory Sizes The devices covered in this document contain 1 program flash block consisting of 1 KB sectors. The amounts of flash memory for the devices covered in this document are: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 68 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-27. KL05 flash memory size Device Program flash (KB) Block 0 (P-Flash) address range MKL05Z8VFK4 8 0x0000_0000 - 0x0000_1FFF MKL05Z16VFK4 16 0x0000_0000 - 0x0000_3FFF MKL05Z32VFK4 32 0x0000_0000 - 0x0000_7FFF MKL05Z8VLC4 8 0x0000_0000 - 0x0000_1FFF MKL05Z16VLC4 16 0x0000_0000 - 0x0000_3FFF MKL05Z32VLC4 32 0x0000_0000 - 0x0000_7FFF MKL05Z8VFM4 8 0x0000_0000 - 0x0000_1FFF MKL05Z16VFM4 16 0x0000_0000 - 0x0000_3FFF MKL05Z32VFM4 32 0x0000_0000 - 0x0000_7FFF MKL05Z16VLF4 16 0x0000_0000 - 0x0000_3FFF MKL05Z32VLF4 32 0x0000_0000 - 0x0000_7FFF 3.6.1.2 Flash Memory Map The flash memory and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map. Flash memory base address Registers Program flash base address Flash configuration field Program flash Figure 3-17. Flash memory map The on-chip Flash is implemented in a portion of the allocated Flash range to form a contiguous block in the memory map beginning at address 0x0000_0000. See Flash Memory Sizes for details of supported ranges. Accesses to the flash memory ranges outside the amount of Flash on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. Read collision events in which flash memory is accessed while a flash memory resource is being manipulated by a flash command also generates a bus error response. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 69 Memories and Memory Interfaces 3.6.1.3 Flash Security How flash security is implemented on this device is described in Chip Security. 3.6.1.4 Flash Modes The flash memory chapter defines two modes of operation - NVM normal and NVM special modes. On this device, The flash memory only operates in NVM normal mode. All references to NVM special mode should be ignored. 3.6.1.5 Erase All Flash Contents In addition to software, the entire flash memory may be erased external to the flash memory via the SW-DP debug port by setting MDM-AP CONTROL[0]. MDM-AP STATUS[0] is set to indicate the mass erase command has been accepted. MDM-AP STATUS[0] is cleared when the mass erase completes. 3.6.1.6 FTFA_FOPT Register The flash memory's FTFA_FOPT register allows the user to customize the operation of the MCU at boot time. See FOPT boot options for details of its definition. 3.6.2 Flash Memory Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. See MCM_PLACR register description for details on the reset configuration of the FMC. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 70 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Transfers Flash memory controller Transfers Flash memory Crossbar switch MCM Figure 3-18. Flash memory controller configuration Table 3-28. Reference links to related information Topic Related module Reference Full description Flash memory controller Flash memory controller System memory map System memory map Clocking Clock Distribution Transfers Flash memory Flash memory Transfers Crossbar switch Crossbar Switch Register access MCM MCM 3.6.3 SRAM Configuration This section summarizes how the module has been configured in the chip. Transfers SRAM upper crossbar Cortex-M0+ core switch SRAM controller SRAM lower Figure 3-19. SRAM configuration Table 3-29. Reference links to related information Topic Related module Reference Full description SRAM SRAM System memory map System memory map Clocking Clock Distribution ARM Cortex-M0+ core ARM Cortex-M0+ core KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 71 Memories and Memory Interfaces 3.6.3.1 SRAM Sizes This device contains SRAM which could be accessed by bus masters through the crossbar switch. The amount of SRAM for the devices covered in this document is shown in the following table. Table 3-30. KL05 SRAM memory size Device SRAM (KB) MKL05Z8VFK4 1 MKL05Z16VFK4 2 MKL05Z32VFK4 4 MKL05Z8VLC4 1 MKL05Z16VLC4 2 MKL05Z32VLC4 4 MKL05Z8VFM4 1 MKL05Z16VFM4 2 MKL05Z32VFM4 4 MKL05Z16VLF4 2 MKL05Z32VLF4 4 3.6.3.2 SRAM Ranges The on-chip SRAM is split into two ranges, 1/4 is allocated SRAM_L and 3/4 is allocated to SRAM_U. The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. As such: * SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending address. * SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning address. Valid address ranges for SRAM_L and SRAM_U are then defined as: * SRAM_L = [0x2000_0000-(SRAM_size/4)] to 0x1FFF_FFFF * SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size*(3/4))-1] This is illustrated in the following figure. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 72 Freescale Semiconductor, Inc. SRAM size *(1/4) Chapter 3 Chip Configuration 0x2000_0000 - SRAM_size/4 SRAM_L SRAM size * (3/4) 0x1FFF_FFFF 0x2000_0000 SRAM_U 0x2000_0000 + SRAM_size(3/4) - 1 Figure 3-20. SRAM blocks memory map For example, for a device containing 16 KB of SRAM the ranges are: * SRAM_L: 0x1FFF_F000 - 0x1FFF_FFFF * SRAM_U: 0x2000_0000 - 0x2000_2FFF 3.6.3.3 SRAM retention in low power modes The SRAM is retained down to VLLS3 mode. In VLLS1 and VLLS0 no SRAM is retained. 3.7 Analog 3.7.1 12-bit SAR ADC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 73 Analog Peripheral bus controller 0 Module signals 12-bit SAR ADC Other peripherals Signal multiplexing Register access Figure 3-21. 12-bit SAR ADC configuration Table 3-31. Reference links to related information Topic Related module Reference Full description 12-bit SAR ADC 12-bit SAR ADC System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.1.1 ADC Instantiation Information This device contains one 12-bit successive approximation ADC with up to 14-channels. The ADC supports both software and hardware triggers. The hardware trigger sources are listed in the Module-to-Module section. The number of ADC channels present on the device is determined by the pinout of the specific device package and is shown in the following table. Table 3-32. Number of KL05 ADC channels Device Number of ADC channels MKL05Z8VFK4 12 MKL05Z16VFK4 12 MKL05Z32VFK4 12 MKL05Z8VLC4 14 MKL05Z16VLC4 14 MKL05Z32VLC4 14 MKL05Z8VFM4 14 MKL05Z16VFM4 14 MKL05Z32VFM4 14 MKL05Z16VLF4 14 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 74 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-32. Number of KL05 ADC channels (continued) Device Number of ADC channels MKL05Z32VLF4 14 3.7.1.2 DMA Support on ADC Applications may require continuous sampling of the ADC that may have considerable load on the CPU. The ADC supports DMA request functionality for higher performance when the ADC is sampled at a very high rate. The ADC can trigger the DMA (via DMA req) on conversion completion. 3.7.1.3 ADC0 Connections/Channel Assignment 3.7.1.3.1 ADC0 Channel Assignment ADC Channel (SC1n[ADCH]) Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 00000 AD0 Reserved ADC0_SE0 00001 AD1 Reserved ADC0_SE1 00010 AD2 Reserved ADC0_SE2 00011 AD3 Reserved ADC0_SE3 00100 AD4 Reserved ADC0_SE4 00101 AD5 Reserved 12-bit DAC0 Output/ ADC0_SE5 00110 AD6 Reserved ADC0_SE6 00111 AD7 Reserved ADC0_SE7 01000 AD8 Reserved ADC0_SE8 01001 AD9 Reserved ADC0_SE9 01010 AD10 Reserved ADC0_SE10 01011 AD11 Reserved ADC0_SE11 01100 AD12 Reserved ADC0_SE12 01101 AD13 Reserved ADC0_SE13 01110 AD14 Reserved Reserved 01111 AD15 Reserved Reserved 10000 AD16 Reserved Reserved 10001 AD17 Reserved Reserved 10010 AD18 Reserved Reserved 10011 AD19 Reserved Reserved Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 75 Analog ADC Channel (SC1n[ADCH]) Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 10100 AD20 Reserved Reserved 10101 AD21 Reserved Reserved 10110 AD22 Reserved Reserved 10111 AD23 Reserved Reserved 11000 AD24 Reserved Reserved 11001 AD25 Reserved Reserved 11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff)1 Bandgap (S.E)1 11100 AD28 Reserved Reserved 11101 AD29 -VREFH (Diff) VREFH (S.E) 11110 AD30 Reserved VREFL 11111 AD31 Module Disabled Module Disabled 1. This is the PMC bandgap 1V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification. 3.7.1.4 ADC Analog Supply and Reference Connections This device internally connects VDDA to VDD and VSSA to VSS. This device contains separate VREFH and VREFL pins on 32-pin and higher devices. These pins are internally connected to VDD and VSS respectively, on packages less than 32-pin. 3.7.1.5 ADC Reference Options The ADC supports the following references: * VREFH/VREFL - connected as the primary reference option * VDDA - connected as the VALT reference option 3.7.1.6 Alternate clock For this device, the alternate clock is connected to OSCERCLK. NOTE This clock option is only usable when OSCERCLK is in the MHz range. A system with OSCERCLK in the kHz range has KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 76 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration the optional clock source below minimum ADC clock operating frequency. 3.7.2 CMP Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge 0 Other peripherals CMP Module signals Signal multiplexing Register access Figure 3-22. CMP configuration Table 3-33. Reference links to related information Topic Related module Reference Full description Comparator (CMP) Comparator System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.2.1 CMP Instantiation Information The device includes one high speed comparator and two 8-input multiplexors for both the inverting and non-inverting inputs of the comparator. Each CMP input channel connects to both muxes. Two of the channels are connected to internal sources, leaving resources to support up to 6 input pins. See the channel assignment table for a summary of CMP input connections for this device. The CMP also includes one 6-bit DAC with a 64-tap resistor ladder network, which provides a selectable voltage reference for applications where voltage reference is needed for internal connection to the CMP. The CMP can be optionally on in all modes except VLLS0. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 77 Analog The CMP has several module to module interconnects in order to facilitate ADC triggering, TPM triggering and UART IR interfaces. For complete details on the CMP module interconnects please refer to the Module-to-Module section. The CMP does not support window compare function and CMP_CR1[WE] must always be written to 0. The sample function has limited functionality since the SAMPLE input to the block is not connected to a valid input. Usage of sample operation is limited to a divided version of the bus clock (CMP_CR1[SE] = 0). Due to the pin number limitation, the CMP pass through mode is not supported by this device, so the CMPx_MUXCR[PSTM] must be left as 0. 3.7.2.2 CMP input connections The following table shows the fixed internal connections to the CMP. Table 3-34. CMP input connections CMP Inputs CMP0 IN0 CMP0_IN0 IN1 CMP0_IN1 IN2 CMP0_IN2 IN3 12-bit DAC0 reference/ CMP0_IN3 IN4 -- IN5 -- IN6 Bandgap1 IN7 6-bit DAC0 reference 1. This is the PMC bandgap 1V reference voltage. Prior to using as CMP input, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification. 3.7.2.3 CMP external references The 6-bit DAC sub-block supports selection of two references. For this device, the references are connected as follows: * VREFH - Vin1 input. When using VREFH, any ADC conversion using this same reference at the same time is negatively impacted. * VDD - Vin2 input KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 78 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.7.2.4 CMP trigger mode The CMP and 6-bit DAC sub-block supports trigger mode operation when the CMP_CR1[TRIGM] is set. When trigger mode is enabled, the trigger event will initiate a compare sequence that must first enable the CMP and DAC prior to performing a CMP operation and capturing the output. In this device, control for this two staged sequencing is provided from the LPTMR. The LPTMR triggering output is always enabled when the LPTMR is enabled. The first signal is supplied to enable the CMP and DAC and is asserted at the same time as the TCF flag is set. The delay to the second signal that triggers the CMP to capture the result of the compare operation is dependent on the LPTMR configuration. In Time Counter mode with prescaler enabled, the delay is 1/2 Prescaler output period. In Time Counter mode with prescaler bypassed, the delay is 1/2 Prescaler clock period. The delay between the first signal from LPTMR and the second signal from LPTMR must be greater than the Analog comparator initialization delay as defined in the device datasheet. 3.7.3 12-bit DAC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bus controller 0 Other peripherals 12-bit DAC Module signals Signal multiplexing Register access Figure 3-23. 12-bit DAC configuration Table 3-35. Reference links to related information Topic Related module Reference Full description 12-bit DAC 12-bit DAC System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 79 Timers 3.7.3.1 12-bit DAC Instantiation Information This device contains one 12-bit digital-to-analog converter (DAC) with programmable reference generator output. The DAC includes a two word FIFO for DMA support. 3.7.3.2 12-bit DAC Output The output of the DAC can be placed on an external pin or selected as an input to the analog comparator or ADC. 3.7.3.3 12-bit DAC Analog Supply and Reference Connections This device internally connects VDDA to VDD and VSSA to VSS. This device contains separate VREFH and VREFL pins on 32-pin and higher devices. These pins are internally connected to VDD and VSS respectively, on packages less than 32-pin. 3.7.3.4 12-bit DAC Reference For this device VREFH and VDDA are selectable as the DAC reference. VREFH is connected to the DACREF_1 input and VDDA is connected to the DACREF_2 input. Use DACx_C0[DACRFS] control bit to select between these two options. Be aware that if the DAC and ADC use the same reference simultaneously, some degradation of ADC accuracy is to be expected due to DAC switching. 3.8 Timers 3.8.1 Timer/PWM Module Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 80 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Peripheral bus controller 0 TPM Other peripherals Module signals Signal multiplexing Register access Figure 3-24. TPM configuration Table 3-36. Reference links to related information Topic Related module Reference Full description Timer/PWM Module Timer/PWM Module System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.8.1.1 TPM Instantiation Information This device contains two Low Power TPM modules (TPM). All TPM modules in the device only are configured as basic TPM function, and no quadrature decoder function and all can be functional in Stop/VLPS mode. The clock source is either external or internal in Stop/VLPS mode. The following table shows how these modules are configured. Table 3-37. TPM configuration TPM instance Number of channels Features/usage TPM0 6 Basic TPM,functional in Stop/VLPS mode TPM1 2 Basic TPM,functional in Stop/VLPS mode There are several connections to and from the TPMs in order to facilitate customer use cases. For complete details on the TPM module interconnects please refer to the Moduleto-Module section. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 81 Timers 3.8.1.2 Clock Options The TPM blocks are clocked from a single TPM clock that can be selected from OSCERCLK, MCGIRCLK, or MCGFLLCLK. The selected source is controlled by SIM_SOPT2[TPMSRC] control registers. Each TPM also supports an external clock mode (TPM_SC[CMOD]=1x) in which the counter increments after a synchronized (to the selected TPM clock source) rising edge detect of an external clock input. The available external clock (either TPM_CLKIN0 or TPM_CLKIN1) is selected by SIM_SOPT4[TPMxCLKSEL] control register. To guarantee valid operation the selected external clock must be less than half the frequency of the selected TPM clock source. 3.8.1.3 Trigger Options Each TPM has a selectable trigger input source controlled by the TPMx_CONF[TRGSEL] field to use for starting the counter and/or reloading the counter. The options available are shown in the following table. Table 3-38. TPM trigger options TPMx_CONF[TRGSEL] Selected source 0000 External trigger pin input (EXTRG_IN) 0001 CMP0 output 0010 Reserved 0011 Reserved 0100 PIT trigger 0 0101 PIT trigger 1 0110 Reserved 0111 Reserved 1000 TPM0 overflow 1001 TPM1 overflow 1010 Reserved 1011 Reserved 1100 RTC alarm 1101 RTC seconds 1110 LPTMR trigger 1111 Reserved KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 82 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.8.1.4 Global Timebase Each TPM has a global timebase feature controlled by the TPMx_CONF[GTBEEN] bit. TPM1 is configured as the global time when this option is enabled. 3.8.1.5 TPM Interrupts The TPM has multiple sources of interrupt. However, these sources are OR'd together to generate a single interrupt request to the interrupt controller. When an TPM interrupt occurs, read the TPM status registers to determine the exact interrupt source. 3.8.2 PIT Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access Periodic interrupt timer Figure 3-25. PIT configuration Table 3-39. Reference links to related information Topic Related module Reference Full description PIT PIT System memory map System memory map Clocking Clock Distribution Power management Power management 3.8.2.1 PIT/DMA Periodic Trigger Assignments The PIT generates periodic trigger events to the DMA channel mux as shown in the table below. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 83 Timers Table 3-40. PIT channel assignments for periodic DMA triggering PIT Channel DMA Channel Number PIT Channel 0 DMA Channel 0 PIT Channel 1 DMA Channel 1 3.8.2.2 PIT/ADC Triggers PIT triggers are selected as ADCx trigger sources using the SOPT7[ADCxTRGSEL] bits in the SIM module. For more details, refer to SIM chapter. 3.8.2.3 PIT/TPM Triggers PIT triggers are selected as TPMx trigger sources using the TPMx_CONF[TRGSEL] bits in the TPM module. For more details, refer to TPM chapter. 3.8.2.4 PIT/DAC Triggers PIT Channel 0 is configured as the DAC hardware trigger source. For more details, refer to DAC chapter. 3.8.3 Low-power timer configuration Peripheral bridge Low-power timer Module signals Signal multiplexing Register access Figure 3-26. LPT configuration Table 3-41. Reference links to related information Topic Related module Reference Full description Low-power timer Low-power timer Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 84 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-41. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.8.3.1 LPTMR Instantiation Information The low-power timer (LPTMR) allows operation during all power modes. The LPTMR can operate as a real-time interrupt or pulse accumulator. It includes a 15-bit prescaler (real-time interrupt mode) or glitch filter (pulse accumulator mode). The LPTMR can be clocked from the internal reference clock, the internal 1 kHz LPO, OSCERCLK, or an external 32.768 kHz crystal. In VLLS0 mode, the clocking option is limited to an external pin with the OSC configured for bypass (external clock) operation. An interrupt is generated (and the counter may reset) when the counter equals the value in the 16-bit compare register. 3.8.3.2 LPTMR pulse counter input options The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this bitfield. LPTMR_CSR[TPS] Pulse counter input number Chip input 00 0 CMP0 output 01 1 LPTMR_ALT1 pin 10 2 LPTMR_ALT2 pin 11 3 LPTMR_ALT3 pin 3.8.3.3 LPTMR prescaler/glitch filter clocking options The prescaler and glitch filter of the LPTMR module can be clocked from one of four sources determined by the LPTMR0_PSR[PCS] bitfield. The following table shows the chip-specific clock assignments for this bitfield. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 85 Timers NOTE The chosen clock must remain enabled if the LPTMR is to continue operating in all required low-power modes. LPTMR0_PSR[PCS] Prescaler/glitch filter clock number Chip clock 00 0 MCGIRCLK -- internal reference clock (not available in LLS and VLLS modes) 01 1 LPO -- 1 kHz clock (not available in VLLS0 mode) 10 2 ERCLK32K (not available in VLLS0 mode when using 32 kHz oscillator) 11 3 OSCERCLK -- external reference clock (not available in VLLS0 mode) See Clock Distribution for more details on these clocks. 3.8.4 RTC configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Module signals Real-time clock Signal multiplexing Register access Figure 3-27. RTC configuration Table 3-42. Reference links to related information Topic Related module Reference Full description RTC RTC System memory map System memory map Clocking Clock Distribution Power management Power management KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 86 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.8.4.1 RTC Instantiation Information RTC prescaler is clocked by ERCLK32K. RTC is reset on POR Only. RTC_CR[OSCE] can override the configuration of the System OSC, configuring the OSC for 32 kHz crystal operation in all power modes except VLLS0, and through any System Reset. When OSCE is enabled, the RTC also overrides the capacitor configurations. 3.8.4.2 RTC_CLKOUT options RTC_CLKOUT pin can be driven either with the RTC 1 Hz output or with the OSCERCLK on-chip clock source. Control for this option is through SIM_SOPT2[RTCCLKOUTSEL] bit. When RTCCLKOUTSEL = 0, the RTC 1 Hz clock is output is selected on the RTC_CLKOUT pin. When RTCCLKOUTSEL = 1, OSCERCLK clock is output on the RTC_CLKOUT pin. 3.9 Communication interfaces 3.9.1 SPI configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 87 Communication interfaces Peripheral bridge SPI Module signals Signal multiplexing Register access Figure 3-28. SPI configuration Table 3-43. Reference links to related information Topic Related module Reference Full description SPI SPI System memory map System memory map Clocking Clock Distribution Signal Multiplexing Port control Signal Multiplexing 3.9.1.1 SPI Instantiation Information This device contains one SPI module that supports 8-bit data length. SPI0 is clocked on the bus clock. The SPI supports DMA request and can operate in VLPS mode. When the SPI is operating in VLPS mode, it will operate as a slave. SPI can wakeup MCU from VLPS mode upon reception of SPI data in slave mode. 3.9.2 I2C Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 88 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Peripheral bridge I2 C Module signals Signal multiplexing Register access Figure 3-29. I2C configuration Table 3-44. Reference links to related information Topic Related module Reference Full description I2C I2C System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.9.2.1 IIC Instantiation Information This device has one IIC module. When the package pins associated with IIC have their mux select configured for IIC operation, the pins (SCL and SDA) are driven in a pseudo open drain configuration. The digital glitch filter implemented in the IIC0 module, controlled by the I2C0_FLT[FLT] registers, is clocked from the bus clock and thus has filter granularity in bus clock cycle counts. 3.9.3 UART Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 89 Communication interfaces Peripheral bridge Module signals UART Signal multiplexing Register access Figure 3-30. UART configuration Table 3-45. Reference links to related information Topic Related module Reference Full description UART0 UART System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.9.3.1 UART0 overview The UART0 module supports basic UART with DMA interface function, x4 to x32 oversampling of baud-rate. This module supports LIN slave operation. The module can remain functional in VLPS mode provided the clock it is using remains enabled. ISO7816 protocol is intended to be handled in software for this product. To support smart card reading, TxD pin can be configured as pseudo open drain for 1-wire half-duplex like ISO7816 communication via the SIM_SOPT5[UART0ODE] bit. 3.9.3.2 UART1 and UART2 Overview This device contains two basic universal asynchronous receiver/transmitter (UART) modules with DMA function support. Generally, these modules are used in RS-232, RS-485, and other communications. This module supports LIN Slave operation. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 90 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.10 Human-machine interfaces (HMI) 3.10.1 GPIO Configuration Peripheral bridge Register access Module signals GPIO controller Signal multiplexing ARM Cortex -M0+ Core Register access Figure 3-31. GPIO configuration Table 3-46. Reference links to related information Topic Related module Reference Full description GPIO GPIO System memory map System memory map Clocking Clock Distribution Power management Power management Crossbar switch Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing 3.10.1.1 GPIO Instantiation Information The device includes four pins, PTB0, PTB1, PTA12, and PTA13, with high current drive capability. These pins can be used to drive LED or power MOSFET directly. The high drive capability applies to all functions which are multiplexed on these pins (UART, TPM, SPI...etc) 3.10.1.1.1 Pull Devices and Directions The pull devices are enabled out of POR only on RESET_B, NMI_b and respective SWD signals. Other pins can be enabled by writing to PORTx_PCRn[PE] field. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 91 Human-machine interfaces (HMI) All the pins are hard wired to be pullup except for SWD_CLK. The state will be reflected in the PORTx_PCRn[PS] field. 3.10.1.2 Port Control and Interrupt Summary The following table provides more information regarding the Port Control and Interrupt configurations . Table 3-47. Ports Summary Feature Port A Port B Pull Select control No No Pull Select at reset PTA0=Pull down, Others=Pull up Pull up Pull Enable control Yes Yes Pull Enable at reset PTA0/PTA2/RESET_b=Enabled; Others=Disabled PTB5=Enabled; Others=Disabled Slew Rate Enable control No No Slew Rate Enable at reset PTA2/PTA6/PTA7/PTA15=Disabled; Others=Enabled PTB0/PTB15/PTB16/PTB17= Disabled; Others=Enabled Passive Filter Enable control RESET_b only PTB5 only Passive Filter Enable at reset RESET_b=Enabled; Others=Disabled Disabled Open Drain Enable control1 No No Open Drain Enable at reset Disabled Disabled Drive Strength Enable control PTA12/PTA13 only PTB0/PTB1 only Drive Strength Enable at reset Disabled Disabled Pin Mux control Yes Yes Pin Mux at reset PTA0/PTA2=ALT3; Others=ALT0 PTB5=ALT3; Others=ALT0 No No PTA0/PTA1/PTA7/PTA10/PTA11/ PTA12/PTA16/PTA17/PTA18 only PTB0/PTB1/PTB2/PTB3/PTB4/PTB5/ PTB6/PTB7/PTB14 only No No Lock Bit Interrupt and DMA Request Digital Glitch Filter 1. UART signals can be configured for open-drain using SIM_SOPT5 register. IIC signals are automatically enabled for open drain when selected. 3.10.1.3 GPIO accessibility in the memory map The GPIO is multi-ported and can be accessed directly by the core with zero wait states at base address 0xF800_0000. It can also be accessed by the core and DMA masters through the cross bar/AIPS interface at 0x400F_F000 and at an aliased slot (15) at KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 92 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration address 0x4000_F000. All BME operations to the GPIO space can be accomplished referencing the aliased slot (15) at address 0x4000_F000. Only some of the BME operations can be accomplished referencing GPIO at address 0x400F_F000. 3.10.2 TSI Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Touch sense input module Module signals Signal multiplexing Register access Figure 3-32. TSI configuration Table 3-48. Reference links to related information Topic Related module Reference Full description TSI TSI System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.10.2.1 TSI Instantiation Information This device includes one TSI module containing the channels as shown in the following table. In Stop, VLPS, LLS and VLLSx modes any one channel can be enabled to be the wakeup source. TSI hardware trigger is from the LPTMR. For complete details on the LPTMR module interconnects refer to the Module-to-Module section. The number of TSI channels present on the device is determined by the pinout of the specific device package and is shown in the following table. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 93 Human-machine interfaces (HMI) Table 3-49. Number of KL05 TSI channels Device TSI channels MKL05Z8VFK4 8 MKL05Z16VFK4 8 MKL05Z32VFK4 8 MKL05Z8VLC4 12 MKL05Z16VLC4 12 MKL05Z32VLC4 12 MKL05Z8VFM4 12 MKL05Z16VFM4 12 MKL05Z32VFM4 12 MKL05Z16VLF4 12 MKL05Z32VLF4 12 3.10.2.2 TSI Interrupts The TSI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request. When a TSI interrupt occurs, read the TSI status register to determine the exact interrupt source. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 94 Freescale Semiconductor, Inc. Chapter 4 Memory Map 4.1 Introduction This device contains various memories and memory-mapped peripherals which are located in a 4 GB memory space. This chapter describes the memory and peripheral locations within that memory space. 4.2 System memory map The following table shows the high-level device memory map. Table 4-1. System memory map System 32-bit Address Range 0x0000_0000-0x07FF_FFFF1 Destination Slave Program flash and read-only data Access All masters (Includes exception vectors in first 196 bytes) 0x0800_0000-0x1FFF_FBFF Reserved -- 0x1FFF_FC00-0x1FFF_FFFF2 SRAM_L: Lower SRAM All masters 0x2000_0000-0x2000_0BFF2 SRAM_U: Upper SRAM All masters 0x2000_0C00-0x3FFF_FFFF Reserved - 0x4000_0000-0x4007_FFFF AIPS Peripherals Cortex-M0+ core & DMA 0x4008_0000-0x400F_EFFF Reserved - 0x400F_F000-0x400F_FFFF General purpose input/output (GPIO) Cortex-M0+ core & DMA 0x4010_0000-0x43FF_FFFF Reserved - 0x4400_0000-0x5FFF_FFFF Bit Manipulation Engine (BME) access to AIPS Peripherals for Cortex-M0+ core slots 0-1273 0x6000_0000-0xDFFF_FFFF Reserved - 0xE000_0000-0xE00F_FFFF Private Peripherals Cortex-M0+ core 0xE010_0000-0xEFFF_FFFF Reserved - 0xF000_0000-0xF000_0FFF Micro Trace Buffer (MTB) registers Cortex-M0+ core Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 95 Flash Memory Map Table 4-1. System memory map (continued) System 32-bit Address Range Destination Slave Access 0xF000_1000-0xF000_1FFF MTB Data Watchpoint and Trace (MTBDWT) registers Cortex-M0+ core 0xF000_2000-0xF000_2FFF ROM table Cortex-M0+ core 0xF000_3000-0xF000_3FFF Miscellaneous Control Module (MCM) Cortex-M0+ core 0xF000_4000-0xF7FF_FFFF Reserved - 0xF800_0000-0xFFFF_FFFF IOPORT: GPIO (single cycle) Cortex-M0+ core 1. The program flash always begins at 0x0000_0000 but the end of implemented flash varies depending on the amount of flash implemented for a particular device. See Flash Memory Sizes for details. 2. This range varies depending on SRAM sizes. See SRAM Ranges for details. 3. Includes BME operations to GPIO at slot 15 (based at 0x4000_F000). 4.3 Flash Memory Map The flash memory and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map. Flash memory base address Registers Program flash base address Flash configuration field Program flash Figure 4-1. Flash memory map The on-chip Flash is implemented in a portion of the allocated Flash range to form a contiguous block in the memory map beginning at address 0x0000_0000. See Flash Memory Sizes for details of supported ranges. Accesses to the flash memory ranges outside the amount of Flash on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. Read collision events in which flash memory is accessed while a flash memory resource is being manipulated by a flash command also generates a bus error response. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 96 Freescale Semiconductor, Inc. Chapter 4 Memory Map 4.3.1 Alternate Non-Volatile IRC User Trim Description The following non-volatile locations (4 bytes) are reserved for custom IRC user trim supported by some development tools. An alternate IRC trim to the factory loaded trim can be stored at this location. To override the factory trim, user software must load new values into the MCG trim registers. Non-Volatile Byte Address Alternate IRC Trim Value 0x0000_03FC Reserved 0x0000_03FD Reserved 0x0000_03FE (bit 0) SCFTRIM 0x0000_03FE (bit 4:1) FCTRIM 0x0000_03FF SCTRIM 4.4 SRAM memory map The on-chip RAM is split between SRAM_L and SRAM_U. The RAM is also implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. See SRAM Ranges for details. Accesses to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. 4.5 Bit Manipulation Engine The Bit Manipulation Engine (BME) provides hardware support for atomic read-modifywrite memory operations to the peripheral address space. By combining the basic load and store instruction support in the Cortex-M instruction set architecture with the concept of decorated storage provided by the BME, the resulting implementation provides a robust and efficient read-modify-write capability to this class of ultra low-end microcontrollers. See the Bit Manipulation Engine Block Guide (BME) for a detailed description of BME functionality. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 97 Peripheral bridge (AIPS-Lite) memory map 4.6 Peripheral bridge (AIPS-Lite) memory map The peripheral memory map is accessible via one slave port on the crossbar in the 0x4000_0000-0x400F_FFFF region. The device implements one peripheral bridge that defines a 1024 KB address space. The three regions associated with this space are: * A 128 KB region, partitioned as 32 spaces, each 4 KB in size and reserved for onplatform peripheral devices. The AIPS controller generates unique module enables for all 32 spaces. * A 384 KB region, partitioned as 96 spaces, each 4 KB in size and reserved for offplatform modules. The AIPS controller generates unique module enables for all 96 spaces. * The last slot is a 4 KB region beginning at 0x400F_F000 for accessing the GPIO module. The GPIO slot (slot 128) is an alias of slot 15. This block is also directly interfaced to the core and provides direct access without incurring wait states associated with accesses via the AIPS controller. Modules that are disabled via their clock gate control bits in the SIM registers disable the associated AIPS slots. Access to any address within an unimplemented or disabled peripheral bridge slot results in a transfer error termination. For programming model accesses via the peripheral bridges, there is generally only a small range within the 4 KB slots that is implemented. Accessing an address that is not implemented in the peripheral results in a transfer error termination. 4.6.1 Read-after-write sequence and required serialization of memory operations In some situations, a write to a peripheral must be completed fully before a subsequent action can occur. Examples of such situations include: * Exiting an interrupt service routine (ISR) * Changing a mode * Configuring a function In these situations, application software must perform a read-after-write sequence to guarantee the required serialization of the memory operations: 1. Write the peripheral register. 2. Read the written peripheral register to verify the write. 3. Continue with subsequent operations. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 98 Freescale Semiconductor, Inc. Chapter 4 Memory Map 4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map Table 4-2. Peripheral bridge 0 slot assignments System 32-bit base address Slot number Module 0x4000_0000 0 -- 0x4000_1000 1 -- 0x4000_2000 2 -- 0x4000_3000 3 -- 0x4000_4000 4 -- 0x4000_5000 5 -- 0x4000_6000 6 -- 0x4000_7000 7 -- 0x4000_8000 8 DMA controller 0x4000_9000 9 -- 0x4000_A000 10 -- 0x4000_B000 11 -- 0x4000_C000 12 -- 0x4000_D000 13 -- 0x4000_E000 14 -- 0x4000_F000 15 GPIO controller (aliased to 0x400F_F000) 0x4001_0000 16 -- 0x4001_1000 17 -- 0x4001_2000 18 -- 0x4001_3000 19 -- 0x4001_4000 20 -- 0x4001_5000 21 -- 0x4001_6000 22 -- 0x4001_7000 23 -- 0x4001_8000 24 -- 0x4001_9000 25 -- 0x4001_A000 26 -- 0x4001_B000 27 -- 0x4001_C000 28 -- 0x4001_D000 29 -- 0x4001_E000 30 -- 0x4001_F000 31 -- 0x4002_0000 32 Flash memory 0x4002_1000 33 DMA channel mutiplexer 0 0x4002_2000 34 -- Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 99 Peripheral bridge (AIPS-Lite) memory map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number Module 0x4002_3000 35 -- 0x4002_4000 36 -- 0x4002_5000 37 -- 0x4002_6000 38 -- 0x4002_7000 39 -- 0x4002_8000 40 -- 0x4002_9000 41 -- 0x4002_A000 42 -- 0x4002_B000 43 -- 0x4002_C000 44 -- 0x4002_D000 45 -- 0x4002_E000 46 -- 0x4002_F000 47 -- 0x4003_0000 48 -- 0x4003_1000 49 -- 0x4003_2000 50 -- 0x4003_3000 51 -- 0x4003_4000 52 -- 0x4003_5000 53 -- 0x4003_6000 54 -- 0x4003_7000 55 Periodic interrupt timers (PIT) 0x4003_8000 56 Timer'/PWM (TPM) 0 0x4003_9000 57 Timer'/PWM (TPM) 1 0x4003_A000 58 -- 0x4003_B000 59 Analog-to-digital converter (ADC) 0 0x4003_C000 60 -- 0x4003_D000 61 Real-time clock (RTC) 0x4003_E000 62 -- 0x4003_F000 63 DAC0 0x4004_0000 64 Low-power timer (LPTMR) 0x4004_1000 65 -- 0x4004_2000 66 -- 0x4004_3000 67 -- 0x4004_4000 68 -- 0x4004_5000 69 Touch sense interface (TSI) 0x4004_6000 70 -- 0x4004_7000 71 SIM low-power logic 0x4004_8000 72 System integration module (SIM) 0x4004_9000 73 Port A multiplexing control Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 100 Freescale Semiconductor, Inc. Chapter 4 Memory Map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number Module 0x4004_A000 74 Port B multiplexing control 0x4004_B000 75 -- 0x4004_C000 76 -- 0x4004_D000 77 -- 0x4004_E000 78 -- 0x4004_F000 79 -- 0x4005_0000 80 -- 0x4005_1000 81 -- 0x4005_2000 82 -- 0x4005_3000 83 -- 0x4005_4000 84 -- 0x4005_5000 85 -- 0x4005_6000 86 -- 0x4005_7000 87 -- 0x4005_8000 88 -- 0x4005_9000 89 -- 0x4005_A000 90 -- 0x4005_B000 91 -- 0x4005_C000 92 -- 0x4005_D000 93 -- 0x4005_E000 94 -- 0x4005_F000 95 -- 0x4006_0000 96 -- 0x4006_1000 97 -- 0x4006_2000 98 -- 0x4006_3000 99 -- 0x4006_4000 100 Multi-purpose Clock Generator (MCG) 0x4006_5000 101 System oscillator (OSC) 0x4006_6000 102 I2C 0 0x4006_7000 103 -- 0x4006_8000 104 -- 0x4006_9000 105 -- 0x4006_A000 106 UART 0 0x4006_B000 107 -- 0x4006_C000 108 -- 0x4006_D000 109 -- 0x4006_E000 110 -- 0x4006_F000 111 -- 0x4007_0000 112 -- Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 101 Private Peripheral Bus (PPB) memory map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number Module 0x4007_1000 113 -- 0x4007_2000 114 -- 0x4007_3000 115 Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) 0x4007_4000 116 -- 0x4007_5000 117 -- 0x4007_6000 118 SPI 0 0x4007_7000 119 -- 0x4007_8000 120 -- 0x4007_9000 121 -- 0x4007_A000 122 -- 0x4007_B000 123 -- 0x4007_C000 124 Low-leakage wakeup unit (LLWU) 0x4007_D000 125 Power management controller (PMC) 0x4007_E000 126 System Mode controller (SMC) 0x4007_F000 127 Reset Control Module (RCM) 0x400F_F000 128 GPIO controller 4.6.3 Modules Restricted Access in User Mode In user mode, for MCG, RCM, SIM (slot 71 and 72), SMC, LLWU, and PMC, reads are allowed, but writes are blocked and generate bus error. 4.7 Private Peripheral Bus (PPB) memory map The PPB is part of the defined ARM bus architecture and provides access to select processor-local modules. These resources are only accessible from the core; other system masters do not have access to them. Table 4-3. PPB memory map System 32-bit Address Range 0xE000_0000-0xE000_DFFF Resource Additional Range Detail Resource Reserved Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 102 Freescale Semiconductor, Inc. Chapter 4 Memory Map Table 4-3. PPB memory map (continued) System 32-bit Address Range 0xE000_E000-0xE000_EFFF Resource System Control Space (SCS) 0xE000_F000-0xE00F_EFFF Reserved 0xE00F_F000-0xE00F_FFFF Core ROM Space (CRS) Additional Range Detail Resource 0xE000_E000-0xE000_E00F Reserved 0xE000_E010-0xE000_E0FF SysTick 0xE000_E100-0xE000_ECFF NVIC 0xE000_ED00-0xE000_ED8F System Control Block 0xE000_ED90-0xE000_EDEF Reserved 0xE000_EDF0-0xE000_EEFF Debug 0xE000_EF00-0xE000_EFFF Reserved KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 103 Private Peripheral Bus (PPB) memory map KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 104 Freescale Semiconductor, Inc. Chapter 5 Clock Distribution 5.1 Introduction This chapter presents the clock architecture for the device, the overview of the clocks and includes a terminology section. The Cortex M0+ resides within a synchronous core platform, where the processor and bus masters, Flash and peripherals clocks can be configured independently. The clock distribution figure shows how clocks from the MCG and XOSC modules are distributed to the microcontroller's other function units. Some modules in the microcontroller have selectable clock input. 5.2 Programming model The selection and multiplexing of system clock sources is controlled and programmed via the MCG module. The setting of clock dividers and module clock gating for the system are programmed via the SIM module. Reference those sections for detailed register and bit descriptions. 5.3 High-Level device clocking diagram The following system oscillator, MCG, and SIM module registers control the multiplexers, dividers, and clock gates shown in the below figure: OSC MCG SIM Multiplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2 Dividers -- MCG_Cx SIM_CLKDIVx Clock gates OSC_CR MCG_C1 SIM_SCGCx KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 105 Clock definitions SIM MCG 4 MHz IRC FCRDIV MCGIRCLK CG 32 kHz IRC FLL OUTDIV1 CG OUTDIV4 CG Clock options for some peripherals (see note) Core clock, platform clock, and system clock MCGOUTCLK Bus clock/ Flash clock FRDIV System oscillator EXTAL0 OSCCLK XTAL_CLK XTAL0 OSC logic OSCERCLK CG ERCLK32K OSC32KCLK RTC_CLKIN Clock options for some peripherals (see note) MCGFLLCLK PMC PMC logic Counter logic LPO RTC_CLKOUT 1Hz RTC CG -- Clock gate Note: See subsequent sections for details on where these clocks are used. Figure 5-1. Clocking diagram 5.4 Clock definitions The following table describes the clocks in the previous block diagram. Clock name Description Core clock MCGOUTCLK divided by OUTDIV1, clocks the ARM CortexM0+ core Platform clock MCGOUTCLK divided by OUTDIV1, clocks the crossbar switch and NVIC System clock MCGOUTCLK divided by OUTDIV1, clocks the bus masters directly Bus clock System clock divided by OUTDIV4, clocks the bus slaves and peripherals. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 106 Freescale Semiconductor, Inc. Chapter 5 Clock Distribution Clock name Description Flash clock Flash memory clock. On this device it is the same as Bus clock. MCGIRCLK MCG output of the slow or fast internal reference clock MCGOUTCLK MCG output of either IRC, MCGFLLCLK or MCG's external reference clock that sources the core, system, bus, and flash clock. MCGFLLCLK MCG output of the FLL. MCGFLLCLK may clock some modules. In addition, this clock is used for UART0 and TPM modules. OSCCLK System oscillator output of the internal oscillator or sourced directly from EXTAL. Used as MCG external reference clock. OSCERCLK System oscillator output sourced from OSCCLK that may clock some on-chip modules OSC32KCLK System oscillator 32kHz output ERCLK32K Clock source for some modules that is chosen as OSC32KCLK or RTC_CLKIN LPO PMC 1kHz output 5.4.1 Device clock summary The following table provides more information regarding the on-chip clocks. Table 5-1. Clock Summary Clock name Run mode VLPR mode Clock source Clock is disabled when... clock frequency clock frequency MCGOUTCLK Up to 48 MHz Up to 4 MHz MCG In all stop modes except for partial stop modes and during PLL locking when MCGOUTCLK derived from PLL. MCGFLLCLK Up to 48 MHz N/A MCG MCG clock controls do not enable and in all stop modes Core clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock divider In all wait and stop modes Platform clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock divider In all stop modes System clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock divider In all stop modes and Compute Operation Bus clock Up to 24 MHz Up to 1 MHz 1 MCGOUTCLK clock divider In all stop modes except for partial STOP2 mode, and Compute Operation SWD Clock Up to 24MHz Up to 1MHz SWD_CLK pin In all stop modes Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 107 Clock definitions Table 5-1. Clock Summary (continued) Clock name Flash clock Run mode VLPR mode clock frequency clock frequency Up to 24 MHz Up to 1 MHz in BLPE Up to 800 kHz in BLPI Internal reference (MCGIRCLK) 30-40 kHz Slow IRC 4 MHz Fast IRC only Clock source Clock is disabled when... MCGOUTCLK clock divider In all stop modes except for partial STOP2 mode MCG MCG_C1[IRCLKEN] cleared, or 4 MHz Fast IRC Stop/VLPS mode and MCG_C1[IREFSTEN] cleared, or LLS/VLLS mode External reference (OSCERCLK) Up to 48 MHz (bypass), Up to 16 MHz (bypass), System OSC 30-40 kHz or 3-32 MHz (crystal) System OSC's OSC_CR[ERCLKEN] cleared, or 30-40 kHz (low-range crystal) Stop mode and OSC_CR[EREFSTEN] cleared or 3-16 MHz (high-range crystal) External reference 32kHz 30-40 kHz 30-40 kHz or VLLS0 and oscillator not in external clock mode. System OSC System OSC's OSC_CR[ERCLKEN] cleared , or RTC_CLKIN (ERCLK32K) and RTC's RTC_CR[OSCE] cleared or VLLS0 and oscillator not in external clock mode. RTC_CLKOUT LPO TPM clock RTC 1Hz, RTC 1Hz, RTC 1Hz, Clock is disabled in LLS and VLLSx modes OSCERCLK OSCERCLK OSCERCLK 1 kHz 1 kHz PMC in VLLS0 Up to 48 MHz Up to 8 MHz MCGIRCLK, MCGFLLCLK, or SIM_SOPT2[TPMSRC ]=00 or selected clock source disabled. OSCERCLK UART0 clock Up to 48 MHz Up to 8 MHz MCGIRCLK, MCGFLLCLK, or SIM_SOPT2[UART0SR C]=00 or selected clock source disabled. OSCERCLK 1. If in BLPI mode, where clocking is derived from the fast internal reference clock, the Bus clock and flash clock frequency needs to be limited to 800 kHz if executing from flash. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 108 Freescale Semiconductor, Inc. Chapter 5 Clock Distribution 5.5 Internal clocking requirements The clock dividers are programmed via the SIM module's CLKDIV registers. The following requirements must be met when configuring the clocks for this device: 1. The core, platform, and system clock are programmable from a divide-by-1 through divide-by-16 setting. The core, platform, and system clock frequencies must be 48 MHz or slower. 2. The bus clock and flash clock frequency is divided from the system clock and is programmable from a divide-by-1 through divide-by-8 setting. The bus clock and flash clock must be programmed to 24 MHz or slower. The following is a common clock configuration for this device: Clock Frequency Core clock 48 MHz Platform clock 48 MHz System clock 48 MHz Bus clock 24 MHz Flash clock 24 MHz 5.5.1 Clock divider values after reset Each clock divider is programmed via the SIM module's CLKDIV1 registers. Two bits in the flash memory's FTFA_FOPT register controls the reset value of the core clock, system clock, bus clock, and flash clock dividers as shown below: FTFA_FOPT [4,0] Core/system clock Bus/Flash clock Description 00 0x7 (divide by 8) 0x1 (divide by 2) Low power boot 01 0x3 (divide by 4) 0x1 (divide by 2) Low power boot 10 0x1 (divide by 2) 0x1 (divide by 2) Low power boot 11 0x0 (divide by 1) 0x1 (divide by 2) Fast clock boot This gives the user flexibility in selecting between a lower frequency, low-power boot option vs. higher frequency, higher power during and after reset. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 109 Clock Gating The flash erased state defaults to fast clocking mode, since these bits reside in flash, which is logic 1 in the flash erased state. To enable a lower power boot option, program the appropriate bits in FTFA_FOPT. During the reset sequence, if either of the control bits is cleared, the system is in a slower clock configuration. Upon any system reset, the clock dividers return to this configurable reset state. 5.5.2 VLPR mode clocking The clock dividers cannot be changed while in VLPR mode. They must be programmed prior to entering VLPR mode to guarantee operation. Max frequency limitations for VLPR mode is as follows : * the core/system clocks are less than or equal to 4 MHz, and * the bus and flash clocks are less than or equal to 1 MHz NOTE When the MCG is in BLPI and clocking is derived from the Fast IRC, the clock divider controls (MCG_SC[FCRDIV], SIM_CLKDIV1[OUTDIV1], and SIM_CLKDIV1[OUTDIV4]) must be programmed such that the resulting flash clock nominal frequency is 800 kHz or less. In this case, one example of correct configuration is MCG_SC[FCRDIV]=000b, SIM_CLKDIV1[OUTDIV1]=0000b and SIM_CLKDIV1[OUTDIV4]=100b, resulting in a divide by 5 setting. 5.6 Clock Gating The clock to each module can be individually gated on and off using the SIM module's SCGCx registers. These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing a module, set the corresponding bit in SCGCx register to enable the clock. Before turning off the clock, make sure to disable the module. Any bus access to a peripheral that has its clock disabled generates an error termination. 5.7 Module clocks The following table summarizes the clocks associated with each module. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 110 Freescale Semiconductor, Inc. Chapter 5 Clock Distribution Table 5-2. Module clocks Module Bus interface clock Internal clocks I/O interface clocks Core modules ARM Cortex-M0+ core Platform clock Core clock -- NVIC Platform clock -- -- DAP Platform clock -- SWD_CLK System modules DMA System clock -- -- DMA Mux Bus clock -- -- Port control Bus clock -- -- Crossbar Switch Platform clock -- -- Peripheral bridges System clock Bus clock -- LLWU, PMC, SIM, RCM Bus clock LPO -- Mode controller Bus clock -- -- MCM Platform clock -- -- Watchdog timer Bus clock LPO -- Clocks MCG Bus clock MCGOUTCLK, MCGFLLCLK, MCGIRCLK, OSCERCLK -- OSC Bus clock OSCERCLK -- Memory and memory interfaces Flash Controller Platform clock Flash clock -- Flash memory Flash clock -- -- Analog ADC Bus clock OSCERCLK -- CMP Bus clock -- -- DAC Bus clock -- -- Timers TPM Bus clock TPM clock TPM_CLKIN0, TPM_CLKIN1 PIT Bus clock -- -- LPTMR Bus clock LPO, OSCERCLK, MCGIRCLK, ERCLK32K -- RTC Bus clock ERCLK32K RTC_CLKOUT Communication interfaces SPI0 Bus clock -- SPI0_SCK I2C0 Bus clock -- I2C0_SCL UART0 Bus clock UART0 clock -- Human-machine interfaces GPIO Platform clock -- -- TSI Bus clock -- -- KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 111 Module clocks 5.7.1 PMC 1-kHz LPO clock The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all modes of operation, including all low power modes except VLLS0. This 1-kHz source is commonly referred to as LPO clock or 1-kHz LPO clock. 5.7.2 COP clocking The COP may be clocked from two clock sources as shown in the following figure. LPO COP clock Bus clock SIM_COPCTRL[COPCLKS] Figure 5-2. COP clock generation 5.7.3 RTC clocking The RTC module can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the RTC is to continue operating in all required low-power modes. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 112 Freescale Semiconductor, Inc. Chapter 5 Clock Distribution LPO ERCLK32K (to RTC) RTC_CLKIN OSC32KCLK SIM_SOPT1[OSC32KSEL] Figure 5-3. RTC clock generation 5.7.4 LPTMR clocking The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes. MCGIRCLK LPO LPO LPTMRx prescaler/glitch filter clock ERCLK32K RTC_CLKIN OSCERCLK OSC32KCLK SIM_SOPT1[OSC32KSEL] LPTMRx_PSR[PCS] Figure 5-4. LPTMRx prescaler/glitch filter clock generation 5.7.5 TPM clocking The counter for the TPM modules have a selectable clock as shown in the following figure. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 113 Module clocks NOTE The chosen clock must remain enabled if the TPMx is to continue operating in all required low-power modes. MCGIRCLK OSCERCLK TPM clock MCGFLLCLK SIM_SOPT2[TPMSRC] Figure 5-5. TPM clock generation 5.7.6 UART clocking The UART0 module has a selectable clock as shown in the following figure. NOTE The chosen clock must remain enabled if the UART0 is to continue operating in all required low-power modes. MCGIRCLK OSCERCLK UART0 clock MCGFLLCLK SIM_SOPT2[UART0SRC] Figure 5-6. UART0 clock generation KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 114 Freescale Semiconductor, Inc. Chapter 6 Reset and Boot 6.1 Introduction The following reset sources are supported in this MCU: Table 6-1. Reset sources Reset sources POR reset Description * Power-on reset (POR) System resets Debug reset * * * * * * * * * External pin reset (PIN) Low-voltage detect (LVD) Computer operating properly (COP) watchdog reset Low leakage wakeup (LLWU) reset Multipurpose clock generator loss of clock (LOC) reset Stop mode acknowledge error (SACKERR) Software reset (SW) Lockup reset (LOCKUP) MDM DAP system reset * Debug reset Each of the system reset sources has an associated bit in the system reset status (SRS) registers. See the Reset Control Module for register details. The MCU can exit and reset in functional mode where the CPU is executing code (default) or the CPU is in a debug halted state. There are several boot options that can be configured. See Boot information for more details. 6.2 Reset This section discusses basic reset mechanisms and sources. Some modules that cause resets can be configured to cause interrupts instead. Consult the individual peripheral chapters for more information. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 115 Reset 6.2.1 Power-on reset (POR) When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (VPOR), the POR circuit causes a POR reset condition. As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has risen above the LVD low threshold (VLVDL). The POR and LVD bits in reset status register are set following a POR. 6.2.2 System reset sources Resetting the MCU provides a way to start processing from a known set of initial conditions. System reset begins with the on-chip regulator in full regulation and system clocking generation from an internal reference. When the processor exits reset, it performs the following: * Reads the start SP (SP_main) from vector-table offset 0 * Reads the start PC from vector-table offset 4 * LR is set to 0xFFFF_FFFF The on-chip peripheral modules are disabled and the non-analog I/O pins are initially configured as disabled. The pins with analog functions assigned to them default to their analog function after reset. During and following a reset, the SWD pins have their associated input pins configured as: * SWD_CLK in pull-down (PD) * SWD_DIO in pull-up (PU) 6.2.2.1 External pin reset (RESET) This pin is open drain and has an internal pullup device. Asserting RESET wakes the device from any mode. The RESET pin can be disabled by programming RESET_PIN_CFG option bit to 0. When this option selected, there could be a short period of contention during a POR ramp where the device drives the pin out low prior to establishing the setting of this option and releasing the RESET function on the pin. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 116 Freescale Semiconductor, Inc. Chapter 6 Reset and Boot 6.2.2.1.1 Reset pin filter The RESET pin filter supports filtering from both the 1 kHz LPO clock and the bus clock. The RPFC[RSTFLTSS], RPFC[RSTFLTSRW], and RPFW[RSTFLTSEL] fields in the reset control (RCM) register set control this functionality; see the RCM chapter. The filters are asynchronously reset by Chip POR. The reset value for each filter assumes the RESET pin is negated. For all stop modes where LPO clock is still active (Stop, VLPS, LLS, VLLS3, and VLLS1), the only filtering option is the LPO based digital filter. The filtering logic either switches to bypass operation or has continued filtering operation depending on the filtering mode selected. When entering VLLS0, the RESET pin filter is disabled and bypassed. The LPO filter has a fixed filter value of 3. Due to a synchronizer on the input data, there is also some associated latency (2 cycles). As a result, 5 cycles are required to complete a transition from low to high or high to low. 6.2.2.2 Low-voltage detect (LVD) The chip includes a system for managing low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system consists of a power-on reset (POR) circuit and an LVD circuit with a user-selectable trip voltage. The LVD system is always enabled in normal run, wait, or stop mode. The LVD system is disabled when entering VLPx, LLS, or VLLSx modes. The LVD can be configured to generate a reset upon detection of a low voltage condition by setting the PMC's LVDSC1[LVDRE] bit to 1. The low voltage detection threshold is determined by the PMC's LVDSC1[LVDV] field. After an LVD reset has occurred, the LVD system holds the MCU in reset until the supply voltage has risen above the low voltage detection threshold. The RCM's SRS0[LVD] bit is set following either an LVD reset or POR. 6.2.2.3 Computer operating properly (COP) watchdog timer The computer operating properly (COP) watchdog timer (WDOG) monitors the operation of the system by expecting periodic communication from the software. This communication is generally known as servicing (or refreshing) the COP watchdog. If this periodic refreshing does not occur, the watchdog issues a system reset. The COP reset causes the RCM's SRS0[WDOG] bit to set. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 117 Reset 6.2.2.4 Low leakage wakeup (LLWU) The LLWU module provides the means for a number of external pins and a number of internal peripherals to wake the MCU from low leakage power modes. The LLWU module is functional only in low leakage power modes. In VLLSx modes, all enabled inputs to the LLWU can generate a system reset. After a system reset, the LLWU retains the flags indicating the input source of the last wakeup until the user clears them. NOTE Some flags are cleared in the LLWU and some flags are required to be cleared in the peripheral module. Refer to the individual peripheral chapters for more information. 6.2.2.5 Multipurpose clock generator loss-of-clock (LOC) The MCG module supports an external reference clock. If the C6[CME] bit in the MCG module is set, the clock monitor is enabled. If the external reference falls below floc_low or floc_high, as controlled by the C2[RANGE] field in the MCG module, the MCU resets. The RCM's SRS0[LOC] bit is set to indicate this reset source. NOTE To prevent unexpected loss of clock reset events, all clock monitors must be disabled before entering any low power modes, including VLPR and VLPW. 6.2.2.6 Stop mode acknowledge error (SACKERR) This reset is generated if the core attempts to enter stop mode or Compute Operation, but not all modules acknowledge stop mode within 1025 cycles of the 1 kHz LPO clock. A module might not acknowledge the entry to stop mode if an error condition occurs. The error can be caused by a failure of an external clock input to a module. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 118 Freescale Semiconductor, Inc. Chapter 6 Reset and Boot 6.2.2.7 Software reset (SW) The SYSRESETREQ bit in the NVIC application interrupt and reset control register can be set to force a software reset on the device. (See ARM's NVIC documentation for the full description of the register fields, especially the VECTKEY field requirements.) Setting SYSRESETREQ generates a software reset request. This reset forces a system reset of all major components except for the debug module. A software reset causes the RCM's SRS1[SW] bit to set. 6.2.2.8 Lockup reset (LOCKUP) The LOCKUP gives immediate indication of seriously errant kernel software. This is the result of the core being locked because of an unrecoverable exception following the activation of the processor's built in system state protection hardware. The LOCKUP condition causes a system reset and also causes the RCM's SRS1[LOCKUP] bit to set. 6.2.2.9 MDM-AP system reset request Set the system reset request bit in the MDM-AP control register to initiate a system reset. This is the primary method for resets via the SWD interface. The system reset is held until this bit is cleared. Set the core hold reset bit in the MDM-AP control register to hold the core in reset as the rest of the chip comes out of system reset. 6.2.3 MCU Resets A variety of resets are generated by the MCU to reset different modules. 6.2.3.1 POR Only The POR Only reset asserts on the POR reset source only. It resets the PMC and RTC. The POR Only reset also causes all other reset types to occur. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 119 Reset 6.2.3.2 Chip POR not VLLS The Chip POR not VLLS reset asserts on POR and LVD reset sources. It resets parts of the SMC and SIM. It also resets the LPTMR. The Chip POR not VLLS reset also causes these resets to occur: Chip POR, Chip Reset not VLLS, and Chip Reset (including Early Chip Reset). 6.2.3.3 Chip POR The Chip POR asserts on POR, LVD, and VLLS Wakeup reset sources. It resets the Reset Pin Filter registers and parts of the SIM and MCG. The Chip POR also causes the Chip Reset (including Early Chip Reset) to occur. 6.2.3.4 Chip Reset not VLLS The Chip Reset not VLLS reset asserts on all reset sources except a VLLS Wakeup that does not occur via the RESET pin. It resets parts of the SMC, LLWU, and other modules that remain powered during VLLS mode. The Chip Reset not VLLS reset also causes the Chip Reset (including Early Chip Reset) to occur. 6.2.3.5 Early Chip Reset The Early Chip Reset asserts on all reset sources. It resets only the flash memory module. It negates before flash memory initialization begins ("earlier" than when the Chip Reset negates). 6.2.3.6 Chip Reset Chip Reset asserts on all reset sources and only negates after flash initialization has completed and the RESET pin has also negated. It resets the remaining modules (the modules not reset by other reset types). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 120 Freescale Semiconductor, Inc. Chapter 6 Reset and Boot 6.2.4 Reset Pin For all reset sources except a VLLS Wakeup that does not occur via the RESET pin, the RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash initialization has completed. After flash initialization has completed, the RESET pin is released, and the internal Chip Reset negates after the RESET pin is pulled high. Keeping the RESET pin asserted externally delays the negation of the internal Chip Reset. The RESET pin can be disabled by programming RESET_PIN_CFG option bit to 0. When this option is selected, there could be a short period of contention during a POR ramp where the device drives the pin out low prior to establishing the setting of this option and releasing the RESET function on the pin. 6.2.5 Debug resets The following sections detail the debug resets available on the device. 6.2.5.1 Resetting the Debug subsystem Use the CDBGRSTREQ bit within the DP CTRL/STAT register to reset the debug modules. However, as explained below, using the CDBGRSTREQ bit does not reset all debug-related registers. CDBGRSTREQ resets the debug-related registers within the following modules: * SW-DP * AHB-AP * MDM-AP (MDM control and status registers) CDBGRSTREQ does not reset the debug-related registers within the following modules: * * * * * * * CM0+ core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR) BPU DWT NVIC Crossbar bus switch1 AHB-AP1 Private peripheral bus1 1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available during System Reset. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 121 Boot 6.3 Boot This section describes the boot sequence, including sources and options. Some configuration information such as clock trim values stored in factory programmed flash locations is autoloaded. 6.3.1 Boot sources The CM0+ core adds support for a programmable Vector Table Offset Register (VTOR) to relocate the exception vector table. This device supports booting from internal flash and RAM. This device supports booting from internal flash with the reset vectors located at addresses 0x0 (initial SP_main), 0x4 (initial PC), and RAM with relocating the exception vector table to RAM. 6.3.2 FOPT boot options The flash option register (FOPT) in flash memory module (FTFA) allows the user to customize the operation of the MCU at boot time. The register contains read-only bits that are loaded from the NVM's option byte in the flash configuration field. The default setting for all values in the FOPT register is logic 1 since it is copied from the option byte residing in flash, which has all bits as logic 1 in the flash erased state. To configure for alternate settings, program the appropriate bits in the NVM option byte. The new settings will take effect on subsequent POR, VLLSx recoveries, and any system reset. For more details on programming the option byte, refer to the flash memory chapter. The MCU uses the FTFA_FOPT register bits to configure the device at reset as shown in the following table. Table 6-2. Flash Option Register (FTFA_FOPT) Bit Definitions Bit Num 7-6 Field Reserved Value Definition Reserved for future expansion. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 122 Freescale Semiconductor, Inc. Chapter 6 Reset and Boot Table 6-2. Flash Option Register (FTFA_FOPT) Bit Definitions (continued) Bit Num 5 3 Field Value FAST_INIT Definition Select initialization speed on POR, VLLSx, and any system reset . RESET_PIN_CFG 0 Slower initialization. The Flash initialization will be slower with the benefit of reduced average current during this time. The duration of the recovery will be controlled by the clock divider selection determined by the LPBOOT setting. 1 Fast Initialization.The Flash has faster recoveries at the expense of higher current during these times. Enable/disable control for the RESET pin. 0 RESET pin is disabled following a POR and cannot be enabled as RESET function. When this option is selected, there could be a short period of contention during a POR ramp where the device drives the pin out low prior to establishing the setting of this option and releasing the RESET function on the pin. This bit is preserved through system resets and low power modes. When RESET pin function is disabled it cannot be used as a source for low power mode wakeup. NOTE: When the reset pin has been disabled and security has been enabled by means of the FSEC register, a mass erase can be performed only by setting both the mass erase and system reset request bits in the MDM-AP register. 1 2 NMI_DIS RESET pin is dedicated. The port is configured with pullup enabled, open drain, passive filter enabled. Enable/disable control for the NMI function. 0 NMI interrupts are always blocked. The associated pin continues to default to NMI pin controls with internal pullup enabled. When NMI pin function is disabled it cannot be used as a source for low power mode wakeup. 1 NMI pin/interrupts reset default to enabled. 1 Reserved Reserved for future expansion. 4,0 LPBOOT Control the reset value of OUTDIV1 value in SIM_CLKDIV1 register. Larger divide value selections produce lower average power consumption during POR, VLLSx recoveries and reset sequencing and after reset exit. The recovery times are also extended if the FAST_INIT option is not selected. 00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) 01 Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) 10 Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) 11 Core and system clock divider (OUTDIV1) is 0x0 (divide by 1) 6.3.3 Boot sequence At power up, the on-chip regulator holds the system in a POR state until the input supply is above the POR threshold. The system continues to be held in this static state until the internally regulated supplies have reached a safe operating voltage as determined by the LVD. The Reset Controller logic then controls a sequence to exit reset. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 123 Boot 1. A system reset is held on internal logic, the RESET pin is driven out low, and the MCG is enabled in its default clocking mode. 2. Required clocks are enabled (System Clock, Flash Clock, and any Bus Clocks that do not have clock gate control reset to disabled). 3. The system reset on internal logic continues to be held, but the Flash Controller is released from reset and begins initialization operation while the Reset Control logic continues to drive the RESET pin out low. 4. Early in reset sequencing the NVM option byte is read and stored to FTFA_FOPT. If the bits associated with LPBOOT are programmed for an alternate clock divider reset value, the system/core clock is switched to a slower clock speed. If the FAST_INIT bit is programmed clear, the Flash initialization switches to slower clock resulting longer recovery times. 5. When Flash Initialization completes, the RESET pin is released. If RESET continues to be asserted (an indication of a slow rise time on the RESET pin or external drive in low), the system continues to be held in reset. Once the RESET pin is detected high, the Core clock is enabled and the system is released from reset. 6. When the system exits reset, the processor sets up the stack, program counter (PC), and link register (LR). The processor reads the start SP (SP_main) from vector-table offset 0. The core reads the start PC from vector-table offset 4. LR is set to 0xFFFF_FFFF. The CPU begins execution at the PC location. Subsequent system resets follow this same reset flow. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 124 Freescale Semiconductor, Inc. Chapter 7 Power Management 7.1 Introduction This chapter describes the various chip power modes and functionality of the individual modules in these modes. 7.2 Clocking Modes This sections describes the various clocking modes supported on this device. 7.2.1 Partial Stop Partial Stop is a clocking option that can be taken instead of entering STOP mode and is configured in the SMC Stop Control Register (SMC_STOPCTRL). The Stop mode is only partially entered, which leaves some additional functionality alive at the expense of higher power consumption. Partial Stop can be entered from either Run mode or VLP Run mode. When configured for PSTOP2, only the core and system clocks are gated and the bus clock remains active. The bus masters and bus slaves clocked by the system clock enter Stop mode, but the bus slaves clocked by bus clock remain in Run (or VLP Run) mode. The clock generators in the MCG and the on-chip regulator in the PMC also remain in Run (or VLP Run) mode. Exit from PSTOP2 can be initiated by a reset, an asynchronous interrupt from a bus master or bus slave clocked by the system clock, or a synchronous interrupt from a bus slave clocked by the bus clock. If configured, a DMA request (using the asynchronous DMA wakeup) can also be used to exit Partial Stop for the duration of a DMA transfer before the device is transitioned back into PSTOP2. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 125 Clocking Modes When configured for PSTOP1, both the system clock and bus clock are gated. All bus masters and bus slaves enter Stop mode, but the clock generators in the MCG and the onchip regulator in the PMC remain in Run (or VLP Run) mode. Exit from PSTOP1 can be initiated by a reset or an asynchronous interrupt from a bus master or bus slave. If configured, an asynchronous DMA request can also be used to exit Partial Stop for the duration of a DMA transfer before the device is transitioned back into PSTOP1. PSTOP1 is functionally similar to STOP mode, but offers faster wakeup at the expense of higher power consumption. Another benefit is that it keeps all of the MCG clocks enabled, which can be useful for some of the asynchronous peripherals that can remain functional in Stop modes. 7.2.2 DMA Wakeup The DMA can be configured to wakeup the device on a DMA request whenever it is placed in stop mode. The wakeup is configured per DMA channel and is supported in Compute Operation, PSTOP, STOP and VLPS low power modes. When a DMA wakeup is detected in PSTOP, STOP or VLPS then the device will initiate a normal exit from the low power mode. This can include restoring the on-chip regulator and internal power switches, enabling the clock generators in the MCG, enabling the system and bus clocks (but not the core clock) and negating the stop mode signal to the bus masters and bus slaves. The only difference is that the CPU will remain in the low power mode with the CPU clock disabled. During Compute Operation, a DMA wakeup will initiate a normal exit from Compute Operation. This includes enabling the clocks and negating the stop mode signal to the bus masters and bus slaves. The core clock always remains enabled during Compute Operation. Since the DMA wakeup will enable the clocks and negate the stop mode signals to all bus masters and slaves, software needs to ensure that bus masters and slaves that are not involved with the DMA wakeup and transfer remain in a known state. That can be accomplished by disabling the modules before entry into the low power mode or by setting the Doze enable bit in selected modules. Once the DMA request that initiated the wakeup negates and the DMA completes the current transfer, the device will transition back into the original low power mode. This includes requesting all non-CPU bus masters to enter Stop mode and then requesting bus slaves to enter Stop mode. In STOP and VLPS modes the MCG and PMC would then also enter their appropriate modes. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 126 Freescale Semiconductor, Inc. Chapter 7 Power Management NOTE If the requested DMA transfer cannot cause the DMA request to negate then the device will remain in a higher power state until the low power mode is fully exited. An enabled DMA wakeup can cause an aborted entry into the low power mode, if the DMA request asserts during the stop mode entry sequence (or reentry if the request asserts during a DMA wakeup) and can cause the SMC to assert its Stop Abort flag. Once the DMA wakeup completes, entry into the low power mode will restart. An interrupt that occurs during a DMA wakeup will cause an immediate exit from the low power mode (this is optional for Compute Operation) without impacting the DMA transfer. A DMA wakeup can be generated by either a synchronous DMA request or an asynchronous DMA request. Not all peripherals can generate an asynchronous DMA request in stop modes, although in general if a peripheral can generate synchronous DMA requests and also supports asynchronous interrupts in stop modes, then it can generate an asynchronous DMA request. 7.2.3 Compute Operation Compute Operation is an execution or compute-only mode of operation that keeps the CPU enabled with full access to the SRAM and Flash read port, but places all other bus masters and bus slaves into their stop mode. Compute Operation can be enabled in either Run mode or VLP Run mode. NOTE Do not enter any stop mode without first exiting Compute Operation. Because Compute Operation reuses the stop mode logic (including the staged entry with bus masters disabled before bus slaves), any bus master or bus slave that can remain functional in stop mode also remains functional in Compute Operation, including generation of asynchronous interrupts and DMA requests. When enabling Compute Operation in Run mode, module functionality for bus masters and slaves is the equivalent of STOP mode. When enabling Compute Operation in VLP Run mode, module functionality for bus masters and slaves is the equivalent of VLPS mode. The MCG, PMC, SRAM and Flash read port are not affected by Compute Operation, although the Flash register interface is disabled. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 127 Clocking Modes During Compute Operation, the AIPS peripheral space is disabled and attempted accesses generate bus errors. The private peripheral space remains accessible during Compute Operation, including the MCM, NVIC, IOPORT and SysTick. Although access to the GPIO registers via the IOPORT is supported, the GPIO port data input registers do not return valid data since clocks are disabled to the Port Control and Interrupt modules. By writing to the GPIO port data output registers, it is possible to control those GPIO ports that are configured as output pins. Compute Operation is controlled by the CPO register in the MCM, which is only accessible to the CPU. Setting or clearing the CPOREQ bit in the MCM initiates entry or exit into Compute Operation. Compute Operation can also be configured to exit automatically on detection of an interrupt, which is required in order to service most interrupts. Only the core system interrupts (exceptions, including NMI and SysTick) and any edge sensitive interrupts can be serviced without exiting Compute Operation. When entering Compute Operation, the CPOACK status bit indicates when entry has completed. When exiting Compute Operation in Run mode, the CPOACK status bit negates immediately. When exiting Compute Operation in VLP Run mode, the exit is delayed to allow the PMC to handle the change in power consumption. This delay means the CPOACK bit is polled to determine when the AIPS peripheral space can be accessed without generating a bus error. The DMA wakeup is also supported during Compute Operation and causes the CPOACK status bit to clear and the AIPS peripheral space to be accessible for the duration of the DMA wakeup. At the completion of the DMA wakeup, the device transitions back into Compute Operation. 7.2.4 Peripheral Doze Several peripherals support a peripheral Doze mode, where a register bit can be used to disable the peripheral for the duration of a low power mode. The Flash can also be placed in a low power state during Peripheral Doze via a register bit in the SIM. Peripheral Doze is defined to include all of the modes of operation listed below. * The CPU is in wait mode. * The CPU is in stop mode, including the entry sequence and for the duration of a DMA wakeup. * The CPU is in Compute Operation, including the entry sequence and for the duration of a DMA wakeup. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 128 Freescale Semiconductor, Inc. Chapter 7 Power Management Peripheral Doze can therefore be used to disable selected bus masters or slaves for the duration of WAIT or VLPW mode. It can also be used to disable selected bus slaves immediately on entry into any stop mode (or Compute Operation), instead of waiting for the bus masters to acknowledge the entry as part of the stop entry sequence. Finally, it can be used to disable selected bus masters or slaves that should remain inactive during a DMA wakeup. If the Flash is not being accessed during WAIT and PSTOP modes, then the Flash Doze mode can be used to reduce power consumption, at the expense of a slightly longer wakeup when executing code and vectors from Flash. It can also be used to reduce power consumption during Compute Operation when executing code and vectors from SRAM. 7.2.5 Clock Gating To conserve power, the clocks to most modules can be turned off using the SCGCx registers in the SIM module. These bits are cleared after any reset, which disables the clock to the corresponding module. Prior to initializing a module, set the corresponding bit in the SCGCx register to enable the clock. Before turning off the clock, make sure to disable the module. For more details, refer to the clock distribution and SIM chapters. 7.3 Power modes The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed. Depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention, partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. The following table compares the various power modes available. For each run mode there is a corresponding wait and stop mode. Wait modes are similar to ARM sleep modes. Stop modes (VLPS, STOP) are similar to ARM sleep deep mode. The very low power run (VLPR) operating mode can drastically reduce runtime power when the maximum bus frequency is not required to handle the application needs. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 129 Power modes The three primary modes of operation are run, wait and stop. The WFI instruction invokes both wait and stop modes for the chip. The primary modes are augmented in a number of ways to provide lower power based on application needs. Table 7-1. Chip power modes Chip mode Description Normal run Allows maximum performance of chip. Default mode out of reset; onchip voltage regulator is on. Core mode Normal recovery method Run -- Normal Wait via WFI Allows peripherals to function while the core is in sleep mode, reducing power. NVIC remains sensitive to interrupts; peripherals continue to be clocked. Sleep Interrupt Normal Stop via WFI Places chip in static state. Lowest power mode that retains all registers while maintaining LVD protection. NVIC is disabled; AWIC is used to wake up from interrupt; peripheral clocks are stopped. Sleep Deep Interrupt Run -- Sleep Interrupt Sleep Deep Interrupt Sleep Deep Wakeup Interrupt1 Sleep Deep Wakeup Reset2 VLPR (Very Low On-chip voltage regulator is in a low power mode that supplies only Power Run) enough power to run the chip at a reduced frequency. Only MCG modes BLPI and BLPE can be used in VLPR. Reduced frequency Flash access mode (1 MHz); LVD off; in BLPI clock mode, only the fast internal reference oscillator is available to provide a low power nominal 4MHz source for the core with the nominal bus and flash clock required to be <800kHz; alternatively, BLPE clock mode can be used with an external clock or the crystal oscillator providing the clock source. VLPW (Very Low Power Wait) -via WFI Same as VLPR but with the core in sleep mode to further reduce power; NVIC remains sensitive to interrupts (FCLK = ON). On-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. VLPS (Very Low Places chip in static state with LVD operation off. Lowest power mode Power Stop)-via with ADC and pin interrupts functional. Peripheral clocks are stopped, WFI but OSC, LPTMR, RTC, CMP, TSI can be used. TPM and UART can optionally be enabled if their clock source is enabled. NVIC is disabled (FCLK = OFF); AWIC is used to wake up from interrupt. On-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. All SRAM is operating (content retained and I/O states held). LLS (Low State retention power mode. Most peripherals are in state retention Leakage Stop) mode (with clocks stopped), but OSC, LLWU, LPTMR, RTC, CMP,, TSI can be used. NVIC is disabled; LLWU is used to wake up. NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. All SRAM is operating (content retained and I/O states held). VLLS3 (Very Low Leakage Stop3) Most peripherals are disabled (with clocks stopped), but OSC, LLWU, LPTMR, RTC, CMP, TSI can be used. NVIC is disabled; LLWU is used to wake up. SRAM_U and SRAM_L remain powered on (content retained and I/O states held). Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 130 Freescale Semiconductor, Inc. Chapter 7 Power Management Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method VLLS1 (Very Low Leakage Stop1) Most peripherals are disabled (with clocks stopped), but OSC, LLWU, LPTMR, RTC, CMP, TSI can be used. NVIC is disabled; LLWU is used to wake up. Sleep Deep Wakeup Reset2 VLLS0 (Very Low Leakage Stop 0) Most peripherals are disabled (with clocks stopped), but LLWU, LPTMR, RTC, TSI can be used. NVIC is disabled; LLWU is used to wake up. Sleep Deep Wakeup Reset2 All of SRAM_U and SRAM_L are powered off. All of SRAM_U and SRAM_L are powered off. LPO disabled, optional POR brown-out detection 1. Resumes normal run mode operation by executing the LLWU interrupt service routine. 2. Follows the reset flow with the LLWU interrupt flag set for the NVIC. 7.4 Entering and exiting power modes The WFI instruction invokes wait and stop modes for the chip. The processor exits the low-power mode via an interrupt. For LLS and VLLS modes, the wakeup sources are limited to LLWU generated wakeups, NMI pin, or RESET pin assertions. When the NMI pin or RESET pin have been disabled through associated FOPT settings, then these pins are ignored as wakeup sources. The wake-up flow from VLLSx is always through reset. NOTE The WFE instruction can have the side effect of entering a lowpower mode, but that is not its intended usage. See ARM documentation for more on the WFE instruction. On VLLS recoveries, the I/O pins continue to be held in a static state after code execution begins, allowing software to reconfigure the system before unlocking the I/O. RAM is retained in VLLS3 only. 7.5 Module Operation in Low Power Modes The following table illustrates the functionality of each module while the chip is in each of the low power modes. The standard behavior is shown with some exceptions for Compute Operation (CPO) and Partial Stop2 (PSTOP2). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 131 Module Operation in Low Power Modes (Debug modules are discussed separately; see Debug in Low Power Modes.) Number ratings (such as 4 MHz and 1 Mbps) represent the maximum frequencies or maximum data rates per mode. Also, these terms are used: * FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as FF. * Async operation = Fully functional with alternate clock source, provided the selected clock source remains enabled * static = Module register states and associated memories are retained. * powered = Memory is powered to retain contents. * low power = Memory is powered to retain contents in a lower power state * OFF = Modules are powered off; module is in reset state upon wakeup. For clocks, OFF means disabled. * wakeup = Modules can serve as a wakeup source for the chip. Table 7-2. Module operation in low power modes Modules VLPR VLPW Stop VLPS LLS VLLSx static static OFF Core modules NVIC FF FF static System modules Mode Controller FF FF FF FF FF FF static static static static FF FF2 low power low power ON low power low power low power in VLLS3, OFF in VLLS0/1 disabled disabled ON disabled disabled disabled Brown-out Detection ON ON ON ON ON ON in VLLS1/3, optionally disabled in VLLS03 DMA FF FF static OFF static static OFF ON ON in VLLS1/3, OFF in VLLS0 LLWU1 Regulator LVD Async operation Async operation Async operation in CPO Watchdog FF FF static in CPO static FF in PSTOP2 Clocks 1kHz LPO System oscillator (OSC) MCG ON ON ON ON OSCERCLK max of 16MHz crystal OSCERCLK max of 16MHz crystal OSCERCLK optional OSCERCLK max of 16MHz crystal 4 MHz IRC 4 MHz IRC static MCGIRCLK optional static MCGIRCLK optional limited to low limited to low range/low power range/low power in VLLS1/3, OFF in VLLS0 static - no clock output OFF Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 132 Freescale Semiconductor, Inc. Chapter 7 Power Management Table 7-2. Module operation in low power modes (continued) Modules VLPR VLPW Stop VLPS LLS VLLSx Core clock 4 MHz max OFF OFF OFF OFF OFF Platform clock 4 MHz max 4 MHz max OFF OFF OFF OFF System clock 4 MHz max 4 MHz max OFF OFF OFF OFF 1 MHz max OFF OFF OFF OFF OFF in CPO Bus clock 1 MHz max OFF in CPO 24 MHz max in PSTOP2 from RUN 1 MHz max in PSTOP2 from VLPR Memory and memory interfaces Flash 1 MHz max access - no program low power low power low power OFF OFF low power low power low power low power low power low power in VLLS3, OFF in VLLS0/1 1 Mbps 1 Mbps static OFF static, slave mode receive static OFF static, address match wakeup static OFF static OFF static OFF No register access in CPO SRAM_U and SRAM_L Communication interfaces UART0 Async operation in CPO SPI0 master mode 500 kbps, Async operation Async operation FF in PSTOP2 master mode 500 kbps, slave mode 250 slave mode 250 kbps kbps static, slave mode receive FF in PSTOP2 static, slave mode receive in CPO I2C0 50 kbps 50 kbps static, address match wakeup in CPO static, address match wakeup FF in PSTOP2 Timers TPM FF FF Async operation in CPO PIT FF Async operation Async operation FF in PSTOP2 FF static static static in CPO LPTMR FF FF Async operation Async operation Async operation FF in PSTOP2 Async operation4 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 133 Module Operation in Low Power Modes Table 7-2. Module operation in low power modes (continued) Modules RTC VLPR VLPW FF FF Stop VLPS LLS Async operation Async operation Async operation Async operation in CPO FF in PSTOP2 VLLSx Async operation5 Analog 12-bit ADC FF FF ADC internal clock only ADC internal clock only in CPO CMP6 FF FF FF HS or LS compare FF OFF HS or LS compare LS compare LS compare in VLLS1/3, OFF in VLLS0 static static static, OFF in VLLS0 static static static static output, wakeup input static, pins latched OFF, pins latched Async operation7 Async operation7 Async operation7 FF in PSTOP2 FF static static in CPO 12-bit DAC static FF in PSTOP2 HS or LS compare in CPO 6-bit DAC ADC internal clock only FF in PSTOP2 FF static static in CPO FF in PSTOP2 Human-machine interfaces GPIO FF FF IOPORT write only in CPO TSI FF Async operation in CPO static output, wakeup input FF in PSTOP2 Async operation7 Async operation7 FF in PSTOP2 1. Using the LLWU module, the external pins available for this chip do not require the associated peripheral function to be enabled. It only requires the function controlling the pin (GPIO or peripheral) to be configured as an input to allow a transition to occur to the LLWU. 2. Since LPO clock source is disabled, filters will be bypassed during VLLS0. 3. The STOPCTRL[PORPO] bit in the SMC module controls this option. 4. LPO clock source is not available in VLLS0. Also, to use system OSC in VLLS0 it must be configured for bypass (external clock) operation. Pulse counting is available in all modes. 5. In VLLS0 the only clocking option is from RTC_CLKIN. 6. CMP in stop or VLPS supports high speed or low speed external pin to pin or external pin to DAC compares. CMP in LLS or VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered modes of operation are not available while in stop, VLPS, LLS, or VLLSx modes. 7. TSI wakeup from all low power modes is limited to a single selectable pin. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 134 Freescale Semiconductor, Inc. Chapter 8 Security 8.1 Introduction This device implements security based on the mode selected from the flash module. The following sections provide an overview of flash security and details the effects of security on non-flash modules. 8.2 Flash Security The flash module provides security information to the MCU based on the state held by the FSEC[SEC] bits. The MCU, in turn, confirms the security request and limits access to flash resources. During reset, the flash module initializes the FSEC register using data read from the security byte of the flash configuration field. NOTE The security features apply only to external accesses: debug. CPU accesses to the flash are not affected by the status of FSEC. In the unsecured state all flash commands are available on the programming interfaces either from the debug port (SWD) or user code execution. When the flash is secured (FSEC[SEC] = 00, 01, or 11), the programmer interfaces are only allowed to launch mass erase operations. Additionally, in this mode, the debug port has no access to memory locations. 8.3 Security Interactions with other Modules The flash security settings are used by the system to determine what resources are available. The following sections describe the interactions between modules and the flash security settings or the impact that the flash security has on non-flash modules. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 135 Security Interactions with other Modules 8.3.1 Security Interactions with Debug When flash security is active the SWD port cannot access the memory resources of the MCU. Although most debug functions are disabled, the debugger can write to the Flash Mass Erase in Progress bit to trigger a mass erase (Erase All Blocks) command. A mass erase via the debugger is allowed even when some memory locations are protected. When mass erase is disabled, mass erase via the debugger is blocked. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 136 Freescale Semiconductor, Inc. Chapter 9 Debug 9.1 Introduction This device's debug is based on the ARM CoreSightTM architecture and is configured to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. It provides register and memory accessibility from the external debugger interface, basic run/halt control plus 2 breakpoints and 2 watchpoints. Only one debug interface is supported: * Serial Wire Debug (SWD) 9.2 Debug Port Pin Descriptions The debug port pins default after POR to their SWD functionality. Table 9-1. Serial wire debug pin description Pin Name Type Description SWD_CLK Input Serial Wire Clock. This pin is the clock for debug logic when in the Serial Wire Debug mode. This pin is pulled down internally. SWD_DIO Input / Output Serial wire debug data input/output. The SWD_DIO pin is used by an external debug tool for communication and device control. This pin is pulled up internally. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 137 SWD status and control registers 9.3 SWD status and control registers Through the ARM Debug Access Port (DAP), the debugger has access to the status and control elements, implemented as registers on the DAP bus as shown in the following figure. These registers provide additional control and status for low power mode recovery and typical run-control scenarios. The status register bits also provide a means for the debugger to get updated status of the core without having to initiate a bus transaction across the crossbar switch, thus remaining less intrusive during a debug session. It is important to note that these DAP control and status registers are not memory mapped within the system memory map and are only accessible via the Debug Access Port using SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers shown in the table below. Table 9-2. MDM-AP Register Summary Address Register Description 0x0100_0000 Status See MDM-AP Status Register 0x0100_0004 Control See MDM-AP Control Register 0x0100_00FC IDR Read-only identification register that always reads as 0x001C_0020 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 138 Freescale Semiconductor, Inc. Chapter 9 Debug DPACC APACC A[3:2] RnW Debug Port 0x0C SW-DP See the ARM Debug Interface v5p1 Supplement. Bus Matrix Status MDM-AP SELECT[7:4] (APBANKSEL) selects the bank A[3:2] from the APACC selects the register within the bank SELECT[31:24] = 0x00 selects the AHB-AP See ARM documentation for further details Access Port (AHB-AP) IDR AHB Access Port SELECT[31:24] (APSEL) selects the AP AHB-AP 0x3F A[7:4] A[3:2] RnW 0x00 Data[31:0] 0x01 APSEL Decode Internal Bus Generic Debug Port (DP) Control 0x08 Data[31:0] Read Buffer (RDBUFF) AP Select (SELECT) 0x04 A[3:2] RnW Control/Status (CTRL/STAT) Debug Port ID Register (IDCODE) DP Registers 0x00 Data[31:0] See Control and Status Register Descriptions MDM-AP SELECT[31:24] = 0x01 selects the MDM-AP SELECT[7:4] = 0x0 selects the bank with Status and Ctrl A[3:2] = 2'b00 selects the Status Register A[3:2] = 2'b01 selects the Control Register SELECT[7:4] = 0xF selects the bank with IDR A[3:2] = 2'b11 selects the IDR Register (IDR register reads 0x001C_0020) Figure 9-1. MDM AP Addressing 9.3.1 MDM-AP Control Register Table 9-3. MDM-AP Control register assignments Bit 0 Name Flash Mass Erase in Progress Secure1 Y Description Set to cause mass erase. Cleared by hardware after mass erase operation completes. When mass erase is disabled (via MEEN and SEC settings), the erase request does not occur and the Flash Mass Erase in Progress bit continues to assert until the next system reset. 1 Debug Disable N Set to disable debug. Clear to allow debug operation. When set it overrides the C_DEBUGEN bit within the DHCSR and force disables Debug logic. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 139 SWD status and control registers Table 9-3. MDM-AP Control register assignments (continued) Bit 2 Name Debug Request Secure1 N Description Set to force the core to halt. If the core is in a stop or wait mode, this bit can be used to wakeup the core and transition to a halted state. 3 System Reset Request Y Set to force a system reset. The system remains held in reset until this bit is cleared. 4 Core Hold Reset N Configuration bit to control core operation at the end of system reset sequencing. 0 Normal operation - release the core from reset along with the rest of the system at the end of system reset sequencing. 1 Suspend operation - hold the core in reset at the end of reset sequencing. Once the system enters this suspended state, clearing this control bit immediately releases the core from reset and CPU operation begins. 5 VLLSx Debug Request (VLLDBGREQ) N Set to configure the system to be held in reset after the next recovery from a VLLSx mode. This bit is ignored on a VLLS wakeup via the Reset pin. During a VLLS wakeup via the Reset pin, the system can be held in reset by holding the reset pin asserted allowing the debugger to re-initialize the debug modules. This bit holds the system in reset when VLLSx modes are exited to allow the debugger time to re-initialize debug IP before the debug session continues. The Mode Controller captures this bit logic on entry to VLLSx modes. Upon exit from VLLSx modes, the Mode Controller will hold the system in reset until VLLDBGACK is asserted. The VLLDBGREQ bit clears automatically due to the POR reset generated as part of the VLLSx recovery. 6 VLLSx Debug Acknowledge (VLLDBGACK) N Set to release a system being held in reset following a VLLSx recovery This bit is used by the debugger to release the system reset when it is being held on VLLSx mode exit. The debugger re-initializes all debug IP and then assert this control bit to allow the Mode Controller to release the system from reset and allow CPU operation to begin. The VLLDBGACK bit is cleared by the debugger or can be left set because it clears automatically due to the POR reset generated as part of the next VLLSx recovery. 7 LLS, VLLSx Status Acknowledge N Set this bit to acknowledge the DAP LLS and VLLS Status bits have been read. This acknowledge automatically clears the status bits. This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger. 8- 31 Reserved for future use N 1. Command available in secure mode KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 140 Freescale Semiconductor, Inc. Chapter 9 Debug 9.3.2 MDM-AP Status Register Table 9-4. MDM-AP Status register assignments Bit 0 Name Flash Mass Erase Acknowledge Description The Flash Mass Erase Acknowledge bit is cleared after any system reset. The bit is also cleared at launch of a mass erase command due to write of Flash Mass Erase in Progress bit in MDM AP Control Register. The Flash Mass Erase Acknowledge is set after Flash control logic has started the mass erase operation. When mass erase is disabled (via MEEN and SEC settings), an erase request due to seting of Flash Mass Erase in Progress bit is not acknowledged. 1 Flash Ready Indicate Flash has been initialized and debugger can be configured even if system is continuing to be held in reset via the debugger. 2 System Security Indicates the security state. When secure, the debugger does not have access to the system bus or any memory mapped peripherals. This bit indicates when the part is locked and no system bus access is possible. 3 System Reset Indicates the system reset state. 0 System is in reset 1 System is not in reset 4 Reserved 5 Mass Erase Enable Indicates if the MCU can be mass erased or not 0 Mass erase is disabled 1 Mass erase is enabled 6 Backdoor Access Key Enable Indicates if the MCU has the backdoor access key enabled. 0 Disabled 1 Enabled 7 LP Enabled Decode of SMC_PMCTRL[STOPM] field to indicate that VLPS, LLS, or VLLSx are the selected power mode the next time the ARM Core enters Deep Sleep. 0 Low Power Stop Mode is not enabled 1 Low Power Stop Mode is enabled Usage intended for debug operation in which Run to VLPS is attempted. Per debug definition, the system actually enters the Stop state. A debugger should interpret deep sleep indication (with SLEEPDEEP and SLEEPING asserted), in conjuntion with this bit asserted as the debuggerVLPS status indication. 8 Very Low Power Mode Indicates current power mode is VLPx. This bit is not `sticky' and should always represent whether VLPx is enabled or not. This bit is used to throttle SWD_CLK frequency up/down. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 141 Debug Resets Table 9-4. MDM-AP Status register assignments (continued) Bit 9 Name LLS Mode Exit Description This bit indicates an exit from LLS mode has occurred. The debugger will lose communication while the system is in LLS (including access to this register). Once communication is reestablished, this bit indicates that the system had been in LLS. Since the debug modules held their state during LLS, they do not need to be reconfigured. This bit is set during the LLS recovery sequence. The LLS Mode Exit bit is held until the debugger has had a chance to recognize that LLS was exited and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in MDM AP Control register. 10 VLLSx Modes Exit This bit indicates an exit from VLLSx mode has occurred. The debugger will lose communication while the system is in VLLSx (including access to this register). Once communication is reestablished, this bit indicates that the system had been in VLLSx. Since the debug modules lose their state during VLLSx modes, they need to be reconfigured. This bit is set during the VLLSx recovery sequence. The VLLSx Mode Exit bit is held until the debugger has had a chance to recognize that a VLLS mode was exited and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in MDM AP Control register. 11 - 15 Reserved for future use Always read 0. 16 Core Halted Indicates the Core has entered debug halt mode 17 Core SLEEPDEEP Indicates the Core has entered a low power mode 18 Core SLEEPING SLEEPING==1 and SLEEPDEEP==0 indicates wait or VLPW mode. SLEEPING==1 and SLEEPDEEP==1 indicates stop or VLPS mode. 19 - 31 Reserved for future use Always read 0. 9.4 Debug Resets The debug system receives the following sources of reset: * Debug reset (CDBGRSTREQ bit within the DP CTRL/STAT register) that allows the debugger to reset the debug logic. * System POR reset Conversely the debug system is capable of generating system reset using the following mechanism: * A system reset in the DAP control register which allows the debugger to hold the system in reset. * SYSRESETREQ bit in the NVIC application interrupt and reset control register * A system reset in the DAP control register which allows the debugger to hold the Core in reset. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 142 Freescale Semiconductor, Inc. Chapter 9 Debug 9.5 Micro Trace Buffer (MTB) The Micro Trace Buffer (MTB) provides a simple execution trace capability for the Cortex-M0+ processor. When enabled, the MTB records changes in program flow reported by the Cortex-M0+ processor, via the execution trace interface, into a configurable region of the SRAM. Subsequently an off-chip debugger may extract the trace information, which would allow reconstruction of an instruction flow trace. The MTB does not include any form of load/store data trace capability or tracing of any other information. In addition to providing the trace capability, the MTB also operates as a simple AHB-Lite SRAM controller. The system bus masters, including the processor, have read/write access to all of the SRAM via the AHB-Lite interface, allowing the memory to also be used to store program and data information. The MTB simultaneously stores the trace information into an attached SRAM and allows bus masters to access the memory. The MTB ensures that trace information write accesses to the SRAM take priority over accesses from the AHB-Lite interface. The MTB includes trace control registers for configuring and triggering the MTB functions. The MTB also supports triggering via TSTART and TSTOP control functions in the MTB DWT module. 9.6 Debug in Low Power Modes In low power modes in which the debug modules are kept static or powered off, the debugger cannot gather any debug data for the duration of the low power mode. In the case that the debugger is held static, the debug port returns to full functionality as soon as the low power mode exits and the system returns to a state with active debug. In the case that the debugger logic is powered off, the debugger is reset on recovery and must be reconfigured once the low power mode is exited. 9.7 Debug & Security When flash security is enabled, the debug port capabilities are limited in order to prevent exploitation of secure data. In the secure state the debugger still has access to the status register and can determine the current security state of the device. In the case of a secure device, the debugger only has the capability of performing a mass erase operation. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 143 Debug & Security KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 144 Freescale Semiconductor, Inc. Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction To optimize functionality in small packages, pins have several functions available via signal multiplexing. This chapter illustrates which of this device's signals are multiplexed on which external pin. The Port Control block controls which signal is present on the external pin. Reference that chapter to find which register controls the operation of a specific pin. 10.2 Signal Multiplexing Integration This section summarizes how the module is integrated into the device. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bus controller 1 Register access Transfers Transfers External Pins Module Signal Multiplexing/ Port Control Module Module Figure 10-1. Signal multiplexing integration Table 10-1. Reference links to related information Topic Related module Reference Full description Port control Port control System memory map System memory map Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 145 Signal Multiplexing Integration Table 10-1. Reference links to related information (continued) Topic Related module Reference Clocking Clock Distribution Register access Peripheral bus controller Peripheral bridge 10.2.1 Port control and interrupt module features * 32-pin ports NOTE Not all pins are available on the device. See the following section for details. * Each port is assigned one interrupt. * For DMA requests, each port has a dedicated input to the DMA MUX. The reset state and read/write characteristics of the bit fields within the PORTx_PCRn registers is summarized in the table below. Table 10-2. Port control register configuration summary This field of PORTx_PC Rn Generally resets to Except for Resets to Configurability PS 1 PTA0 0 Fixed - All are read only PE 0 PTA0 and PTA2 1 Yes - All GPIO are configurable DSE 0 No exceptions - all DSE are cleared on reset. -- 4 pins are configurable for High Drive (PTB0, PTB1, PTA12 and PTA13). All are others are fixed for Normal Drive and the associated DSE bit is read only. SRE 1 PTA2, PTA6, PTA7, PTA15, PTB0, PTB15, PTB16 and PTB17 0 Yes - All GPIO are configurable MUX 000 PTA0, PTA2 and PTB5 011 Yes - All GPIO are configurable. MSB (bit2) of MUX is not writable and always reads 0. PFE 0 No exceptions - all PFE are cleared on reset.1 -- The GPIO shared with NMI_b pin is configurable. All other GPIO is fixed and read only. IRQC 000 No exceptions - all are cleared on reset. -- Yes Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 146 Freescale Semiconductor, Inc. Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-2. Port control register configuration summary (continued) This field of PORTx_PC Rn Generally resets to ISF 0 Except for Resets to No exceptions - all are cleared on reset. Configurability -- 1. The RESET pin has the passive analog filter fixed enabled when functioning as the RESET pin (FOPT[RESET_PIN_CFG] = 1) and fixed disabled when configured for other shared functions. 10.2.2 Clock gating The clock to the port control module can be gated on and off using the SCGC5[PORTx] bits in the SIM module. These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing the corresponding module, set SCGC5[PORTx] in the SIM module to enable the clock. Before turning off the clock, make sure to disable the module. For more details, refer to the clock distribution chapter. 10.2.3 Signal multiplexing constraints 1. A given peripheral function must be assigned to a maximum of one package pin. Do not program the same function to more than one pin. 2. To ensure the best signal timing for a given peripheral's interface, choose the pins in closest proximity to each other. 10.3 Pinout 10.3.1 KL05 signal multiplexing and pin assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 48 LQFP 32 QFN 32 LQFP 24 QFN Pin Name Default ALT0 ALT1 ALT2 1 1 1 1 PTB6/ IRQ_2/ LPTMR0_ALT3 DISABLED DISABLED PTB6/ IRQ_2/ LPTMR0_ALT3 TPM0_CH3 2 2 2 2 PTB7/ IRQ_3 DISABLED DISABLED PTB7/ IRQ_3 TPM0_CH2 ALT3 TPM_CLKIN1 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 147 Pinout 48 LQFP 32 QFN 32 LQFP 24 QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 3 -- -- -- PTA14 DISABLED DISABLED PTA14 TPM_CLKIN0 4 -- -- -- PTA15 DISABLED DISABLED PTA15 CLKOUT 5 3 3 3 VDD VDD VDD 6 4 4 3 VREFH VREFH VREFH 7 5 5 4 VREFL VREFL VREFL 8 6 6 4 VSS VSS VSS 9 7 7 5 PTA3 EXTAL0 EXTAL0 PTA3 I2C0_SCL I2C0_SDA 10 8 8 6 PTA4/ LLWU_P0 XTAL0 XTAL0 PTA4/ LLWU_P0 I2C0_SDA I2C0_SCL 11 -- -- -- VSS VSS VSS 12 -- -- -- PTB18 DISABLED DISABLED PTB18 13 -- -- -- PTB19 DISABLED DISABLED PTB19 14 9 9 7 PTA5/ LLWU_P1/ RTC_CLK_IN DISABLED DISABLED PTA5/ LLWU_P1/ RTC_CLK_IN TPM0_CH5 SPI0_SS_b 15 10 10 8 PTA6/ LLWU_P2 DISABLED DISABLED PTA6/ LLWU_P2 TPM0_CH4 SPI0_MISO 16 11 11 -- PTB8 ADC0_SE11 ADC0_SE11 PTB8 TPM0_CH3 17 12 12 -- PTB9 ADC0_SE10 ADC0_SE10 PTB9 TPM0_CH2 18 -- -- -- PTA16/ IRQ_4 DISABLED DISABLED PTA16/ IRQ_4 19 -- -- -- PTA17/ IRQ_5 DISABLED DISABLED PTA17/ IRQ_5 20 -- -- -- PTA18/ IRQ_6 DISABLED DISABLED PTA18/ IRQ_6 21 13 13 9 PTB10 ADC0_SE9/ TSI0_IN7 ADC0_SE9/ TSI0_IN7 PTB10 TPM0_CH1 22 14 14 10 PTB11 ADC0_SE8/ TSI0_IN6 ADC0_SE8/ TSI0_IN6 PTB11 TPM0_CH0 23 15 15 11 PTA7/ IRQ_7/ LLWU_P3 ADC0_SE7/ TSI0_IN5 ADC0_SE7/ TSI0_IN5 PTA7/ IRQ_7/ LLWU_P3 SPI0_MISO SPI0_MOSI 24 16 16 12 PTB0/ IRQ_8/ LLWU_P4 ADC0_SE6/ TSI0_IN4 ADC0_SE6/ TSI0_IN4 PTB0/ IRQ_8/ LLWU_P4 EXTRG_IN SPI0_SCK 25 17 17 13 PTB1/ IRQ_9 ADC0_SE5/ TSI0_IN3/ DAC0_OUT/ CMP0_IN3 ADC0_SE5/ TSI0_IN3/ DAC0_OUT/ CMP0_IN3 PTB1/ IRQ_9 UART0_TX UART0_RX 26 18 18 14 PTB2/ IRQ_10/ LLWU_P5 ADC0_SE4/ TSI0_IN2 ADC0_SE4/ TSI0_IN2 PTB2/ IRQ_10/ LLWU_P5 UART0_RX UART0_TX 27 19 19 15 PTA8 ADC0_SE3/ TSI0_IN1 ADC0_SE3/ TSI0_IN1 PTA8 28 20 20 16 PTA9 ADC0_SE2/ TSI0_IN0 ADC0_SE2/ TSI0_IN0 PTA9 29 -- -- -- PTB20 DISABLED DISABLED PTB20 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 148 Freescale Semiconductor, Inc. Chapter 10 Signal Multiplexing and Signal Descriptions 48 LQFP 32 QFN 32 LQFP 24 QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 30 -- -- -- VSS VSS VSS 31 -- -- -- VDD VDD VDD 32 -- -- -- PTB14/ IRQ_11 DISABLED DISABLED PTB14/ IRQ_11 33 21 21 -- PTA10/ IRQ_12 DISABLED TSI0_IN11 PTA10/ IRQ_12 34 22 22 -- PTA11/ IRQ_13 DISABLED TSI0_IN10 PTA11/ IRQ_13 35 23 23 17 PTB3/ IRQ_14 DISABLED DISABLED PTB3/ IRQ_14 I2C0_SCL UART0_TX 36 24 24 18 PTB4/ IRQ_15/ LLWU_P6 DISABLED DISABLED PTB4/ IRQ_15/ LLWU_P6 I2C0_SDA UART0_RX 37 25 25 19 PTB5/ IRQ_16 NMI_b ADC0_SE1/ CMP0_IN1 PTB5/ IRQ_16 TPM1_CH1 NMI_b 38 26 26 20 PTA12/ IRQ_17/ LPTMR0_ALT2 ADC0_SE0/ CMP0_IN0 ADC0_SE0/ CMP0_IN0 PTA12/ IRQ_17/ LPTMR0_ALT2 TPM1_CH0 TPM_CLKIN0 39 27 27 -- PTA13 TSI0_IN9 TSI0_IN9 PTA13 40 28 28 -- PTB12 TSI0_IN8 TSI0_IN8 PTB12 41 -- -- -- PTA19 DISABLED DISABLED PTA19 42 -- -- -- PTB15 DISABLED DISABLED PTB15 SPI0_MOSI SPI0_MISO 43 -- -- -- PTB16 DISABLED DISABLED PTB16 SPI0_MISO SPI0_MOSI 44 -- -- -- PTB17 DISABLED DISABLED PTB17 TPM_CLKIN1 SPI0_SCK 45 29 29 21 PTB13 ADC0_SE13 ADC0_SE13 PTB13 TPM1_CH1 RTC_CLKOUT 46 30 30 22 PTA0/ IRQ_0/ LLWU_P7 SWD_CLK ADC0_SE12/ CMP0_IN2 PTA0/ IRQ_0/ LLWU_P7 TPM1_CH0 SWD_CLK 47 31 31 23 PTA1/ IRQ_1/ LPTMR0_ALT1 RESET_b DISABLED PTA1/ IRQ_1/ LPTMR0_ALT1 TPM_CLKIN0 RESET_b 48 32 32 24 PTA2 SWD_DIO DISABLED PTA2 CMP0_OUT SWD_DIO EXTRG_IN SPI0_SS_b 10.3.2 KL05 Pinouts The following figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 149 PTA2 PTA1/IRQ_1/LPTMR0_ALT1 PTA0/IRQ_0/LLWU_P7 PTB13 PTB17 PTB16 PTB15 PTA19 PTB12 PTA13 PTA12/IRQ_17/LPTMR0_ALT2 PTB5/IRQ_16 48 47 46 45 44 43 42 41 40 39 38 37 Pinout VREFL 7 30 VSS VSS 8 29 PTB20 PTA3 9 28 PTA9 PTA4/LLWU_P0 10 27 PTA8 VSS 11 26 PTB2/IRQ_10/LLWU_P5 PTB18 12 25 PTB1/IRQ_9 24 VDD PTB0/IRQ_8/LLWU_P4 31 23 6 PTA7/IRQ_7/LLWU_P3 VREFH 22 PTB14/IRQ_11 PTB11 32 21 5 PTB10 VDD 20 PTA10/IRQ_12 PTA18/IRQ_6 33 19 4 PTA17/IRQ_5 PTA15 18 PTA11/IRQ_13 PTA16/IRQ_4 34 17 3 PTB9 PTA14 16 PTB3/IRQ_14 PTB8 35 15 2 PTA6/LLWU_P2 PTB7/IRQ_3 14 PTB4/IRQ_15/LLWU_P6 PTA5/LLWU_P1/RTC_CLK_IN 36 13 1 PTB19 PTB6/IRQ_2/LPTMR0_ALT3 Figure 10-2. KL05 48-pin LQFP pinout diagram KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 150 Freescale Semiconductor, Inc. PTA2 PTA1/IRQ_1/LPTMR0_ALT1 PTA0/IRQ_0/LLWU_P7 PTB13 PTB12 PTA13 PTA12/IRQ_17/LPTMR0_ALT2 PTB5/IRQ_16 32 31 30 29 28 27 26 25 Chapter 10 Signal Multiplexing and Signal Descriptions 21 PTA10/IRQ_12 VREFL 5 20 PTA9 VSS 6 19 PTA8 PTA3 7 18 PTB2/IRQ_10/LLWU_P5 PTA4/LLWU_P0 8 17 PTB1/IRQ_9 PTA6/LLWU_P2 PTA5/LLWU_P1/RTC_CLK_IN 16 4 PTB0/IRQ_8/LLWU_P4 VREFH 15 PTA11/IRQ_13 PTA7/IRQ_7/LLWU_P3 22 14 3 PTB11 VDD 13 PTB3/IRQ_14 PTB10 23 12 2 PTB9 PTB7/IRQ_3 11 PTB4/IRQ_15/LLWU_P6 PTB8 24 10 1 9 PTB6/IRQ_2/LPTMR0_ALT3 Figure 10-3. KL05 32-pin LQFP pinout diagram KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 151 PTA2 PTA1/IRQ_1/LPTMR0_ALT1 PTA0/IRQ_0/LLWU_P7 PTB13 PTB12 PTA13 PTA12/IRQ_17/LPTMR0_ALT2 PTB5/IRQ_16 32 31 30 29 28 27 26 25 Pinout 21 PTA10/IRQ_12 VREFL 5 20 PTA9 VSS 6 19 PTA8 PTA3 7 18 PTB2/IRQ_10/LLWU_P5 PTA4/LLWU_P0 8 17 PTB1/IRQ_9 PTA6/LLWU_P2 PTA5/LLWU_P1/RTC_CLK_IN 16 4 PTB0/IRQ_8/LLWU_P4 VREFH 15 PTA11/IRQ_13 PTA7/IRQ_7/LLWU_P3 22 14 3 PTB11 VDD 13 PTB3/IRQ_14 PTB10 23 12 2 PTB9 PTB7/IRQ_3 11 PTB4/IRQ_15/LLWU_P6 PTB8 24 10 1 9 PTB6/IRQ_2/LPTMR0_ALT3 Figure 10-4. KL05 32-pin QFN pinout diagram KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 152 Freescale Semiconductor, Inc. PTA2 PTA1/IRQ_1/LPTMR0_ALT1 PTA0/IRQ_0/LLWU_P7 PTB13 PTA12/IRQ_17/LPTMR0_ALT2 PTB5/IRQ_16 24 23 22 21 20 19 Chapter 10 Signal Multiplexing and Signal Descriptions VDD VREFH 3 16 PTA9 VREFL VSS 4 15 PTA8 PTA3 5 14 PTB2/IRQ_10/LLWU_P5 PTA4/LLWU_P0 6 13 PTB1/IRQ_9 8 PTB10 PTA6/LLWU_P2 PTA5/LLWU_P1/RTC_CLK_IN 12 PTB3/IRQ_14 PTB0/IRQ_8/LLWU_P4 17 11 2 PTA7/IRQ_7/LLWU_P3 PTB7/IRQ_3 10 PTB4/IRQ_15/LLWU_P6 PTB11 18 9 1 7 PTB6/IRQ_2/LPTMR0_ALT3 Figure 10-5. KL05 24-pin QFN pinout diagram 10.4 Module Signal Description Tables The following sections correlate the chip-level signal name with the signal name used in the module's chapter. They also briefly describe the signal function and direction. 10.4.1 Core Modules Table 10-3. SWD Signal Descriptions Chip signal name Module signal name SWD_DIO SWD_DIO Description Serial wire debug data input/output. The SWD_DIO pin is used by an external debug tool for communication and device control. This pin is pulled up internally. I/O Input / Output Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 153 Module Signal Description Tables Table 10-3. SWD Signal Descriptions (continued) Chip signal name Module signal name SWD_CLK SWD_CLK Description I/O Serial Wire Clock. This pin is the clock for debug logic when in the Serial Wire Debug mode. This pin is pulled down internally. Input 10.4.2 System Modules Table 10-4. System Signal Descriptions Chip signal name Module signal name NMI -- Description I/O Non-maskable interrupt I NOTE: Driving the NMI signal low forces a non-maskable interrupt, if the NMI function is selected on the corresponding pin. RESET -- Reset bi-directional signal I/O VDD -- MCU power I VSS -- MCU ground I 10.4.3 Clock Modules Table 10-5. OSC Signal Descriptions Chip signal name Module signal name EXTAL0 EXTAL XTAL0 XTAL Description I/O External clock/Oscillator input I Oscillator output O 10.4.4 Memories and Memory Interfaces KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 154 Freescale Semiconductor, Inc. Chapter 10 Signal Multiplexing and Signal Descriptions 10.4.5 Analog Table 10-6. ADC 0 Signal Descriptions Chip signal name Module signal name ADC0_SEn ADn VREFH VREFL VDDA VSSA Description I/O Single-Ended Analog Channel Inputs I VREFSH Voltage Reference Select High I VREFSL Voltage Reference Select Low I VDDA Analog Power Supply I VSSA Analog Ground I Table 10-7. CMP 0 Signal Descriptions Chip signal name Module signal name Description I/O CMP0_IN[5:0] IN[5:0] Analog voltage inputs I CMP0_OUT CMPO Comparator output O Table 10-8. DAC 0 Signal Descriptions Chip signal name Module signal name DAC0_OUT -- Description I/O DAC output O 10.4.6 Timer Modules Table 10-9. TPM 0 Signal Descriptions Chip signal name Module signal name TPM_CLKIN[1:0] EXTCLK TPM0_CH[5:0] CHn Description External clock. FTM external clock can be selected to drive the FTM counter. FTM channel (n), where n can be 7-0 I/O I I/O Table 10-10. TPM 1 Signal Descriptions Chip signal name Module signal name Description TPM_CLKIN[1:0] TPM_EXTCLK External clock. TPM external clock can be selected to increment the TPM counter on every rising edge synchronized to the counter clock. TPM1_CH[1:0] TPM_CHn TPM channel (n = 5 to 0) I/O I I/O KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 155 Module Signal Description Tables Table 10-11. LPTMR 0 Signal Descriptions Chip signal name Module signal name Description LPTMR0_ALT[2:1] LPTMR_ALTn Pulse Counter Input pin I/O I Table 10-12. RTC Signal Descriptions Chip signal name Module signal name Description I/O RTC_CLKOUT1 RTC_CLKOUT 1 Hz square-wave output O 1. RTC_CLKOUT can also be driven with OSCERCLK via SIM control bit SIM_SOPT[RCTCLKOUTSEL] 10.4.7 Communication Interfaces Table 10-13. SPI0 Signal Descriptions Chip signal name Module signal name Description I/O SPI0_MISO MISO Master Data In, Slave Data Out I/O SPI0_MOSI MOSI Master Data Out, Slave Data In I/O SPI0_SCLK SPSCK SPI Serial Clock I/O SPI0_PCS0 SS Slave Select I/O Table 10-14. I2C 0 Signal Descriptions Chip signal name Module signal name Description I/O I2C0_SCL SCL Bidirectional serial clock line of the I2C system. I/O I2C0_SDA SDA Bidirectional serial data line of the I2C system. I/O Table 10-15. UART 0 Signal Descriptions Chip signal name Module signal name Description I/O UART0_TX TXD Transmit data O UART0_RX RXD Receive data I KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 156 Freescale Semiconductor, Inc. Chapter 10 Signal Multiplexing and Signal Descriptions 10.4.8 Human-Machine Interfaces (HMI) Table 10-16. GPIO Signal Descriptions Chip signal name Module signal name Description I/O PTA[31:0]1 PORTA31-PORTA0 General-purpose input/output I/O PTB[31:0]1 PORTB31-PORTB0 General-purpose input/output I/O 1. The available GPIO pins depends on the specific package. See the signal multiplexing section for which exact GPIO signals are available. Table 10-17. TSI Signal Descriptions Chip signal name Module signal name TSI0_CH[15:0] TSI[15:0] Description I/O TSI capacitive pins. Switches driver that connects directly to the electrode pins TSI[15:0] can operate as GPIO pins. I/O KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 157 Module Signal Description Tables KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 158 Freescale Semiconductor, Inc. Chapter 11 Port control and interrupts (PORT) 11.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. 11.2 Overview The port control and interrupt (PORT) module provides support for port control, and external interrupt functions. Most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state. There is one instance of the PORT module for each port. Not all pins within each port are implemented on a specific device. 11.2.1 Features The PORT module has the following features: * Pin interrupt on selected pins * Interrupt flag and enable registers for each pin * Support for edge sensitive (rising, falling, both) or level sensitive (low, high) configured per pin * Support for interrupt or DMA request configured per pin * Asynchronous wakeup in Low-Power modes * Pin interrupt is functional in all digital Pin Muxing modes * Port control KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 159 External signal description * Individual pull control fields with pullup, pulldown, and pull-disablesupport on selected pins * Individual drive strength field supporting high and low drive strength on selected pins * Individual slew rate field supporting fast and slow slew rates on selected pins * Individual input passive filter field supporting enable and disable of the individual input passive filter on selected pins * Individual mux control field supporting analog or pin disabled, GPIO, and up to four chip-specific digital functions * Pad configuration fields are functional in all digital Pin Muxing modes 11.2.2 Modes of operation 11.2.2.1 Run mode In Run mode, the PORT operates normally. 11.2.2.2 Wait mode In Wait mode, PORT continues to operate normally and may be configured to exit the Low-Power mode if an enabled interrupt is detected. DMA requests are still generated during the Wait mode, but do not cause an exit from the Low-Power mode. 11.2.2.3 Stop mode In Stop mode, the PORT can be configured to exit the Low-Power mode via an asynchronous wakeup signal if an enabled interrupt is detected. 11.2.2.4 Debug mode In Debug mode, PORT operates normally. 11.3 External signal description The following table describes the PORT external signal. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 160 Freescale Semiconductor, Inc. Chapter 11 Port control and interrupts (PORT) Table 11-1. Signal properties Name Function I/O Reset Pull PORTx[31:0] External interrupt I/O 0 - NOTE Not all pins within each port are implemented on each device. 11.4 Detailed signal description The following table contains the detailed signal description for the PORT interface. Table 11-2. PORT interface--detailed signal description Signal PORTx[31:0] I/O I/O Description External interrupt. State meaning Asserted--pin is logic one. Negated--pin is logic zero. Timing Assertion--may occur at any time and can assert asynchronously to the system clock. Negation--may occur at any time and can assert asynchronously to the system clock. 11.5 Memory map and register definition Any read or write access to the PORT memory space that is outside the valid memory map results in a bus error. All register accesses complete with zero wait states. PORT memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_9000 Pin Control Register n (PORTA_PCR0) 32 R/W See section 11.5.1/164 4004_9004 Pin Control Register n (PORTA_PCR1) 32 R/W See section 11.5.1/164 4004_9008 Pin Control Register n (PORTA_PCR2) 32 R/W See section 11.5.1/164 4004_900C Pin Control Register n (PORTA_PCR3) 32 R/W See section 11.5.1/164 4004_9010 Pin Control Register n (PORTA_PCR4) 32 R/W See section 11.5.1/164 4004_9014 Pin Control Register n (PORTA_PCR5) 32 R/W See section 11.5.1/164 4004_9018 Pin Control Register n (PORTA_PCR6) 32 R/W See section 11.5.1/164 4004_901C Pin Control Register n (PORTA_PCR7) 32 R/W See section 11.5.1/164 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 161 Memory map and register definition PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_9020 Pin Control Register n (PORTA_PCR8) 32 R/W See section 11.5.1/164 4004_9024 Pin Control Register n (PORTA_PCR9) 32 R/W See section 11.5.1/164 4004_9028 Pin Control Register n (PORTA_PCR10) 32 R/W See section 11.5.1/164 4004_902C Pin Control Register n (PORTA_PCR11) 32 R/W See section 11.5.1/164 4004_9030 Pin Control Register n (PORTA_PCR12) 32 R/W See section 11.5.1/164 4004_9034 Pin Control Register n (PORTA_PCR13) 32 R/W See section 11.5.1/164 4004_9038 Pin Control Register n (PORTA_PCR14) 32 R/W See section 11.5.1/164 4004_903C Pin Control Register n (PORTA_PCR15) 32 R/W See section 11.5.1/164 4004_9040 Pin Control Register n (PORTA_PCR16) 32 R/W See section 11.5.1/164 4004_9044 Pin Control Register n (PORTA_PCR17) 32 R/W See section 11.5.1/164 4004_9048 Pin Control Register n (PORTA_PCR18) 32 R/W See section 11.5.1/164 4004_904C Pin Control Register n (PORTA_PCR19) 32 R/W See section 11.5.1/164 4004_9050 Pin Control Register n (PORTA_PCR20) 32 R/W See section 11.5.1/164 4004_9054 Pin Control Register n (PORTA_PCR21) 32 R/W See section 11.5.1/164 4004_9058 Pin Control Register n (PORTA_PCR22) 32 R/W See section 11.5.1/164 4004_905C Pin Control Register n (PORTA_PCR23) 32 R/W See section 11.5.1/164 4004_9060 Pin Control Register n (PORTA_PCR24) 32 R/W See section 11.5.1/164 4004_9064 Pin Control Register n (PORTA_PCR25) 32 R/W See section 11.5.1/164 4004_9068 Pin Control Register n (PORTA_PCR26) 32 R/W See section 11.5.1/164 4004_906C Pin Control Register n (PORTA_PCR27) 32 R/W See section 11.5.1/164 4004_9070 Pin Control Register n (PORTA_PCR28) 32 R/W See section 11.5.1/164 4004_9074 Pin Control Register n (PORTA_PCR29) 32 R/W See section 11.5.1/164 4004_9078 Pin Control Register n (PORTA_PCR30) 32 R/W See section 11.5.1/164 4004_907C Pin Control Register n (PORTA_PCR31) 32 R/W See section 11.5.1/164 4004_9080 Global Pin Control Low Register (PORTA_GPCLR) 32 W (always 0000_0000h reads 0) 11.5.2/166 4004_9084 Global Pin Control High Register (PORTA_GPCHR) 32 W (always 0000_0000h reads 0) 11.5.3/167 4004_90A0 Interrupt Status Flag Register (PORTA_ISFR) 32 w1c 0000_0000h 11.5.4/167 4004_A000 Pin Control Register n (PORTB_PCR0) 32 R/W See section 11.5.1/164 4004_A004 Pin Control Register n (PORTB_PCR1) 32 R/W See section 11.5.1/164 4004_A008 Pin Control Register n (PORTB_PCR2) 32 R/W See section 11.5.1/164 4004_A00C Pin Control Register n (PORTB_PCR3) 32 R/W See section 11.5.1/164 4004_A010 Pin Control Register n (PORTB_PCR4) 32 R/W See section 11.5.1/164 4004_A014 Pin Control Register n (PORTB_PCR5) 32 R/W See section 11.5.1/164 4004_A018 Pin Control Register n (PORTB_PCR6) 32 R/W See section 11.5.1/164 4004_A01C Pin Control Register n (PORTB_PCR7) 32 R/W See section 11.5.1/164 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 162 Freescale Semiconductor, Inc. Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_A020 Pin Control Register n (PORTB_PCR8) 32 R/W See section 11.5.1/164 4004_A024 Pin Control Register n (PORTB_PCR9) 32 R/W See section 11.5.1/164 4004_A028 Pin Control Register n (PORTB_PCR10) 32 R/W See section 11.5.1/164 4004_A02C Pin Control Register n (PORTB_PCR11) 32 R/W See section 11.5.1/164 4004_A030 Pin Control Register n (PORTB_PCR12) 32 R/W See section 11.5.1/164 4004_A034 Pin Control Register n (PORTB_PCR13) 32 R/W See section 11.5.1/164 4004_A038 Pin Control Register n (PORTB_PCR14) 32 R/W See section 11.5.1/164 4004_A03C Pin Control Register n (PORTB_PCR15) 32 R/W See section 11.5.1/164 4004_A040 Pin Control Register n (PORTB_PCR16) 32 R/W See section 11.5.1/164 4004_A044 Pin Control Register n (PORTB_PCR17) 32 R/W See section 11.5.1/164 4004_A048 Pin Control Register n (PORTB_PCR18) 32 R/W See section 11.5.1/164 4004_A04C Pin Control Register n (PORTB_PCR19) 32 R/W See section 11.5.1/164 4004_A050 Pin Control Register n (PORTB_PCR20) 32 R/W See section 11.5.1/164 4004_A054 Pin Control Register n (PORTB_PCR21) 32 R/W See section 11.5.1/164 4004_A058 Pin Control Register n (PORTB_PCR22) 32 R/W See section 11.5.1/164 4004_A05C Pin Control Register n (PORTB_PCR23) 32 R/W See section 11.5.1/164 4004_A060 Pin Control Register n (PORTB_PCR24) 32 R/W See section 11.5.1/164 4004_A064 Pin Control Register n (PORTB_PCR25) 32 R/W See section 11.5.1/164 4004_A068 Pin Control Register n (PORTB_PCR26) 32 R/W See section 11.5.1/164 4004_A06C Pin Control Register n (PORTB_PCR27) 32 R/W See section 11.5.1/164 4004_A070 Pin Control Register n (PORTB_PCR28) 32 R/W See section 11.5.1/164 4004_A074 Pin Control Register n (PORTB_PCR29) 32 R/W See section 11.5.1/164 4004_A078 Pin Control Register n (PORTB_PCR30) 32 R/W See section 11.5.1/164 4004_A07C Pin Control Register n (PORTB_PCR31) 32 R/W See section 11.5.1/164 4004_A080 Global Pin Control Low Register (PORTB_GPCLR) 32 W (always 0000_0000h reads 0) 11.5.2/166 4004_A084 Global Pin Control High Register (PORTB_GPCHR) 32 W (always 0000_0000h reads 0) 11.5.3/167 4004_A0A0 Interrupt Status Flag Register (PORTB_ISFR) 32 w1c 0000_0000h 11.5.4/167 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 163 Memory map and register definition 11.5.1 Pin Control Register n (PORTx_PCRn) NOTE Refer to the Signal Multiplexing and Pin Assignment chapter for the reset value of this device. See the GPIO Configuration section for details on the available functions for each pin. Do not modify pin configuration registers associated with pins not available in your selected package. All un-bonded pins not available in your package will default to DISABLE state for lowest power consumption. Address: Base address + 0h offset + (4d x i), where i=0d to 31d Bit 31 30 29 28 27 26 25 0 R 24 22 ISF 21 20 19 18 0 Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 0 R 0 0 0 0 0 * * 0 7 6 0 MUX W 0 * 0 DSE * 17 16 IRQC w1c W Reset 23 0 0 5 4 0 0 PFE * 0 0 0 0 3 2 1 0 SRE PE PS * * * 0 0 * Notes: * MUX field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. * DSE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. * PFE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. * SRE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. * PE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. * PS field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. PORTx_PCRn field descriptions Field 31-25 Reserved 24 ISF Description This field is reserved. This read-only field is reserved and always has the value 0. Interrupt Status Flag This bit is read only for pins that do not support interrupt generation. The pin interrupt configuration is valid in all digital pin muxing modes. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 164 Freescale Semiconductor, Inc. Chapter 11 Port control and interrupts (PORT) PORTx_PCRn field descriptions (continued) Field Description 0 1 23-20 Reserved 19-16 IRQC Configured interrupt is not detected. Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. This field is reserved. This read-only field is reserved and always has the value 0. Interrupt Configuration This field is read only for pins that do not support interrupt generation. The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configured to generate interrupt/DMA request as follows: 0000 0001 0010 0011 1000 1001 1010 1011 1100 Others 15-11 Reserved 10-8 MUX Interrupt/DMA request disabled. DMA request on rising edge. DMA request on falling edge. DMA request on either edge. Interrupt when logic zero. Interrupt on rising edge. Interrupt on falling edge. Interrupt on either edge. Interrupt when logic one. Reserved. This field is reserved. This read-only field is reserved and always has the value 0. Pin Mux Control Not all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved and may result in configuring the pin for a different pin muxing slot. The corresponding pin is configured in the following pin muxing slot as follows: 000 001 010 011 100 101 110 111 7 Reserved 6 DSE Pin disabled (analog). Alternative 1 (GPIO). Alternative 2 (chip-specific). Alternative 3 (chip-specific). Alternative 4 (chip-specific). Alternative 5 (chip-specific). Alternative 6 (chip-specific). Alternative 7 (chip-specific). This field is reserved. This read-only field is reserved and always has the value 0. Drive Strength Enable This bit is read only for pins that do not support a configurable drive strength. Drive strength configuration is valid in all digital pin muxing modes. 0 1 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. High drive strength is configured on the corresponding pin, if pin is configured as a digital output. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 165 Memory map and register definition PORTx_PCRn field descriptions (continued) Field Description 5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 PFE Passive Filter Enable This bit is read only for pins that do not support a configurable passive input filter. Passive filter configuration is valid in all digital pin muxing modes. 0 1 3 Reserved Passive input filter is disabled on the corresponding pin. Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. This field is reserved. This read-only field is reserved and always has the value 0. 2 SRE Slew Rate Enable This bit is read only for pins that do not support a configurable slew rate. Slew rate configuration is valid in all digital pin muxing modes. 0 1 1 PE Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. Pull Enable This bit is read only for pins that do not support a configurable pull resistor. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for the pins that support a configurable pull resistor. Pull configuration is valid in all digital pin muxing modes. 0 1 0 PS Internal pullup or pulldown resistor is not enabled on the corresponding pin. Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. Pull Select This bit is read only for pins that do not support a configurable pull resistor direction. Pull configuration is valid in all digital pin muxing modes. 0 1 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. 11.5.2 Global Pin Control Low Register (PORTx_GPCLR) Only 32-bit writes are supported to this register. Address: Base address + 80h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 R 0 0 W GPWE GPWD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 166 Freescale Semiconductor, Inc. Chapter 11 Port control and interrupts (PORT) PORTx_GPCLR field descriptions Field Description 31-16 GPWE Global Pin Write Enable Selects which Pin Control Registers (15 through 0) bits [15:0] update with the value in GPWD. 0 1 15-0 GPWD Corresponding Pin Control Register is not updated with the value in GPWD. Corresponding Pin Control Register is updated with the value in GPWD. Global Pin Write Data Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. 11.5.3 Global Pin Control High Register (PORTx_GPCHR) Only 32-bit writes are supported to this register. Address: Base address + 84h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 R 0 0 W GPWE GPWD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PORTx_GPCHR field descriptions Field 31-16 GPWE Description Global Pin Write Enable Selects which Pin Control Registers (31 through 16) bits [15:0] update with the value in GPWD. 0 1 15-0 GPWD Corresponding Pin Control Register is not updated with the value in GPWD. Corresponding Pin Control Register is updated with the value in GPWD. Global Pin Write Data Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. 11.5.4 Interrupt Status Flag Register (PORTx_ISFR) The corresponding bit is read only for pins that do not support interrupt generation. The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt Status Flag for each pin is also visible in the corresponding Pin Control Register, and each flag can be cleared in either location. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 167 Functional description Address: Base address + A0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R ISF W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_ISFR field descriptions Field 31-0 ISF Description Interrupt Status Flag Each bit in the field indicates the detection of the configured interrupt of the same number as the field. 0 1 Configured interrupt is not detected. Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. 11.6 Functional description 11.6.1 Pin control Each port pin has a corresponding pin control register, PORT_PCRn, associated with it. The upper half of the pin control register configures the pin's capability to either interrupt the CPU or request a DMA transfer, on a rising/falling edge or both edges as well as a logic level occurring on the port pin. It also includes a flag to indicate that an interrupt has occurred. The lower half of the pin control register configures the following functions for each pin within the 32-bit port. * * * * Pullup or pulldown enable on selected pins Drive strength and slew rate configuration on selected pins Passive input filter enable on selected pins Pin Muxing mode The functions apply across all digital Pin Muxing modes and individual peripherals do not override the configuration in the pin control register. For example, if an I2C function is enabled on a pin, that does not override the pullup configuration for that pin. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 168 Freescale Semiconductor, Inc. Chapter 11 Port control and interrupts (PORT) When the Pin Muxing mode is configured for analog or is disabled, all the digital functions on that pin are disabled. This includes the pullup and pulldown enables, and passive filter enable. The configuration of each pin control register is retained when the PORT module is disabled. 11.6.2 Global pin control The two global pin control registers allow a single register write to update the lower half of the pin control register on up to sixteen pins, all with the same value. The global pin control registers are designed to enable software to quickly configure multiple pins within the one port for the same peripheral function. However, the interrupt functions cannot be configured using the global pin control registers. The global pin control registers are write-only registers, that always read as zero. 11.6.3 External interrupts The external interrupt capability of the PORT module is available in all digital pin muxing modes provided the PORT module is enabled. Each pin can be individually configured for any of the following external interrupt modes: * * * * * * * * * Interrupt disabled, default out of reset Active high level sensitive interrupt Active low level sensitive interrupt Rising edge sensitive interrupt Falling edge sensitive interrupt Rising and falling edge sensitive interrupt Rising edge sensitive DMA request Falling edge sensitive DMA request Rising and falling edge sensitive DMA request The interrupt status flag is set when the configured edge or level is detected on the output of the pin. When not in Stop mode, the input is first synchronized to the bus clock to detect the configured level or edge transition. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 169 Functional description The PORT module generates a single interrupt that asserts when the interrupt status flag is set for any enabled interrupt for that port. The interrupt negates after the interrupt status flags for all enabled interrupts have been cleared by writing a logic 1 to the ISF flag in either the PORT_ISFR or PORT_PCRn registers. The PORT module generates a single DMA request that asserts when the interrupt status flag is set for any enabled DMA request in that port. The DMA request negates after the DMA transfer is completed, because that clears the interrupt status flags for all enabled DMA requests. During Stop mode, the interrupt status flag for any enabled interrupt is asynchronously set if the required level or edge is detected. This also generates an asynchronous wakeup signal to exit the Low-Power mode. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 170 Freescale Semiconductor, Inc. Chapter 12 System integration module (SIM) 12.1 Introduction The system integration module (SIM) provides system control and chip configuration registers. 12.1.1 Features * System clocking configuration * System clock divide values * Architectural clock gating control * ERCLK32K clock selection * UART0 and TPM clock selection * Flash and System RAM size configuration * TPM external clock and input capture selection * UART receive/transmit source selection/configuration 12.2 Memory map and register definition The SIM module contains many bitfields for selecting the clock source and dividers for various module clocks. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 171 Memory map and register definition NOTE The SIM registers can be written only in supervisor mode. In user mode, write accesses are blocked and will result in a bus error. NOTE The SIM_SOPT1 and SIM_SOPT1CFG registers are located at a different base address than the other SIM registers. SIM memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_7000 System Options Register 1 (SIM_SOPT1) 32 R/W 0000_0000h 12.2.1/173 4004_7004 SOPT1 Configuration Register (SIM_SOPT1CFG) 32 R/W 0000_0000h 12.2.2/173 4004_8004 System Options Register 2 (SIM_SOPT2) 32 R/W 0000_0000h 12.2.3/174 4004_800C System Options Register 4 (SIM_SOPT4) 32 R/W 0000_0000h 12.2.4/176 4004_8010 System Options Register 5 (SIM_SOPT5) 32 R/W 0000_0000h 12.2.5/177 4004_8018 System Options Register 7 (SIM_SOPT7) 32 R/W 0000_0000h 12.2.6/178 4004_8024 System Device Identification Register (SIM_SDID) 32 R See section 12.2.7/180 4004_8034 System Clock Gating Control Register 4 (SIM_SCGC4) 32 R/W F000_0030h 12.2.8/182 4004_8038 System Clock Gating Control Register 5 (SIM_SCGC5) 32 R/W 0000_0180h 12.2.9/183 4004_803C System Clock Gating Control Register 6 (SIM_SCGC6) 32 R/W 0000_0001h 12.2.10/185 4004_8040 System Clock Gating Control Register 7 (SIM_SCGC7) 32 R/W 0000_0100h 12.2.11/186 4004_8044 System Clock Divider Register 1 (SIM_CLKDIV1) 32 R/W See section 12.2.12/187 4004_804C Flash Configuration Register 1 (SIM_FCFG1) 32 R/W See section 12.2.13/189 4004_8050 Flash Configuration Register 2 (SIM_FCFG2) 32 R See section 12.2.14/190 4004_8058 Unique Identification Register Mid-High (SIM_UIDMH) 32 R See section 12.2.15/191 4004_805C Unique Identification Register Mid Low (SIM_UIDML) 32 R See section 12.2.16/191 4004_8060 Unique Identification Register Low (SIM_UIDL) 32 R See section 12.2.17/192 4004_8100 COP Control Register (SIM_COPC) 32 R/W 4004_8104 Service COP Register (SIM_SRVCOP) 32 W 0000_000Ch 12.2.18/192 0000_0000h 12.2.19/193 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 172 Freescale Semiconductor, Inc. Chapter 12 System integration module (SIM) 12.2.1 System Options Register 1 (SIM_SOPT1) NOTE The SOPT1 register is only reset on POR or LVD. Address: 4004_7000h base + 0h offset = 4004_7000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 0 R 19 18 17 16 0 OSC32KSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 R W Reset 0 0 0 0 0 0 0 0 SIM_SOPT1 field descriptions Field Description 31-20 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 19-18 OSC32KSEL 32K oscillator clock select Selects the 32 kHz clock source (ERCLK32K) for RTC and LPTMR. This bit is reset only on POR/LVD. 00 01 10 11 17-0 Reserved System oscillator (OSC32KCLK) Reserved RTC_CLKIN LPO 1kHz This field is reserved. This read-only field is reserved and always has the value 0. 12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG) NOTE The SOPT1CFG register is reset on System Reset not VLLS. Address: 4004_7000h base + 4h offset = 4004_7004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 0 R 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 173 Memory map and register definition SIM_SOPT1CFG field descriptions Field Description 31-24 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 23-0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12.2.3 System Options Register 2 (SIM_SOPT2) SOPT2 contains the controls for selecting many of the module clock source options on this device. See the Clock Distribution chapter for more information including clocking diagrams and definitions of device clocks. Address: 4004_7000h base + 1004h offset = 4004_8004h Bit 31 30 29 28 27 26 25 24 23 22 21 0 R 20 19 18 17 0 UART0SRC 16 0 TPMSRC W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 RTCCLKOUTS EL Reset 0 R CLKOUTSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SOPT2 field descriptions Field 31-28 Reserved 27-26 UART0SRC Description This field is reserved. This read-only field is reserved and always has the value 0. UART0 clock source select Selects the clock source for the UART0 transmit and receive clock. 00 01 10 11 25-24 TPMSRC Clock disabled MCGFLLCLK clock OSCERCLK clock MCGIRCLK clock TPM clock source select Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 174 Freescale Semiconductor, Inc. Chapter 12 System integration module (SIM) SIM_SOPT2 field descriptions (continued) Field Description Selects the clock source for the TPM counter clock 00 01 10 11 Clock disabled MCGFLLCLK clock OSCERCLK clock MCGIRCLK clock 23-18 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 17-16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7-5 CLKOUTSEL CLKOUT select Selects the clock to output on the CLKOUT pin. 000 001 010 011 100 101 110 111 Reserved Reserved Bus clock LPO clock (1 kHz) MCGIRCLK Reserved OSCERCLK Reserved 4 RTC clock out select RTCCLKOUTSEL Selects either the RTC 1 Hz clock or the OSC clock to be output on the RTC_CLKOUT pin. 0 1 3-0 Reserved RTC 1 Hz clock is output on the RTC_CLKOUT pin. OSCERCLK clock is output on the RTC_CLKOUT pin. This field is reserved. This read-only field is reserved and always has the value 0. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 175 Memory map and register definition 12.2.4 System Options Register 4 (SIM_SOPT4) Address: 4004_7000h base + 100Ch offset = 4004_800Ch 29 28 27 26 25 24 23 22 21 20 19 0 0 18 17 TPM1CH0SRC 30 16 TPM0CLKSEL 31 TPM1CLKSEL Bit Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 R 0 W 0 0 0 R W Reset 0 0 0 0 0 0 0 0 SIM_SOPT4 field descriptions Field Description 31-27 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 26 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 25 TPM1CLKSEL TPM1 External Clock Pin Select Selects the external pin used to drive the clock to the TPM1 module. NOTE: The selected pin must also be configured for the TPM external clock function through the appropriate pin control register in the port control module. 0 1 24 TPM0CLKSEL TPM1 external clock driven by TPM_CLKIN0 pin. TPM1 external clock driven by TPM_CLKIN1 pin. TPM0 External Clock Pin Select Selects the external pin used to drive the clock to the TPM0 module. NOTE: The selected pin must also be configured for the TPM external clock function through the appropriate pin control register in the port control module. 0 1 TPM0 external clock driven by TPM_CLKIN0 pin. TPM0 external clock driven by TPM_CLKIN1 pin. 23-21 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 20 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 176 Freescale Semiconductor, Inc. Chapter 12 System integration module (SIM) SIM_SOPT4 field descriptions (continued) Field Description 18 TPM1CH0SRC TPM1 channel 0 input capture source select Selects the source for TPM1 channel 0 input capture. NOTE: When TPM1 is not in input capture mode, clear this field. 0 1 17-0 Reserved TPM1_CH0 signal CMP0 output This field is reserved. This read-only field is reserved and always has the value 0. 12.2.5 System Options Register 5 (SIM_SOPT5) Bit 31 30 29 28 27 26 25 24 23 22 21 20 0 R 19 18 17 16 0 0 0 UART0ODE Address: 4004_7000h base + 1010h offset = 4004_8010h W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART0TXSRC 0 UART0RXSRC Reset 0 SIM_SOPT5 field descriptions Field Description 31-20 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 17 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 16 UART0ODE UART0 Open Drain Enable 0 1 Open drain is disabled on UART0 Open drain is enabled on UART0 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 177 Memory map and register definition SIM_SOPT5 field descriptions (continued) Field Description 15-7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6-4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 UART0RXSRC UART0 receive data source select Selects the source for the UART0 receive data. 0 1 1 Reserved UART0_RX pin CMP0 output This field is reserved. This read-only field is reserved and always has the value 0. 0 UART0TXSRC UART0 transmit data source select Selects the source for the UART0 transmit data. 0 1 UART0_TX pin UART0_TX pin modulated with TPM1 channel 0 output 12.2.6 System Options Register 7 (SIM_SOPT7) Address: 4004_7000h base + 1018h offset = 4004_8018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R W Reset 0 0 0 0 0 0 0 0 0 ADC0PRETRGS EL 0 ADC0ALTTRGE N Reset 0 0 0 0 ADC0TRGSEL 0 0 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 178 Freescale Semiconductor, Inc. Chapter 12 System integration module (SIM) SIM_SOPT7 field descriptions Field 31-8 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 7 ADC0 alternate trigger enable ADC0ALTTRGEN Enable alternative conversion triggers for ADC0. 0 1 6-5 Reserved TPM1 channel 0 (A) and channel 1 (B) triggers selected for ADC0. Alternate trigger selected for ADC0. This field is reserved. This read-only field is reserved and always has the value 0. 4 ADC0 pretrigger select ADC0PRETRGSEL Selects the ADC0 pre-trigger source when alternative triggers are enabled through ADC0ALTTRGEN. 0 1 3-0 ADC0TRGSEL Pre-trigger A Pre-trigger B ADC0 trigger select Selects the ADC0 trigger source when alternative triggers are functional in stop and VLPS modes. . 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 External trigger pin input (EXTRG_IN) CMP0 output Reserved Reserved PIT trigger 0 PIT trigger 1 Reserved Reserved TPM0 overflow TPM1 overflow Reserved Reserved RTC alarm RTC seconds LPTMR0 trigger Reserved KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 179 Memory map and register definition 12.2.7 System Device Identification Register (SIM_SDID) Address: 4004_7000h base + 1024h offset = 4004_8024h Bit 31 30 29 28 FAMID R 27 26 25 24 23 SUBFAMID 22 21 20 SERIESID 19 18 17 16 15 SRAMSIZE 14 13 12 11 10 REVID 9 8 7 6 DIEID 5 4 3 0 2 1 0 PINID W Reset * * * * * * * * 0 0 0 1 * * * * * * * * 0 1 0 0 0 0 0 0 * * * * * Notes: * FAMID field: Device specific value. * SUBFAMID field: Device specific value. * SRAMSIZE field: Device specific value. * REVID field: Device specific value. * PINID field: Device specific value. SIM_SDID field descriptions Field 31-28 FAMID Description Kinetis family ID Specifies the Kinetis family of the device. 0000 0001 0010 0011 0100 27-24 SUBFAMID Kinetis Sub-Family ID Specifies the Kinetis sub-family of the device. 0010 0100 0101 0110 23-20 SERIESID KLx2 Subfamily (low end) KLx4 Subfamily (basic analog) KLx5 Subfamily (advanced analog) KLx6 Subfamily (advanced analog with I2S) Kinetis Series ID Specifies the Kinetis family of the device. 0001 19-16 SRAMSIZE KL0x Family (low end) KL1x Family (basic) KL2x Family (USB) KL3x Family (Segment LCD) KL4x Family (USB and Segment LCD) KL family System SRAM Size Specifies the size of the System SRAM 0000 0001 0010 0011 0100 0101 0.5 KB 1 KB 2 KB 4 KB 8 KB 16 KB Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 180 Freescale Semiconductor, Inc. Chapter 12 System integration module (SIM) SIM_SDID field descriptions (continued) Field Description 0110 0111 32 KB 64 KB 15-12 REVID Device revision number 11-7 DIEID Device die number 6-4 Reserved 3-0 PINID Specifies the silicon implementation number for the device. Specifies the silicon implementation number for the device. This field is reserved. This read-only field is reserved and always has the value 0. Pincount identification Specifies the pincount of the device. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 16-pin 24-pin 32-pin Reserved 48-pin 64-pin 80-pin Reserved 100-pin Reserved Reserved Reserved Reserved Reserved Reserved Reserved KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 181 Memory map and register definition 12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4) Address: 4004_7000h base + 1034h offset = 4004_8034h Bit 31 30 29 28 27 26 1 R 25 24 0 23 22 21 0 20 19 0 18 17 0 SPI0 16 0 CMP W Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 W Reset 0 0 0 0 0 UART0 0 R 0 0 0 1 0 I2C0 0 0 0 0 1 1 0 0 SIM_SCGC4 field descriptions Field Description 31-28 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 27-24 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 23 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 22 SPI0 SPI0 Clock Gate Control This bit controls the clock gate to the SPI0 module. 0 1 21-20 Reserved 19 CMP Clock disabled Clock enabled This field is reserved. This read-only field is reserved and always has the value 0. Comparator Clock Gate Control This bit controls the clock gate to the comparator module. 0 1 Clock disabled Clock enabled 18 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 17-14 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 13 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 182 Freescale Semiconductor, Inc. Chapter 12 System integration module (SIM) SIM_SCGC4 field descriptions (continued) Field Description 11 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 10 UART0 UART0 Clock Gate Control This bit controls the clock gate to the UART0 module. 0 1 Clock disabled Clock enabled 9-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6 I2C0 I2C0 Clock Gate Control This bit controls the clock gate to the I 2 C0 module. 0 1 Clock disabled Clock enabled 5-4 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 3-0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5) Address: 4004_7000h base + 1038h offset = 4004_8038h Bit 31 30 29 28 27 26 25 24 23 22 21 20 0 R 19 18 0 17 16 0 W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R 0 W Reset 0 0 0 0 0 0 0 1 0 0 0 TSI 1 1 0 0 0 0 0 0 LPTMR 0 PORTA 0 PORTB Reset 0 SIM_SCGC5 field descriptions Field 31-20 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 183 Memory map and register definition SIM_SCGC5 field descriptions (continued) Field Description 19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18-14 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 13-11 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 10 PORTB Port B Clock Gate Control This bit controls the clock gate to the Port B module. 0 1 9 PORTA Clock disabled Clock enabled Port A Clock Gate Control This bit controls the clock gate to the Port A module. 0 1 Clock disabled Clock enabled 8-7 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 TSI TSI Access Control This bit controls software access to the TSI module. 0 1 Access disabled Access enabled 4-2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 LPTMR Low Power Timer Access Control This bit controls software access to the Low Power Timer module. 0 1 Access disabled Access enabled KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 184 Freescale Semiconductor, Inc. Chapter 12 System integration module (SIM) 12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6) Address: 4004_7000h base + 103Ch offset = 4004_803Ch 31 29 26 24 23 22 21 20 19 18 17 16 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 DMAMUX 0 25 TPM0 0 27 TPM1 0 28 PIT FTF 0 1 W DAC0 R 30 RTC ADC0 Bit 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SCGC6 field descriptions Field 31 DAC0 Description DAC0 Clock Gate Control This bit controls the clock gate to the DAC0 module. 0 1 30 Reserved 29 RTC This field is reserved. This read-only field is reserved and always has the value 0. RTC Access Control This bit controls software access and interrupts to the RTC module. 0 1 28 Reserved 27 ADC0 25 TPM1 Access and interrupts disabled Access and interrupts enabled This field is reserved. This read-only field is reserved and always has the value 0. ADC0 Clock Gate Control This bit controls the clock gate to the ADC0 module. 0 1 26 Reserved Clock disabled Clock enabled Clock disabled Clock enabled This field is reserved. This read-only field is reserved and always has the value 0. TPM1 Clock Gate Control This bit controls the clock gate to the TPM1 module. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 185 Memory map and register definition SIM_SCGC6 field descriptions (continued) Field Description 0 1 24 TPM0 Clock disabled Clock enabled TPM0 Clock Gate Control This bit controls the clock gate to the TPM0 module. 0 1 23 PIT Clock disabled Clock enabled PIT Clock Gate Control This bit controls the clock gate to the PIT module. 0 1 Clock disabled Clock enabled 22-16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 14-2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 DMAMUX DMA Mux Clock Gate Control This bit controls the clock gate to the DMA Mux module. 0 1 0 FTF Clock disabled Clock enabled Flash Memory Clock Gate Control This bit controls the clock gate to the flash memory. Flash reads are still supported while the flash memory is clock gated, but entry into low power modes is blocked. 0 1 Clock disabled Clock enabled 12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7) Address: 4004_7000h base + 1040h offset = 4004_8040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 3 2 1 0 0 0 0 0 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 0 R DMA W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 186 Freescale Semiconductor, Inc. Chapter 12 System integration module (SIM) SIM_SCGC7 field descriptions Field Description 31-9 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 8 DMA DMA Clock Gate Control This bit controls the clock gate to the DMA module. 0 1 7-0 Reserved Clock disabled Clock enabled This field is reserved. This read-only field is reserved and always has the value 0. 12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1) NOTE The CLKDIV1 register cannot be written to when the device is in VLPR mode. NOTE Reset value loaded during System Reset from FTF_FOPT[LPBOOT]. Address: 4004_7000h base + 1044h offset = 4004_8044h Bit 31 R 29 28 27 26 25 24 * * * 23 22 21 20 19 0 OUTDIV1 W Reset 30 * 0 0 0 0 0 18 17 16 15 14 13 12 11 10 9 8 0 0 0 0 0 1 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 OUTDIV4 0 7 0 0 0 0 0 0 0 0 * Notes: * OUTDIV1 field: The reset value depends on the FTF_FOPT[LPBOOT]. it is loaded with 0000 (divide by one), 0001 (divide by two), 0011 (divide by four), or 0111 (divide by eight). SIM_CLKDIV1 field descriptions Field 31-28 OUTDIV1 Description Clock 1 output divider value This field sets the divide value for the core/system clock, as well as the bus/flash clocks. At the end of reset, it is loaded with 0000 (divide by one), 0001 (divide by two), 0011 (divide by four), or 0111 (divide by eight) depending on the setting of the two FTF_FOPT[LPBOOT] configuration bits. 0000 0001 0010 0011 0100 0101 Divide-by-1. Divide-by-2. Divide-by-3. Divide-by-4. Divide-by-5. Divide-by-6. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 187 Memory map and register definition SIM_CLKDIV1 field descriptions (continued) Field Description 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Divide-by-7. Divide-by-8. Divide-by-9. Divide-by-10. Divide-by-11. Divide-by-12. Divide-by-13. Divide-by-14. Divide-by-15. Divide-by-16. 27-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18-16 OUTDIV4 Clock 4 output divider value This field sets the divide value for the bus and flash clock and is in addition to the System clock divide ratio. At the end of reset, it is loaded with 0001 (divide by two). 000 001 010 011 100 101 110 111 15-0 Reserved Divide-by-1. Divide-by-2. Divide-by-3. Divide-by-4. Divide-by-5. Divide-by-6. Divide-by-7. Divide-by-8. This field is reserved. This read-only field is reserved and always has the value 0. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 188 Freescale Semiconductor, Inc. Chapter 12 System integration module (SIM) 12.2.13 Flash Configuration Register 1 (SIM_FCFG1) Address: 4004_7000h base + 104Ch offset = 4004_804Ch Bit 31 30 29 28 27 0 R 26 25 24 23 22 21 20 PFSIZE 19 18 17 16 0 Reset 0 0 0 0 * * * * 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLASHDOZE FLASHDIS W 0 0 0 0 0 0 0 0 0 0 R W Reset 0 0 0 0 0 0 0 * Notes: * PFSIZE field: Device specific value. SIM_FCFG1 field descriptions Field 31-28 Reserved 27-24 PFSIZE Description This field is reserved. This read-only field is reserved and always has the value 0. Program flash size This field specifies the amount of program flash memory available on the device . Undefined values are reserved. 0000 0001 0011 0101 0111 1001 1111 8 KB of program flash memory, 0.25 KB protection region 16 KB of program flash memory, 0.5 KB protection region 32 KB of program flash memory, 1 KB protection region 64 KB of program flash memory, 2 KB protection region 128 KB of program flash memory, 4 KB protection region 256 KB of program flash memory, 8 KB protection region 32 KB of program flash memory, 1 KB protection region Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 189 Memory map and register definition SIM_FCFG1 field descriptions (continued) Field Description 23-2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 FLASHDOZE Flash Doze When set, Flash memory is disabled for the duration of Doze mode. This bit should be clear during VLP modes. The Flash will be automatically enabled again at the end of Doze mode so interrupt vectors do not need to be relocated out of Flash memory. The wakeup time from Doze mode is extended when this bit is set. An attempt by the DMA or other bus master to access the Flash when the Flash is disabled will result in a bus error. 0 1 0 FLASHDIS Flash remains enabled during Doze mode Flash is disabled for the duration of Doze mode Flash Disable Flash accesses are disabled (and generate a bus error) and the Flash memory is placed in a low power state. This bit should not be changed during VLP modes. Relocate the interrupt vectors out of Flash memory before disabling the Flash. 0 1 Flash is enabled Flash is disabled 12.2.14 Flash Configuration Register 2 (SIM_FCFG2) Address: 4004_7000h base + 1050h offset = 4004_8050h Bit 31 R 0 30 29 28 27 26 25 24 23 MAXADDR0 22 21 20 1 19 18 17 16 0 W Reset 0 * * * * * * * Bit 15 14 13 12 11 10 9 8 1 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 R W Reset 0 0 0 0 0 0 0 0 * Notes: * MAXADDR0 field: Device specific value indicating amount of implemented flash. SIM_FCFG2 field descriptions Field 31 Reserved 30-24 MAXADDR0 Description This field is reserved. This read-only field is reserved and always has the value 0. Max address block This field concatenated with leading zeros indicates the first invalid address of program flash. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 190 Freescale Semiconductor, Inc. Chapter 12 System integration module (SIM) SIM_FCFG2 field descriptions (continued) Field Description For example, if MAXADDR0 = 0x10 the first invalid address of program flash is 0x0002_0000. This would be the MAXADDR0 value for a device with 128 KB program flash. 23 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 22-16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15-0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12.2.15 Unique Identification Register Mid-High (SIM_UIDMH) Address: 4004_7000h base + 1058h offset = 4004_8058h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 8 7 6 5 4 3 2 1 0 * * * * * * * UID W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * * * * * * * * Notes: * UID field: Device specific value. SIM_UIDMH field descriptions Field Description 31-16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15-0 UID Unique Identification Unique identification for the device. 12.2.16 Unique Identification Register Mid Low (SIM_UIDML) Address: 4004_7000h base + 105Ch offset = 4004_805Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * * * * * * * * * * * * UID R W Reset * * * * * * * * * * * * * * * * * * Notes: * UID field: Device specific value. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 191 Memory map and register definition SIM_UIDML field descriptions Field Description 31-0 UID Unique Identification Unique identification for the device. 12.2.17 Unique Identification Register Low (SIM_UIDL) Address: 4004_7000h base + 1060h offset = 4004_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * * * * * * * * * * * * UID R W Reset * * * * * * * * * * * * * * * * * * Notes: * UID field: Device specific value. SIM_UIDL field descriptions Field Description 31-0 UID Unique Identification Unique identification for the device. 12.2.18 COP Control Register (SIM_COPC) All of the bits in this register can be written only once after a reset. Address: 4004_7000h base + 1100h offset = 4004_8100h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COPCLKS COPW W 0 0 0 R COPT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 192 Freescale Semiconductor, Inc. Chapter 12 System integration module (SIM) SIM_COPC field descriptions Field Description 31-4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3-2 COPT COP Watchdog Timeout These write-once bits select the timeout period of the COP. The COPT field along with the COPCLKS bit define the COP timeout period. 00 01 10 11 1 COPCLKS COP disabled COP timeout after 25 LPO cycles or 213 bus clock cycles COP timeout after 28 LPO cycles or 216 bus clock cycles COP timeout after 210 LPO cycles or 218 bus clock cycles COP Clock Select This write-once bit selects the clock source of the COP watchdog. 0 1 0 COPW Internal 1 kHz clock is source to COP Bus clock is source to COP COP windowed mode Windowed mode is only supported when COP is running from the bus clock. The COP window is opened three quarters through the timeout period. 0 1 Normal mode Windowed mode 12.2.19 Service COP Register (SIM_SRVCOP) Address: 4004_7000h base + 1104h offset = 4004_8104h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 R Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 SRVCOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SRVCOP field descriptions Field Description 31-8 Reserved This field is reserved. 7-0 SRVCOP Sevice COP Register Write 0x55 and then 0xAA (in that order) to reset the COP timeout counter. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 193 Functional description 12.3 Functional description See Introduction section. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 194 Freescale Semiconductor, Inc. Chapter 13 System Mode Controller (SMC) 13.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The system mode controller (SMC) is responsible for sequencing the system into and out of all low power stop and run modes. Specifically, it monitors events to trigger transitions between power modes while controlling the power, clocks, and memories of the system to achieve the power consumption and functionality of that mode. This chapter describes all the available low power modes, the sequence followed to enter/ exit each mode, and the functionality available while in each of the modes. The SMC is able to function during even the deepest low power modes. 13.2 Modes of operation The ARM CPU has three primary modes of operation: * Run * Sleep * Deep Sleep The WFI or WFE instruction is used to invoke Sleep and Deep Sleep modes. Run, wait and stop are the common terms used for the primary operating modes of Freescale microcontrollers. The following table shows the translation between the ARM CPU modes and the Freescale MCU power modes. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 195 Modes of operation ARM CPU mode MCU mode Sleep Wait Deep Sleep Stop Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the Freescale MCU documentation normally uses wait and stop. In addition, Freescale MCUs also augment stop, wait, and run modes in a number of ways. The power management controller (PMC) contains a run and a stop mode regulator. Run regulation is used in normal run, wait and stop modes. Stop mode regulation is used during all very low power and low leakage modes. During stop mode regulation, the bus frequencies are limited in the very low power modes. The SMC provides the user with multiple power options. The Very Low Power Run (VLPR) mode can drastically reduce run time power when maximum bus frequency is not required to handle the application needs. From Normal Run mode, the Run Mode (RUNM) field can be modified to change the MCU into VLPR mode when limited frequency is sufficient for the application. From VLPR mode, a corresponding wait (VLPW) and stop (VLPS) mode can be entered. Depending on the needs of the user application, a variety of stop modes are available that allow the state retention, partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. Several registers are used to configure the various modes of operation for the device. The following table describes the power modes available for the device. Table 13-1. Power modes Mode Description RUN The MCU can be run at full speed and the internal supply is fully regulated, that is, in run regulation. This mode is also referred to as Normal Run mode. WAIT The core clock is gated off. The system clock continues to operate. Bus clocks, if enabled, continue to operate. Run regulation is maintained. STOP The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. VLPR The core, system, bus, and flash clock maximum frequencies are restricted in this mode. See the Power Management chapter for details about the maximum allowable frequencies. VLPW The core clock is gated off. The system, bus, and flash clocks continue to operate, although their maximum frequency is restricted. See the Power Management chapter for details on the maximum allowable frequencies. VLPS The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. LLS The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by reducing the voltage to internal logic. Internal logic states are retained. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 196 Freescale Semiconductor, Inc. Chapter 13 System Mode Controller (SMC) Table 13-1. Power modes (continued) Mode Description VLLS3 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic. All system RAM contents are retained and I/O states are held. Internal logic states are not retained. VLLS1 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic and all system RAM. I/O states are held. Internal logic states are not retained. VLLS0 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic and all system RAM. I/O states are held. Internal logic states are not retained. The 1kHz LPO clock is disabled and the power on reset (POR) circuit can be optionally enabled using STOPCTRL[PORPO]. 13.3 Memory map and register descriptions Details follow about the registers related to the system mode controller. Different SMC registers reset on different reset types. Each register's description provides details. For more information about the types of reset on this chip, refer to the Reset section details. NOTE The SMC registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. SMC memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4007_E000 Power Mode Protection register (SMC_PMPROT) 8 R/W 00h 13.3.1/197 4007_E001 Power Mode Control register (SMC_PMCTRL) 8 R/W 00h 13.3.2/199 4007_E002 Stop Control Register (SMC_STOPCTRL) 8 R/W 03h 13.3.3/200 4007_E003 Power Mode Status register (SMC_PMSTAT) 8 R 01h 13.3.4/201 13.3.1 Power Mode Protection register (SMC_PMPROT) This register provides protection for entry into any low-power run or stop mode. The enabling of the low-power run or stop mode occurs by configuring the Power Mode Control register (PMCTRL). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 197 Memory map and register descriptions The PMPROT register can be written only once after any system reset. If the MCU is configured for a disallowed or reserved power mode, the MCU remains in its current power mode. For example, if the MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using PMCTRL[RUNM] is blocked and the RUNM bits remain 00b, indicating the MCU is still in Normal Run mode. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 0h offset = 4007_E000h Bit Read Write Reset 7 6 5 0 0 0 4 AVLP 0 0 0 3 2 1 0 ALLS 0 AVLLS 0 0 0 0 0 SMC_PMPROT field descriptions Field 7-6 Reserved 5 AVLP Description This field is reserved. This read-only field is reserved and always has the value 0. Allow Very-Low-Power Modes Provided the appropriate control bits are set up in PMCTRL, this write-once bit allows the MCU to enter any very-low-power modes: VLPR, VLPW, and VLPS. 0 1 4 Reserved 3 ALLS This field is reserved. This read-only field is reserved and always has the value 0. Allow Low-Leakage Stop Mode This write once bit allows the MCU to enter any low-leakage stop mode (LLS), provided the appropriate control bits are set up in PMCTRL. 0 1 2 Reserved 1 AVLLS LLS is not allowed LLS is allowed This field is reserved. This read-only field is reserved and always has the value 0. Allow Very-Low-Leakage Stop Mode Provided the appropriate control bits are set up in PMCTRL, this write once bit allows the MCU to enter any very-low-leakage stop mode (VLLSx). 0 1 0 Reserved VLPR, VLPW and VLPS are not allowed VLPR, VLPW and VLPS are allowed Any VLLSx mode is not allowed Any VLLSx mode is allowed This field is reserved. This read-only field is reserved and always has the value 0. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 198 Freescale Semiconductor, Inc. Chapter 13 System Mode Controller (SMC) 13.3.2 Power Mode Control register (SMC_PMCTRL) The PMCTRL register controls entry into low-power run and stop modes, provided that the selected power mode is allowed via an appropriate setting of the protection (PMPROT) register. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 1h offset = 4007_E001h Bit 7 Read 0 6 RUNM Write Reset 5 0 0 0 4 3 0 STOPA 0 0 2 1 0 STOPM 0 0 0 SMC_PMCTRL field descriptions Field 7 Reserved 6-5 RUNM Description This field is reserved. This read-only field is reserved and always has the value 0. Run Mode Control When written, causes entry into the selected run mode. Writes to this field are blocked if the protection level has not been enabled using the PMPROT register. This field is cleared by hardware on any exit to normal RUN mode. NOTE: RUNM must be set to VLPR only when PMSTAT=RUN. After being written to VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR. NOTE: RUNM must be set to RUN only when PMSTAT=VLPR. After being written to RUN, RUNM should not be written back to VLPR until PMSTAT=RUN. 00 01 10 11 4 Reserved 3 STOPA Normal Run mode (RUN) Reserved Very-Low-Power Run mode (VLPR) Reserved This field is reserved. This read-only field is reserved and always has the value 0. Stop Aborted When set, this read-only status bit indicates an interrupt or reset occured during the previous stop mode entry sequence, preventing the system from entering that mode. This bit is cleared by hardware at the beginning of any stop mode entry sequence and is set if the sequence was aborted. 0 1 The previous stop mode entry was successsful. The previous stop mode entry was aborted. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 199 Memory map and register descriptions SMC_PMCTRL field descriptions (continued) Field 2-0 STOPM Description Stop Mode Control When written, controls entry into the selected stop mode when Sleep-Now or Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are blocked if the protection level has not been enabled using the PMPROT register. After any system reset, this field is cleared by hardware on any successful write to the PMPROT register. NOTE: When set to VLLSx, the VLLSM bits in the STOPCTRL register is used to further select the particular VLLS submode which will be entered. NOTE: When set to STOP, the PSTOPO bits in the STOPCTRL register can be used to select a Partial Stop mode if desired. 000 001 010 011 100 101 110 111 Normal Stop (STOP) Reserved Very-Low-Power Stop (VLPS) Low-Leakage Stop (LLS) Very-Low-Leakage Stop (VLLSx) Reserved Reseved Reserved 13.3.3 Stop Control Register (SMC_STOPCTRL) The STOPCTRL register provides various control bits allowing the user to fine tune power consumption during the stop mode selected by the STOPM field. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 2h offset = 4007_E002h Bit Read Write Reset 7 6 5 PSTOPO 0 0 4 3 PORPO 0 0 0 0 0 2 1 0 VLLSM 0 1 1 SMC_STOPCTRL field descriptions Field 7-6 PSTOPO Description Partial Stop Option These bits control whether a Partial Stop mode is entered when STOPM=STOP. When entering a Partial Stop mode from RUN mode, the PMC, MCG and flash remain fully powered, allowing the device to wakeup almost instantaneously at the expense of higher power consumption. In PSTOP2, only system Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 200 Freescale Semiconductor, Inc. Chapter 13 System Mode Controller (SMC) SMC_STOPCTRL field descriptions (continued) Field Description clocks are gated allowing peripherals running on bus clock to remain fully functional. In PSTOP1, both system and bus clocks are gated. 00 01 10 11 5 PORPO STOP - Normal Stop mode PSTOP1 - Partial Stop with both system and bus clocks disabled PSTOP2 - Partial Stop with system clock disabled and bus clock enabled Reserved POR Power Option This bit controls whether the POR detect circuit is enabled in VLLS0 mode. 0 1 POR detect circuit is enabled in VLLS0 POR detect circuit is disabled in VLLS0 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2-0 VLLSM VLLS Mode Control. This field controls which VLLS sub-mode to enter if STOPM=VLLS. 000 001 010 011 100 101 110 111 VLLS0 VLLS1 Reserved VLLS3 Reserved Reserved Reserved Reserved 13.3.4 Power Mode Status register (SMC_PMSTAT) PMSTAT is a read-only, one-hot register which indicates the current power mode of the system. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 201 Functional description Address: 4007_E000h base + 3h offset = 4007_E003h Bit 7 Read 0 6 5 4 3 2 1 0 0 0 1 PMSTAT Write Reset 0 0 0 0 0 SMC_PMSTAT field descriptions Field 7 Reserved 6-0 PMSTAT Description This field is reserved. This read-only field is reserved and always has the value 0. NOTE: When debug is enabled, the PMSTAT will not update to STOP or VLPS NOTE: When a PSTOP mode is enabled, the PMSTAT will not update to STOP or VLPS 000_0001 000_0010 000_0100 000_1000 001_0000 010_0000 100_0000 Current power mode is RUN Current power mode is STOP Current power mode is VLPR Current power mode is VLPW Current power mode is VLPS Current power mode is LLS Current power mode is VLLS 13.4 Functional description 13.4.1 Power mode transitions The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal run state. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 202 Freescale Semiconductor, Inc. Chapter 13 System Mode Controller (SMC) Any RESET VLPW 4 5 VLPR WAIT 1 3 RUN 7 2 STOP 6 VLPS 10 8 VLLS 3, 1, 0 LLS 9 11 Figure 13-5. Power mode state diagram The following table defines triggers for the various state transitions shown in the previous figure. Table 13-7. Power mode transition triggers Transition # From To 1 RUN WAIT Trigger conditions Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core. See note.1 WAIT RUN Interrupt or Reset Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 203 Functional description Table 13-7. Power mode transition triggers (continued) Transition # From To 2 RUN STOP Trigger conditions PMCTRL[RUNM]=00, PMCTRL[STOPM]=0002 Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note.1 3 STOP RUN Interrupt or Reset RUN VLPR The core, system, bus and flash clock frequencies are restricted in this mode. See the Power Management chapter for the maximum allowable frequencies. Set PMPROT[AVLP]=1, PMCTRL[RUNM]=10. VLPR RUN Set PMCTRL[RUNM]=00 or Reset. 4 VLPR VLPW Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, which is controlled in System Control Register in ARM core. See note.1 VLPW VLPR Interrupt 5 VLPW RUN Reset 6 VLPR VLPS PMCTRL[STOPM]=0003 or 010, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note.1 VLPS VLPR Interrupt NOTE: If VLPS was entered directly from RUN, hardware will not allow this transition and will force exit back to RUN 7 RUN VLPS PMPROT[AVLP]=1, PMCTRL[STOPM]=010, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note.1 VLPS RUN Interrupt and VLPS mode was entered directly from RUN or Reset 8 9 RUN VLLSx VLLSx RUN VLPR VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, STOPCTRL[VLLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. Wakeup from enabled LLWU input source or RESET pin PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, STOPCTRL[VLLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 204 Freescale Semiconductor, Inc. Chapter 13 System Mode Controller (SMC) Table 13-7. Power mode transition triggers (continued) Transition # From To 10 RUN LLS PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. LLS RUN Wakeup from enabled LLWU input source or RESET pin. VLPR LLS PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. 11 Trigger conditions 1. If debug is enabled, the core clock remains to support debug. 2. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of STOP 3. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=00, then VLPS mode is entered instead of STOP. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of VLPS 13.4.2 Power mode entry/exit sequencing When entering or exiting low-power modes, the system must conform to an orderly sequence to manage transitions safely. The SMC manages the system's entry into and exit from all power modes. The following diagram illustrates the connections of the SMC with other system components in the chip that are necessary to sequence the system through all power modes. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 205 Functional description Reset Control Module LowLeakage Wakeup CPU (RCM) (LLWU) Stop/Wait LP exit LP exit System Mode Controller CCM low power bus (SMC) Clock Control Module Bus masters low power bus (non-CPU) Bus slaves low power bus (CCM) PMC low power bus MCG enable System Power (PMC) System Clocks (MCG) Flash low power bus Flash Memory Module Figure 13-6. Low-power system components and connections 13.4.2.1 Stop mode entry sequence Entry into a low-power stop mode (Stop, VLPS, LLS, VLLSx) is initiated by CPU execution of the WFI instruction. After the instruction is executed, the following sequence occurs: 1. The CPU clock is gated off immediately. 2. Requests are made to all non-CPU bus masters to enter Stop mode. 3. After all masters have acknowledged they are ready to enter Stop mode, requests are made to all bus slaves to enter Stop mode. 4. After all slaves have acknowledged they are ready to enter Stop mode, all system and bus clocks are gated off. 5. Clock generators are disabled in the MCG. 6. The on-chip regulator in the PMC and internal power switches are configured to meet the power consumption goals for the targeted low-power mode. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 206 Freescale Semiconductor, Inc. Chapter 13 System Mode Controller (SMC) 13.4.2.2 Stop mode exit sequence Exit from a low-power stop mode is initiated either by a reset or an interrupt event. The following sequence then executes to restore the system to a run mode (RUN or VLPR): 1. The on-chip regulator in the PMC and internal power switches are restored. 2. Clock generators are enabled in the MCG. 3. System and bus clocks are enabled to all masters and slaves. 4. The CPU clock is enabled and the CPU begins servicing the reset or interrupt that initiated the exit from the low-power stop mode. 13.4.2.3 Aborted stop mode entry If an interrupt or a reset occurs during a stop entry sequence, the SMC can abort the transition early and return to RUN mode without completely entering the stop mode. An aborted entry is possible only if the reset or interrupt occurs before the PMC begins the transition to stop mode regulation. After this point, the interrupt or reset is ignored until the PMC has completed its transition to stop mode regulation. When an aborted stop mode entry sequence occurs, the SMC's PMCTRL[STOPA] is set to 1. 13.4.2.4 Transition to wait modes For wait modes (WAIT and VLPW), the CPU clock is gated off while all other clocking continues, as in RUN and VLPR mode operation. Some modules that support stop-inwait functionality have their clocks disabled in these configurations. 13.4.2.5 Transition from stop modes to Debug mode The debugger module supports a transition from STOP, WAIT, VLPS, and VLPW back to a Halted state when the debugger has been enabled, that is, ENBDM is 1. As part of this transition, system clocking is re-established and is equivalent to the normal RUN and VLPR mode clocking configuration. 13.4.3 Run modes The device contains two different run modes: * Run * Very Low-Power Run (VLPR) KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 207 Functional description 13.4.3.1 RUN mode This is the normal operating mode for the device. This mode is selected after any reset. When the ARM processor exits reset, it sets up the stack, program counter (PC), and link register (LR): * The processor reads the start SP (SP_main) from vector-table offset 0x000 * The processor reads the start PC from vector-table offset 0x004 * LR is set to 0xFFFF_FFFF. To reduce power in this mode, disable the clocks to unused modules using their corresponding clock gating control bits in the SIM's registers. 13.4.3.2 Very-Low Power Run (VLPR) mode In VLPR mode, the on-chip voltage regulator is put into a stop mode regulation state. In this state, the regulator is designed to supply enough current to the MCU over a reduced frequency. To further reduce power in this mode, disable the clocks to unused modules using their corresponding clock gating control bits in the SIM's registers. Before entering this mode, the following conditions must be met: * The MCG must be configured in a mode which is supported during VLPR. See the Power Management details for information about these MCG modes. * All clock monitors in the MCG must be disabled. * The maximum frequencies of the system, bus, flash, and core are restricted. See the Power Management details about which frequencies are supported. * Mode protection must be set to allow VLP modes, that is, PMPROT[AVLP] is 1. * PMCTRL[RUNM] is set to 10b to enter VLPR. * Flash programming/erasing is not allowed. NOTE Do not change the clock frequency while in VLPR mode, because the regulator is slow responding and cannot manage fast load transitions. In addition, do not modify the clock source in the MCG module, the module clock enables in the SIM, or any clock divider registers. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 208 Freescale Semiconductor, Inc. Chapter 13 System Mode Controller (SMC) To reenter Normal Run mode, clear RUNM. The PMSTAT register is a read-only status register that can be used to determine when the system has completed an exit to RUN mode. When PMSTAT=RUN, the system is in run regulation and the MCU can run at full speed in any clock mode. If a higher execution frequency is desired, poll the PMSTAT register until it is set to RUN when returning from VLPR mode. Any reset always causes an exit from VLPR and returns the device to RUN mode after the MCU exits its reset flow. 13.4.4 Wait modes This device contains two different wait modes: * Wait * Very-Low Power Wait (VLPW) 13.4.4.1 WAIT mode WAIT mode is entered when the ARM core enters the Sleep-Now or Sleep-On-Exit modes while SLEEDEEP is cleared. The ARM CPU enters a low-power state in which it is not clocked, but peripherals continue to be clocked provided they are enabled. Clock gating to the peripheral is enabled via the SIM.. When an interrupt request occurs, the CPU exits WAIT mode and resumes processing in RUN mode, beginning with the stacking operations leading to the interrupt service routine. A system reset will cause an exit from WAIT mode, returning the device to normal RUN mode. 13.4.4.2 Very-Low-Power Wait (VLPW) mode VLPW is entered by the entering the Sleep-Now or Sleep-On-Exit mode while SLEEPDEEP is cleared and the MCU is in VLPR mode. In VLPW, the on-chip voltage regulator remains in its stop regulation state. In this state, the regulator is designed to supply enough current to the MCU over a reduced frequency. To further reduce power in this mode, disable the clocks to unused modules by clearing the peripherals' corresponding clock gating control bits in the SIM. VLPR mode restrictions also apply to VLPW. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 209 Functional description When an interrupt from VLPW occurs, the device returns to VLPR mode to execute the interrupt service routine. A system reset will cause an exit from VLPW mode, returning the device to normal RUN mode. 13.4.5 Stop modes This device contains a variety of stop modes to meet your application needs. The stop modes range from: * a stopped CPU, with all I/O, logic, and memory states retained, and certain asynchronous mode peripherals operating to: * a powered down CPU, with only I/O and a small register file retained, very few asynchronous mode peripherals operating, while the remainder of the MCU is powered down. The choice of stop mode depends upon the user's application, and how power usage and state retention versus functional needs may be traded off. NOTE All clock monitors must be disabled before entering these lowpower modes: Stop, VLPS, VLPR, VLPW, LLS, and VLLSx. The various stop modes are selected by setting the appropriate fields in PMPROT and PMCTRL. The selected stop mode mode is entered during the sleep-now or sleep-on-exit entry with the SLEEPDEEP bit set in the System Control Register in the ARM core. The available stop modes are: * * * * Normal Stop (STOP) Very-Low Power Stop (VLPS) Low-Leakage Stop (LLS) Very-Low-Leakage Stop (VLLSx) 13.4.5.1 STOP mode STOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core. The MCG module can be configured to leave the reference clocks running. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 210 Freescale Semiconductor, Inc. Chapter 13 System Mode Controller (SMC) A module capable of providing an asynchronous interrupt to the device takes the device out of STOP mode and returns the device to normal RUN mode. Refer to the device's Power Management chapter for peripheral, I/O, and memory operation in STOP mode. When an interrupt request occurs, the CPU exits STOP mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. A system reset will cause an exit from STOP mode, returning the device to normal RUN mode via an MCU reset. 13.4.5.2 Very-Low-Power Stop (VLPS) mode VLPS mode can be entered in one of two ways: * Entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core while the MCU is in VLPR mode and STOPM=010 or 000 in the PMCTRL register. * Entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core while the MCU is in normal RUN mode and STOPM=010 in the PMCTRL register. When VLPS is entered directly from RUN mode, exit to VLPR is disabled by hardware and the system will always exit back to RUN. In VLPS, the on-chip voltage regulator remains in its stop regulation state as in VLPR. A module capable of providing an asynchronous interrupt to the device takes the device out of VLPS and returns the device to VLPR mode. A system reset will also cause a VLPS exit, returning the device to normal RUN mode. 13.4.5.3 Low-Leakage Stop (LLS) mode Low-Leakage Stop (LLS) mode can be entered from normal RUN or VLPR modes. The MCU enters LLS mode if: * In Sleep-Now or Sleep-On-Exit mode, SLEEPDEEP is set in the System Control Register in the ARM core, and * The device is configured as shown in Table 13-7. In LLS, the on-chip voltage regulator is in stop regulation. Most of the peripherals are put in a state-retention mode that does not allow them to operate while in LLS. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 211 Functional description Before entering LLS mode, the user should configure the low-leakage wakeup (LLWU) module to enable the desired wakeup sources. The available wakeup sources in LLS are detailed in the chip configuration details for this device. After wakeup from LLS, the device returns to normal RUN mode with a pending LLWU module interrupt. In the LLWU interrupt service routine (ISR), the user can poll the LLWU module wakeup flags to determine the source of the wakeup. NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. An asserted RESET pin will cause an exit from LLS mode, returning the device to normal RUN mode. When LLS is exiting via the RESET pin, the PIN and WAKEUP bits are set in the SRS0 register of the reset control module (RCM). 13.4.5.4 Very-Low-Leakage Stop (VLLSx) modes This device contains these very low leakage modes: * VLLS3 * VLLS1 * VLLS0 VLLSx is often used in this document to refer to all of these modes. All VLLSx modes can be entered from normal RUN or VLPR modes. The MCU enters the configured VLLS mode if: * In Sleep-Now or Sleep-On-Exit mode, the SLEEPDEEP bit is set in the System Control Register in the ARM core, and * The device is configured as shown in Table 13-7. In VLLS, the on-chip voltage regulator is in its stop-regulation state while most digital logic is powered off. Before entering VLLS mode, the user should configure the low-leakage wakeup (LLWU) module to enable the desired wakeup sources. The available wakeup sources in VLLS are detailed in the chip configuration details for this device. After wakeup from VLLS, the device returns to normal RUN mode with a pending LLWU interrupt. In the LLWU interrupt service routine (ISR), the user can poll the LLWU module wakeup flags to determine the source of the wakeup. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 212 Freescale Semiconductor, Inc. Chapter 13 System Mode Controller (SMC) When entering VLLS, each I/O pin is latched as configured before executing VLLS. Because all digital logic in the MCU is powered off, all port and peripheral data is lost during VLLS. This information must be restored before the ACKISO bit in the PMC is set. An asserted RESET pin will cause an exit from any VLLS mode, returning the device to normal RUN mode. When exiting VLLS via the RESET pin, the PIN and WAKEUP bits are set in the SRS0 register of the reset control module (RCM). 13.4.6 Debug in low power modes When the MCU is secure, the device disables/limits debugger operation. When the MCU is unsecure, the ARM debugger can assert two power-up request signals: * System power up, via SYSPWR in the Debug Port Control/Stat register * Debug power up, via CDBGPWRUPREQ in the Debug Port Control/Stat register When asserted while in RUN, WAIT, VLPR, or VLPW, the mode controller drives a corresponding acknowledge for each signal, that is, both CDBGPWRUPACK and CSYSPWRUPACK. When both requests are asserted, the mode controller handles attempts to enter STOP and VLPS by entering an emulated stop state. In this emulated stop state: * * * * * the regulator is in run regulation, the MCG-generated clock source is enabled, all system clocks, except the core clock, are disabled, the debug module has access to core registers, and access to the on-chip peripherals is blocked. No debug is available while the MCU is in LLS or VLLS modes. LLS is a state-retention mode and all debug operation can continue after waking from LLS, even in cases where system wakeup is due to a system reset event. Entering into a VLLS mode causes all of the debug controls and settings to be powered off. To give time to the debugger to sync with the MCU, the MDM AP Control Register includes a Very-Low-Leakage Debug Request (VLLDBGREQ) bit that is set to configure the Reset Controller logic to hold the system in reset after the next recovery from a VLLS mode. This bit allows the debugger time to reinitialize the debug module before the debug session continues. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 213 Functional description The MDM AP Control Register also includes a Very Low Leakage Debug Acknowledge (VLLDBGACK) bit that is set to release the ARM core being held in reset following a VLLS recovery. The debugger reinitializes all debug IP, and then asserts the VLLDBGACK control bit to allow the RCM to release the ARM core from reset and allow CPU operation to begin. The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clears automatically due to the reset generated as part of the next VLLS recovery. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 214 Freescale Semiconductor, Inc. Chapter 14 Power Management Controller (PMC) 14.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The power management controller (PMC) contains the internal voltage regulator, power on reset (POR), and low voltage detect system. 14.2 Features The PMC features include: * Internal voltage regulator * Active POR providing brown-out detect * Low-voltage detect supporting two low-voltage trip points with four warning levels per trip point 14.3 Low-voltage detect (LVD) system This device includes a system to guard against low-voltage conditions. This protects memory contents and controls MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and a LVD circuit with a userselectable trip voltage: high (VLVDH) or low (VLVDL). The trip voltage is selected by the LVDSC1[LVDV] bits. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes. Two flags are available to indicate the status of the low-voltage detect system: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 215 Low-voltage detect (LVD) system * The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDF bit is set when the supply voltage falls below the selected trip point (VLVD). The LVDF bit is cleared by writing one to the LVDACK bit, but only if the internal supply has returned above the trip point; otherwise, the LVDF bit remains set. * The low voltage warning flag (LVWF) operates in a level sensitive manner. The LVWF bit is set when the supply voltage falls below the selected monitor trip point (VLVW). The LVWF bit is cleared by writing one to the LVWACK bit, but only if the internal supply has returned above the trip point; otherwise, the LVWF bit remains set. 14.3.1 LVD reset operation By setting the LVDRE bit, the LVD generates a reset upon detection of a low voltage condition. The low voltage detection threshold is determined by the LVDV bits. After an LVD reset occurs, the LVD system holds the MCU in reset until the supply voltage rises above this threshold. The LVD bit in the SRS register is set following an LVD or poweron reset. 14.3.2 LVD interrupt operation By configuring the LVD circuit for interrupt operation (LVDIE set and LVDRE clear), LVDSC1[LVDF] is set and an LVD interrupt request occurs upon detection of a low voltage condition. The LVDF bit is cleared by writing one to the LVDSC1[LVDACK] bit. 14.3.3 Low-voltage warning (LVW) interrupt operation The LVD system contains a low-voltage warning flag (LVWF) to indicate that the supply voltage is approaching, but is above, the LVD voltage. The LVW also has an interrupt, which is enabled by setting the LVDSC2[LVWIE] bit. If enabled, an LVW interrupt request occurs when the LVWF is set. LVWF is cleared by writing one to the LVDSC2[LVWACK] bit. The LVDSC2[LVWV] bits select one of four trip voltages: * Highest: VLVW4 * Two mid-levels: VLVW3 and VLVW2 * Lowest: VLVW1 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 216 Freescale Semiconductor, Inc. Chapter 14 Power Management Controller (PMC) 14.4 I/O retention When in LLS mode, the I/O pins are held in their input or output state. Upon wakeup, the PMC is re-enabled, goes through a power up sequence to full regulation, and releases the logic from state retention mode. The I/O are released immediately after a wakeup or reset event. In the case of LLS exit via a RESET pin, the I/O default to their reset state. When in VLLS modes, the I/O states are held on a wakeup event (with the exception of wakeup by reset event) until the wakeup has been acknowledged via a write to the ACKISO bit. In the case of VLLS exit via a RESET pin, the I/O are released and default to their reset state. In this case, no write to the ACKISO is needed. 14.5 Memory map and register descriptions PMC register details follow. NOTE Different portions of PMC registers are reset only by particular reset types. Each register's description provides details. For more information about the types of reset on this chip, refer to the Reset section details. The PMC registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. PMC memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4007_D000 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1) 8 R/W 10h 14.5.1/218 4007_D001 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2) 8 R/W 00h 14.5.2/219 4007_D002 Regulator Status And Control register (PMC_REGSC) 8 R/W 04h 14.5.3/220 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 217 Memory map and register descriptions 14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1) This register contains status and control bits to support the low voltage detect function. This register should be written during the reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect systems that must have LVD always on, configure the SMC's power mode protection register (PMPROT) to disallow any very low power or low leakage modes from being enabled. See the device's data sheet for the exact LVD trip voltages. NOTE The LVDV bits are reset solely on a POR Only event. The register's other bits are reset on Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details. Address: 4007_D000h base + 0h offset = 4007_D000h Bit Read 7 6 LVDF 0 Write Reset LVDACK 0 0 5 4 3 LVDIE LVDRE 0 1 2 1 0 0 0 LVDV 0 0 0 PMC_LVDSC1 field descriptions Field 7 LVDF Description Low-Voltage Detect Flag This read-only status bit indicates a low-voltage detect event. 0 1 6 LVDACK 5 LVDIE Low-voltage event not detected Low-voltage event detected Low-Voltage Detect Acknowledge This write-only bit is used to acknowledge low voltage detection errors. Write 1 to clear LVDF. Reads always return 0. Low-Voltage Detect Interrupt Enable Enables hardware interrupt requests for LVDF. 0 1 Hardware interrupt disabled (use polling) Request a hardware interrupt when LVDF = 1 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 218 Freescale Semiconductor, Inc. Chapter 14 Power Management Controller (PMC) PMC_LVDSC1 field descriptions (continued) Field 4 LVDRE Description Low-Voltage Detect Reset Enable This write-once bit enables LVDF events to generate a hardware reset. Additional writes are ignored. 0 1 3-2 Reserved 1-0 LVDV LVDF does not generate hardware resets Force an MCU reset when LVDF = 1 This field is reserved. This read-only field is reserved and always has the value 0. Low-Voltage Detect Voltage Select Selects the LVD trip point voltage (V LVD ). 00 01 10 11 Low trip point selected (V LVD = V LVDL ) High trip point selected (V LVD = V LVDH ) Reserved Reserved 14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2) This register contains status and control bits to support the low voltage warning function. While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC2 settings. See the device's data sheet for the exact LVD trip voltages. NOTE The LVW trip voltages depend on LVWV and LVDV bits. NOTE The LVWV bits are reset solely on a POR Only event. The register's other bits are reset on Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details. Address: 4007_D000h base + 1h offset = 4007_D001h Bit Read 7 6 LVWF 0 Write Reset LVWACK 0 0 5 4 2 1 0 LVWIE 0 3 0 0 0 LVWV 0 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 219 Memory map and register descriptions PMC_LVDSC2 field descriptions Field 7 LVWF Description Low-Voltage Warning Flag This read-only status bit indicates a low-voltage warning event. LVWF is set when VSupply transitions below the trip point, or after reset and VSupply is already below VLVW. LVWF bit may be 1 after power on reset, therefore, to use LVW interrupt function, before enabling LVWIE, LVWF must be cleared by writing LVWACK first. 0 1 6 LVWACK 5 LVWIE Low-Voltage Warning Acknowledge This write-only bit is used to acknowledge low voltage warning errors. Write 1 to clear LVWF. Reads always return 0. Low-Voltage Warning Interrupt Enable Enables hardware interrupt requests for LVWF. 0 1 4-2 Reserved 1-0 LVWV Low-voltage warning event not detected Low-voltage warning event detected Hardware interrupt disabled (use polling) Request a hardware interrupt when LVWF = 1 This field is reserved. This read-only field is reserved and always has the value 0. Low-Voltage Warning Voltage Select Selects the LVW trip point voltage (VLVW). The actual voltage for the warning depends on LVDSC1[LVDV]. 00 01 10 11 Low trip point selected (VLVW = VLVW1) Mid 1 trip point selected (VLVW = VLVW2) Mid 2 trip point selected (VLVW = VLVW3) High trip point selected (VLVW = VLVW4) 14.5.3 Regulator Status And Control register (PMC_REGSC) The PMC contains an internal voltage regulator. The voltage regulator design uses a bandgap reference that is also available through a buffer as input to certain internal peripherals, such as the CMP and ADC. The internal regulator provides a status bit (REGONS) indicating the regulator is in run regulation. NOTE This register is reset on Chip Reset Not VLLS and by reset types that trigger Chip Reset not VLLS. See the Reset section for more information. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 220 Freescale Semiconductor, Inc. Chapter 14 Power Management Controller (PMC) Address: 4007_D000h base + 2h offset = 4007_D002h Bit 7 Read 6 5 0 Write Reset 0 4 Reserved BGEN 0 0 0 3 2 ACKISO REGONS w1c 0 1 1 0 Reserved BGBE 0 0 PMC_REGSC field descriptions Field Description 7-6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 Reserved This field is reserved. 4 BGEN Bandgap Enable In VLPx Operation BGEN controls whether the bandgap is enabled in lower power modes of operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage reference in low power modes of operation, set BGEN to continue to enable the bandgap operation. NOTE: When the bandgap voltage reference is not needed in low power modes, clear BGEN to avoid excess power consumption. 0 1 3 ACKISO Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes Acknowledge Isolation Reading this bit indicates whether certain peripherals and the I/O pads are in a latched state as a result of having been in a VLLS mode. Writing one to this bit when it is set releases the I/O pads and certain peripherals to their normal run mode state. NOTE: After recovering from a VLLS mode, user should restore chip configuration before clearing ACKISO. In particular, pin configuration for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from being falsely set when ACKISO is cleared. 0 1 2 REGONS Regulator In Run Regulation Status This read-only bit provides the current status of the internal voltage regulator. 0 1 1 Reserved Peripherals and I/O pads are in normal run state Certain peripherals and I/O pads are in an isolated and latched state Regulator is in stop regulation or in transition to/from it Regulator is in run regulation This field is reserved. NOTE: This reserved bit must remain cleared (set to 0). 0 BGBE Bandgap Buffer Enable Enables the bandgap buffer. 0 1 Bandgap buffer not enabled Bandgap buffer enabled KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 221 Memory map and register descriptions KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 222 Freescale Semiconductor, Inc. Chapter 15 Low-Leakage Wakeup Unit (LLWU) 15.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The LLWU module allows the user to select up to 16 external pin sources and up to 8 internal modules as a wakeup source from low-leakage power modes. The input sources are described in the device's chip configuration details. Each of the available wakeup sources can be individually enabled. The LLWU module also includes two optional digital pin filters for the external wakeup pins. 15.1.1 Features The LLWU module features include: * Support for up to 16 external input pins and up to 8 internal modules with individual enable bits * Input sources may be external pins or from internal peripherals capable of running in LLS or VLLS. See the chip configuration information for wakeup input sources for this device. * External pin wakeup inputs, each of which is programmable as falling-edge, risingedge, or any change * Wakeup inputs that are activated if enabled after MCU enters a low-leakage power mode * Optional digital filters provided to qualify an external pin detect. When entering VLLS0, the filters are disabled and bypassed. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 223 Introduction 15.1.2 Modes of operation The LLWU module becomes functional on entry into a low-leakage power mode. After recovery from LLS, the LLWU is immediately disabled. After recovery from VLLS, the LLWU continues to detect wakeup events until the user has acknowledged the wakeup via a write to the PMC_REGSC[ACKISO] bit. 15.1.2.1 LLS mode The LLWU module provides up to 16 external wakeup inputs and up to 8 internal module wakeup inputs. Wakeup events due to external wakeup inputs and internal module wakeup inputs result in an interrupt flow when exiting LLS. NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit Stop mode on an LLS recovery. 15.1.2.2 VLLS modes The LLWU module provides up to 16 external wakeup inputs and up to 8 internal module wakeup inputs. All wakeup events result in VLLS exit via a reset flow. 15.1.2.3 Non-low leakage modes The LLWU is not active in all non-low leakage modes where detection and control logic are in a static state. The LLWU registers are accessible in non-low leakage modes and are available for configuring and reading status when bus transactions are possible. When the wakeup pin filters are enabled, filter operation begins immediately. If a low leakage mode is entered within 5 LPO clock cycles of an active edge, the edge event will be detected by the LLWU. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 224 Freescale Semiconductor, Inc. Chapter 15 Low-Leakage Wakeup Unit (LLWU) 15.1.2.4 Debug mode When the chip is in Debug mode and then enters LLS or a VLLSx mode, no debug logic works in the fully-functional low-leakage mode. Upon an exit from the LLS or VLLSx mode, the LLWU becomes inactive. 15.1.3 Block diagram The following figure is the block diagram for the LLWU module. enter low leakge mode WUME7 Module7 interrupt flag (LLWU_M7IF) Module0 interrupt flag (LLWU_M0IF) Interrupt module flag detect LLWU_MWUF7 occurred Internal module sources Interrupt module flag detect FILT1[FILTSEL] LLWU_MWUF0 occurred WUME0 LPO LLWU_P15 Synchronizer LLWU_P0 Pin filter 1 LPO Synchronizer Pin filter 2 FILT1[FILTE] Edge detect Pin filter 1 wakeup occurred LLWU controller FILT2[FILTE] Edge detect exit low leakge mode Pin filter 2 wakeup occurred interrupt flow reset flow WUPE15 2 FILT2[FILTSEL] Edge detect Edge detect LLWU_P15 wakeup occurred LLWU_P0 wakeup occurred External pin sources 2 WUPE0 Figure 15-1. LLWU block diagram KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 225 LLWU signal descriptions 15.2 LLWU signal descriptions The signal properties of LLWU are shown in the following table. The external wakeup input pins can be enabled to detect either rising-edge, falling-edge, or on any change. Table 15-1. LLWU signal descriptions Signal LLWU_Pn Description I/O Wakeup inputs (n = 0-15) I 15.3 Memory map/register definition The LLWU includes the following registers: * Five 8-bit wakeup source enable registers * Enable external pin input sources * Enable internal peripheral sources * Three 8-bit wakeup flag registers * Indication of wakeup source that caused exit from a low-leakage power mode includes external pin or internal module interrupt * Two 8-bit wakeup pin filter enable registers NOTE The LLWU registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. All LLWU registers are reset by Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. Each register's displayed reset value represents this subset of reset types. LLWU registers are unaffected by reset types that do not trigger Chip Reset not VLLS. For more information about the types of reset on this chip, refer to the Introduction details. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 226 Freescale Semiconductor, Inc. Chapter 15 Low-Leakage Wakeup Unit (LLWU) LLWU memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_C000 LLWU Pin Enable 1 register (LLWU_PE1) 8 R/W 00h 15.3.1/227 4007_C001 LLWU Pin Enable 2 register (LLWU_PE2) 8 R/W 00h 15.3.2/228 4007_C002 LLWU Module Enable register (LLWU_ME) 8 R/W 00h 15.3.3/229 4007_C003 LLWU Flag 1 register (LLWU_F1) 8 R/W 00h 15.3.4/231 4007_C004 LLWU Flag 3 register (LLWU_F3) 8 R 00h 15.3.5/232 4007_C005 LLWU Pin Filter 1 register (LLWU_FILT1) 8 R/W 00h 15.3.6/234 4007_C006 LLWU Pin Filter 2 register (LLWU_FILT2) 8 R/W 00h 15.3.7/235 15.3.1 LLWU Pin Enable 1 register (LLWU_PE1) LLWU_PE1 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P3-LLWU_P0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 0h offset = 4007_C000h Bit Read Write Reset 7 6 5 WUPE3 0 4 3 WUPE2 0 0 2 1 WUPE1 0 0 0 WUPE0 0 0 0 LLWU_PE1 field descriptions Field 7-6 WUPE3 Description Wakeup Pin Enable For LLWU_P3 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 5-4 WUPE2 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P2 Enables and configures the edge detection for the wakeup pin. 00 01 External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 227 Memory map/register definition LLWU_PE1 field descriptions (continued) Field Description 10 11 3-2 WUPE1 Wakeup Pin Enable For LLWU_P1 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 1-0 WUPE0 External input pin enabled with falling edge detection External input pin enabled with any change detection External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P0 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 15.3.2 LLWU Pin Enable 2 register (LLWU_PE2) LLWU_PE2 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P7-LLWU_P4. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 1h offset = 4007_C001h Bit Read Write Reset 7 6 5 WUPE7 0 4 3 WUPE6 0 0 2 1 WUPE5 0 0 0 WUPE4 0 0 0 LLWU_PE2 field descriptions Field 7-6 WUPE7 Description Wakeup Pin Enable For LLWU_P7 Enables and configures the edge detection for the wakeup pin. 00 01 External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 228 Freescale Semiconductor, Inc. Chapter 15 Low-Leakage Wakeup Unit (LLWU) LLWU_PE2 field descriptions (continued) Field Description 10 11 5-4 WUPE6 Wakeup Pin Enable For LLWU_P6 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 3-2 WUPE5 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P5 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 1-0 WUPE4 External input pin enabled with falling edge detection External input pin enabled with any change detection External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P4 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 15.3.3 LLWU Module Enable register (LLWU_ME) LLWU_ME contains the bits to enable the internal module flag as a wakeup input source for inputs MWUF7-MWUF0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 2h offset = 4007_C002h Bit Read Write Reset 7 6 5 4 3 2 1 0 WUME7 WUME6 WUME5 WUME4 WUME3 WUME2 WUME1 WUME0 0 0 0 0 0 0 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 229 Memory map/register definition LLWU_ME field descriptions Field 7 WUME7 Description Wakeup Module Enable For Module 7 Enables an internal module as a wakeup source input. 0 1 6 WUME6 Wakeup Module Enable For Module 6 Enables an internal module as a wakeup source input. 0 1 5 WUME5 Enables an internal module as a wakeup source input. Enables an internal module as a wakeup source input. Enables an internal module as a wakeup source input. Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable for Module 1 Enables an internal module as a wakeup source input. 0 1 0 WUME0 Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 2 0 1 1 WUME1 Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 3 0 1 2 WUME2 Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 4 0 1 3 WUME3 Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 5 0 1 4 WUME4 Internal module flag not used as wakeup source Internal module flag used as wakeup source Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 0 Enables an internal module as a wakeup source input. 0 1 Internal module flag not used as wakeup source Internal module flag used as wakeup source KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 230 Freescale Semiconductor, Inc. Chapter 15 Low-Leakage Wakeup Unit (LLWU) 15.3.4 LLWU Flag 1 register (LLWU_F1) LLWU_F1 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will remain set if the associated WUPEx bit is cleared. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 3h offset = 4007_C003h Bit 7 6 5 4 3 2 1 0 Read WUF7 WUF6 WUF5 WUF4 WUF3 WUF2 WUF1 WUF0 Write w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 LLWU_F1 field descriptions Field 7 WUF7 Description Wakeup Flag For LLWU_P7 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF7. 0 1 6 WUF6 Wakeup Flag For LLWU_P6 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF6. 0 1 5 WUF5 LLWU_P7 input was not a wakeup source LLWU_P7 input was a wakeup source LLWU_P6 input was not a wakeup source LLWU_P6 input was a wakeup source Wakeup Flag For LLWU_P5 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF5. 0 1 LLWU_P5 input was not a wakeup source LLWU_P5 input was a wakeup source Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 231 Memory map/register definition LLWU_F1 field descriptions (continued) Field 4 WUF4 Description Wakeup Flag For LLWU_P4 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF4. 0 1 3 WUF3 Wakeup Flag For LLWU_P3 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF3. 0 1 2 WUF2 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF2. LLWU_P2 input was not a wakeup source LLWU_P2 input was a wakeup source Wakeup Flag For LLWU_P1 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF1. 0 1 0 WUF0 LLWU_P3 input was not a wakeup source LLWU_P3 input was a wakeup source Wakeup Flag For LLWU_P2 0 1 1 WUF1 LLWU_P4 input was not a wakeup source LLWU_P4 input was a wakeup source LLWU_P1 input was not a wakeup source LLWU_P1 input was a wakeup source Wakeup Flag For LLWU_P0 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF0. 0 1 LLWU_P0 input was not a wakeup source LLWU_P0 input was a wakeup source 15.3.5 LLWU Flag 3 register (LLWU_F3) LLWU_F3 contains the wakeup flags indicating which internal wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. For internal peripherals that are capable of running in a low-leakage power mode, such as iRTC or CMP modules, the flag from the associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared in the peripheral instead of writing a 1 to the MWUFx bit. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 232 Freescale Semiconductor, Inc. Chapter 15 Low-Leakage Wakeup Unit (LLWU) NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 4h offset = 4007_C004h Bit Read 7 6 5 4 3 2 1 0 MWUF7 MWUF6 MWUF5 MWUF4 MWUF3 MWUF2 MWUF1 MWUF0 0 0 0 0 0 0 0 0 Write Reset LLWU_F3 field descriptions Field 7 MWUF7 Description Wakeup flag For module 7 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 6 MWUF6 Wakeup flag For module 6 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 5 MWUF5 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. Module 4 input was not a wakeup source Module 4 input was a wakeup source Wakeup flag For module 3 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 2 MWUF2 Module 5 input was not a wakeup source Module 5 input was a wakeup source Wakeup flag For module 4 0 1 3 MWUF3 Module 6 input was not a wakeup source Module 6 input was a wakeup source Wakeup flag For module 5 0 1 4 MWUF4 Module 7 input was not a wakeup source Module 7 input was a wakeup source Module 3 input was not a wakeup source Module 3 input was a wakeup source Wakeup flag For module 2 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 233 Memory map/register definition LLWU_F3 field descriptions (continued) Field Description Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 1 MWUF1 Wakeup flag For module 1 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 0 MWUF0 Module 2 input was not a wakeup source Module 2 input was a wakeup source Module 1 input was not a wakeup source Module 1 input was a wakeup source Wakeup flag For module 0 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 Module 0 input was not a wakeup source Module 0 input was a wakeup source 15.3.6 LLWU Pin Filter 1 register (LLWU_FILT1) LLWU_FILT1 is a control and status register that is used to enable/disable the digital filter 1 features for an external pin. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 5h offset = 4007_C005h Bit 7 Read FILTF Write w1c Reset 0 6 5 3 2 0 FILTE 0 4 0 0 1 0 0 0 FILTSEL 0 0 LLWU_FILT1 field descriptions Field 7 FILTF Description Filter Detect Flag Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 234 Freescale Semiconductor, Inc. Chapter 15 Low-Leakage Wakeup Unit (LLWU) LLWU_FILT1 field descriptions (continued) Field Description 0 1 6-5 FILTE Pin Filter 1 was not a wakeup source Pin Filter 1 was a wakeup source Digital Filter On External Pin Controls the digital filter options for the external pin detect. 00 01 10 11 Filter disabled Filter posedge detect enabled Filter negedge detect enabled Filter any edge detect enabled 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3-0 FILTSEL Filter Pin Select Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 ... 1111 Select LLWU_P0 for filter ... Select LLWU_P15 for filter 15.3.7 LLWU Pin Filter 2 register (LLWU_FILT2) LLWU_FILT2 is a control and status register that is used to enable/disable the digital filter 2 features for an external pin. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 6h offset = 4007_C006h Bit 7 Read FILTF Write w1c Reset 0 6 5 FILTE 0 4 3 2 0 0 0 1 0 0 0 FILTSEL 0 0 LLWU_FILT2 field descriptions Field 7 FILTF Description Filter Detect Flag Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 235 Functional description LLWU_FILT2 field descriptions (continued) Field Description 0 1 6-5 FILTE Pin Filter 2 was not a wakeup source Pin Filter 2 was a wakeup source Digital Filter On External Pin Controls the digital filter options for the external pin detect. 00 01 10 11 Filter disabled Filter posedge detect enabled Filter negedge detect enabled Filter any edge detect enabled 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3-0 FILTSEL Filter Pin Select Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 ... 1111 Select LLWU_P0 for filter ... Select LLWU_P15 for filter 15.4 Functional description This on-chip peripheral module is called a low-leakage wakeup unit (LLWU) module because it allows internal peripherals and external input pins as a source of wakeup from low-leakage modes. It is operational only in LLS and VLLSx modes. The LLWU module contains pin enables for each external pin and internal module. For each external pin, the user can disable or select the edge type for the wakeup. Type options are: * Falling-edge * Rising-edge * Either-edge When an external pin is enabled as a wakeup source, the pin must be configured as an input pin. The LLWU implements optional 3-cycle glitch filters, based on the LPO clock. A detected external pin is required to remain asserted until the enabled glitch filter times out. Additional latency of up to 2 cycles is due to synchronization, which results in a total of up to 5 cycles of delay before the detect circuit alerts the system to the wakeup or reset event when the filter function is enabled. Two wakeup detect filters are available to detect up to two external pins. Glitch filtering is not provided on the internal modules. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 236 Freescale Semiconductor, Inc. Chapter 15 Low-Leakage Wakeup Unit (LLWU) For internal module wakeup operation, the WUMEx bit enables the associated module as a wakeup source. 15.4.1 LLS mode Wakeup events triggered from either an external pin input or an internal module input result in a CPU interrupt flow to begin user code execution. 15.4.2 VLLS modes In the case of a wakeup due to external pin or internal module wakeup, recovery is always via a reset flow and the RCM_SRS[WAKEUP] is set indicating the low-leakage mode was active. State retention data is lost and I/O will be restored after PMC_REGSC[ACKISO] has been written. 15.4.3 Initialization For an enabled peripheral wakeup input, the peripheral flag must be cleared by software before entering LLS or VLLSx mode to avoid an immediate exit from the mode. Flags associated with external input pins, filtered and unfiltered, must also be cleared by software prior to entry to LLS or VLLSx mode. After enabling an external pin filter or changing the source pin, wait at least 5 LPO clock cycles before entering LLS or VLLSx mode to allow the filter to initialize. NOTE After recovering from a VLLS mode, user must restore chip configuration before clearing ACKISO. In particular, pin configuration for enabled LLWU wakeup pins must be restored to avoid any LLWU flag from being falsely set when ACKISO is cleared. The signal selected as a wakeup source pin must be a digital pin, as selected in the pin mux control. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 237 Functional description KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 238 Freescale Semiconductor, Inc. Chapter 16 Reset Control Module (RCM) 16.1 Introduction This chapter describes the registers of the Reset Control Module (RCM). The RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. 16.2 Reset memory map and register descriptions The Reset Control Module (RCM) registers provide reset status information and reset filter control. NOTE The RCM registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. RCM memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4007_F000 System Reset Status Register 0 (RCM_SRS0) 8 R 82h 16.2.1/239 4007_F001 System Reset Status Register 1 (RCM_SRS1) 8 R 00h 16.2.2/241 4007_F004 Reset Pin Filter Control register (RCM_RPFC) 8 R/W 00h 16.2.3/242 4007_F005 Reset Pin Filter Width register (RCM_RPFW) 8 R/W 00h 16.2.4/243 16.2.1 System Reset Status Register 0 (RCM_SRS0) This register includes read-only status flags to indicate the source of the most recent reset. The reset state of these bits depends on what caused the MCU to reset. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 239 Reset memory map and register descriptions NOTE The reset value of this register depends on the reset source: * POR (including LVD) -- 0x82 * LVD (without POR) -- 0x02 * VLLS mode wakeup due to RESET pin assertion -- 0x41 * VLLS mode wakeup due to other wakeup sources -- 0x01 * Other reset -- a bit is set if its corresponding reset source caused the reset Address: 4007_F000h base + 0h offset = 4007_F000h Bit Read 7 6 5 POR PIN WDOG 1 0 0 4 3 0 2 1 0 LOC LVD WAKEUP 0 1 0 Write Reset 0 0 RCM_SRS0 field descriptions Field 7 POR Description Power-On Reset Indicates a reset has been caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold. 0 1 6 PIN External Reset Pin Indicates a reset has been caused by an active-low level on the external RESET pin. 0 1 5 WDOG 2 LOC Reset not caused by external reset pin Reset caused by external reset pin Watchdog Indicates a reset has been caused by the watchdog timer Computer Operating Properly (COP) timing out. This reset source can be blocked by disabling the COP watchdog: write 00 to the SIM's COPC[COPT] field. 0 1 4-3 Reserved Reset not caused by POR Reset caused by POR Reset not caused by watchdog timeout Reset caused by watchdog timeout This field is reserved. This read-only field is reserved and always has the value 0. Loss-of-Clock Reset Indicates a reset has been caused by a loss of external clock. The MCG clock monitor must be enabled for a loss of clock to be detected. Refer to the detailed MCG description for information on enabling the clock monitor. 0 1 Reset not caused by a loss of external clock. Reset caused by a loss of external clock. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 240 Freescale Semiconductor, Inc. Chapter 16 Reset Control Module (RCM) RCM_SRS0 field descriptions (continued) Field 1 LVD Description Low-Voltage Detect Reset If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This bit is also set by POR. 0 1 0 WAKEUP Reset not caused by LVD trip or POR Reset caused by LVD trip or POR Low Leakage Wakeup Reset Indicates a reset has been caused by an enabled LLWU module wakeup source while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx mode causes a reset. This bit is cleared by any reset except WAKEUP. 0 1 Reset not caused by LLWU module wakeup source Reset caused by LLWU module wakeup source 16.2.2 System Reset Status Register 1 (RCM_SRS1) This register includes read-only status flags to indicate the source of the most recent reset. The reset state of these bits depends on what caused the MCU to reset. NOTE The reset value of this register depends on the reset source: * POR (including LVD) -- 0x00 * LVD (without POR) -- 0x00 * VLLS mode wakeup -- 0x00 * Other reset -- a bit is set if its corresponding reset source caused the reset Address: 4007_F000h base + 1h offset = 4007_F001h Bit 7 6 5 4 3 2 1 0 Read 0 0 SACKERR 0 MDM_AP SW LOCKUP 0 0 0 0 0 0 0 0 0 Write Reset RCM_SRS1 field descriptions Field Description 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 241 Reset memory map and register descriptions RCM_SRS1 field descriptions (continued) Field 5 SACKERR Description Stop Mode Acknowledge Error Reset Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more peripherals to acknowledge within approximately one second to enter stop mode. 0 1 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode Reset caused by peripheral failure to acknowledge attempt to enter stop mode 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 MDM_AP MDM-AP System Reset Request Indicates a reset has been caused by the host debugger system setting of the System Reset Request bit in the MDM-AP Control Register. 0 1 2 SW Software Indicates a reset has been caused by software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register in the ARM core. 0 1 1 LOCKUP Reset not caused by software setting of SYSRESETREQ bit Reset caused by software setting of SYSRESETREQ bit Core Lockup Indicates a reset has been caused by the ARM core indication of a LOCKUP event. 0 1 0 Reserved Reset not caused by host debugger system setting of the System Reset Request bit Reset caused by host debugger system setting of the System Reset Request bit Reset not caused by core LOCKUP event Reset caused by core LOCKUP event This field is reserved. This read-only field is reserved and always has the value 0. 16.2.3 Reset Pin Filter Control register (RCM_RPFC) NOTE The reset values of bits 2-0 are for Chip POR only. They are unaffected by other reset types. NOTE The bus clock filter is reset when disabled or when entering stop mode. The LPO filter is reset when disabled . Address: 4007_F000h base + 4h offset = 4007_F004h Bit Read Write Reset 7 6 5 4 3 0 0 0 0 2 1 RSTFLTSS 0 0 0 0 RSTFLTSRW 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 242 Freescale Semiconductor, Inc. Chapter 16 Reset Control Module (RCM) RCM_RPFC field descriptions Field 7-3 Reserved 2 RSTFLTSS Description This field is reserved. This read-only field is reserved and always has the value 0. Reset Pin Filter Select in Stop Mode Selects how the reset pin filter is enabled in Stop and VLPS modes , and also during LLS and VLLS modes. On exit from VLLS mode, this bit should be reconfigured before clearing ACKISO in the PMC. 0 1 1-0 RSTFLTSRW All filtering disabled LPO clock filter enabled Reset Pin Filter Select in Run and Wait Modes Selects how the reset pin filter is enabled in run and wait modes. 00 01 10 11 All filtering disabled Bus clock filter enabled for normal operation LPO clock filter enabled for normal operation Reserved 16.2.4 Reset Pin Filter Width register (RCM_RPFW) NOTE The reset values of the bits in the RSTFLTSEL field are for Chip POR only. They are unaffected by other reset types. Address: 4007_F000h base + 5h offset = 4007_F005h Bit Read Write Reset 7 6 5 4 3 0 0 0 2 1 0 0 0 RSTFLTSEL 0 0 0 0 RCM_RPFW field descriptions Field 7-5 Reserved 4-0 RSTFLTSEL Description This field is reserved. This read-only field is reserved and always has the value 0. Reset Pin Filter Bus Clock Select Selects the reset pin bus clock filter width. 00000 00001 00010 00011 00100 Bus clock filter count is 1 Bus clock filter count is 2 Bus clock filter count is 3 Bus clock filter count is 4 Bus clock filter count is 5 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 243 Reset memory map and register descriptions RCM_RPFW field descriptions (continued) Field Description 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Bus clock filter count is 6 Bus clock filter count is 7 Bus clock filter count is 8 Bus clock filter count is 9 Bus clock filter count is 10 Bus clock filter count is 11 Bus clock filter count is 12 Bus clock filter count is 13 Bus clock filter count is 14 Bus clock filter count is 15 Bus clock filter count is 16 Bus clock filter count is 17 Bus clock filter count is 18 Bus clock filter count is 19 Bus clock filter count is 20 Bus clock filter count is 21 Bus clock filter count is 22 Bus clock filter count is 23 Bus clock filter count is 24 Bus clock filter count is 25 Bus clock filter count is 26 Bus clock filter count is 27 Bus clock filter count is 28 Bus clock filter count is 29 Bus clock filter count is 30 Bus clock filter count is 31 Bus clock filter count is 32 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 244 Freescale Semiconductor, Inc. Chapter 17 Bit Manipulation Engine (BME) 17.1 Introduction The Bit Manipulation Engine (BME) provides hardware support for atomic read-modifywrite memory operations to the peripheral address space in Cortex-M0+ based microcontrollers. This architectural capability is also known as "decorated storage" as it defines a mechanism for providing additional semantics for load and store operations to memory-mapped peripherals beyond just the reading and writing of data values to the addressed memory locations. In the BME definition, the "decoration", that is, the additional semantic information, is encoded into the peripheral address used to reference the memory. By combining the basic load and store instructions of the Cortex-M instruction set architecture (v6M, v7M) with the concept of decorated storage provided by the BME, the resulting implementation provides a robust and efficient read-modify-write capability to this class of ultra low-end microcontrollers. The resulting architectural capability defined by this core platform function is targeted at the manipulation of n-bit fields in peripheral registers and is consistent with I/O hardware addressing in the Embedded C standard. For most BME commands, a single core read or write bus cycle is converted into an atomic read-modify-write, that is, an indivisible "read followed by a write" bus sequence. BME decorated references are only available on system bus transactions generated by the processor core and targeted at the standard 512 KB peripheral address space based at 0x4000_00001. The decoration semantic is embedded into address bits[28:19], creating a 448 MB space at addresses 0x4400_0000 - 0x5FFF_FFFF; these bits are stripped out of the actual address sent to the peripheral bus controller and used by the BME to define and control its operation. 1. To be perfectly accurate, the peripheral address space occupies a 516 KB region: 512 KB based at 0x4000_0000 plus a 4 KB space based at 0x400F_F000 for GPIO accesses. This organization provides compatibility with the Kinetis K Family. Attempted accesses to the memory space located between 0x4008_0000 - 0x400E_FFFF are error terminated due to an illegal address. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 245 Introduction 17.1.1 Overview The following figure is a generic block diagram of the processor core and platform for this class of ultra low-end microcontrollers. Cortex-M0+ Core NVIC CM0+ Core Platform Fetch Dbg AGU Dec Rn LD/ST SHFT ALU MUL AHB Bus IO Port MTB Port 32 PRAM RAM Array RGPIO m0 s1 AXBS -Lite Alt-Master DMA_4ch 32 m3 s2 m2 s0 BME PBRIDGE 32 FMC Slave Peripherals NVM Array Note: BME can be accessed only by the core. Figure 17-1. Generic Cortex-M0+ core platform block diagram As shown in the block diagram, the BME module interfaces to a crossbar switch AHB slave port as its primary input and sources an AHB bus output to the Peripheral Bridge (PBRIDGE) controller. The BME hardware microarchitecture is a 2-stage pipeline design matching the protocol of the AMBA-AHB system bus interfaces. The PBRIDGE module converts the AHB system bus protocol into the IPS/APB protocol used by the attached slave peripherals. 17.1.2 Features The key features of the BME include: * Lightweight implementation of decorated storage for peripheral address space * Additional access semantics encoded into the reference address KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 246 Freescale Semiconductor, Inc. Chapter 17 Bit Manipulation Engine (BME) * * * * * * * * Resides between a crossbar switch slave port and a peripheral bridge bus controller 2-stage pipeline design matching the AHB system bus protocol Combinationally passes non-decorated accesses to peripheral bridge bus controller Conversion of decorated loads and stores from processor core into atomic readmodify-writes Decorated loads support unsigned bit field extracts, load-and-{set,clear}-1bit operations Decorated stores support bit field inserts, logical AND, OR and XOR operations Support for byte, halfword and word-sized decorated operations Supports minimum signal toggling on AHB output bus to reduce power dissipation 17.1.3 Modes of Operation The BME module does not support any special modes of operation. As a memorymapped device located on a crossbar slave AHB system bus port, BME responds based strictly on memory addresses for accesses to the connected peripheral bridge bus controller. All functionality associated with the BME module resides in the core platform's clock domain; this includes its connections with the crossbar slave port and the PBRIDGE bus controller. 17.2 External Signal Description The BME module does not directly support any external interfaces. The internal interfaces include two standard AHB buses with 32-bit datapath widths: the primary input from the appropriate crossbar slave port (mx_h<signal>) and the primary output to the PBRIDGE bus controller (sx_h<signal>). Note the signal directions are defined by the BME's view and are labeled based on the dominant direction. Accordingly, the mx_h<signal> AHB bus is the primary input, even though there are certain data phase signals (mx_h{rdata, ready, resp}) which are outputs from BME. Likewise, the sx_h<signal> AHB bus is the primary output even though there are specific data phase signals (sx_h{rdata, ready, resp}) which are inputs to BME. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 247 Memory Map and Register Definition 17.3 Memory Map and Register Definition The BME module provides a memory-mapped capability and does not include any programming model registers. The exact set of functions supported by the BME are detailed in the Functional Description. The peripheral address space occupies a 516 KB region: 512 KB based at 0x4000_0000 plus a 4 KB space based at 0x400F_F000 for GPIO accesses; the decorated address space is mapped to the 448 MB region located at 0x4400_0000 - 0x5FFF_FFFF. 17.4 Functional Description This section details the specific functions supported by the BME. Recall the combination of the basic load and store instructions of the Cortex-M instruction set architecture (v6M, v7M) plus the concept of decorated storage provided by the BME, the resulting implementation provides a robust and efficient read-modify-write capability to this class of ultra low-end microcontrollers. The resulting architectural capability defined by this core platform function is targeted at the manipulation of n-bit fields in peripheral registers and is consistent with I/O hardware addressing in the Embedded C standard. For most BME commands, a single core read or write bus cycle is converted into an atomic read-modify-write, that is, an indivisible "read followed by a write" bus sequence. Consider decorated store operations first, then decorated loads. 17.4.1 BME Decorated Stores The functions supported by the BME's decorated stores include three logical operators (AND, OR, XOR) plus a bit field insert. For all these operations, BME converts a single decorated AHB store transaction into a 2-cycle atomic read-modify-write sequence, where the combined read-modify operation is performed in the first AHB data phase, and then the write is performed in the second AHB data phase. A generic timing diagram of a decorated store showing a bit field insert operation is shown as follows: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 248 Freescale Semiconductor, Inc. Chapter 17 Bit Manipulation Engine (BME) CYCLE RULER x x+1 x+2 x+3 hclk BME AHB Input Bus mx_haddr next 5..v_wxyz mx_hattr next mx_hwrite next mx_hwdata wdata mx_hrdata mx_hready BME AHB Output Bus sx_haddr 400v_wxyz 400v_wxyz next sx_hattr next sx_hwrite next sx_hwdata wdata bfi rdata sx_hrdata rdata sx_hready BME States + Datapath control_state_dp1 control_state_dp2 reg_addr_data_dp 5..v_wxyz wdata bfi rdata Figure 17-2. Decorated store: bit field insert timing diagram All the decorated store operations follow the same execution template shown in the figure above, a 2-cycle read-modify-write operation: * Cycle x, 1st AHB address phase: Write from input bus (mx_h<signal>) is translated into a read operation on the output bus (sx_h<signal>) using the actual memory address (with the decoration removed) and then captured in a register (reg_addr_data_dp) * Cycle x+1, 2nd AHB address phase: Write access with the registered (but actual) memory address is output (sx_h<signal>) * Cycle x+1, 1st AHB data phase: Memory read data (sx_hrdata) is modified using the input bus write data (mx_hwdata) and the function defined by the decoration and captured in a data register (reg_addr_data_dp); the input bus cycle is stalled (mx_hready = 0) * Cycle x+2, 2nd AHB data phase: Registered write data is sourced onto the output write data bus (sx_hwdata) KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 249 Functional Description NOTE Any wait states inserted by the peripheral slave device (sx_hready = 0) are simply passed through the BME back to the master input bus, stalling the AHB transaction cycle for cycle. 17.4.1.1 Decorated Store Logical AND (AND) This command performs an atomic read-modify-write of the referenced memory location. First, the location is read; it is then modified by performing a logical AND operation using the write data operand sourced for the system bus cycle; finally, the result of the AND operation is written back into the referenced memory location. The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit) or word (32-bit). The core performs the required write data lane replication on byte and halfword transfers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ioandb 0 1 0 0 0 1 - - - - - - mem_addr ioandh 0 1 0 0 0 1 - - - - - - mem_addr ioandw 0 1 0 0 0 1 - - - - - - mem_addr 7 6 5 4 3 2 1 0 0 0 0 Figure 17-3. Decorated store address: logical AND where addr[28:26] = 001 specifies the AND operation, and mem_addr[19:0] specifies the address offset into the peripheral space based at 0x4000_0000. The "-" indicates an address bit "don't care". The decorated AND write operation is defined in the following pseudo-code as: ioand<sz>(accessAddress, wdata) tmp = mem[accessAddress & 0xE00FFFFF, size] tmp = tmp & wdata mem[accessAddress & 0xE00FFFFF, size] = tmp // // // // decorated store AND memory read modify memory write where the operand size <sz> is defined as b(yte, 8-bit), h(alfword, 16-bit) and w(ord, 32bit). This notation is used throughout the document. In the cycle definition tables, the notation AHB_ap and AHB_dp refers to the address and data phases of the BME AHB transaction. The cycle-by-cycle BME operations are detailed in the following table. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 250 Freescale Semiconductor, Inc. Chapter 17 Bit Manipulation Engine (BME) Table 17-1. Cycle definitions of decorated store: logical AND Pipeline Stage Cycle x BME AHB_ap x+1 Forward addr to memory; Decode decoration; Convert master_wt to slave_rd; Capture address, attributes BME AHB_dp <previous> x+2 Recirculate captured addr + attr to memory as slave_wt <next> Perform memory read; Form (rdata & wdata) and capture destination data in register Perform write sending registered data to memory 17.4.1.2 Decorated Store Logical OR (OR) This command performs an atomic read-modify-write of the referenced memory location. First, the location is read; it is then modified by performing a logical OR operation using the write data operand sourced for the system bus cycle; finally, the result of the OR operation is written back into the referenced memory location. The data size is specified by the write operation and can be byte (8 bit), halfword (16 bit) or word (32 bit). The core performs the required write data lane replication on byte and halfword transfers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ioorb 0 1 0 0 1 0 - - - - - - mem_addr ioorh 0 1 0 0 1 0 - - - - - - mem_addr ioorw 0 1 0 0 1 0 - - - - - - mem_addr 7 6 5 4 3 2 1 0 0 0 0 Figure 17-4. Decorated Address Store: Logical OR where addr[28:26] = 010 specifies the OR operation, and mem_addr[19:0] specifies the address offset into the peripheral space based at 0x4000_0000. The "-" indicates an address bit "don't care". The decorated OR write operation is defined in the following pseudo-code as: ioor<sz>(accessAddress, wdata) // decorated store OR tmp = mem[accessAddress & 0xE00FFFFF, size] tmp = tmp | wdata mem[accessAddress & 0xE00FFFFF, size] = tmp // memory read // modify // memory write The cycle-by-cycle BME operations are detailed in the following table KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 251 Functional Description Table 17-2. Cycle definitions of decorated store: logical OR Pipeline Stage Cycle x BME AHB_ap x+1 Forward addr to memory; Decode decoration; Convert master_wt to slave_rd; Capture address, attributes BME AHB_dp <previous> x+2 Recirculate captured addr + attr to memory as slave_wt <next> Perform memory read; Form (rdata | wdata) and capture destination data in register Perform write sending registered data to memory 17.4.1.3 Decorated Store: Logical XOR (XOR) This command performs an atomic read-modify-write of the referenced memory location. First, the location is read; it is then modified by performing a logical XOR (exclusiveOR) operation using the write data operand sourced for the system bus cycle; finally, the result of the XOR operation is written back into the referenced memory location. The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit) or word (32-bit). The core performs the required write data lane replication on byte and halfword transfers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ioxorb 0 1 0 0 1 1 - - - - - - mem_addr ioxorh 0 1 0 0 1 1 - - - - - - mem_addr ioxorw 0 1 0 0 1 1 - - - - - - mem_addr 7 6 5 4 3 2 1 0 0 0 0 Figure 17-5. Decorated Address Store: Logical XOR where addr[28:26] = 011 specifies the XOR operation, and mem_addr[19:0] specifies the address offset into the peripheral space based at 0x4000_0000. The "-" indicates an address bit "don't care". The decorated XOR write operation is defined in the following pseudo-code as: ioxor<sz>(accessAddress, wdata) // decorated store XOR tmp = mem[accessAddress & 0xE00FFFFF, size] tmp = tmp ^ wdata mem[accessAddress & 0xE00FFFFF, size] = tmp // memory read // modify // memory write The cycle-by-cycle BME operations are detailed in the following table. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 252 Freescale Semiconductor, Inc. Chapter 17 Bit Manipulation Engine (BME) Table 17-3. Cycle definitions of decorated store: logical XOR Pipeline Stage Cycle x BME AHB_ap Forward addr to memory; Decode decoration; Convert master_wt to slave_rd; Capture address, attributes BME AHB_dp <previous> x+1 x+2 Recirculate captured addr + attr to memory as slave_wt <next> Perform memory read; Form (rdata ^ wdata) and capture destination data in register Perform write sending registered data to memory 17.4.1.4 Decorated Store Bit Field Insert (BFI) This command inserts a bit field contained in the write data operand, defined by LSB position (b) and the bit field width (w+1), into the memory "container" defined by the access size associated with the store instruction using an atomic read-modify-write sequence. The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit) or word (32-bit). Note for the word sized operation, the maximum bit field width is 16 bits. The core performs the required write data lane replication on byte and halfword transfers. The BFI operation can be used to insert a single bit into a peripheral. For this case, the w field is simply set to 0, indicating a bit field width of 1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - 9 8 iobfib 0 1 0 1 - - b b b w w w mem_addr iobfih 0 1 0 1 - b b b b w w w w mem_addr iobfiw 0 1 0 1 b b b b b w w w w mem_addr 7 6 5 4 3 2 1 0 0 0 0 Figure 17-6. Decorated address store: bit field insert where addr[28] = 1 signals a BFI operation, addr[27:23] is "b", the LSB identifier, addr[22:19] is "w", the bit field width minus 1 identifier, and addr[18:0] specifies the address offset into the peripheral space based at 0x4000_0000. The "-" indicates an address bit "don't care". Note, unlike the other decorated store operations, BFI uses addr[19] as the least significant bit in the "w" specifier and not as an address bit. The decorated BFI write operation is defined in the following pseudo-code as: iobfi<sz>(accessAddress, wdata) // decorated bit field insert tmp mask // memory read // generate bit mask = mem[accessAddress & 0xE007FFFF, size] = ((1 << (w+1)) - 1) << b KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 253 Functional Description tmp = tmp & ~mask | wdata & mask mem[accessAddress & 0xE007FFFF, size] = tmp // modify // memory write The write data operand (wdata) associated with the store instruction contains the bit field to be inserted. It must be properly aligned within a right-justified container, that is, within the lower 8 bits for a byte operation, the lower 16 bits for a halfword or the entire 32 bits for a word operation. To illustrate, consider the following example of the insertion of the 3-bit field "xyz" into an 8-bit memory container, initially set to "abcd_efgh". For all cases, w is 2, signaling a bit field width of 3. if b = 0 and the decorated store (strb) then destination is "abcd_exyz" if b = 1 and the decorated store (strb) then destination is "abcd_xyzh" if b = 2 and the decorated store (strb) then destination is "abcx_yzgh" if b = 3 and the decorated store (strb) then destination is "abxy_zfgh" if b = 4 and the decorated store (strb) then destination is "axyz_efgh" if b = 5 and the decorated store (strb) then destination is "xyzd_efgh" if b = 6 and the decorated store (strb) then destination is "yzcd_efgh" if b = 7 and the decorated store (strb) then destination is "zbcd_efgh" Rt register[7:0] = ----_-xyz, Rt register[7:0] = ----_xyz-, Rt register[7:0] = ---x_yz--, Rt register[7:0] = --xy_z---, Rt register[7:0] = -xyz_----, Rt register[7:0] = xyz-_----, Rt register[7:0] = yz--_----, Rt register[7:0] = z---_----, Note from the example, when the starting bit position plus the field width exceeds the container size, only part of the source bit field is inserted into the destination memory location. Stated differently, if (b + w+1) > container_width, only the low-order "container_width - b" bits are actually inserted. The cycle-by-cycle BME operations are detailed in the following table. Table 17-4. Cycle definitions of decorated store: bit field insert Pipeline Stage Cycle x BME AHB_ap BME AHB_dp Forward addr to memory; Decode decoration; Convert master_wt to slave_rd; Capture address, attributes <previous> x+1 x+2 Recirculate captured addr + attr to memory as slave_wt Perform memory read; Form bit mask; Form bitwise ((mask) ? wdata : rdata)) and capture destination data in register <next> Perform write sending registered data to memory KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 254 Freescale Semiconductor, Inc. Chapter 17 Bit Manipulation Engine (BME) 17.4.2 BME Decorated Loads The functions supported by the BME's decorated loads include two single-bit load-and{set, clear} operators plus unsigned bit field extracts. For the two load-and-{set, clear} operations, BME converts a single decorated AHB load transaction into a 2-cycle atomic read-modify-write sequence, where the combined read-modify operations are performed in the first AHB data phase, and then the write is performed in the second AHB data phase as the original read data is returned to the processor core. For an unsigned bit field extract, the decorated load transaction is stalled for one cycle in the BME as the data field is extracted, then aligned and returned to the processor in the 2nd AHB data phase. This is the only decorated transaction that is not an atomic read-modify-write, as it is a simple data read. A generic timing diagram of a decorated load showing a load-and-set 1-bit operation is shown as follows. CYCLE RULER x x+1 x+2 x+3 hclk BME AHB Input Bus mx_haddr 4c.v_wxyz next mx_hattr next mx_hwrite next mx_hwdata orig_1bit mx_hrdata mx_hready BME AHB Output Bus sx_haddr 400v_wxyz 400v_wxyz next sx_hattr next sx_hwrite next sx_hwdata rdata + 1bit sx_hrdata rdata sx_hready BME States + Datapath control_state_dp1 control_state_dp2 reg_addr_data_dp 4c.v_wxyz rdata + 1bit Figure 17-7. Decorated load: load-and-set 1-bit field insert timing diagram Decorated load-and-{set, clear} 1-bit operations follow the execution template shown in the above figure: a 2-cycle read-modify-write operation: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 255 Functional Description * Cycle x, 1st AHB address phase: Read from input bus is translated into a read operation on the output bus with the actual memory address (with the decoration removed) and then captured in a register * Cycle x+1, 2nd AHB address phase: Write access with the registered (but actual) memory address is output * Cycle x+1, 1st AHB data phase: The "original" 1-bit memory read data is captured in a register, while the 1-bit field is set or clear based on the function defined by the decoration with the modified data captured in a register; the input bus cycle is stalled * Cycle x+2, 2nd AHB data phase: The selected original 1-bit is right justified, zero filled and then driven onto the input read data bus, while the registered write data is sourced onto the output write data bus NOTE Any wait states inserted by the peripheral slave device (sx_hready = 0) are simply passed through the BME back to the master input bus, stalling the AHB transaction cycle for cycle. A generic timing diagram of a decorated load showing an unsigned bit field operation is shown in the following figure. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 256 Freescale Semiconductor, Inc. Chapter 17 Bit Manipulation Engine (BME) CYCLE RULER 1 2 3 4 hclk BME AHB Input Bus mx_haddr 5..v_wxyz next mx_hattr next mx_hwrite next mx_hwdata ubfx mx_hrdata mx_hready BME AHB Output Bus sx_haddr 400v_wxyz next sx_hattr next sx_hwrite next sx_hwdata sx_hrdata rdata sx_hready BME States + Datapath control_state_dp1 control_state_dp2 reg_addr_data_dp 5..v_wxyz rdata Figure 17-8. Decorated load: unsigned bit field insert timing diagram The decorated unsigned bit field extract follows the same execution template shown in the above figure, a 2-cycle read operation: * Cycle x, 1st AHB address phase: Read from input bus is translated into a read operation on the output bus with the actual memory address (with the decoration removed) and then captured in a register * Cycle x+1, 2nd AHB address phase: Idle cycle * Cycle x+1, 1st AHB data phase: A bit mask is generated based on the starting bit position and the field width; the mask is AND'ed with the memory read data to isolate the bit field; the resulting data is captured in a data register; the input bus cycle is stalled * Cycle x+2, 2nd AHB data phase: Registered data is logically right shifted for proper alignment and driven onto the input read data bus NOTE Any wait states inserted by the peripheral slave device (sx_hready = 0) are simply passed through the BME back to the master input bus, stalling the AHB transaction cycle for cycle. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 257 Functional Description 17.4.2.1 Decorated Load Load-and-Clear 1 Bit (LAC1) This command loads a 1-bit field defined by the LSB position (b) into the core's general purpose destination register (Rt) and zeroes the bit in the memory space after performing an atomic read-modify-write sequence. The extracted one bit data field from the memory address is right justified and zero filled in the operand returned to the core. The data size is specified by the read operation and can be byte (8-bit), halfword (16-bit) or word (32-bit). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 iolac1b 0 1 0 0 1 0 iolac1h 0 1 0 0 1 iolac1w 0 1 0 0 1 9 8 - - b b b - mem_addr 0 - b b b b - mem_addr 0 b b b b b - mem_addr 7 6 5 4 3 2 1 0 0 0 0 Figure 17-9. Decorated load address: load-and-clear 1 bit where addr[28:26] = 010 specifies the load-and-clear 1 bit operation, addr[25:21] is "b", the bit identifier, and mem_addr[19:0] specifies the address offset into the peripheral space based at 0x4000_0000. The "-" indicates an address bit "don't care". The decorated Load-and-Clear 1 Bit read operation is defined in the following pseudocode as: rdata = iolac1<sz>(accessAddress) // decorated load-and-clear 1 tmp = mem[accessAddress & 0xE00FFFFF, size] mask = 1 << b rdata = (tmp & mask) >> b tmp = tmp & ~mask mem[accessAddress & 0xE00FFFFF, size] = tmp // // // // // memory read generate bit mask read data returned to core modify memory write The cycle-by-cycle BME operations are detailed in the following table. Table 17-5. Cycle definitions of decorated load: load-and-clear 1 bit Pipeline Stage Cycle x BME AHB_ap BME AHB_dp Forward addr to memory; Decode decoration; Capture address, attributes <previous> x+1 x+2 Recirculate captured addr + attr to memory as slave_wt <next> Perform memory read; Form bit mask; Extract bit from rdata; Form (rdata & ~mask) and capture destination data in register Return extracted bit to master; Perform write sending registered data to memory KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 258 Freescale Semiconductor, Inc. Chapter 17 Bit Manipulation Engine (BME) 17.4.2.2 Decorated Load: Load-and-Set 1 Bit (LAS1) This command loads a 1-bit field defined by the LSB position (b) into the core's general purpose destination register (Rt) and sets the bit in the memory space after performing an atomic read-modify-write sequence. The extracted one bit data field from the memory address is right justified and zero filled in the operand returned to the core. The data size is specified by the read operation and can be byte (8-bit), halfword (16-bit) or word (32-bit). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 iolas1b 0 1 0 0 1 1 - - b b b - mem_addr iolas1h 0 1 0 0 1 1 - b b b b - mem_addr iolas1w 0 1 0 0 1 1 b b b b b - mem_addr 7 6 5 4 3 2 1 0 0 0 0 Figure 17-10. Decorated load address: load-and-set 1 bit where addr[28:26] = 011 specifies the load-and-set 1 bit operation, addr[25:21] is "b", the bit identifier, and mem_addr[19:0] specifies the address offset into the peripheral space based at 0x4000_0000. The "-" indicates an address bit "don't care". The decorated Load-and-Set 1 Bit read operation is defined in the following pseudo-code as: rdata = iolas1<sz>(accessAddress) // decorated load-and-set 1 tmp = mem[accessAddress & 0xE00FFFFF, size] mask = 1 << b rdata = (tmp & mask) >> b tmp = tmp | mask mem[accessAddress & 0xE00FFFFF, size] = tmp // // // // // memory read generate bit mask read data returned to core modify memory write The cycle-by-cycle BME operations are detailed in the following table. Table 17-6. Cycle definitions of decorated load: load-and-set 1-bit Pipeline Stage Cycle x BME AHB_ap Forward addr to memory; Decode decoration; Capture address, attributes BME AHB_dp <previous> x+1 x+2 Recirculate captured addr + attr to memory as slave_wt <next> Perform memory read; Form bit mask; Extract bit from rdata; Form (rdata | mask) and capture destination data in register Return extracted bit to master; Perform write sending registered data to memory KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 259 Functional Description 17.4.2.3 Decorated Load Unsigned Bit Field Extract (UBFX) This command extracts a bit field defined by LSB position (b) and the bit field width (w +1) from the memory "container" defined by the access size associated with the load instruction using a 2-cycle read sequence. The extracted bit field from the memory address is right justified and zero filled in the operand returned to the core. Recall this is the only decorated operation that does not perform a memory write, that is, UBFX only performs a read. The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit) or word (32-bit). Note for the word sized operation, the maximum bit field width is 16 bits. The use of a UBFX operation is recommended to extract a single bit from a peripheral. For this case, the w field is simply set to 0, indicating a bit field width of 1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - 9 8 7 ioubfxb 0 1 0 1 - - b b b w w w mem_addr ioubfxh 0 1 0 1 - b b b b w w w w mem_addr ioubfxw 0 1 0 1 b b b b b w w w w mem_addr 6 5 4 3 2 1 0 0 0 0 Figure 17-11. Decorated load address: unsigned bit field extract where addr[28] = 1 specifies the unsigned bit field extract operation, addr[27:23] is "b", the LSB identifier, addr[22:19] is "w", the bit field width minus 1 identifier, and mem_addr[18:0] specifies the address offset into the peripheral space based at 0x4000_0000. The "-" indicates an address bit "don't care". Note, unlike the other decorated load operations, UBFX uses addr[19] as the least significant bit in the "w" specifier and not as an address bit. The decorated unsigned bit field extract read operation is defined in the following pseudo-code as: rdata = ioubfx<sz>(accessAddress) tmp = mem[accessAddress & 0xE007FFFF, size] mask = ((1 << (w+1)) - 1) << b rdata = (tmp & mask) >> b // unsigned bit field extract // memory read // generate bit mask // read data returned to core Like the BFI operation, when the starting bit position plus the field width exceeds the container size, only part of the source bit field is extracted from the destination memory location. Stated differently, if (b + w+1) > container_width, only the low-order "container_width - b" bits are actually extracted. The cycle-by-cycle BME operations are detailed in the following table. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 260 Freescale Semiconductor, Inc. Chapter 17 Bit Manipulation Engine (BME) Table 17-7. Cycle definitions of decorated load: unsigned bit field extract Pipeline Stage Cycle x BME AHB_ap Forward addr to memory; Decode decoration; Capture address, attributes BME AHB_dp <previous> x+1 Idle AHB address phase x+2 <next> Perform memory read; Form Logically right shift registered bit mask; Form (rdata & mask) data; Return justified rdata to and capture destination data master in register 17.4.3 Additional Details on Decorated Addresses and GPIO Accesses As previously noted, the peripheral address space occupies a 516 KB region: 512 KB based at 0x4000_0000 plus a 4 KB space based at 0x400F_F000 for GPIO accesses. This memory layout provides compatibility with the Kinetis K Family and provides 129 address "slots", each 4 KB in size. The GPIO address space is multiply-mapped by the hardware: it appears at the "standard" system address 0x400F_F000 and is physically located in the address slot corresponding to address 0x4000_F000. Decorated loads and stores create a slight complication involving accesses to the GPIO. Recall the use of address[19] varies by decorated operation; for AND, OR, XOR, LAC1 and LAS1, this bit functions as a true address bit, while for BFI and UBFX, this bit defines the least significant bit of the "w" bit field specifier. As a result, undecorated GPIO references and decorated AND, OR, XOR, LAC1 and LAS1 operations can use the standard 0x400F_F000 base address, while decorated BFI and UBFX operations must use the alternate 0x4000_F000 base address. Another implementation can simply use 0x400F_F000 as the base address for all undecorated GPIO accesses and 0x4000_F000 as the base address for all decorated accesses. Both implementations are supported by the hardware. Table 17-8. Decorated peripheral and GPIO address details Peripheral address space Description 0x4000_0000 - 0x4007_FFFF Undecorated (normal) peripheral accesses 0x4008_0000 - 0x400F_EFFF Illegal addresses; attempted references are aborted and error terminated 0x400F_F000 - 0x400F_FFFF Undecorated (normal) GPIO accesses using standard address 0x4010_0000 - 0x43FF_FFFF Illegal addresses; attempted references are aborted and error terminated Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 261 Application Information Table 17-8. Decorated peripheral and GPIO address details (continued) Peripheral address space Description 0x4400_0000 - 0x4FFF_FFFF Decorated AND, OR, XOR, LAC1, LAS1 references to peripherals and GPIO based at either 0x4000_F000 or 0x400F_F000 0x5000_0000 - 0x5FFF_FFFF Decorated BFI, UBFX references to peripherals and GPIO only based at 0x4000_F000 17.5 Application Information In this section, GNU assembler macros with C expression operands are presented as examples of the required instructions to perform decorated operations. This section specifically presents a partial bme.h file defining the assembly language expressions for decorated logical stores: AND, OR and XOR. Comparable functions for BFI and the decorated loads are more complex and available in the complete BME header file. These macros use the same function names presented in Functional Description. #define IOANDW(ADDR,WDATA) \ __asm("ldr r3, =(1<<26);" \ "orr r3, %[addr];" \ "mov r2, %[wdata];" \ "str r2, [r3];" \ :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOANDH(ADDR,WDATA) \ __asm("ldr r3, =(1<<26);" \ "orr r3, %[addr];" \ "mov r2, %[wdata];" \ "strh r2, [r3];" \ :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOANDB(ADDR,WDATA) \ __asm("ldr r3, =(1<<26);" \ "orr r3, %[addr];" \ "mov r2, %[wdata];" \ "strb r2, [r3];" \ :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOORW(ADDR,WDATA) \ __asm("ldr r3, =(1<<27);" \ "orr r3, %[addr];" \ "mov r2, %[wdata];" \ "str r2, [r3];" \ :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOORH(ADDR,WDATA) \ __asm("ldr r3, =(1<<27);" \ "orr r3, %[addr];" \ "mov r2, %[wdata];" \ "strh r2, [r3];" \ :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOORB(ADDR,WDATA) __asm("ldr r3, =(1<<27);" "orr r3, %[addr];" "mov r2, %[wdata];" "strb r2, [r3];" \ \ \ \ \ KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 262 Freescale Semiconductor, Inc. Chapter 17 Bit Manipulation Engine (BME) :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOXORW(ADDR,WDATA) \ __asm("ldr r3, =(3<<26);" \ "orr r3, %[addr];" \ "mov r2, %[wdata];" \ "str r2, [r3];" \ :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOXORH(ADDR,WDATA) \ __asm("ldr r3, =(3<<26);" \ "orr r3, %[addr];" \ "mov r2, %[wdata];" \ "strh r2, [r3];" \ :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOXORB(ADDR,WDATA) \ __asm("ldr r3, =(3<<26);" \ "orr r3, %[addr];" \ "mov r2, %[wdata];" \ "strb r2, [r3];" \ :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 263 Application Information KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 264 Freescale Semiconductor, Inc. Chapter 18 Miscellaneous Control Module (MCM) 18.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions. 18.1.1 Features The MCM includes the following features: * Program-visible information on the platform configuration * Crossbar master arbitration policy selection * Flash controller speculation buffer and cache configurations 18.2 Memory map/register descriptions The memory map and register descriptions below describe the registers using byte addresses. MCM memory map Absolute address (hex) F000_3008 Register name Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC) Width Access (in bits) 16 Reset value Section/ page 0007h 18.2.1/266 R Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 265 Memory map/register descriptions MCM memory map (continued) Absolute address (hex) F000_300A Width Access (in bits) Register name Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC) Reset value Section/ page 16 R 0005h 18.2.2/267 F000_300C Platform Control Register (MCM_PLACR) 32 R/W 0000_0000h 18.2.3/267 F000_3040 32 R/W 0000_0000h 18.2.4/270 Compute Operation Control Register (MCM_CPO) 18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC) PLASC is a 16-bit read-only register identifying the presence/absence of bus slave connections to the device's crossbar switch. Address: F000_3000h base + 8h offset = F000_3008h Bit 15 14 13 12 Read 11 10 9 8 7 6 5 4 0 3 2 1 0 0 1 1 1 ASC Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 MCM_PLASC field descriptions Field 15-8 Reserved 7-0 ASC Description This field is reserved. This read-only field is reserved and always has the value 0. Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 1 A bus slave connection to AXBS input port n is absent A bus slave connection to AXBS input port n is present KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 266 Freescale Semiconductor, Inc. Chapter 18 Miscellaneous Control Module (MCM) 18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC) PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the device's crossbar switch. Address: F000_3000h base + Ah offset = F000_300Ah Bit 15 14 13 12 Read 11 10 9 8 7 6 5 4 0 3 2 1 0 0 1 0 1 AMC Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 MCM_PLAMC field descriptions Field 15-8 Reserved 7-0 AMC Description This field is reserved. This read-only field is reserved and always has the value 0. Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 1 A bus master connection to AXBS input port n is absent A bus master connection to AXBS input port n is present 18.2.3 Platform Control Register (MCM_PLACR) The PLACR register selects the arbitration policy for the crossbar masters and configures the flash memory controller. The speculation buffer and cache in the flash memory controller is configurable via MCM_PLACR[15:10]. The speculation buffer is enabled only for instructions after reset. It is possible to have these states for the speculation buffer: DFCS EFDS Description 0 0 Speculation buffer is on for instruction and off for data. 0 1 Speculation buffer is on for instruction and on for data. 1 X Speculation buffer is off. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 267 Memory map/register descriptions The cache in flash controller is enabled and caching both instruction and data type fetches after reset. It is possible to have these states for the cache: DFCC DFCIC DFCDA Description 0 0 0 Cache is on for both instruction and data. 0 0 1 Cache is on for instruction and off for data. 0 1 0 Cache is off for instruction and on for data. 0 1 1 Cache is off for both instruction and data. 1 X X Cache is off. Address: F000_3000h base + Ch offset = F000_300Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R ESFC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 EFDS DFCC DFCIC DFCDA 0 0 0 0 0 W Reset 0 ARB CFCC DFCS R 0 0 0 0 0 0 0 MCM_PLACR field descriptions Field 31-17 Reserved 16 ESFC Description This field is reserved. This read-only field is reserved and always has the value 0. Enable Stalling Flash Controller This field is used to enable stalling flash controller when flash is busy. 0 1 Disable stalling flash controller when flash is busy. Enable stalling flash controller when flash is busy. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 268 Freescale Semiconductor, Inc. Chapter 18 Miscellaneous Control Module (MCM) MCM_PLACR field descriptions (continued) Field 15 DFCS Description Disable Flash Controller Speculation This field is used to disable flash controller speculation. 0 1 14 EFDS Enable Flash Data Speculation This field is used to enable flash data speculation. 0 1 13 DFCC This field is used to disable flash controller cache. This field is used to disable flash controller instruction caching. 9 ARB 8-0 Reserved Enable flash controller instruction caching. Disable flash controller instruction caching. Disable Flash Controller Data Caching This field is used to disable flash controller data caching. 0 1 10 CFCC Enable flash controller cache. Disable flash controller cache. Disable Flash Controller Instruction Caching 0 1 11 DFCDA Disable flash data speculation. Enable flash data speculation. Disable Flash Controller Cache 0 1 12 DFCIC Enable flash controller speculation. Disable flash controller speculation. Enable flash controller data caching Disable flash controller data caching. Clear Flash Controller Cache Writing a 1 to this field clears the cache. Writing a 0 to this field is ignored. This field always reads as 0. Arbitration select 0 1 Fixed-priority arbitration for the crossbar masters Round-robin arbitration for the crossbar masters This field is reserved. This read-only field is reserved and always has the value 0. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 269 Memory map/register descriptions 18.2.4 Compute Operation Control Register (MCM_CPO) This register controls the Compute Operation. Address: F000_3000h base + 40h offset = F000_3040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 CPOWOI R CPOREQ 0 CPOACK Reset W Reset 0 0 0 0 0 0 0 0 0 0 MCM_CPO field descriptions Field Description 31-3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 CPOWOI Compute Operation wakeup on interrupt 1 CPOACK Compute Operation acknowledge 0 CPOREQ Compute Operation request 0 1 0 1 No effect. When set, the CPOREQ is cleared on any interrupt or exception vector fetch. Compute operation entry has not completed or compute operation exit has completed. Compute operation entry has completed or compute operation exit has not completed. This bit is auto-cleared by vector fetching if CPOWOI = 1. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 270 Freescale Semiconductor, Inc. Chapter 18 Miscellaneous Control Module (MCM) MCM_CPO field descriptions (continued) Field Description 0 1 Request is cleared. Request Compute Operation. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 271 Memory map/register descriptions KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 272 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) 19.1 Introduction Microcontrollers using the Cortex-M0+ processor core include support for a CoreSight Micro Trace Buffer to provide program trace capabilities. The proper name for this function is the CoreSight Micro Trace Buffer for the Cortex-M0+ Processor; in this document, it is simply abbreviated as the MTB. The simple program trace function creates instruction address change-of-flow data packets in a user-defined region of the system RAM. Accordingly, the system RAM controller manages requests from two sources: * AMBA-AHB reads and writes from the system bus * program trace packet writes from the processor As part of the MTB functionality, there is a DWT (Data Watchpoint and Trace) module that allows the user to define watchpoint addresses, or optionally, an address and data value, that when triggered, can be used to start or stop the program trace recording. This document details the functionality of both the MTB_RAM and MTB_DWT capabilities. 19.1.1 Overview A generic block diagram of the processor core and platform for this class of ultra low-end microcontrollers is shown as follows: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 273 Introduction Cortex-M0+ Core Dbg NVIC CM0+ Core Platform Fetch AGU Dec Rn LD/ST SHFT ALU MUL AHB Bus IO Port MTB Port 32 PRAM RAM Array RGPIO s1 m0 32 Alt-Master s2 m3 DMA_4ch m2 AXBS BME PBRIDGE Slave Peripherals s0 32 FMC NVM Array Figure 19-1. Generic Cortex-M0+ core platform block diagram As shown in the block diagram, the platform RAM (PRAM) controller connects to two input buses: * the crossbar slave port for system bus accesses * a "private execution MTB port" from the core The logical paths from the crossbar master input ports to the PRAM controller are highlighted along with the private execution trace port from the processor core. The private MTB port signals the instruction address information needed for the 64-bit program trace packets written into the system RAM. The PRAM controller output interfaces to the attached RAM array. In this document, the PRAM controller is the MTB_RAM controller. The following information is taken from the ARM CoreSight Micro Trace Buffer documentation. "The execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects the processor PC value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during exception entry. The processor can cause a trace packet to be generated for any instruction. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 274 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) The following figure shows how the execution trace information is stored in memory as a sequence of packets. 31 1 Nth destination address Nth source address Incrementing SRAM memory address 31 1 2nd destination address 2nd source address 1st destination address 1st source address 0 S A 0 S A S A Odd word address Even word address Start bit Odd word address Even word address Atom bit Figure 19-2. MTB execution trace storage format The first, lower addressed, word contains the source of the branch, the address it branched from. The value stored only records bits[31:1] of the source address, because Thumb instructions are at least halfword aligned. The least significant bit of the value is the A-bit. The A-bit indicates the atomic state of the processor at the time of the branch, and can differentiate whether the branch originated from an instruction in a program, an exception, or a PC update in Debug state. When it is zero the branch originated from an instruction, when it is one the branch originated from an exception or PC update in Debug state. This word is always stored at an even word location. The second, higher addressed word contains the destination of the branch, the address it branched to. The value stored only records bits[31:1] of the branch address. The least significant bit of the value is the S-bit. The S-bit indicates where the trace started. An Sbit value of 1 indicates where the first packet after the trace started and a value of 0 is used for other packets. Because it is possible to start and stop tracing multiple times in a trace session, the memory might contain several packets with the S-bit set to 1. This word is always stored in the next higher word in memory, an odd word address. When the A-bit is set to 1, the source address field contains the architecturally-preferred return address for the exception. For example, if an exception was caused by an SVC instruction, then the source address field contains the address of the following instruction. This is different from the case where the A-bit is set to 0. In this case, the source address contains the address of the branch instruction. For an exception return operation, two packets are generated: * The first packet has the: * Source address field set to the address of the instruction that causes the exception return, BX or POP. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 275 Introduction * Destination address field set to bits[31:1] of the EXC_RETURN value. See the ARM v6-M Architecture Reference Manual. * The A-bit set to 0. * The second packet has the: * Source address field set to bits[31:1] of the EXC_RETURN value. * Destination address field set to the address of the instruction where execution commences. * A-bit set to 1." Given the recorded change-of-flow trace packets in system RAM and the memory image of the application, a debugger can read out the data and create an instruction-byinstruction program trace. In keeping with the low area and power implementation cost design targets, the MTB trace format is less efficient than other CoreSight trace modules, for example, the ETM (Embedded Trace Macrocell). Since each branch packet is 8 bytes in size, a 1 KB block of system RAM can contain 128 branches. Using the Dhrystone 2.1 benchmark's dynamic runtime as an example, this corresponds to about 875 instructions per KB of trace RAM, or with a zero wait state memory, this corresponds to approximately 1600 processor cycles per KB. This metric is obviously very sensitive to the runtime characteristics of the user code. The MTB_DWT function (not shown in the core platform block diagram) monitors the processor address and data buses so that configurable watchpoints can be detected to trigger the appropriate response in the MTB recording. 19.1.2 Features The key features of the MTB_RAM and MTB_DWT include: * Memory controller for system RAM and Micro Trace Buffer for program trace packets * Read/write capabilities for system RAM accesses, write-only for program trace packets * Supports zero wait state response to system bus accesses when no trace data is being written * Can buffer two AHB address phases and one data write for system RAM accesses * Supports 64-bit program trace packets including source and destination instruction addresses * Program trace information in RAM available to MCU's application code or external debugger * Program trace watchpoint configuration accessible by MCU's application code or debugger * Location and size of RAM trace buffer is configured by software KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 276 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) * Two DWT comparators (addresses or address + data) provide programmable start/ stop recording * CoreSight compliant debug functionality 19.1.3 Modes of Operation The MTB_RAM and MTB_DWT functions do not support any special modes of operation. The MTB_RAM controller, as a memory-mapped device located on the platform's slave AHB system bus, responds based strictly on memory addresses for accesses to its attached RAM array. The MTB private execution bus provides program trace packet write information to the RAM controller. Both the MTB_RAM and MTB_DWT modules are memory-mapped so their programming models can be accessed. All functionality associated with the MTB_RAM and MTB_DWT modules resides in the core platform's clock domain; this includes its connections with the RAM array. 19.2 External Signal Description The MTB_RAM and MTB_DWT modules do not directly support any external interfaces. The internal interfaces includes a standard AHB bus with a 32-bit datapath width from the appropriate crossbar slave port plus the private execution trace bus from the processor core. The signals in the private execution trace bus are detailed in the following table taken from the ARM CoreSight Micro Trace Buffer documentation. The signal direction is defined as viewed by the MTB_RAM controller. Table 19-1. Private execution trace port from the core to MTB_RAM Signal Direction Description LOCKUP Input Indicates the processor is in the Lockup state. This signal is driven LOW for cycles when the processor is executing normally and driven HIGH for every cycle the processor is waiting in the Lockup state. This signal is valid on every cycle. IAESEQ Input Indicates the next instruction address in execute, IAEX, is sequential, that is nonbranching. IAEXEN Input IAEX register enable. IAEX[30:0] Input Registered address of the instruction in the execution stage, shifted right by one bit, that is, PC >> 1. ATOMIC Input Indicates the processor is performing non-instruction related activities. EDBGRQ Output Request for the processor to enter the Debug state, if enabled, and halt. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 277 Memory Map and Register Definition In addition, there are two signals formed by the MTB_DWT module and driven to the MTB_RAM controller: TSTART (trace start) and TSTOP (trace stop). These signals can be configured using the trace watchpoints to define programmable addresses and data values to affect the program trace recording state. 19.3 Memory Map and Register Definition The MTB_RAM and MTB_DWT modules each support a sparsely-populated 4 KB address space for their programming models. For each address space, there are a variety of control and configurable registers near the base address, followed by a large unused address space and finally a set of CoreSight registers to support dynamic determination of the debug configuration for the device. Accesses to the programming model follow standard ARM conventions. Taken from the ARM CoreSight Micro Trace Buffer documentation, these are: * Do not attempt to access reserved or unused address locations. Attempting to access these locations can result in UNPREDICTABLE behavior. * The behavior of the MTB is UNPREDICTABLE if the registers with UNKNOWN reset values are not programmed prior to enabling trace. * Unless otherwise stated in the accompanying text: * Do not modify reserved register bits * Ignore reserved register bits on reads * All register bits are reset to a logic 0 by a system or power-on reset * Use only word size, 32-bit, transactions to access all registers 19.3.1 MTB_RAM Memory Map MTB memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page F000_0000 MTB Position Register (MTB_POSITION) 32 R/W Undefined 19.31.1/279 F000_0004 MTB Master Register (MTB_MASTER) 32 R/W See section 19.31.2/281 F000_0008 MTB Flow Register (MTB_FLOW) 32 R/W Undefined 19.31.3/283 F000_000C MTB Base Register (MTB_BASE) 32 R Undefined 19.31.4/285 F000_0F00 32 R 0000_0000h 19.31.5/285 F000_0FA0 Claim TAG Set Register (MTB_TAGSET) 32 R 0000_0000h 19.31.6/286 F000_0FA4 Claim TAG Clear Register (MTB_TAGCLEAR) 32 R 0000_0000h 19.31.7/286 F000_0FB0 Lock Access Register (MTB_LOCKACCESS) 32 R 0000_0000h 19.31.8/287 Integration Mode Control Register (MTB_MODECTRL) Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 278 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) MTB memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page F000_0FB4 Lock Status Register (MTB_LOCKSTAT) 32 R 0000_0000h 19.31.9/287 F000_0FB8 Authentication Status Register (MTB_AUTHSTAT) 32 R 0000_0000h 19.31.10/ 288 F000_0FBC Device Architecture Register (MTB_DEVICEARCH) 32 R 4770_0A31h 19.31.11/ 289 F000_0FC8 Device Configuration Register (MTB_DEVICECFG) 32 R 0000_0000h 19.31.12/ 289 F000_0FCC Device Type Identifier Register (MTB_DEVICETYPID) 32 R 0000_0031h 19.31.13/ 290 F000_0FD0 Peripheral ID Register (MTB_PERIPHID4) 32 R See section 19.31.14/ 290 F000_0FD4 Peripheral ID Register (MTB_PERIPHID5) 32 R See section 19.31.14/ 290 F000_0FD8 Peripheral ID Register (MTB_PERIPHID6) 32 R See section 19.31.14/ 290 F000_0FDC Peripheral ID Register (MTB_PERIPHID7) 32 R See section 19.31.14/ 290 F000_0FE0 Peripheral ID Register (MTB_PERIPHID0) 32 R See section 19.31.14/ 290 F000_0FE4 Peripheral ID Register (MTB_PERIPHID1) 32 R See section 19.31.14/ 290 F000_0FE8 Peripheral ID Register (MTB_PERIPHID2) 32 R See section 19.31.14/ 290 F000_0FEC Peripheral ID Register (MTB_PERIPHID3) 32 R See section 19.31.14/ 290 F000_0FF0 Component ID Register (MTB_COMPID0) 32 R See section 19.31.15/ 291 F000_0FF4 Component ID Register (MTB_COMPID1) 32 R See section 19.31.15/ 291 F000_0FF8 Component ID Register (MTB_COMPID2) 32 R See section 19.31.15/ 291 F000_0FFC Component ID Register (MTB_COMPID3) 32 R See section 19.31.15/ 291 19.31.1 MTB Position Register (MTB_POSITION) The MTB_POSITION register is the trace write address pointer and wrap bit. This register can be modified by the explicit programming model writes. It is also automatically updated by the MTB hardware when trace packets are being recorded. The base address of the system RAM in the memory map dictates special consideration for the placement of the MTB. Consider the following guidelines: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 279 Memory Map and Register Definition For the standard configuration where the size of the MTB is 25% of the total RAM capacity, it is recommended the MTB be based at the address defined by the MTB_BASE register. The read-only MTB_BASE register is defined by the expression (0x2000_0000 (RAM_Size/4)). For this configuration, the MTB_POSITION register is initialized to (MTB_BASE & 0x0000_7FF8). If the size of the MTB is more than 25% but less than or equal to 50% of the total RAM capacity, it is recommended the MTB be based at address 0x2000_0000. In this configuration, the MTB_POSITION register is initialized to (0x2000_0000 & 0x0000_7FF8) = 0x0000_00000. Following these two suggested placements provides a full-featured circular memory buffer containing program trace packets. In the unlikely event an even larger trace buffer is required, a write-once capacity of 75% of the total RAM capacity can be based at address 0x2000_0000. The MTB_POSITION register is initialized to (0x2000_0000 & 0x0000_7FF8) = 0x0000_0000. However, this configuration cannot support operation as a circular queue and instead requires the use of the MTB_FLOW[WATERMARK] capability to automatically disable tracing or halting the processor as the number of packet writes approach the buffer capacity. See the MTB_FLOW register description for more details. Address: F000_0000h base + 0h offset = F000_0000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R POINTER W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POINTER W Reset x* x* x* x* x* x* x* 0 WRAP R x* x* x* x* x* x* x* 0 0 * Notes: * x = Undefined at reset. MTB_POSITION field descriptions Field 31-3 POINTER Description Trace Packet Address Pointer[28:0] Trace packet address pointer. Because a packet consists of two words, the POINTER field is the address of the first word of a packet. This field contains bits[31:3] of the RAM address where the next trace packet is written. Therefore, it points to an unused location and is automatically incremented. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 280 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) MTB_POSITION field descriptions (continued) Field Description A debug agent can calculate the system memory map address for the current location in the MTB using the following "generic" equation: Given mtb_size = 1 << (MTB_MASTER[MASK] + 4), systemAddress = MTB_BASE + (((MTB_POSITION & 0xFFFF_FFF8) + (mtb_size - (MTB_BASE & (mtb_size-1)))) & 0x0000_7FF8); For this device, a simpler expression also applies. See the following pseudo-code: if ((MTB_POSITION >> 13) == 0x3) systemAddress = (0x1FFF << 16) + (0x1 << 15) + (MTB_POSITION & 0x7FF8); else systemAddress = (0x2000 << 16) + (0x0 << 15) + (MTB_POSITION & 0x7FF8); NOTE: The size of the RAM is parameterized and the most significant bits of the POINTER field are RAZ/WI. For these devices, POSITION[31:15] == POSITION[POINTER[28:12]] are RAZ/WI. Therefore, the active bits in this field are POSITION[14:3] == POSITION[POINTER[11:0]]. 2 WRAP 1-0 Reserved This bit is set to 1 automatically when the POINTER value wraps as determined by the MTB_MASTER[MASK] field in the MASTER Trace Control Register. A debug agent might use the WRAP bit to determine whether the trace information above and below the pointer address is valid. This field is reserved. This read-only field is reserved and always has the value 0. 19.31.2 MTB Master Register (MTB_MASTER) The MTB_MASTER register contains the main program trace enable plus other trace controls. This register can be modified by the explicit programming model writes. MTB_MASTER[EN] and MTB_MASTER[HALTREQ] fields are also automatically updated by the MTB hardware. Before the MTB_MASTER[EN] or MTB_MASTER[TSTARTEN] bits are set to 1, software must initialize the MTB_POSITION and MTB_FLOW registers. If the MTB_FLOW[WATERMARK] field is used to stop tracing or to halt the processor, the MTB_MASTER[MASK] field must still be set to a value that prevents the MTB_POSITION[POINTER] field from wrapping before it reaches the MTB_FLOW[WATERMARK] value. NOTE The format of this mask field is different than the MTBDWT_MASKn[MASK]. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 281 Memory Map and Register Definition Address: F000_0000h base + 4h offset = F000_0004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R EN Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HALTREQ RAMPRIV SFRWPRIV TSTOPEN TSTARTEN W 0 0 1 0 0 x* x* 0 R W Reset 0 0 0 0 0 0 MASK x* x* x* * Notes: * x = Undefined at reset. MTB_MASTER field descriptions Field 31 EN Description Main trace enable bit When this bit is 1, trace data is written into the RAM memory location addressed by MTB_POSITION[POINTER]. The MTB_POSITION[POINTER] value auto increments after the trace data packet is written. The EN bit can be automatically set to 0 using the MTB_FLOW[WATERMARK] field and the MTB_FLOW[AUTOSTOP] bit. The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and the TSTART signal is HIGH. The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the TSTOP signal is HIGH. NOTE: If the EN bit is set to 0 because the MTB_FLOW[WATERMARK] field is set, then it is not automatically set to 1 if the TSTARTEN bit is 1 and the TSTART input is HIGH. In this case, tracing can only be restarted if the MTB_FLOW[WATERMARK] or MTB_POSITION[POINTER] value is changed by software. 30-10 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 9 HALTREQ Halt request bit 8 RAMPRIV RAM privilege bit 7 SFRWPRIV This bit is connected to the halt request signal of the trace logic, EDBGRQ. When HALTREQ is set to 1, the EDBFGRQ is asserted if DBGEN (invasive debug enable, one of the debug authentication interface signals) is also HIGH. The HALTREQ bit can be automatically set to 1 using the MTB_FLOW[WATERMARK] field. If this bit is 0, then user or privileged AHB read and write accesses to the RAM are permitted. If this bit is 1, then only privileged AHB read and write accesses to the RAM are permitted and user accesses are RAZ/WI. The HPROT[1] signal determines if an access is a user or privileged mode reference. Special Function Register Write Privilege bit If this bit is 0, then user or privileged AHB read and write accesses to the MTB_RAM Special Function Registers (programming model) are permitted. If this bit is 1, then only privileged write accesses are Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 282 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) MTB_MASTER field descriptions (continued) Field Description permitted; user write accesses are ignored. The HPROT[1] signal determines if an access is user or privileged. Note MTB_RAM SFR read access are not controlled by this bit and are always permitted. 6 TSTOPEN Trace stop input enable 5 TSTARTEN Trace start input enable 4-0 MASK If this bit is 1 and the TSTOP signal is HIGH, then the EN bit is set to 0. If a trace packet is being written to memory, the write is completed before tracing is stopped. If this bit is 1 and the TSTART signal is HIGH, then the EN bit is set to 1. Tracing continues until a stop condition occurs. Mask This value determines the maximum size of the trace buffer in RAM. It specifies the most-significant bit of the MTB_POSITION[POINTER] field that can be updated by automatic increment. If the trace tries to advance past this power of two, the MTB_POSITION[WRAP] bit is set to 1, the MTB_POSITION[MASK +3:3] == MTB_POSITION[POINTER[MASK:0]] bits are set to zero, and the MTB_POSITION[14:MASK+3] == MTB_POSITION[POINTER[11:MASK+1]] bits remain unchanged. This field causes the trace packet information to be stored in a circular buffer of size 2^[MASK+4] bytes, that can be positioned in memory at multiples of this size. As detailed in the MTB_POSITION description, typical "upper limits" for the MTB size are RAM_Size/4 or RAM_Size/2. Values greater than the maximum have the same effect as the maximum. 19.31.3 MTB Flow Register (MTB_FLOW) The MTB_FLOW register contains the watermark address and the autostop/autohalt control bits. If tracing is stopped using the watermark autostop feature, it cannot be restarted until software clears the watermark autostop. This can be achieved in one of the following ways: * Changing the MTB_POSITION[POINTER] field value to point to the beginning of the trace buffer, or * Setting MTB_FLOW[AUTOSTOP] = 0. A debug agent can use the MTB_FLOW[AUTOSTOP] bit to fill the trace buffer once only without halting the processor. A debug agent can use the MTB_FLOW[AUTOHALT] bit to fill the trace buffer once before causing the Cortex-M0+ processor to enter the Debug state. To enter Debug state, the Cortex-M0+ processor might have to perform additional branch type operations. Therefore, the MTB_FLOW[WATERMARK] field must be set below the final entry in the trace buffer region. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 283 Memory Map and Register Definition Address: F000_0000h base + 8h offset = F000_0008h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R WATERMARK Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 AUTOHALT AUTOSTOP W 0 x* x* R WATERMARK W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. MTB_FLOW field descriptions Field 31-3 WATERMARK 2 Reserved Description WATERMARK[28:0] This field contains an address in the same format as the MTB_POSITION[POINTER] field. When the MTB_POSITION[POINTER] matches the WATERMARK field value, actions defined by the AUTOHALT and AUTOSTOP bits are performed. This field is reserved. This read-only field is reserved and always has the value 0. 1 AUTOHALT If this bit is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then the MTB_MASTER[HALTREQ] bit is automatically set to 1. If the DBGEN signal is HIGH, the MTB asserts this halt request to the Cortex-M0+ processor by asserting the EDBGRQ signal. 0 AUTOSTOP If this bit is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then the MTB_MASTER[EN] bit is automatically set to 0. This stops tracing. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 284 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) 19.31.4 MTB Base Register (MTB_BASE) The read-only MTB_BASE Register indicates where the RAM is located in the system memory map. This register is provided to enable auto discovery of the MTB RAM location, by a debug agent and is defined by a hardware design parameter. For this device, the base address is defined by the expression: MTB_BASE[BASEADDR] = 0x2000_0000 - (RAM_Size/4) Address: F000_0000h base + Ch offset = F000_000Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BASEADDR R W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. MTB_BASE field descriptions Field Description 31-0 BASEADDR This value is defined with a hardwired signal and the expression: 0x2000_0000 - (RAM_Size/4). For example, if the total RAM capacity is 16 KB, this field is 0x1FFF_F000. 19.31.5 Integration Mode Control Register (MTB_MODECTRL) This register enables the device to switch from a functional mode, or default behavior, into integration mode. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + F00h offset = F000_0F00h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODECTRL R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTB_MODECTRL field descriptions Field 31-0 MODECTRL Description Hardwired to 0x0000_0000 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 285 Memory Map and Register Definition 19.31.6 Claim TAG Set Register (MTB_TAGSET) The Claim Tag Set Register returns the number of bits that can be set on a read, and enables individual bits to be set on a write. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FA0h offset = F000_0FA0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAGSET R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTB_TAGSET field descriptions Field Description 31-0 TAGSET Hardwired to 0x0000_0000 19.31.7 Claim TAG Clear Register (MTB_TAGCLEAR) The read/write Claim Tag Clear Register is used to read the claim status on debug resources. A read indicates the claim tag status. Writing 1 to a specific bit clears the corresponding claim tag to 0. It is hardwired to specific values used during the autodiscovery process by an external debug agent. Address: F000_0000h base + FA4h offset = F000_0FA4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAGCLEAR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTB_TAGCLEAR field descriptions Field 31-0 TAGCLEAR Description Hardwired to 0x0000_0000 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 286 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) 19.31.8 Lock Access Register (MTB_LOCKACCESS) The Lock Access Register enables a write access to component registers. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FB0h offset = F000_0FB0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKACCESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTB_LOCKACCESS field descriptions Field Description 31-0 LOCKACCESS Hardwired to 0x0000_0000 19.31.9 Lock Status Register (MTB_LOCKSTAT) The Lock Status Register indicates the status of the lock control mechanism. This register is used in conjunction with the Lock Access Register. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FB4h offset = F000_0FB4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKSTAT R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTB_LOCKSTAT field descriptions Field 31-0 LOCKSTAT Description Hardwired to 0x0000_0000 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 287 Memory Map and Register Definition 19.31.10 Authentication Status Register (MTB_AUTHSTAT) The Authentication Status Register reports the required security level and current status of the security enable bit pairs. Where functionality changes on a given security level, this change must be reported in this register. It is connected to specific signals used during the auto-discovery process by an external debug agent. MTB_AUTHSTAT[3:2] indicates if nonsecure, noninvasive debug is enabled or disabled, while MTB_AUTHSTAT[1:0] indicates the enabled/disabled state of nonsecure, invasive debug. For both 2-bit fields, 0b10 indicates the functionality is disabled and 0b11 indicates it is enabled. Address: F000_0000h base + FB8h offset = F000_0FB8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 BIT2 1 BIT0 0 0 0 0 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 MTB_AUTHSTAT field descriptions Field Description 31-4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 Reserved This read-only field is reserved and always has the value 1. 2 BIT2 1 Reserved 0 BIT0 Connected to NIDEN or DBGEN signal. This read-only field is reserved and always has the value 1. Connected to DBGEN. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 288 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) 19.31.11 Device Architecture Register (MTB_DEVICEARCH) This register indicates the device architecture. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FBCh offset = F000_0FBCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 0 0 0 1 1 0 0 0 1 DEVICEARCH R W Reset 0 1 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 MTB_DEVICEARCH field descriptions Field Description 31-0 DEVICEARCH Hardwired to 0x4770_0A31. 19.31.12 Device Configuration Register (MTB_DEVICECFG) This register indicates the device configuration. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FC8h offset = F000_0FC8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVICECFG R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTB_DEVICECFG field descriptions Field 31-0 DEVICECFG Description Hardwired to 0x0000_0000. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 289 Memory Map and Register Definition 19.31.13 Device Type Identifier Register (MTB_DEVICETYPID) This register indicates the device type ID. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FCCh offset = F000_0FCCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 DEVICETYPID R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTB_DEVICETYPID field descriptions Field Description 31-0 DEVICETYPID Hardwired to 0x0000_0031. 19.31.14 Peripheral ID Register (MTB_PERIPHIDn) These registers indicate the peripheral IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FD0h offset + (4d x i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PERIPHID R W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * See field descriptions for the reset values.x = Undefined at reset. MTB_PERIPHIDn field descriptions Field 31-0 PERIPHID Description Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 290 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) 19.31.15 Component ID Register (MTB_COMPIDn) These registers indicate the component IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FF0h offset + (4d x i), where i=0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMPID R W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * See field descriptions for the reset values.x = Undefined at reset. MTB_COMPIDn field descriptions Field 31-0 COMPID Description Component ID Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to 0x0000_00B1. 19.3.2 MTB_DWT Memory Map The MTB_DWT programming model supports a very simplified subset of the v7M debug architecture and follows the standard ARM DWT definition. MTBDWT memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page F000_1000 MTB DWT Control Register (MTBDWT_CTRL) 32 R 2F00_0000h 19.32.1/292 F000_1020 MTB_DWT Comparator Register (MTBDWT_COMP0) 32 R/W 0000_0000h 19.32.2/293 F000_1024 MTB_DWT Comparator Mask Register (MTBDWT_MASK0) 32 R/W 0000_0000h 19.32.3/294 F000_1028 MTB_DWT Comparator Function Register 0 (MTBDWT_FCT0) 32 R/W 0000_0000h 19.32.4/295 F000_1030 MTB_DWT Comparator Register (MTBDWT_COMP1) 32 R/W 0000_0000h 19.32.2/293 F000_1034 MTB_DWT Comparator Mask Register (MTBDWT_MASK1) 32 R/W 0000_0000h 19.32.3/294 F000_1038 MTB_DWT Comparator Function Register 1 (MTBDWT_FCT1) 32 R/W 0000_0000h 19.32.5/297 F000_1200 MTB_DWT Trace Buffer Control Register (MTBDWT_TBCTRL) 32 R/W 2000_0000h 19.32.6/298 F000_1FC8 Device Configuration Register (MTBDWT_DEVICECFG) 32 R 0000_0000h 19.32.7/300 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 291 Memory Map and Register Definition MTBDWT memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page F000_1FCC Device Type Identifier Register (MTBDWT_DEVICETYPID) 32 R 0000_0004h 19.32.8/300 F000_1FD0 Peripheral ID Register (MTBDWT_PERIPHID4) 32 R See section 19.32.9/301 F000_1FD4 Peripheral ID Register (MTBDWT_PERIPHID5) 32 R See section 19.32.9/301 F000_1FD8 Peripheral ID Register (MTBDWT_PERIPHID6) 32 R See section 19.32.9/301 F000_1FDC Peripheral ID Register (MTBDWT_PERIPHID7) 32 R See section 19.32.9/301 F000_1FE0 Peripheral ID Register (MTBDWT_PERIPHID0) 32 R See section 19.32.9/301 F000_1FE4 Peripheral ID Register (MTBDWT_PERIPHID1) 32 R See section 19.32.9/301 F000_1FE8 Peripheral ID Register (MTBDWT_PERIPHID2) 32 R See section 19.32.9/301 F000_1FEC Peripheral ID Register (MTBDWT_PERIPHID3) 32 R See section 19.32.9/301 F000_1FF0 Component ID Register (MTBDWT_COMPID0) 32 R See section 19.32.10/ 301 F000_1FF4 Component ID Register (MTBDWT_COMPID1) 32 R See section 19.32.10/ 301 F000_1FF8 Component ID Register (MTBDWT_COMPID2) 32 R See section 19.32.10/ 301 F000_1FFC Component ID Register (MTBDWT_COMPID3) 32 R See section 19.32.10/ 301 19.32.1 MTB DWT Control Register (MTBDWT_CTRL) The MTBDWT_CTRL register provides read-only information on the watchpoint configuration for the MTB_DWT. Address: F000_1000h base + 0h offset = F000_1000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NUMCMP R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 DWTCFGCTRL W Reset 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 MTBDWT_CTRL field descriptions Field 31-28 NUMCMP Description Number of comparators The MTB_DWT implements two comparators. 27-0 DWT configuration controls DWTCFGCTRL This field is hardwired to 0xF00_0000, disabling all the remaining DWT functionality. The specific fields and their state are: MTBDWT_CTRL[27] = NOTRCPKT = 1, trace sample and exception trace is not supported Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 292 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) MTBDWT_CTRL field descriptions (continued) Field Description MTBDWT_CTRL[26] = NOEXTTRIG = 1, external match signals are not supported MTBDWT_CTRL[25] = NOCYCCNT = 1, cycle counter is not supported MTBDWT_CTRL[24] = NOPRFCNT = 1, profiling counters are not supported MTBDWT_CTRL[22] = CYCEBTENA = 0, no POSTCNT underflow packets generated MTBDWT_CTRL[21] = FOLDEVTENA = 0, no folded instruction counter overflow events MTBDWT_CTRL[20] = LSUEVTENA = 0, no LSU counter overflow events MTBDWT_CTRL[19] = SLEEPEVTENA = 0, no sleep counter overflow events MTBDWT_CTRL[18] = EXCEVTENA = 0, no exception overhead counter events MTBDWT_CTRL[17] = CPIEVTENA = 0, no CPI counter overflow events MTBDWT_CTRL[16] = EXCTRCENA = 0, generation of exception trace disabled MTBDWT_CTRL[12] = PCSAMPLENA = 0, no periodic PC sample packets generated MTBDWT_CTRL[11:10] = SYNCTAP = 0, no synchronization packets MTBDWT_CTRL[9] = CYCTAP = 0, cycle counter is not supported MTBDWT_CTRL[8:5] = POSTINIT = 0, cycle counter is not supported MTBDWT_CTRL[4:1] = POSTPRESET = 0, cycle counter is not supported MTBDWT_CTRL[0] = CYCCNTENA = 0, cycle counter is not supported 19.32.2 MTB_DWT Comparator Register (MTBDWT_COMPn) The MTBDWT_COMPn registers provide the reference value for comparator n. Address: F000_1000h base + 20h offset + (16d x i), where i=0d to 1d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTBDWT_COMPn field descriptions Field 31-0 COMP Description Reference value for comparison If MTBDWT_COMP0 is used for a data value comparator and the access size is byte or halfword, the data value must be replicated across all appropriate byte lanes of this register. For example, if the data is a byte-sized "x" value, then COMP[31:24] = COMP[23:16] = COMP[15:8] = COMP[7:0] = "x". Likewise, if the data is a halfword-size "y" value, then COMP[31:16] = COMP[15:0] = "y". KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 293 Memory Map and Register Definition 19.32.3 MTB_DWT Comparator Mask Register (MTBDWT_MASKn) The MTBDWT_MASKn registers define the size of the ignore mask applied to the reference address for address range matching by comparator n. Note the format of this mask field is different than the MTB_MASTER[MASK]. Address: F000_1000h base + 24h offset + (16d x i), where i=0d to 1d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 MASK W Reset 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTBDWT_MASKn field descriptions Field 31-5 Reserved 4-0 MASK Description This field is reserved. This read-only field is reserved and always has the value 0. MASK The value of the ignore mask, 0-31 bits, is applied to address range matching. MASK = 0 is used to include all bits of the address in the comparison, except if MASK = 0 and the comparator is configured to watch instruction fetch addresses, address bit [0] is ignored by the hardware since all fetches must be at least halfword aligned. For MASK != 0 and regardless of watch type, address bits [x-1:0] are ignored in the address comparison. Using a mask means the comparator matches on a range of addresses, defined by the unmasked most significant bits of the address, bits [31:x]. The maximum MASK value is 24, producing a 16 Mbyte mask. An attempted write of a MASK value > 24 is limited by the MTBDWT hardware to 24. If MTBDWT_COMP0 is used as a data value comparator, then MTBDWT_MASK0 should be programmed to zero. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 294 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) 19.32.4 MTB_DWT Comparator Function Register 0 (MTBDWT_FCT0) The MTBDWT_FCTn registers control the operation of comparator n. Address: F000_1000h base + 28h offset = F000_1028h 31 30 29 28 27 26 25 0 R 24 23 22 MATCHED Bit 21 20 19 18 0 17 16 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATAVADDR0 DATAVSIZE W Reset 0 0 0 0 0 0 0 0 DATAVMATCH 0 R 0 FUNCTION 0 0 0 0 0 0 0 0 MTBDWT_FCT0 field descriptions Field 31-25 Reserved 24 MATCHED Description This field is reserved. This read-only field is reserved and always has the value 0. Comparator match If this read-only flag is asserted, it indicates the operation defined by the FUNCTION field occurred since the last read of the register. Reading the register clears this bit. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 295 Memory Map and Register Definition MTBDWT_FCT0 field descriptions (continued) Field Description 0 1 No match. Match occurred. 23-20 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 19-16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15-12 DATAVADDR0 Data Value Address 0 Since the MTB_DWT implements two comparators, the DATAVADDR0 field is restricted to values {0,1}. When the DATAVMATCH bit is asserted, this field defines the comparator number to use for linked address comparison. If MTBDWT_COMP0 is used as a data watchpoint and MTBDWT_COMP1 as an address watchpoint, DATAVADDR0 must be set. 11-10 DATAVSIZE Data Value Size For data value matching, this field defines the size of the required data comparison. 00 01 10 11 9 Reserved 8 DATAVMATCH This field is reserved. This read-only field is reserved and always has the value 0. Data Value Match The assertion of this bit enables data value comparison. For this implementation, MTBDWT_COMP0 supports address or data value comparisons; MTBDWT_COMP1 only supports address comparisons. 0 1 7-4 Reserved 3-0 FUNCTION Byte. Halfword. Word. Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. Perform address comparison. Perform data value comparison. This field is reserved. This read-only field is reserved and always has the value 0. Function Selects the action taken on a comparator match. If MTBDWT_COMP0 is used for a data value and MTBDWT_COMP1 for an address value, then MTBDWT_FCT1[FUNCTION] must be set to zero. For this configuration, MTBDWT_MASK1 can be set to a non-zero value, so the combined comparators match on a range of addresses. 0000 0100 0101 0110 0111 others Disabled. Instruction fetch. Data operand read. Data operand write. Data operand (read + write). Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 296 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) 19.32.5 MTB_DWT Comparator Function Register 1 (MTBDWT_FCT1) The MTBDWT_FCTn registers control the operation of comparator n. Since the MTB_DWT only supports data value comparisons on comparator 0, there are several fields in the MTBDWT_FCT1 register that are RAZ/WI (bits 12, 11:10, 8). Address: F000_1000h base + 38h offset = F000_1038h 31 30 29 28 27 26 25 0 R 24 23 22 21 20 MATCHED Bit 19 18 17 16 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R FUNCTION W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTBDWT_FCT1 field descriptions Field 31-25 Reserved 24 MATCHED Description This field is reserved. This read-only field is reserved and always has the value 0. Comparator match If this read-only flag is asserted, it indicates the operation defined by the FUNCTION field occurred since the last read of the register. Reading the register clears this bit. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 297 Memory Map and Register Definition MTBDWT_FCT1 field descriptions (continued) Field Description 0 1 23-4 Reserved No match. Match occurred. This field is reserved. This read-only field is reserved and always has the value 0. 3-0 FUNCTION Function Selects the action taken on a comparator match. If MTBDWT_COMP0 is used for a data value and MTBDWT_COMP1 for an address value, then MTBDWT_FCT1[FUNCTION] must be set to zero. For this configuration, MTBDWT_MASK1 can be set to a non-zero value, so the combined comparators match on a range of addresses. 0000 0100 0101 0110 0111 others Disabled. Instruction fetch. Data operand read. Data operand write. Data operand (read + write). Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. 19.32.6 MTB_DWT Trace Buffer Control Register (MTBDWT_TBCTRL) The MTBDWT_TBCTRL register defines how the watchpoint comparisons control the actual trace buffer operation. Recall the MTB supports starting and stopping the program trace based on the watchpoint comparisons signaled via TSTART and TSTOP. The watchpoint comparison signals are enabled in the MTB's control logic by setting the appropriate enable bits, MTB_MASTER[TSTARTEN, TSTOPEN]. In the event of simultaneous assertion of both TSTART and TSTOP, TSTART takes priority. Address: F000_1000h base + 200h offset = F000_1200h Bit 31 30 29 28 27 26 25 24 23 22 NUMCOMP R 21 20 19 18 17 16 0 0 0 0 0 0 0 W Reset 0 0 1 0 0 0 0 0 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 298 Freescale Semiconductor, Inc. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 1 0 ACOMP0 Bit ACOMP1 Chapter 19 Micro Trace Buffer (MTB) 0 0 0 R W Reset 0 0 0 0 0 0 0 MTBDWT_TBCTRL field descriptions Field 31-28 NUMCOMP Description Number of Comparators This read-only field specifies the number of comparators in the MTB_DWT. This implementation includes two registers. 27-2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 ACOMP1 Action based on Comparator 1 match When the MTBDWT_FCT1[MATCHED] is set, it indicates MTBDWT_COMP1 address compare has triggered and the trace buffer's recording state is changed. 0 1 0 ACOMP0 Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED]. Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED]. Action based on Comparator 0 match When the MTBDWT_FCT0[MATCHED] is set, it indicates MTBDWT_COMP0 address compare has triggered and the trace buffer's recording state is changed. The assertion of MTBDWT_FCT0[MATCHED] is caused by the following conditions: * Address match in MTBDWT_COMP0 when MTBDWT_FCT0[DATAVMATCH] = 0 * Data match in MTBDWT_COMP0 when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,0} * Data match in MTBDWT_COMP0 and address match in MTBDWT_COMP1 when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,1} 0 1 Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 299 Memory Map and Register Definition 19.32.7 Device Configuration Register (MTBDWT_DEVICECFG) This register indicates the device configuration. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_1000h base + FC8h offset = F000_1FC8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVICECFG R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTBDWT_DEVICECFG field descriptions Field Description 31-0 DEVICECFG Hardwired to 0x0000_0000. 19.32.8 Device Type Identifier Register (MTBDWT_DEVICETYPID) This register indicates the device type ID. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_1000h base + FCCh offset = F000_1FCCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 DEVICETYPID R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTBDWT_DEVICETYPID field descriptions Field 31-0 DEVICETYPID Description Hardwired to 0x0000_0004. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 300 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) 19.32.9 Peripheral ID Register (MTBDWT_PERIPHIDn) These registers indicate the peripheral IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_1000h base + FD0h offset + (4d x i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PERIPHID R W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * See field descriptions for the reset values. x = Undefined at reset. MTBDWT_PERIPHIDn field descriptions Field Description 31-0 PERIPHID Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the others to 0x0000_0000. 19.32.10 Component ID Register (MTBDWT_COMPIDn) These registers indicate the component IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_1000h base + FF0h offset + (4d x i), where i=0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMPID R W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * See field descriptions for the reset values.x = Undefined at reset. MTBDWT_COMPIDn field descriptions Field 31-0 COMPID Description Component ID Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to 0x0000_00B1. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 301 Memory Map and Register Definition 19.3.3 System ROM Memory Map The System ROM Table registers are also mapped into a sparsely-populated 4 KB address space. For core configurations like that supported by Cortex-M0+, ARM recommends that a debugger identifies and connects to the debug components using the CoreSight debug infrastructure. ARM recommends that a debugger follows the flow as shown in the following figure to discover the components in the CoreSight debug infrastructure. In this case a debugger reads the peripheral and component ID registers for each CoreSight component in the CoreSight system. Figure 19-56. CoreSight discovery process ROM memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page F000_2000 Entry (ROM_ENTRY0) 32 R See section 19.33.1/303 F000_2004 Entry (ROM_ENTRY1) 32 R See section 19.33.1/303 F000_2008 Entry (ROM_ENTRY2) 32 R See section 19.33.1/303 F000_200C End of Table Marker Register (ROM_TABLEMARK) 32 R 0000_0000h 19.33.2/304 F000_2FCC System Access Register (ROM_SYSACCESS) 32 R 0000_0001h 19.33.3/304 F000_2FD0 Peripheral ID Register (ROM_PERIPHID4) 32 R See section 19.33.4/305 F000_2FD4 Peripheral ID Register (ROM_PERIPHID5) 32 R See section 19.33.4/305 F000_2FD8 Peripheral ID Register (ROM_PERIPHID6) 32 R See section 19.33.4/305 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 302 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) ROM memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page F000_2FDC Peripheral ID Register (ROM_PERIPHID7) 32 R See section 19.33.4/305 F000_2FE0 Peripheral ID Register (ROM_PERIPHID0) 32 R See section 19.33.4/305 F000_2FE4 Peripheral ID Register (ROM_PERIPHID1) 32 R See section 19.33.4/305 F000_2FE8 Peripheral ID Register (ROM_PERIPHID2) 32 R See section 19.33.4/305 F000_2FEC Peripheral ID Register (ROM_PERIPHID3) 32 R See section 19.33.4/305 F000_2FF0 Component ID Register (ROM_COMPID0) 32 R See section 19.33.5/305 F000_2FF4 Component ID Register (ROM_COMPID1) 32 R See section 19.33.5/305 F000_2FF8 Component ID Register (ROM_COMPID2) 32 R See section 19.33.5/305 F000_2FFC Component ID Register (ROM_COMPID3) 32 R See section 19.33.5/305 19.33.1 Entry (ROM_ENTRYn) The System ROM Table begins with "n" relative 32-bit addresses, one for each debug component present in the device and terminating with an all-zero value signaling the end of the table at the "n+1"-th value. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_2000h base + 0h offset + (4d x i), where i=0d to 2d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENTRY R W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * See field descriptions for reset values.x = Undefined at reset. ROM_ENTRYn field descriptions Field 31-0 ENTRY Description ENTRY Entry 0 (MTB) is hardwired to 0xFFFF_E003; Entry 1 (MTBDWT) to 0xFFFF_F003; Entry 2 (CM0+ ROM Table) to 0xF00F_D003. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 303 Memory Map and Register Definition 19.33.2 End of Table Marker Register (ROM_TABLEMARK) This register indicates end of table marker. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_2000h base + Ch offset = F000_200Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARK R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROM_TABLEMARK field descriptions Field Description 31-0 MARK Hardwired to 0x0000_0000 19.33.3 System Access Register (ROM_SYSACCESS) This register indicates system access. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_2000h base + FCCh offset = F000_2FCCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SYSACCESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROM_SYSACCESS field descriptions Field 31-0 SYSACCESS Description Hardwired to 0x0000_0001 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 304 Freescale Semiconductor, Inc. Chapter 19 Micro Trace Buffer (MTB) 19.33.4 Peripheral ID Register (ROM_PERIPHIDn) These registers indicate the peripheral IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_2000h base + FD0h offset + (4d x i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PERIPHID R W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * See field descriptions for reset values.x = Undefined at reset. ROM_PERIPHIDn field descriptions Field Description 31-0 PERIPHID Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the others to 0x0000_0000. 19.33.5 Component ID Register (ROM_COMPIDn) These registers indicate the component IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_2000h base + FF0h offset + (4d x i), where i=0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMPID R W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * See field descriptions for reset values.x = Undefined at reset. ROM_COMPIDn field descriptions Field 31-0 COMPID Description Component ID Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0010; ID2 to 0x0000_0005; ID3 to 0x0000_00B1. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 305 Memory Map and Register Definition KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 306 Freescale Semiconductor, Inc. Chapter 20 Crossbar Switch Lite (AXBS-Lite) 20.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. This chapter provides information on the layout, configuration, and programming of the crossbar switch. The crossbar switch connects bus masters and bus slaves using a crossbar switch structure. This structure allows up to four bus masters to access different bus slaves simultaneously, while providing arbitration among the bus masters when they access the same slave. 20.1.1 Features The crossbar switch includes these features: * Symmetric crossbar bus switch implementation * Allows concurrent accesses from different masters to different slaves * 32-bit data bus * Operation at a 1-to-1 clock frequency with the bus masters * Programmable configuration for fixed-priority or round-robin slave port arbitration 20.2 Memory Map / Register Definition This crossbar switch is designed for minimal gate count. It, therefore, has no memorymapped configuration registers. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 307 Functional Description 20.3 Functional Description 20.3.1 General operation When a master accesses the crossbar switch the access is immediately taken. If the targeted slave port of the access is available, then the access is immediately presented on the slave port. Single-clock or zero-wait-state accesses are possible through the crossbar. If the targeted slave port of the access is busy or parked on a different master port, the requesting master simply sees wait states inserted until the targeted slave port can service the master's request. The latency in servicing the request depends on each master's priority level and the responding slave's access time. Because the crossbar switch appears to be just another slave to the master device, the master device has no knowledge of whether it actually owns the slave port it is targeting. While the master does not have control of the slave port it is targeting, it simply waits. A master is given control of the targeted slave port only after a previous access to a different slave port completes, regardless of its priority on the newly targeted slave port. This prevents deadlock from occurring when: * A higher priority master has: * An outstanding request to one slave port that has a long response time and * A pending access to a different slave port, and * A lower priority master is also making a request to the same slave port as the pending access of the higher priority master. After the master has control of the slave port it is targeting, the master remains in control of the slave port until it relinquishes the slave port by running an IDLE cycle or by targeting a different slave port for its next access. The master can also lose control of the slave port if another higher-priority master makes a request to the slave port. The crossbar terminates all master IDLE transfers, as opposed to allowing the termination to come from one of the slave buses. Additionally, when no master is requesting access to a slave port, the crossbar drives IDLE transfers onto the slave bus, even though a default master may be granted access to the slave port. When a slave bus is being idled by the crossbar, it remains parked with the last master to use the slave port. This is done to save the initial clock of arbitration delay that otherwise would be seen if the master had to arbitrate to gain control of the slave port. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 308 Freescale Semiconductor, Inc. Chapter 20 Crossbar Switch Lite (AXBS-Lite) 20.3.2 Arbitration The crossbar switch supports two arbitration algorithms: * Fixed priority * Round robin The selection of the global slave port arbitration is controlled by MCM_PLACR[ARB]. For fixed priority, set ARB to 0. For round robin, set ARB to 1. This arbitration setting applies to all slave ports. 20.3.2.1 Arbitration During Undefined Length Bursts All lengths of burst accesses lock out arbitration until the last beat of the burst. 20.3.2.2 Fixed-priority operation When operating in fixed-priority mode, each master is assigned a unique priority level with the highest numbered master having the highest priority (master 1 has lower priority than master 3). If two masters request access to the same slave port, the master with the highest priority gains control over the slave port. NOTE In this arbitration mode, a higher-priority master can monopolize a slave port, preventing accesses from any lowerpriority master to the port. When a master makes a request to a slave port, the slave port checks whether the new requesting master's priority level is higher than that of the master that currently has control over the slave port, unless the slave port is in a parked state. The slave port performs an arbitration check at every clock edge to ensure that the proper master, if any, has control of the slave port. The following table describes possible scenarios based on the requesting master port: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 309 Initialization/application information Table 20-1. How AXBS grants control of a slave port to a master When Then AXBS grants control to the requesting master Both of the following are true: At the next clock edge * The current master is not running a transfer. * The new requesting master's priority level is higher than that of the current master. The requesting master's priority level is lower than the current At the conclusion of one of the following cycles: master. * An IDLE cycle * A non-IDLE cycle to a location other than the current slave port 20.3.2.3 Round-robin priority operation When operating in round-robin mode, each master is assigned a relative priority based on the master port number. This relative priority is compared to the master port number (ID) of the last master to perform a transfer on the slave bus. The highest priority requesting master becomes owner of the slave bus at the next transfer boundary. Priority is based on how far ahead the ID of the requesting master is to the ID of the last master. After granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port. The next master in line is granted access to the slave port at the next transfer boundary, or possibly on the next clock cycle if the current master has no pending access request. As an example of arbitration in round-robin mode, assume the crossbar is implemented with master ports 0, 1, 4, and 5. If the last master of the slave port was master 1, and master 0, 4, and 5 make simultaneous requests, they are serviced in the order: 4 then 5 then 0. The round-robin arbitration mode generally provides a more fair allocation of the available slave-port bandwidth (compared to fixed priority) as the fixed master priority does not affect the master selection. 20.4 Initialization/application information No initialization is required for the crossbar switch. See the AXBS section of the configuration chapter for the reset state of the arbitration scheme. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 310 Freescale Semiconductor, Inc. Chapter 21 Peripheral Bridge (AIPS-Lite) 21.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The peripheral bridge converts the crossbar switch interface to an interface that can access most of the slave peripherals on this chip. The peripheral bridge supports up to 128 peripherals, each with a 4K-byte address space. (Not all peripheral slots might be used. See the chip configuration chapter and memory map chapter for details on slot assignment.) The bridge includes separate clock enable inputs for each of the slots to accommodate slower peripherals. 21.1.1 Features Key features of the peripheral bridge are: * Supports peripheral slots with 8-, 16-, and 32-bit datapath width * Dedicated clock enables for independently configurable peripherals allow each on- or off-platform peripheral to operate at any integer-divisible speed less than or equal to the system clock frequency. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 311 Functional description 21.1.2 General operation The slave devices connected to the peripheral bridge are modules which contain a programming model of control and status registers. The system masters read and write these registers through the peripheral bridge. The peripheral bridge performs a bus protocol conversion of the master transactions and generates the following as inputs to the peripherals: * Module enables * Module addresses * Transfer attributes * Byte enables * Write data The peripheral bridge selects and captures read data from the peripheral interface and returns it to the crossbar switch. The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is allocated one or more 4-KB block(s) of the memory map. The AIPS-Lite module uses the accessed peripheral's data width to perform proper data byte lane routing; bus decomposition (bus sizing) is performed when the access size is larger than the peripheral's data width. 21.2 Functional description The peripheral bridge functions as a bus protocol translator between the crossbar switch and the slave peripheral bus. The peripheral bridge manages all transactions destined for the attached slave devices and generates select signals for modules on the peripheral bus by decoding accesses within the attached address space. By default, reads and writes on the crossbar side of the peripheral bridge take two dataphase cycles. On the IPS side, accesses complete in one cycle. If wait states are inserted by the slave peripheral, access time will be extended accordingly. 21.2.1 Access support All combinations of access size and peripheral data port width are supported. An access that is larger than the target peripheral's data width will be decomposed to multiple, smaller accesses. Bus decomposition is terminated by a transfer error caused by an access to an empty register area. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 312 Freescale Semiconductor, Inc. Chapter 22 Direct Memory Access Multiplexer (DMAMUX) 22.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. 22.1.1 Overview The direct memory access multiplexer (DMAMUX) routes DMA sources, called slots, to any of the 4 DMA channels. This process is illustrated in the following figure. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 313 Introduction DMAMUX Source #1 DMA channel #0 DMA channel #1 Source #2 Source #3 Source #x Always #1 Always #y Trigger #1 DMA channel #n Trigger #z Figure 22-1. DMAMUX block diagram 22.1.2 Features The DMAMUX module provides these features: * 6353 peripheral slots and 6 always-on slots can be routed to 4 channels. * 4 independently selectable DMA channel routers. * The first 2 channels additionally provide a trigger functionality. * Each channel router can be assigned to one of the 6353 possible peripheral DMA slots or to one of the 6 always-on slots. 22.1.3 Modes of operation The following operating modes are available: * Disabled mode KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 314 Freescale Semiconductor, Inc. Chapter 22 Direct Memory Access Multiplexer (DMAMUX) In this mode, the DMA channel is disabled. Because disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place, for example, changing the period of a DMA trigger. * Normal mode In this mode, a DMA source is routed directly to the specified DMA channel. The operation of the DMAMUX in this mode is completely transparent to the system. * Periodic Trigger mode In this mode, a DMA source may only request a DMA transfer, such as when a transmit buffer becomes empty or a receive buffer becomes full, periodically. Configuration of the period is done in the registers of the periodic interrupt timer (PIT). This mode is available only for channels 0-1. 22.2 External signal description The DMAMUX has no external pins. 22.3 Memory map/register definition This section provides a detailed description of all memory-mapped registers in the DMAMUX. DMAMUX memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_1000 Channel Configuration register (DMAMUX0_CHCFG0) 8 R/W 00h 22.3.1/315 4002_1001 Channel Configuration register (DMAMUX0_CHCFG1) 8 R/W 00h 22.3.1/315 4002_1002 Channel Configuration register (DMAMUX0_CHCFG2) 8 R/W 00h 22.3.1/315 4002_1003 Channel Configuration register (DMAMUX0_CHCFG3) 8 R/W 00h 22.3.1/315 22.3.1 Channel Configuration register (DMAMUXx_CHCFGn) Each of the DMA channels can be independently enabled/disabled and associated with one of the DMA slots (peripheral slots or always-on slots) in the system. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 315 Functional description NOTE Setting multiple CHCFG registers with the same Source value will result in unpredictable behavior. NOTE Before changing the trigger or source settings a DMA channel must be disabled via the CHCFGn[ENBL] bit. Address: 4002_1000h base + 0h offset + (1d x i), where i=0d to 3d Bit Read Write Reset 0 1 ENBL TRIG 2 0 0 3 4 5 6 7 0 0 0 SOURCE 0 0 0 DMAMUXx_CHCFGn field descriptions Field 0 ENBL Description DMA Channel Enable Enables the DMA channel. 0 1 1 TRIG DMA Channel Trigger Enable Enables the periodic trigger capability for the triggered DMA channel. 0 1 2-7 SOURCE DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. DMA channel is enabled Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in Periodic Trigger mode. DMA Channel Source (Slot) Specifies which DMA source, if any, is routed to a particular DMA channel. See your device's chip configuration details for further details about the peripherals and their slot numbers. 22.4 Functional description The primary purpose of the DMAMUX is to provide flexibility in the system's use of the available DMA channels. As such, configuration of the DMAMUX is intended to be a static procedure done during execution of the system boot code. However, if the procedure outlined in Enabling and configuring sources is followed, the configuration of the DMAMUX may be changed during the normal operation of the system. Functionally, the DMAMUX channels may be divided into two classes: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 316 Freescale Semiconductor, Inc. Chapter 22 Direct Memory Access Multiplexer (DMAMUX) * Channels which implement the normal routing functionality plus periodic triggering capability * Channels which implement only the normal routing functionality 22.4.1 DMA channels with periodic triggering capability Besides the normal routing functionality, the first 2 channels of the DMAMUX provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames, or packets at fixed intervals without the need for processor intervention. The trigger is generated by the periodic interrupt timer (PIT); as such, the configuration of the periodic triggering interval is done via configuration registers in the PIT. See the section on periodic interrupt timer for more information on this topic. Note Because of the dynamic nature of the system (due to DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed. Source #1 Source #2 Source #3 Trigger #1 Trigger #2 DMA channel #0 DMA channel #1 Source #x Trigger #4 Always #1 DMA channel #3 Always #y Figure 22-12. DMAMUX triggered channels KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 317 Functional description The DMA channel triggering capability allows the system to schedule regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor. This trigger works by gating the request from the peripheral to the DMA until a trigger event has been seen. This is illustrated in the following figure. Peripheral request Trigger DMA request Figure 22-13. DMAMUX channel triggering: normal operation After the DMA request has been serviced, the peripheral will negate its request, effectively resetting the gating mechanism until the peripheral re-asserts its request AND the next trigger event is seen. This means that if a trigger is seen, but the peripheral is not requesting a transfer, then that trigger will be ignored. This situation is illustrated in the following figure. Peripheral request Trigger DMA request Figure 22-14. DMAMUX channel triggering: ignored trigger This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful for two types of situations: * Periodically polling external devices on a particular bus As an example, the transmit side of an SPI is assigned to a DMA channel with a trigger, as described above. After it has been set up, the SPI will request DMA transfers, presumably from memory, as long as its transmit buffer is empty. By using a trigger on this channel, the SPI transfers can be automatically performed every 5s (as an example). On the receive side of the SPI, the SPI and DMA can be configured to transfer receive data into memory, effectively implementing a method to periodically read data from external devices and transfer the results into memory without processor intervention. * Using the GPIO ports to drive or sample waveforms KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 318 Freescale Semiconductor, Inc. Chapter 22 Direct Memory Access Multiplexer (DMAMUX) By configuring the DMA to transfer data to one or more GPIO ports, it is possible to create complex waveforms using tabular data stored in on-chip memory. Conversely, using the DMA to periodically transfer data from one or more GPIO ports, it is possible to sample complex waveforms and store the results in tabular form in onchip memory. A more detailed description of the capability of each trigger, including resolution, range of values, and so on, may be found in the periodic interrupt timer section. 22.4.2 DMA channels with no triggering capability The other channels of the DMAMUX provide the normal routing functionality as described in Modes of operation. 22.4.3 Always-enabled DMA sources In addition to the peripherals that can be used as DMA sources, there are 6 additional DMA sources that are always enabled. Unlike the peripheral DMA sources, where the peripheral controls the flow of data during DMA transfers, the sources that are always enabled provide no such "throttling" of the data transfers. These sources are most useful in the following cases: * Performing DMA transfers to/from GPIO--Moving data from/to one or more GPIO pins, either unthrottled (that is as fast as possible), or periodically (using the DMA triggering capability). * Performing DMA transfers from memory to memory--Moving data from memory to memory, typically as fast as possible, sometimes with software activation. * Performing DMA transfers from memory to the external bus, or vice-versa--Similar to memory to memory transfers, this is typically done as quickly as possible. * Any DMA transfer that requires software activation--Any DMA transfer that should be explicitly started by software. In cases where software should initiate the start of a DMA transfer, an always-enabled DMA source can be used to provide maximum flexibility. When activating a DMA channel via software, subsequent executions of the minor loop require that a new start event be sent. This can either be a new software activation, or a transfer request from the DMA channel MUX. The options for doing this are: * Transfer all data in a single minor loop. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 319 Initialization/application information By configuring the DMA to transfer all of the data in a single minor loop (that is, major loop counter = 1), no reactivation of the channel is necessary. The disadvantage to this option is the reduced granularity in determining the load that the DMA transfer will impose on the system. For this option, the DMA channel must be disabled in the DMA channel MUX. * Use explicit software reactivation. In this option, the DMA is configured to transfer the data using both minor and major loops, but the processor is required to reactivate the channel by writing to the DMA registers after every minor loop. For this option, the DMA channel must be disabled in the DMA channel MUX. * Use an always-enabled DMA source. In this option, the DMA is configured to transfer the data using both minor and major loops, and the DMA channel MUX does the channel reactivation. For this option, the DMA channel should be enabled and pointing to an "always enabled" source. Note that the reactivation of the channel can be continuous (DMA triggering is disabled) or can use the DMA triggering capability. In this manner, it is possible to execute periodic transfers of packets of data from one source to another, without processor intervention. 22.5 Initialization/application information This section provides instructions for initializing the DMA channel MUX. 22.5.1 Reset The reset state of each individual bit is shown in Memory map/register definition. In summary, after reset, all channels are disabled and must be explicitly enabled before use. 22.5.2 Enabling and configuring sources To enable a source with periodic triggering: 1. Determine with which DMA channel the source will be associated. Note that only the first 2 DMA channels have periodic triggering capability. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 320 Freescale Semiconductor, Inc. Chapter 22 Direct Memory Access Multiplexer (DMAMUX) 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point. 4. Configure the corresponding timer. 5. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are set. NOTE The following is an example. See chip configuration section for the number of this device's DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 2, with periodic triggering capability: 1. Write 0x00 to CHCFG2 (base address + 0x02). 2. Configure channel 2 in the DMA, including enabling the channel. 3. Configure a timer for the desired trigger interval. 4. Write 0xC5 to CHCFG2 (base address + 0x02). The following code example illustrates steps 1 and 4 above: In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only /* Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG0 = (volatile unsigned volatile unsigned char *CHCONFIG1 = (volatile unsigned volatile unsigned char *CHCONFIG2 = (volatile unsigned volatile unsigned char *CHCONFIG3 = (volatile unsigned volatile unsigned char *CHCONFIG4 = (volatile unsigned volatile unsigned char *CHCONFIG5 = (volatile unsigned volatile unsigned char *CHCONFIG6 = (volatile unsigned volatile unsigned char *CHCONFIG7 = (volatile unsigned volatile unsigned char *CHCONFIG8 = (volatile unsigned volatile unsigned char *CHCONFIG9 = (volatile unsigned volatile unsigned char *CHCONFIG10= (volatile unsigned volatile unsigned char *CHCONFIG11= (volatile unsigned volatile unsigned char *CHCONFIG12= (volatile unsigned volatile unsigned char *CHCONFIG13= (volatile unsigned volatile unsigned char *CHCONFIG14= (volatile unsigned volatile unsigned char *CHCONFIG15= (volatile unsigned ! */ char char char char char char char char char char char char char char char char *) *) *) *) *) *) *) *) *) *) *) *) *) *) *) *) (DMAMUX_BASE_ADDR+0x0000); (DMAMUX_BASE_ADDR+0x0001); (DMAMUX_BASE_ADDR+0x0002); (DMAMUX_BASE_ADDR+0x0003); (DMAMUX_BASE_ADDR+0x0004); (DMAMUX_BASE_ADDR+0x0005); (DMAMUX_BASE_ADDR+0x0006); (DMAMUX_BASE_ADDR+0x0007); (DMAMUX_BASE_ADDR+0x0008); (DMAMUX_BASE_ADDR+0x0009); (DMAMUX_BASE_ADDR+0x000A); (DMAMUX_BASE_ADDR+0x000B); (DMAMUX_BASE_ADDR+0x000C); (DMAMUX_BASE_ADDR+0x000D); (DMAMUX_BASE_ADDR+0x000E); (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include "registers.h" : : *CHCONFIG2 = 0x00; *CHCONFIG2 = 0xC5; To enable a source without periodic triggering: 1. Determine with which DMA channel the source will be associated. Note that only the first 2 DMA channels have periodic triggering capability. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 321 Initialization/application information 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point. 4. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that CHCFG[ENBL] is set while CHCFG[TRIG] is cleared. NOTE The following is an example. See chip configuration section for the number of this device's DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 2, with no periodic triggering capability: 1. Write 0x00 to CHCFG2 (base address + 0x02). 2. Configure channel 2 in the DMA, including enabling the channel. 3. Write 0x85 to CHCFG2 (base address + 0x02). The following code example illustrates steps 1 and 3 above: In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only /* Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG0 = (volatile unsigned volatile unsigned char *CHCONFIG1 = (volatile unsigned volatile unsigned char *CHCONFIG2 = (volatile unsigned volatile unsigned char *CHCONFIG3 = (volatile unsigned volatile unsigned char *CHCONFIG4 = (volatile unsigned volatile unsigned char *CHCONFIG5 = (volatile unsigned volatile unsigned char *CHCONFIG6 = (volatile unsigned volatile unsigned char *CHCONFIG7 = (volatile unsigned volatile unsigned char *CHCONFIG8 = (volatile unsigned volatile unsigned char *CHCONFIG9 = (volatile unsigned volatile unsigned char *CHCONFIG10= (volatile unsigned volatile unsigned char *CHCONFIG11= (volatile unsigned volatile unsigned char *CHCONFIG12= (volatile unsigned volatile unsigned char *CHCONFIG13= (volatile unsigned volatile unsigned char *CHCONFIG14= (volatile unsigned volatile unsigned char *CHCONFIG15= (volatile unsigned ! */ char char char char char char char char char char char char char char char char *) *) *) *) *) *) *) *) *) *) *) *) *) *) *) *) (DMAMUX_BASE_ADDR+0x0000); (DMAMUX_BASE_ADDR+0x0001); (DMAMUX_BASE_ADDR+0x0002); (DMAMUX_BASE_ADDR+0x0003); (DMAMUX_BASE_ADDR+0x0004); (DMAMUX_BASE_ADDR+0x0005); (DMAMUX_BASE_ADDR+0x0006); (DMAMUX_BASE_ADDR+0x0007); (DMAMUX_BASE_ADDR+0x0008); (DMAMUX_BASE_ADDR+0x0009); (DMAMUX_BASE_ADDR+0x000A); (DMAMUX_BASE_ADDR+0x000B); (DMAMUX_BASE_ADDR+0x000C); (DMAMUX_BASE_ADDR+0x000D); (DMAMUX_BASE_ADDR+0x000E); (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include "registers.h" : : *CHCONFIG2 = 0x00; *CHCONFIG2 = 0x85; To disable a source: A particular DMA source may be disabled by not writing the corresponding source value into any of the CHCFG registers. Additionally, some module-specific configuration may be necessary. See the appropriate section for more details. To switch the source of a DMA channel: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 322 Freescale Semiconductor, Inc. Chapter 22 Direct Memory Access Multiplexer (DMAMUX) 1. Disable the DMA channel in the DMA and re-configure the channel for the new source. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel. 3. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are set. To switch DMA channel 8 from source #5 transmit to source #7 transmit: 1. In the DMA configuration registers, disable DMA channel 8 and reconfigure it to handle the transfers to peripheral slot 7. This example assumes channel 8 doesn't have triggering capability. 2. Write 0x00 to CHCFG8 (base address + 0x08). 3. Write 0x87 to CHCFG8 (base address + 0x08). (In this example, setting CHCFG[TRIG] would have no effect, due to the assumption that channel 8 does not support the periodic triggering functionality). The following code example illustrates steps 2 and 3 above: In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only /* Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG0 = (volatile unsigned volatile unsigned char *CHCONFIG1 = (volatile unsigned volatile unsigned char *CHCONFIG2 = (volatile unsigned volatile unsigned char *CHCONFIG3 = (volatile unsigned volatile unsigned char *CHCONFIG4 = (volatile unsigned volatile unsigned char *CHCONFIG5 = (volatile unsigned volatile unsigned char *CHCONFIG6 = (volatile unsigned volatile unsigned char *CHCONFIG7 = (volatile unsigned volatile unsigned char *CHCONFIG8 = (volatile unsigned volatile unsigned char *CHCONFIG9 = (volatile unsigned volatile unsigned char *CHCONFIG10= (volatile unsigned volatile unsigned char *CHCONFIG11= (volatile unsigned volatile unsigned char *CHCONFIG12= (volatile unsigned volatile unsigned char *CHCONFIG13= (volatile unsigned volatile unsigned char *CHCONFIG14= (volatile unsigned volatile unsigned char *CHCONFIG15= (volatile unsigned ! */ char char char char char char char char char char char char char char char char *) *) *) *) *) *) *) *) *) *) *) *) *) *) *) *) (DMAMUX_BASE_ADDR+0x0000); (DMAMUX_BASE_ADDR+0x0001); (DMAMUX_BASE_ADDR+0x0002); (DMAMUX_BASE_ADDR+0x0003); (DMAMUX_BASE_ADDR+0x0004); (DMAMUX_BASE_ADDR+0x0005); (DMAMUX_BASE_ADDR+0x0006); (DMAMUX_BASE_ADDR+0x0007); (DMAMUX_BASE_ADDR+0x0008); (DMAMUX_BASE_ADDR+0x0009); (DMAMUX_BASE_ADDR+0x000A); (DMAMUX_BASE_ADDR+0x000B); (DMAMUX_BASE_ADDR+0x000C); (DMAMUX_BASE_ADDR+0x000D); (DMAMUX_BASE_ADDR+0x000E); (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include "registers.h" : : *CHCONFIG8 = 0x00; *CHCONFIG8 = 0x87; KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 323 Initialization/application information KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 324 Freescale Semiconductor, Inc. Chapter 23 DMA Controller Module 23.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. This chapter describes the direct memory access (DMA) controller module. It provides an overview of the module and describes in detail its signals and programming model. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail. Note The designation n is used throughout this section to refer to registers or signals associated with one of the four identical DMA channels: DMA0, DMA1, DMA2, or DMA3. 23.1.1 Overview The DMA controller module enables fast transfers of data, providing an efficient way to move blocks of data with minimal processor interaction. The DMA module, shown in the following figure, has four channels that allow 8-bit, 16-bit, or 32-bit data transfers. Each channel has a dedicated source address register (SARn), destination address register (DARn), status register (DSRn), byte count register (BCRn), and control register (DCRn). Collectively, the combined program-visible registers associated with each channel define a transfer control descriptor (TCD). All transfers are dual address, moving data from a source memory location to a destination memory location with the module operating as a 32-bit bus master connected to the system bus. The programming model is accessed through a 32-bit connection with the slave peripheral bus. DMA data transfers may be explicitly initiated by software or by peripheral hardware requests. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 325 Introduction The following figure is a simplified block diagram of the 4-channel DMA controller. DREQ3 DREQ0 DREQ1 DREQ2 DACK0 DACK1 DACK2 DACK3 Channel 0 Channel 1 Channel 2 Channel 3 Slave Peripheral Bus SAR0 SAR1 SAR2 SAR3 DAR0 DAR1 DAR2 DAR3 DSR0 DSR1 DSR2 DSR3 BCR0 BCR1 BCR2 BCR3 DCR0 DCR1 DCR2 DCR3 Channel Requests Channel Attributes Channel Enables System Bus Address MUX MUX Control SysBus Interface Data Path Read Data Bus Interrupts System Bus Size Current Master Attributes Arbitraton/ Control Data Path Control SysBus Interface Addr + Attr Registered Addr Phase Bus Signals Write Data Bus Figure 23-1. 4-Channel DMA Block Diagram The terms peripheral request and DREQ refer to a DMA request from one of the on-chip peripherals or package pins. The DMA provides hardware handshake signals: either a DMA acknowledge (DACK) or a done indicator back to the peripheral. 23.1.2 Features The DMA controller module features: * Four independently programmable DMA controller channels * Dual-address transfers via 32-bit master connection to the system bus * Data transfers in 8-, 16-, or 32-bit blocks KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 326 Freescale Semiconductor, Inc. Chapter 23 DMA Controller Module * Continuous-mode or cycle-steal transfers from software or peripheral initiation * Automatic hardware acknowledge/done indicator from each channel * Independent source and destination address registers * Optional modulo addressing and automatic updates of source and destination addresses * Independent transfer sizes for source and destination * Optional auto-alignment feature for source or destination accesses * Optional automatic single or double channel linking * Programming model accessed via 32-bit slave peripheral bus * Channel arbitration on transfer boundaries using fixed priority scheme 23.2 DMA Transfer Overview The DMA module can move data within system memory (including memory and peripheral devices) with minimal processor intervention, greatly improving overall system performance. The DMA module consists of four independent, functionally equivalent channels, so references to DMA in this chapter apply to any of the channels. It is not possible to address all four channels at once. As soon as a channel has been initialized, it may be started by setting DCRn[START] or a properly-selected peripheral DMA request, depending on the status of DCRn[ERQ]. The DMA controller supports dual-address transfers using its bus master connection to the system bus. The DMA channels support transfers up to 32 data bits in size and have the same memory map addressibility as the processor. * Dual-address transfers--A dual-address transfer consists of a read followed by a write and is initiated by a request using the DCRn[START] bit or by a peripheral DMA request. The read data is temporarily held in the DMA channel hardware until the write operation. Two types of single transfers occur: a read from a source address followed by a write to a destination address. See the following figure. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 327 Memory Map and Registers Control and Data Read Memory/ Peripheral DMA Write Control and Data Memory/ Peripheral Figure 23-2. Dual-Address Transfer Any operation involving a DMA channel follows the same three steps: 1. Channel initialization--The transfer control descriptor, contained in the channel registers, is loaded with address pointers, a byte-transfer count, and control information using accesses from the slave peripheral bus. 2. Data transfer--The DMA accepts requests for data transfers. Upon receipt of a request, it provides address and bus control for the transfers via its master connection to the system bus and temporary storage for the read data. The channel performs one or more source read and destination write data transfers. 3. Channel termination--Occurs after the operation is finished successfully or due to an error. The channel indicates the operation status in the channel's DSR, described in the definitions of the DMA Status Registers (DSRn) and Byte Count Registers (BCRn). 23.3 Memory Map and Registers Descriptions of each register and its bit assignments follow. Modifying DMA control registers during a transfer can result in undefined operation. The following table shows the mapping of DMA controller registers. The DMA programming model is accessed via the slave peripheral bus. The concatenation of the source and destination address registers, the status and byte count register, and the control register create a 128-bit transfer control descriptor (TCD) that defines the operation of each DMA channel. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 328 Freescale Semiconductor, Inc. Chapter 23 DMA Controller Module DMA memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4000_8100 Source Address Register (DMA_SAR0) 32 R/W 0000_0000h 23.3.1/329 4000_8104 Destination Address Register (DMA_DAR0) 32 R/W 0000_0000h 23.3.2/330 4000_8108 DMA Status Register / Byte Count Register (DMA_DSR_BCR0) 32 R/W 0000_0000h 23.3.3/331 4000_810C DMA Control Register (DMA_DCR0) 32 R/W 0000_0000h 23.3.4/333 4000_8110 Source Address Register (DMA_SAR1) 32 R/W 0000_0000h 23.3.1/329 4000_8114 Destination Address Register (DMA_DAR1) 32 R/W 0000_0000h 23.3.2/330 4000_8118 DMA Status Register / Byte Count Register (DMA_DSR_BCR1) 32 R/W 0000_0000h 23.3.3/331 4000_811C DMA Control Register (DMA_DCR1) 32 R/W 0000_0000h 23.3.4/333 4000_8120 Source Address Register (DMA_SAR2) 32 R/W 0000_0000h 23.3.1/329 4000_8124 Destination Address Register (DMA_DAR2) 32 R/W 0000_0000h 23.3.2/330 4000_8128 DMA Status Register / Byte Count Register (DMA_DSR_BCR2) 32 R/W 0000_0000h 23.3.3/331 4000_812C DMA Control Register (DMA_DCR2) 32 R/W 0000_0000h 23.3.4/333 4000_8130 Source Address Register (DMA_SAR3) 32 R/W 0000_0000h 23.3.1/329 4000_8134 Destination Address Register (DMA_DAR3) 32 R/W 0000_0000h 23.3.2/330 4000_8138 DMA Status Register / Byte Count Register (DMA_DSR_BCR3) 32 R/W 0000_0000h 23.3.3/331 4000_813C DMA Control Register (DMA_DCR3) 32 R/W 0000_0000h 23.3.4/333 23.3.1 Source Address Register (DMA_SARn) Restriction For this register: * Only 32-bit writes are allowed. 16-bit and 8-bit writes result in a bus error. * Only four values are allowed to be written to bits 31-20 of this register. A write of any other value to these bits causes a configuration error when the channel starts to execute. For more information about the configuration error, see the description of the CE field of DSR. Address: 4000_8000h base + 100h offset + (16d x i), where i=0d to 3d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 329 Memory Map and Registers DMA_SARn field descriptions Field Description 31-0 SAR Each SAR contains the byte address used by the DMA controller to read data. The SARn is typically aligned on a 0-modulo-ssize boundary--that is, on the natural alignment of the source data. Restriction: Bits 31-20 of this register must be written with one of only four allowed values. Each of these four allowed values corresponds to a valid region of the device's memory map. The allowed values are: * 0x000x_xxxx * 0x1FFx_xxxx * 0x200x_xxxx * 0x400x_xxxx After being written with one of the allowed values, bits 31-20 read back as the written value. After being written with any other value, bits 31-20 read back as an indeterminate value. 23.3.2 Destination Address Register (DMA_DARn) Restriction For this register: * Only 32-bit writes are allowed. 16-bit and 8-bit writes result in a bus error. * Only four values are allowed to be written to bits 31-20 of this register. A write of any other value to these bits causes a configuration error when the channel starts to execute. For more information about the configuration error, see the description of the CE field of DSR. Address: 4000_8000h base + 104h offset + (16d x i), where i=0d to 3d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_DARn field descriptions Field 31-0 DAR Description Each DAR contains the byte address used by the DMA controller to write data. The DARn is typically aligned on a 0-modulo-dsize boundary--that is, on the natural alignment of the destination data. Restriction: Bits 31-20 of this register must be written with one of only four allowed values. Each of these four allowed values corresponds to a valid region of the device's memory map. The allowed values are: * 0x000x_xxxx * 0x1FFx_xxxx * 0x200x_xxxx * 0x400x_xxxx KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 330 Freescale Semiconductor, Inc. Chapter 23 DMA Controller Module DMA_DARn field descriptions (continued) Field Description After being written with one of the allowed values, bits 31-20 read back as the written value. After being written with any other value, bits 31-20 read back as an indeterminate value. 23.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn) DSR and BCR are two logical registers that occupy one 32-bit address. DSRn occupies bits 31-24, and BCRn occupies bits 23-0. DSRn contains flags indicating the channel status, and BCRn contains the number of bytes yet to be transferred for a given block. On the successful completion of the write transfer, BCRn decrements by 1, 2, or 4 for 8bit, 16-bit, or 32-bit accesses, respectively. BCRn is cleared if a 1 is written to DSR[DONE]. In response to an event, the DMA controller writes to the appropriate DSRn bit. Only a write to DSRn[DONE] results in action. DSRn[DONE] is set when the block transfer is complete. When a transfer sequence is initiated and BCRn[BCR] is not a multiple of 4 or 2 when the DMA is configured for 32-bit or 16-bit transfers, respectively, DSRn[CE] is set and no transfer occurs. Bit 31 30 29 28 27 26 25 24 R 0 CE BES BED 0 REQ BSY DONE Address: 4000_8000h base + 108h offset + (16d x i), where i=0d to 3d 23 22 21 20 19 18 17 16 BCR w1c W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R BCR W Reset 0 0 0 0 0 0 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 331 Memory Map and Registers DMA_DSR_BCRn field descriptions Field 31 Reserved 30 CE Description This field is reserved. This read-only field is reserved and always has the value 0. Configuration error Any of the following conditions causes a configuration error: * BCR, SAR, or DAR does not match the requested transfer size. * A value greater than 0F_FFFFh is written to BCR. * Bits 31-20 of SAR or DAR are written with a value other than one of the allowed values. See SAR and DAR. * SSIZE or DSIZE is set to an unsupported value. * BCR equals 0 when the DMA receives a start condition. CE is cleared at hardware reset or by writing a 1 to the DONE bit. 0 1 29 BES Bus error on source BES is cleared at hardware reset or by writing a 1 to the DONE bit. 0 1 28 BED No bus error occurred. The DMA channel terminated with a bus error during the read portion of a transfer. Bus error on destination BED is cleared at hardware reset or by writing a 1 to the DONE bit. 0 1 27 Reserved No configuration error exists. A configuration error has occurred. No bus error occurred. The DMA channel terminated with a bus error during the write portion of a transfer. This field is reserved. This read-only field is reserved and always has the value 0. 26 REQ Request 25 BSY Busy 24 DONE 0 1 0 1 DMA channel is inactive. Cleared when the DMA has finished the last transaction. BSY is set the first time the channel is enabled after a transfer is initiated. Transactions done Set when all DMA controller transactions complete as determined by transfer count, or based on error conditions. When BCR reaches zero, DONE is set when the final transfer completes successfully. DONE can also be used to abort a transfer by resetting the status bits. When a transfer completes, software must clear DONE before reprogramming the DMA. 0 1 23-0 BCR No request is pending or the channel is currently active. Cleared when the channel is selected. The DMA channel has a transfer remaining and the channel is not selected. DMA transfer is not yet complete. Writing a 0 has no effect. DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits. This field contains the number of bytes yet to be transferred for a given block. Restriction: BCR must be written with a value equal to or less than 0F_FFFFh. After being written with a value in this range, bits 23-20 of BCR read back as 1110b. A write to BCR of a value Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 332 Freescale Semiconductor, Inc. Chapter 23 DMA Controller Module DMA_DSR_BCRn field descriptions (continued) Field Description greater than 0F_FFFFh causes a configuration error when the channel starts to execute. After being written with a value in this range, bits 23-20 of BCR read back as 1111b. 23.3.4 DMA Control Register (DMA_DCRn) Address: 4000_8000h base + 10Ch offset + (16d x i), where i=0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 EINT ERQ CS AA EADREQ 0 Reserved R SINC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DINC DSIZE START SSIZE W 0 SMOD D_REQ R DMOD LINKCC LCH1 LCH2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_DCRn field descriptions Field 31 EINT Description Enable interrupt on completion of transfer Determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition. 0 1 30 ERQ No interrupt is generated. Interrupt signal is enabled. Enable peripheral request CAUTION: Be careful: a collision can occur between the START bit and D_REQ when the ERQ bit is 1. 0 1 Peripheral request is ignored. Enables peripheral request to initiate transfer. A software-initiated request (setting the START bit) is always enabled. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 333 Memory Map and Registers DMA_DCRn field descriptions (continued) Field Description 29 CS Cycle steal 28 AA Auto-align 0 1 DMA continuously makes read/write transfers until the BCR decrements to 0. Forces a single read/write transfer per request. AA and SIZE bits determine whether the source or destination is auto-aligned; that is, transfers are optimized based on the address and size. 0 1 Auto-align disabled If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. 27-25 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 24 Reserved This field is reserved. CAUTION: Must be written as zero; otherwise, undefined behavior results. 23 EADREQ Enable asynchronous DMA requests Enables the channel to support asynchronous DREQs while the MCU is in Stop mode. 0 1 22 SINC Source increment Controls whether the source address increments after each successful transfer. 0 1 21-20 SSIZE Determines the data size of the source bus cycle for the DMA controller. 32-bit 8-bit 16-bit Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) Destination increment Controls whether the destination address increments after each successful transfer. 0 1 18-17 DSIZE No change to SAR after a successful transfer. The SAR increments by 1, 2, 4 as determined by the transfer size. Source size 00 01 10 11 19 DINC Disabled Enabled No change to the DAR after a successful transfer. The DAR increments by 1, 2, 4 depending upon the size of the transfer. Destination size Determines the data size of the destination bus cycle for the DMA controller. 00 01 32-bit 8-bit Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 334 Freescale Semiconductor, Inc. Chapter 23 DMA Controller Module DMA_DCRn field descriptions (continued) Field Description 10 11 16-bit Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) 16 START Start transfer 15-12 SMOD Source address modulo 0 1 DMA inactive The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0. Defines the size of the source data circular buffer used by the DMA Controller. If enabled (SMOD is nonzero), the buffer base address is located on a boundary of the buffer size. The value of this boundary is based upon the initial source address (SAR). The base address should be aligned to a 0-modulo-(circular buffer size) boundary. Misaligned buffers are not possible. The boundary is forced to the value determined by the upper address bits in the field selection. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 11-8 DMOD Buffer disabled Circular buffer size is 16 bytes Circular buffer size is 32 bytes Circular buffer size is 64 bytes Circular buffer size is 128 bytes Circular buffer size is 256 bytes Circular buffer size is 512 bytes Circular buffer size is 1 KB Circular buffer size is 2 KB Circular buffer size is 4 KB Circular buffer size is 8 KB Circular buffer size is 16 KB Circular buffer size is 32 KB Circular buffer size is 64 KB Circular buffer size is 128 KB Circular buffer size is 256 KB Destination address modulo Defines the size of the destination data circular buffer used by the DMA Controller. If enabled (DMOD value is non-zero), the buffer base address is located on a boundary of the buffer size. The value of this boundary depends on the initial destination address (DAR). The base address should be aligned to a 0modulo-(circular buffer size) boundary. Misaligned buffers are not possible. The boundary is forced to the value determined by the upper address bits in the field selection. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Buffer disabled Circular buffer size is 16 bytes Circular buffer size is 32 bytes Circular buffer size is 64 bytes Circular buffer size is 128 bytes Circular buffer size is 256 bytes Circular buffer size is 512 bytes Circular buffer size is 1 KB Circular buffer size is 2 KB Circular buffer size is 4 KB Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 335 Memory Map and Registers DMA_DCRn field descriptions (continued) Field Description 1010 1011 1100 1101 1110 1111 7 D_REQ Disable request DMA hardware automatically clears the corresponding DCRn[ERQ] bit when the byte count register reaches zero. 0 1 6 Reserved 5-4 LINKCC Circular buffer size is 8 KB Circular buffer size is 16 KB Circular buffer size is 32 KB Circular buffer size is 64 KB Circular buffer size is 128 KB Circular buffer size is 256 KB ERQ bit is not affected. ERQ bit is cleared when the BCR is exhausted. This field is reserved. This read-only field is reserved and always has the value 0. Link channel control Allows DMA channels to have their transfers linked. The current DMA channel triggers a DMA request to the linked channels (LCH1 or LCH2) depending on the condition described by the LINKCC bits. If not in cycle steal mode (DCRn[CS]=0) and LINKCC equals 01 or 10, no link to LCH1 occurs. If LINKCC equals 01, a link to LCH1 is created after each cycle-steal transfer performed by the current DMA channel is completed. As the last cycle-steal is performed and the BCR reaches zero, then the link to LCH1 is closed and a link to LCH2 is created. 00 01 10 11 3-2 LCH1 Link channel 1 Indicates the DMA channel assigned as link channel 1. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set). 00 01 10 11 1-0 LCH2 No channel-to-channel linking Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to zero Perform a link to channel LCH1 after each cycle-steal transfer Perform a link to channel LCH1 after the BCR decrements to zero DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 Link channel 2 Indicates the DMA channel assigned as link channel 2. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set). 00 01 10 11 DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 336 Freescale Semiconductor, Inc. Chapter 23 DMA Controller Module 23.4 Functional Description In the following discussion, the term DMA request implies that DCRn[START] is set, or DCRn[ERQ] is set and then followed by assertion of the properly selected DMA peripheral request. The START bit is cleared when the channel is activated. Before initiating a dual-address access, the DMA module verifies that DCRn[SSIZE] and DCRn[DSIZE] are consistent with the source and destination addresses. If they are not consistent, the configuration error bit, DSRn[CE], is set. If misalignment is detected, no transfer occurs, DSRn[CE] is set, and, depending on the DCR configuration, an interrupt event may be issued. If the auto-align bit, DCRn[AA], is set, error checking is performed on the appropriate registers. A read/write transfer sequence reads data from the source address and writes it to the destination address. The number of bytes transferred is the largest of the sizes specified by DCRn[SSIZE] and DCRn[DSIZE] in the DMA Control Registers (DCRn). Source and destination address registers (SARn and DARn) can be programmed in the DCRn to increment at the completion of a successful transfer. 23.4.1 Transfer Requests (Cycle-Steal and Continuous Modes) The DMA channel supports software-initiated or peripheral-initiated requests. A request is issued by setting DCRn[START] or when the selected peripheral request asserts and DCRn[ERQ] is set. Setting DCRn[ERQ] enables recognition of the peripheral DMA requests. Selecting between cycle-steal and continuous modes minimizes bus usage for either type of request. * Cycle-steal mode (DCRn[CS] = 1)--Only one complete transfer from source to destination occurs for each request. If DCRn[ERQ] is set, the request is peripheral initiated. A software-initiated request is enabled by setting DCRn[START]. * Continuous mode (DCRn[CS] = 0)--After a software-initiated or peripheral request, the DMA continuously transfers data until BCRn reaches zero. The DMA performs the specified number of transfers, then retires the channel. In either mode, the crossbar switch performs independent arbitration on each slave port after each transaction. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 337 Functional Description 23.4.2 Channel Initialization and Startup Before a data transfer starts, the channel's transfer control descriptor must be initialized with information describing configuration, request-generation method, and pointers to the data to be moved. 23.4.2.1 Channel Prioritization The four DMA channels are prioritized based on number, with channel 0 having highest priority and channel 3 having the lowest, that is, channel 0 > channel 1 > channel 2 > channel 3. Simultaneous peripheral requests activate the channels based on this priority order. Once activated, a channel runs to completion as defined by DCRn[CS] and BCRn. 23.4.2.2 Programming the DMA Controller Module CAUTION During a channel's execution, writes to programming model registers can corrupt the data transfer. The DMA module itself does not have a mechanism to prevent writes to registers during a channel's execution. General guidelines for programming the DMA are: * TCDn is initialized. * SARn is loaded with the source (read) address. If the transfer is from a peripheral device to memory or to another peripheral, the source address is the location of the peripheral data register. If the transfer is from memory to a peripheral device or to memory, the source address is the starting address of the data block. This can be any appropriately aligned address. * DARn is initialized with the destination (write) address. If the transfer is from a peripheral device to memory, or from memory to memory, DARn is loaded with the starting address of the data block to be written. If the transfer is from memory to a peripheral device, or from a peripheral device to a peripheral device, DARn is loaded with the address of the peripheral data register. This address can be any appropriately aligned address. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 338 Freescale Semiconductor, Inc. Chapter 23 DMA Controller Module * SARn and DARn change after each data transfer depending on DCRn[SSIZE, DSIZE, SINC, DINC, SMOD, DMOD] and the starting addresses. Increment values can be 1, 2, or 4 for 8-bit, 16-bit, or 32-bit transfers, respectively. If the address register is programmed to remain unchanged, the register is not incremented after the data transfer. * BCRn[BCR] must be loaded with the total number of bytes to be transferred. It is decremented by 1, 2, or 4 at the end of each transfer, depending on the transfer size. DSRn[DONE] must be cleared for channel startup. * After the channel has been initialized, it may be started by setting DCRn[START] or a properly selected peripheral DMA request, depending on the status of DCRn[ERQ]. For a software-initiated transfer, the channel can be started by setting DCRn[START] as part of a single 32-bit write to the last 32 bits of the TCDn; that is, it is not required to write the DCRn with START cleared and then perform a second write to explicitly set START. * Programming the channel for a software-initiated request causes the channel to request the system bus and start transferring data immediately. If the channel is programmed for peripheral-initiated request, a properly selected peripheral DMA request must be asserted before the channel begins the system bus transfers. * The hardware can automatically clear DCRn[ERQ], disabling the peripheral request, when BCRn reaches zero by setting DCRn[D_REQ]. * Changes to DCRn are effective immediately while the channel is active. To avoid problems with changing a DMA channel setup, write a one to DSRn[DONE] to stop the DMA channel. 23.4.3 Dual-Address Data Transfer Mode Each channel supports dual-address transfers. Dual-address transfers consist of a source data read and a destination data write. The DMA controller module begins a dual-address transfer sequence after a DMA request. If no error condition exists, DSRn[REQ] is set. * Dual-address read--The DMA controller drives the SARn value onto the system address bus. If DCRn[SINC] is set, the SARn increments by the appropriate number of bytes upon a successful read cycle. When the appropriate number of read cycles complete (multiple reads if the destination size is larger than the source), the DMA initiates the write portion of the transfer. If a termination error occurs, DSRn[BES, DONE] are set and DMA transactions stop. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 339 Functional Description * Dual-address write--The DMA controller drives the DARn value onto the system address bus. When the appropriate number of write cycles complete (multiple writes if the source size is larger than the destination), DARn increments by the appropriate number of bytes if DCRn[DINC] is set. BCRn decrements by the appropriate number of bytes. DSRn[DONE] is set when BCRn reaches zero. If the BCRn is greater than zero, another read/write transfer is initiated if continuous mode is enabled (DCRn[CS] = 0). If a termination error occurs, DSRn[BED, DONE] are set and DMA transactions stop. 23.4.4 Advanced Data Transfer Controls: Auto-Alignment Typically, auto-alignment for DMA transfers applies for transfers of large blocks of data. As a result, it does not apply for peripheral-initiated cycle-steal transfers. Auto-alignment allows block transfers to occur at the optimal size based on the address, byte count, and programmed size. To use this feature, DCRn[AA] must be set. The source is auto-aligned if DCRn[SSIZE] indicates a transfer size larger than DCRn[DSIZE]. Source alignment takes precedence over the destination when the source and destination sizes are equal. Otherwise, the destination is auto-aligned. The address register chosen for alignment increments regardless of the increment value. Configuration error checking is performed on registers not chosen for alignment. If BCRn is greater than 16, the address determines transfer size. Transfers of 8 bits, 16 bits, or 32 bits are transferred until the address is aligned to the programmed size boundary, at which time accesses begin using the programmed size. If BCRn is less than 16 at the start of a transfer, the number of bytes remaining dictates transfer size. Consider this example: * AA equals 1. * SARn equals 0x2000_0001. * BCRn equals 0x00_00F0. * SSIZE equals 00 (32 bits). * DSIZE equals 01 (8 bits). Because SSIZE > DSIZE, the source is auto-aligned. Error checking is performed on destination registers. The access sequence is as follows: 1. Read 1 byte from 0x2000_0001, increment SARn, write 1 byte (using DARn). 2. Read 2 bytes from 0x2000_0002, increment SARn, write 2 bytes. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 340 Freescale Semiconductor, Inc. Chapter 23 DMA Controller Module 3. Read 4 bytes from 0x2000_0004, increment SARn, write 4 bytes. 4. Repeat 4-byte operations until SARn equals 0x2000_00F0. 5. Read byte from 0x2000_00F0, increment SARn, write byte. If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address, but not exceeding the configured size. 23.4.5 Termination An unsuccessful transfer can terminate for one of the following reasons: * Error conditions--When the DMA encounters a read or write cycle that terminates with an error condition, DSRn[BES] is set for a read and DSRn[BED] is set for a write before the transfer is halted. If the error occurred in a write cycle, data in the internal holding registers is lost. * Interrupts--If DCRn[EINT] is set, the DMA drives the appropriate interrupt request signal. The processor can read DSRn to determine whether the transfer terminated successfully or with an error. DSRn[DONE] is then written with a one to clear the interrupt, the DONE, and error status bits. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 341 Functional Description KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 342 Freescale Semiconductor, Inc. Chapter 24 Multipurpose Clock Generator (MCG) 24.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The multipurpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL). The FLL is controllable by either an internal or an external reference clock. The module can select either of the FLL orthe internal or external reference clocks as a source for the MCU system clock. The MCG operates in conjuction with a crystal oscillator, which allows an external crystal, ceramic resonator, or another external clock source to produce the external reference clock. 24.1.1 Features Key features of the MCG module are: * Frequency-locked loop (FLL): * Digitally-controlled oscillator (DCO) * DCO frequency range is programmable for up to four different frequency ranges. * Option to program and maximize DCO output frequency for a low frequency external reference clock source. * Option to prevent FLL from resetting its current locked frequency when switching clock modes if FLL reference frequency is not changed. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 343 Introduction * Internal or external reference clock can be used as the FLL source. * Can be used as a clock source for other on-chip peripherals. * Internal reference clock generator: * Slow clock with nine trim bits for accuracy * Fast clock with four trim bits * Can be used as source clock for the FLL. In FEI mode, only the slow Internal Reference Clock (IRC) can be used as the FLL source. * Either the slow or the fast clock can be selected as the clock source for the MCU. * Can be used as a clock source for other on-chip peripherals. * Control signals for the MCG external reference low power oscillator clock generators are provided: * HGO0, RANGE0, EREFS0 * External clock from the Crystal Oscillator : * Can be used as a source for the FLL. * Can be selected as the clock source for the MCU. * External clock monitor with reset and interrupt request capability to check for external clock failure when running in FBE, BLPE, or FEE modes * Internal Reference Clocks Auto Trim Machine (ATM) capability using an external clock as a reference * Reference dividers for the FLL are provided * Reference dividers for the Fast Internal Reference Clock are provided * MCG FLL Clock (MCGFLLCLK) is provided as a clock source for other on-chip peripherals * MCG Fixed Frequency Clock (MCGFFCLK) is provided as a clock source for other on-chip peripherals * MCG Internal Reference Clock (MCGIRCLK) is provided as a clock source for other on-chip peripherals KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 344 Freescale Semiconductor, Inc. Chapter 24 Multipurpose Clock Generator (MCG) Crystal Oscillator External Reference Clock CLKS OSCINIT0 MCG Crystal Oscillator Enable Detect IREFS EREFS0 HGO0 ATMS RANGE0 STOP IREFSTEN Auto Trim Machine IRCLKEN SCTRIM Internal Reference SCFTRIM Clock Generator FCTRIM MCGIRCLK IRCS CLKS Slow Clock Fast Clock / 2n IRCSCLK n=0-7 MCGOUTCLK CME0 LOCRE0 DRS External Clock Monitor DMX32 MCGFLLCLK Filter DCO FLTPRSRV LOCS0 DCOOUT FLL FRDIV / Clock Valid LP 2n n=0-7 / 25 MCGFFCLK Sync IREFS Peripheral BUSCLK Multipurpose Clock Generator (MCG) Figure 24-1. Multipurpose Clock Generator (MCG) block diagram KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 345 External Signal Description 24.1.2 Modes of Operation The MCG has the following modes of operation: FEI, FEE, FBI, FBE, BLPI, BLPE, and Stop. For details, see MCG modes of operation. 24.2 External Signal Description There are no MCG signals that connect off chip. 24.3 Memory Map/Register Definition This section includes the memory map and register definition. The MCG registers can only be written when in supervisor mode. Write accesses when in user mode will result in a bus error. Read accesses may be performed in both supervisor and user mode. MCG memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 04h 24.3.1/346 4006_4000 MCG Control 1 Register (MCG_C1) 8 R/W 4006_4001 MCG Control 2 Register (MCG_C2) 8 R/W 80h 24.3.2/348 4006_4002 MCG Control 3 Register (MCG_C3) 8 R/W Undefined 24.3.3/349 4006_4003 MCG Control 4 Register (MCG_C4) 8 R/W Undefined 24.3.4/349 4006_4005 MCG Control 6 Register (MCG_C6) 8 R/W 00h 24.3.5/351 4006_4006 MCG Status Register (MCG_S) 8 R 10h 24.3.6/351 4006_4008 MCG Status and Control Register (MCG_SC) 8 R/W 02h 24.3.7/352 4006_400A MCG Auto Trim Compare Value High Register (MCG_ATCVH) 8 R/W 00h 24.3.8/354 4006_400B MCG Auto Trim Compare Value Low Register (MCG_ATCVL) 8 R/W 00h 24.3.9/354 2 1 0 IREFS IRCLKEN IREFSTEN 1 0 0 24.3.1 MCG Control 1 Register (MCG_C1) Address: 4006_4000h base + 0h offset = 4006_4000h Bit Read Write Reset 7 6 5 CLKS 0 4 3 FRDIV 0 0 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 346 Freescale Semiconductor, Inc. Chapter 24 Multipurpose Clock Generator (MCG) MCG_C1 field descriptions Field 7-6 CLKS Description Clock Source Select Selects the clock source for MCGOUTCLK . 00 01 10 11 5-3 FRDIV FLL External Reference Divider Selects the amount to divide down the external reference clock for the FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is not required to meet this range, but it is recommended in the cases when trying to enter a FLL mode from FBE). 000 001 010 011 100 101 110 111 2 IREFS Selects the reference clock source for the FLL. External reference clock is selected. The slow internal reference clock is selected. Internal Reference Clock Enable Enables the internal reference clock for use as MCGIRCLK. 0 1 0 IREFSTEN If RANGE 0 = 0 , Divide Factor is 1; for all other RANGE 0 values, Divide Factor is 32. If RANGE 0 = 0 , Divide Factor is 2; for all other RANGE 0 values, Divide Factor is 64. If RANGE 0 = 0 , Divide Factor is 4; for all other RANGE 0 values, Divide Factor is 128. If RANGE 0 = 0 , Divide Factor is 8; for all other RANGE 0 values, Divide Factor is 256. If RANGE 0 = 0 , Divide Factor is 16; for all other RANGE 0 values, Divide Factor is 512. If RANGE 0 = 0 , Divide Factor is 32; for all other RANGE 0 values, Divide Factor is 1024. If RANGE 0 = 0 , Divide Factor is 64; for all other RANGE 0 values, Divide Factor is 1280 . If RANGE 0 = 0 , Divide Factor is 128; for all other RANGE 0 values, Divide Factor is 1536 . Internal Reference Select 0 1 1 IRCLKEN Encoding 0 -- Output of FLL is selected. Encoding 1 -- Internal reference clock is selected. Encoding 2 -- External reference clock is selected. Encoding 3 -- Reserved. MCGIRCLK inactive. MCGIRCLK active. Internal Reference Stop Enable Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. 0 1 Internal reference clock is disabled in Stop mode. Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 347 Memory Map/Register Definition 24.3.2 MCG Control 2 Register (MCG_C2) Address: 4006_4000h base + 1h offset = 4006_4001h Bit Read Write Reset 7 6 LOCRE0 0 1 0 5 4 RANGE0 0 3 2 1 0 HGO0 EREFS0 LP IRCS 0 0 0 0 0 MCG_C2 field descriptions Field 7 LOCRE0 Description Loss of Clock Reset Enable Determines whether an interrupt or a reset request is made following a loss of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is set. 0 1 Interrupt request is generated on a loss of OSC0 external reference clock. Generate a reset request on a loss of OSC0 external reference clock. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5-4 RANGE0 Frequency Range Select Selects the frequency range for the crystal oscillator or external clock source. See the Oscillator (OSC) chapter for more details and the device data sheet for the frequency ranges used. 00 01 1X 3 HGO0 High Gain Oscillator Select Controls the crystal oscillator mode of operation. See the Oscillator (OSC) chapter for more details. 0 1 2 EREFS0 Selects the source for the external reference clock. See the Oscillator (OSC) chapter for more details. External reference clock requested. Oscillator requested. Low Power Select Controls whether the FLL is disabled in BLPI and BLPE modes. In FBE mode, setting this bit to 1 will transition the MCG into BLPE mode; in FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any other MCG mode, LP bit has no affect. 0 1 0 IRCS Configure crystal oscillator for low-power operation. Configure crystal oscillator for high-gain operation. External Reference Select 0 1 1 LP Encoding 0 -- Low frequency range selected for the crystal oscillator . Encoding 1 -- High frequency range selected for the crystal oscillator . Encoding 2 -- Very high frequency range selected for the crystal oscillator . FLL is not disabled in bypass modes. FLL is disabled in bypass modes (lower power) Internal Reference Clock Select Selects between the fast or slow internal reference clock source. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 348 Freescale Semiconductor, Inc. Chapter 24 Multipurpose Clock Generator (MCG) MCG_C2 field descriptions (continued) Field Description 0 1 Slow internal reference clock selected. Fast internal reference clock selected. 24.3.3 MCG Control 3 Register (MCG_C3) Address: 4006_4000h base + 2h offset = 4006_4002h Bit Read Write Reset 7 6 5 4 3 2 1 0 x* x* x* x* SCTRIM x* x* x* x* * Notes: * x = Undefined at reset. MCG_C3 field descriptions Field 7-0 SCTRIM Description Slow Internal Reference Clock Trim Setting SCTRIM 1 controls the slow internal reference clock frequency by controlling the slow internal reference clock period. The SCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value increases the period, and decreasing the value decreases the period. An additional fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset, this value is loaded with a factory trim value. If an SCTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register. 1. A value for SCTRIM is loaded during reset from a factory programmed location . 24.3.4 MCG Control 4 Register (MCG_C4) NOTE Reset values for DRST and DMX32 bits are 0. Address: 4006_4000h base + 3h offset = 4006_4003h Bit Read Write Reset 7 6 DMX32 5 4 3 DRST_DRS 0 0 2 1 FCTRIM 0 x* x* 0 SCFTRIM x* x* x* * Notes: * x = Undefined at reset. * A value for FCTRIM is loaded during reset from a factory programmed location . x = Undefined at reset. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 349 Memory Map/Register Definition MCG_C4 field descriptions Field 7 DMX32 Description DCO Maximum Frequency with 32.768 kHz Reference The DMX32 bit controls whether the DCO frequency range is narrowed to its maximum frequency with a 32.768 kHz reference. The following table identifies settings for the DCO frequency range. NOTE: The system clocks derived from this source should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 0 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 0 31.25-39.0625 kHz 2560 80-100 MHz 1 32.768 kHz 2929 96 MHz 01 10 11 0 1 6-5 DRST_DRS DCO Range Select The DRS bits select the frequency range for the FLL output, DCOOUT. When the LP bit is set, writes to the DRS bits are ignored. The DRST read field indicates the current frequency range for DCOOUT. The DRST field does not update immediately after a write to the DRS field due to internal synchronization between clock domains. See the DCO Frequency Range table for more details. 00 01 10 11 4-1 FCTRIM DCO has a default range of 25%. DCO is fine-tuned for maximum frequency with 32.768 kHz reference. Encoding 0 -- Low range (reset default). Encoding 1 -- Mid range. Encoding 2 -- Mid-high range. Encoding 3 -- High range. Fast Internal Reference Clock Trim Setting FCTRIM 1 controls the fast internal reference clock frequency by controlling the fast internal reference clock period. The FCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value increases the period, and decreasing the value decreases the period. If an FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register. 0 SCFTRIM Slow Internal Reference Clock Fine Trim SCFTRIM 2 controls the smallest adjustment of the slow internal reference clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM decreases the period by the smallest amount possible. If an SCFTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this bit. 1. A value for FCTRIM is loaded during reset from a factory programmed location . 2. A value for SCFTRIM is loaded during reset from a factory programmed location . KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 350 Freescale Semiconductor, Inc. Chapter 24 Multipurpose Clock Generator (MCG) 24.3.5 MCG Control 6 Register (MCG_C6) Address: 4006_4000h base + 5h offset = 4006_4005h Bit Read Write Reset 7 6 0 0 5 4 3 2 CME 0 0 1 0 0 0 0 0 0 0 MCG_C6 field descriptions Field 7-6 Reserved 5 CME Description Reserved This field is reserved. This read-only field is reserved and always has the value 0. Clock Monitor Enable Determines if a reset request is made following a loss of external clock indication. The CME bit should only be set to a logic 1 when the MCG is in an operational mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). Whenever the CME bit is set to a logic 1, the value of the RANGE bits in the C2 register should not be changed. CME bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a reset request may occur when in Stop mode. CME should also be set to a logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode. 0 1 4-0 Reserved External clock monitor is disabled. Generate a reset request on loss of external clock. Reserved This field is reserved. This read-only field is reserved and always has the value 0. 24.3.6 MCG Status Register (MCG_S) Address: 4006_4000h base + 6h offset = 4006_4006h Bit 7 6 Read 5 0 4 3 IREFST 2 CLKST 1 0 OSCINIT0 IRCST 0 0 Write Reset 0 0 0 1 0 0 MCG_S field descriptions Field 7-5 Reserved Description Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 351 Memory Map/Register Definition MCG_S field descriptions (continued) Field 4 IREFST Description Internal Reference Status This bit indicates the current source for the FLL reference clock. The IREFST bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock domains. 0 1 3-2 CLKST Source of FLL reference clock is the external reference clock. Source of FLL reference clock is the internal reference clock. Clock Mode Status These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 01 10 11 1 OSCINIT0 0 IRCST Encoding 0 -- Output of the FLL is selected (reset default). Encoding 1 -- Internal reference clock is selected. Encoding 2 -- External reference clock is selected. Reserved. OSC Initialization This bit, which resets to 0, is set to 1 after the initialization cycles of the crystal oscillator clock have completed. After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed description for more information. Internal Reference Clock Status The IRCST bit indicates the current source for the internal reference clock select clock (IRCSCLK). The IRCST bit does not update immediately after a write to the IRCS bit due to internal synchronization between clock domains. The IRCST bit will only be updated if the internal reference clock is enabled, either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] bit . 0 1 Source of internal reference clock is the slow clock (32 kHz IRC). Source of internal reference clock is the fast clock (4 MHz IRC). 24.3.7 MCG Status and Control Register (MCG_SC) Address: 4006_4000h base + 8h offset = 4006_4008h Bit Read Write Reset 7 6 ATME ATMS 0 0 5 ATMF 0 4 3 FLTPRSRV 0 2 1 LOCS0 FCRDIV 0 0 0 1 0 MCG_SC field descriptions Field 7 ATME Description Automatic Trim Machine Enable Enables the Auto Trim Machine to start automatically trimming the selected Internal Reference Clock. NOTE: ATME deasserts after the Auto Trim Machine has completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 352 Freescale Semiconductor, Inc. Chapter 24 Multipurpose Clock Generator (MCG) MCG_SC field descriptions (continued) Field Description Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim operation and clears this bit. 0 1 6 ATMS Automatic Trim Machine Select Selects the IRCS clock for Auto Trim Test. 0 1 5 ATMF Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC registers is detected or the MCG enters into any Stop mode. A write to ATMF clears the flag. This bit will prevent the FLL filter values from resetting allowing the FLL output frequency to remain the same during clock mode changes where the FLL/DCO output is still valid. (Note: This requires that the FLL reference frequency to remain the same as what it was prior to the new clock mode switch. Otherwise FLL filter and frequency values will change.) FLL filter and FLL frequency will reset on changes to currect clock mode. Fll filter and FLL frequency retain their previous values during new clock mode change. Fast Clock Internal Reference Divider Selects the amount to divide down the fast internal reference clock. The resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the divider when the Fast IRC is enabled is not supported). 000 001 010 011 100 101 110 111 0 LOCS0 Automatic Trim Machine completed normally. Automatic Trim Machine failed. FLL Filter Preserve Enable 0 1 3-1 FCRDIV 32 kHz Internal Reference Clock selected. 4 MHz Internal Reference Clock selected. Automatic Trim Machine Fail Flag 0 1 4 FLTPRSRV Auto Trim Machine disabled. Auto Trim Machine enabled. Divide Factor is 1 Divide Factor is 2. Divide Factor is 4. Divide Factor is 8. Divide Factor is 16 Divide Factor is 32 Divide Factor is 64 Divide Factor is 128. OSC0 Loss of Clock Status The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a logic 1 to it when set. 0 1 Loss of OSC0 has not occurred. Loss of OSC0 has occurred. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 353 Functional Description 24.3.8 MCG Auto Trim Compare Value High Register (MCG_ATCVH) Address: 4006_4000h base + Ah offset = 4006_400Ah Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 ATCVH 0 0 0 0 MCG_ATCVH field descriptions Field 7-0 ATCVH Description ATM Compare Value High Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 24.3.9 MCG Auto Trim Compare Value Low Register (MCG_ATCVL) Address: 4006_4000h base + Bh offset = 4006_400Bh Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 ATCVL 0 0 0 0 MCG_ATCVL field descriptions Field 7-0 ATCVL Description ATM Compare Value Low Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 24.4 Functional Description 24.4.1 MCG mode state diagram The seven states of the MCG are shown in the following figure and are described in Table 24-11. The arrows indicate the permitted MCG mode transitions. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 354 Freescale Semiconductor, Inc. Chapter 24 Multipurpose Clock Generator (MCG) Reset FEI FEE FBI FBE BLPE BLPI Entered from any state when the MCU enters Stop mode Stop Returns to the state that was active before the MCU entered Stop mode, unless a reset occurs while in Stop mode. Figure 24-11. MCG mode state diagram 24.4.1.1 MCG modes of operation The MCG operates in one of the following modes. Note The MCG restricts transitions between modes. For the permitted transitions, see Figure 24-11. Table 24-11. MCG modes of operation Mode Description FLL Engaged Internal (FEI) FLL engaged internal (FEI) is the default mode of operation and is entered when all the following condtions occur: * C1[CLKS] bits are written to 00 * C1[IREFS] bit is written to 1 In FEI mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the 32 kHz Internal Reference Clock (IRC). The FLL loop will lock the DCO frequency to the FLL factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See the C4[DMX32] bit description for more details. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 355 Functional Description Table 24-11. MCG modes of operation (continued) Mode Description FLL Engaged External (FEE) FLL engaged external (FEE) mode is entered when all the following conditions occur: * C1[CLKS] bits are written to 00 * C1[IREFS] bit is written to 0 * C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz In FEE mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the external reference clock. The FLL loop will lock the DCO frequency to the FLL factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the external reference frequency, as specified by C1[FRDIV] and C2[RANGE0]. See the C4[DMX32] bit description for more details. FLL Bypassed Internal (FBI) FLL bypassed internal (FBI) mode is entered when all the following conditions occur: * C1[CLKS] bits are written to 01 * C1[IREFS] bit is written to 1 * C2[LP] is written to 0 In FBI mode, the MCGOUTCLK is derived either from the slow (32 kHz IRC) or fast (4 MHz IRC) internal reference clock, as selected by the C2[IRCS] bit. The FLL is operational but its output is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK is driven from the C2[IRCS] selected internal reference clock. The FLL clock (DCOCLK) is controlled by the slow internal reference clock, and the DCO clock frequency locks to a multiplication factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See the C4[DMX32] bit description for more details. FLL Bypassed External FLL bypassed external (FBE) mode is entered when all the following conditions occur: (FBE) * C1[CLKS] bits are written to 10 * C1[IREFS] bit is written to 0 * C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz. * C2[LP] is written to 0 In FBE mode, the MCGOUTCLK is derived from the external reference clock. The FLL is operational but its output is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK is driven from the external reference clock. The FLL clock (DCOCLK) is controlled by the external reference clock, and the DCO clock frequency locks to a multiplication factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the divided external reference frequency. See the C4[DMX32] bit description for more details. Bypassed Low Power Internal (BLPI)1 Bypassed Low Power Internal (BLPI) mode is entered when all the following conditions occur: * C1[CLKS] bits are written to 01 * C1[IREFS] bit is written to 1 * C2[LP] bit is written to 1 In BLPI mode, MCGOUTCLK is derived from the internal reference clock. The FLL is disabled Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 356 Freescale Semiconductor, Inc. Chapter 24 Multipurpose Clock Generator (MCG) Table 24-11. MCG modes of operation (continued) Mode Description Bypassed Low Power External (BLPE) Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur: * C1[CLKS] bits are written to 10 * C1[IREFS] bit is written to 0 * C2[LP] bit is written to 1 In BLPE mode, MCGOUTCLK is derived from the external reference clock. The FLL is disabled Stop Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power mode assignments, see the chapter that describes how modules are configured and MCG behavior during Stop recovery. Entering Stop mode, the FLL is disabled, and all MCG clock signals are static except in the following case: MCGIRCLK is active in Normal Stop mode when all the following conditions become true: * C1[IRCLKEN] = 1 * C1[IREFSTEN] = 1 1. If entering VLPR mode, MCG has to be configured and enter BLPE mode or BLPI mode with the Fast IRC clock selected (C2[IRCS]=1). After it enters VLPR mode, writes to any of the MCG control registers that can cause an MCG clock mode switch to a non low power clock mode must be avoided. NOTE For the chip-specific modes of operation, see the power management chapter of this MCU. 24.4.1.2 MCG mode switching The C1[IREFS] bit can be changed at any time, but the actual switch to the newly selected reference clocks is shown by the S[IREFST] bit. When switching between engaged internal and engaged external modes, the FLL will begin locking again after the switch is completed. The C1[CLKS] bits can also be changed at any time, but the actual switch to the newly selected clock is shown by the S[CLKST] bits. If the newly selected clock is not available, the previous clock will remain selected. The C4[DRST_DRS] write bits can be changed at any time except when C2[LP] bit is 1. If the C4[DRST_DRS] write bits are changed while in FLL engaged internal (FEI) or FLL engaged external (FEE), the MCGOUTCLK will switch to the new selected DCO range within three clocks of the selected DCO clock. After switching to the new DCO, the FLL remains unlocked for several reference cycles. DCO startup time is equal to the FLL acquisition time. After the selected DCO startup time is over, the FLL is locked. The completion of the switch is shown by the C4[DRST_DRS] read bits. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 357 Functional Description 24.4.2 Low Power Bit Usage The C2[LP] bit is provided to allow the FLL to be disabled and thus conserve power when these systems are not being used. The C4[DRST_DRS] can not be written while C2[LP] bit is 1. However, in some applications, it may be desirable to enable the FLL and allow it to lock for maximum accuracy before switching to an engaged mode. Do this by writing C2[LP] to 0. 24.4.3 MCG Internal Reference Clocks This module supports two internal reference clocks with nominal frequencies of 32 kHz (slow IRC) and 4 MHz (fast IRC). The fast IRC frequency can be divided down by programming of the FCRDIV to produce a frequency range of 32 kHz to 4 MHz. 24.4.3.1 MCG Internal Reference Clock The MCG Internal Reference Clock (MCGIRCLK) provides a clock source for other onchip peripherals and is enabled when C1[IRCLKEN]=1. When enabled, MCGIRCLK is driven by either the fast internal reference clock (4 MHz IRC which can be divided down by the FRDIV factors) or the slow internal reference clock (32 kHz IRC). The IRCS clock frequency can be re-targeted by trimming the period of its IRCS selected internal reference clock. This can be done by writing a new trim value to the C3[SCTRIM]:C4[SCFTRIM] bits when the slow IRC clock is selected or by writing a new trim value to the C4[FCTRIM] bits when the fast IRC clock is selected. The internal reference clock period is proportional to the trim value written. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) and C4[FCTRIM] (if C2[IRCS]=1) bits affect the MCGOUTCLK frequency if the MCG is in FBI or BLPI modes. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) bits also affect the MCGOUTCLK frequency if the MCG is in FEI mode. Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and C1[IREFSTEN], otherwise this clock is disabled in Stop mode. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 358 Freescale Semiconductor, Inc. Chapter 24 Multipurpose Clock Generator (MCG) 24.4.4 External Reference Clock The MCG module can support an external reference clock in all modes. See the device datasheet for external reference frequency range. When C1[IREFS] is set, the external reference clock will not be used by the FLL. In these mode, the frequency can be equal to the maximum frequency the chip-level timing specifications will support. If any of the CME bits are asserted the slow internal reference clock is enabled along with the enabled external clock monitor. For the case when C6[CME0]=1, a loss of clock is detected if the OSC0 external reference falls below a minimum frequency (floc_high or floc_low depending on C2[RANGE0]). NOTE All clock monitors must be disabled before entering these lowpower modes: Stop, VLPS, VLPR, VLPW, LLS, and VLLSx. Upon detect of a loss of clock event, the MCU generates a system reset if the respective LOCRE bit is set. Otherwise the MCG sets the respective LOCS bit and the MCG generates a LOCS interrupt request. 24.4.5 MCG Fixed frequency clock The MCG Fixed Frequency Clock (MCGFFCLK) provides a fixed frequency clock source for other on-chip peripherals; see the block diagram. This clock is driven by either the slow clock from the internal reference clock generator or the external reference clock from the Crystal Oscillator, divided by the FLL reference clock divider. The source of MCGFFCLK is selected by C1[IREFS]. This clock is synchronized to the peripheral bus clock and is valid only when its frequency is not more than 1/8 of the MCGOUTCLK frequency. When it is not valid, it is disabled and held high. The MCGFFCLK is not available when the MCG is in BLPI mode. This clock is also disabled in Stop mode. The FLL reference clock must be set within the valid frequency range for the MCGFFCLK. 24.4.6 MCG Auto TRIM (ATM) The MCG Auto Trim (ATM) is a MCG feature that when enabled, it configures the MCG hardware to automatically trim the MCG Internal Reference Clocks using an external clock as a reference. The selection between which MCG IRC clock gets tested and KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 359 Functional Description enabled is controlled by the ATC[ATMS] control bit (ATC[ATMS]=0 selects the 32 kHz IRC and ATC[ATMS]=1 selects the 4 MHz IRC). If 4 MHz IRC is selected for the ATM, a divide by 128 is enabled to divide down the 4 MHz IRC to a range of 31.250 kHz. When MCG ATM is enabled by writing ATC[ATME] bit to 1, The ATM machine will start auto trimming the selected IRC clock. During the autotrim process, ATC[ATME] will remain asserted and will deassert after ATM is completed or an abort occurs. The MCG ATM is aborted if a write to any of the following control registers is detected : C1, C3, C4, or ATC or if Stop mode is entered. If an abort occurs, ATC[ATMF] fail flag is asserted. The ATM machine uses the bus clock as the external reference clock to perform the IRC auto-trim. Therefore, it is required that the MCG is configured in a clock mode where the reference clock used to generate the system clock is the external reference clock such as FBE clock mode. The MCG must not be configured in a clock mode where selected IRC ATM clock is used to generate the system clock. The bus clock is also required to be running with in the range of 8-16 MHz. To perform the ATM on the selected IRC, the ATM machine uses the successive approximation technique to adjust the IRC trim bits to generate the desired IRC trimmed frequency. The ATM SARs each of the ATM IRC trim bits starting with the MSB. For each trim bit test, the ATM uses a pulse that is generated by the ATM selected IRC clock to enable a counter that counts number of ATM external clocks. At end of each trim bit, the ATM external counter value is compared to the ATCV[15:0] register value. Based on the comparison result, the ATM trim bit under test will get cleared or stay asserted. This is done until all trim bits have been tested by ATM SAR machine. Before the ATM can be enabled, the ATM expected count needs to be derived and stored into the ATCV register. The ATCV expected count is derived based on the required target Internal Reference Clock (IRC) frequency, and the frequency of the external reference clock using the following formula: ATCV * Fr = Target Internal Reference Clock (IRC) Trimmed Frequency * Fe = External Clock Frequency If the auto trim is being performed on the 4 MHz IRC, the calculated expected count value must be multiplied by 128 before storing it in the ATCV register. Therefore, the ATCV Expected Count Value for trimming the 4 MHz IRC is calculated using the following formula. (128) KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 360 Freescale Semiconductor, Inc. Chapter 24 Multipurpose Clock Generator (MCG) 24.5 Initialization / Application information This section describes how to initialize and configure the MCG module in an application. The following sections include examples on how to initialize the MCG and properly switch between the various available modes. 24.5.1 MCG module initialization sequence The MCG comes out of reset configured for FEI mode. The internal reference will stabilize in tirefsts microseconds before the FLL can acquire lock. As soon as the internal reference is stable, the FLL will acquire lock in tfll_acquire milliseconds. 24.5.1.1 Initializing the MCG Because the MCG comes out of reset in FEI mode, the only MCG modes that can be directly switched to upon reset are FEE, FBE, and FBI modes (see Figure 24-11). Reaching any of the other modes requires first configuring the MCG for one of these three intermediate modes. Care must be taken to check relevant status bits in the MCG status register reflecting all configuration changes within each mode. To change from FEI mode to FEE or FBE modes, follow this procedure: 1. Enable the external clock source by setting the appropriate bits in C2 register. 2. Write to C1 register to select the clock mode. * If entering FEE mode, set C1[FRDIV] appropriately, clear the C1[IREFS] bit to switch to the external reference, and leave the C1[CLKS] bits at 2'b00 so that the output of the FLL is selected as the system clock source. * If entering FBE, clear the C1[IREFS] bit to switch to the external reference and change the C1[CLKS] bits to 2'b10 so that the external reference clock is selected as the system clock source. The C1[FRDIV] bits should also be set KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 361 Initialization / Application information appropriately here according to the external reference frequency to keep the FLL reference clock in the range of 31.25 kHz to 39.0625 kHz. Although the FLL is bypassed, it is still on in FBE mode. * The internal reference can optionally be kept running by setting the C1[IRCLKEN] bit. This is useful if the application will switch back and forth between internal and external modes. For minimum power consumption, leave the internal reference disabled while in an external clock mode. 3. Once the proper configuration bits have been set, wait for the affected bits in the MCG status register to be changed appropriately, reflecting that the MCG has moved into the proper mode. * If the MCG is in FEE, FBE, or BLPE mode, and C2[EREFS0] was also set in step 1, wait here for S[OSCINIT0] bit to become set indicating that the external clock source has finished its initialization cycles and stabilized. * If in FEE mode, check to make sure the S[IREFST] bit is cleared before moving on. * If in FBE mode, check to make sure the S[IREFST] bit is cleared and S[CLKST] bits have changed to 2'b10 indicating the external reference clock has been appropriately selected. Although the FLL is bypassed, it is still on in FBE mode. 4. Write to the C4 register to determine the DCO output (MCGFLLCLK) frequency range. * By default, with C4[DMX32] cleared to 0, the FLL multiplier for the DCO output is 640. For greater flexibility, if a mid-low-range FLL multiplier of 1280 is desired instead, set C4[DRST_DRS] bits to 2'b01 for a DCO output frequency of 40 MHz. If a mid high-range FLL multiplier of 1920 is desired instead, set the C4[DRST_DRS] bits to 2'b10 for a DCO output frequency of 60 MHz. If a highrange FLL multiplier of 2560 is desired instead, set the C4[DRST_DRS] bits to 2'b11 for a DCO output frequency of 80 MHz. * When using a 32.768 kHz external reference, if the maximum low-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24 MHz. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 362 Freescale Semiconductor, Inc. Chapter 24 Multipurpose Clock Generator (MCG) * When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b01 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 1464 will be 48 MHz. * When using a 32.768 kHz external reference, if the maximum mid high-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b10 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 2197 will be 72 MHz. * When using a 32.768 kHz external reference, if the maximum high-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b11 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 2929 will be 96 MHz. 5. Wait for the FLL lock time to guarantee FLL is running at new C4[DRST_DRS] and C4[DMX32] programmed frequency. To change from FEI clock mode to FBI clock mode, follow this procedure: 1. Change C1[CLKS] bits in C1 register to 2'b01 so that the internal reference clock is selected as the system clock source. 2. Wait for S[CLKST] bits in the MCG status register to change to 2'b01, indicating that the internal reference clock has been appropriately selected. 3. Write to the C2 register to determine the IRCS output (IRCSCLK) frequency range. * By default, with C2[IRCS] cleared to 0, the IRCS selected output clock is the slow internal reference clock (32 kHz IRC). If the faster IRC is desired, set C2[IRCS] bit to 1 for a IRCS clock derived from the 4 MHz IRC source. 24.5.2 Using a 32.768 kHz reference In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor of 640, the DCO output (MCGFLLCLK) frequency is 20.97 MHz at low-range. If C4[DRST_DRS] bits are set to 2'b01, the multiplication factor is doubled to 1280, and the resulting DCO output frequency is 41.94 MHz at mid-low-range. If C4[DRST_DRS] bits are set to 2'b10, the multiplication factor is set to 1920, and the KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 363 Initialization / Application information resulting DCO output frequency is 62.91 MHz at mid high-range. If C4[DRST_DRS] bits are set to 2'b11, the multiplication factor is set to 2560, and the resulting DCO output frequency is 83.89 MHz at high-range. In FBI and FEI modes, setting C4[DMX32] bit is not recommended. If the internal reference is trimmed to a frequency above 32.768 kHz, the greater FLL multiplication factor could potentially push the microcontroller system clock out of specification and damage the part. 24.5.3 MCG mode switching When switching between operational modes of the MCG, certain configuration bits must be changed in order to properly move from one mode to another. Each time any of these bits are changed (C1[IREFS], C1[CLKS], C2[IRCS], or C2[EREFS0]), the corresponding bits in the MCG status register (IREFST, CLKST, IRCST, or OSCINIT) must be checked before moving on in the application software. Additionally, care must be taken to ensure that the reference clock divider (C1[FRDIV]) is set properly for the mode being switched to. For instance, in FEE mode, if using a 4MHz crystal, C1[FRDIV] must be set to 3'b010 (divide-by-128) to devide the external frequency down to the required frequency between 31.25 and 39.0625 kHz. In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL multiplication factor between 640, 1280, 1920, and 2560 with C4[DRST_DRS] bits. Writes to C4[DRST_DRS] bits will be ignored if C2[LP]=1. The table below shows MCGOUTCLK frequency calculations using C1[FRDIV]settings for each clock mode. Table 24-12. MCGOUTCLK Frequency Calculation Options Clock Mode fMCGOUTCLK1 Note FEI (FLL engaged internal) (fint * F) Typical fMCGOUTCLK = 21 MHz immediately after reset. FEE (FLL engaged external) (fext / FLL_R) *F fext / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz FBE (FLL bypassed external) OSCCLK OSCCLK / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz FBI (FLL bypassed internal) MCGIRCLK Selectable between slow and fast IRC BLPI (Bypassed low power internal) MCGIRCLK Selectable between slow and fast IRC BLPE (Bypassed low power external) OSCCLK 1. FLL_R is the reference divider selected by the C1[FRDIV] bits, F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 364 Freescale Semiconductor, Inc. Chapter 24 Multipurpose Clock Generator (MCG) This section will include three mode switching examples using an 4 MHz external crystal. 24.5.3.1 Example 1: Moving from FEI to BLPE mode: External Crystal = 4 MHz, MCGOUTCLK frequency = 4 MHz In this example, the MCG will move through the proper operational modes from FEI to BLPE to achieve 4 MHz MCGOUTCLK frequency from 4 MHz external crystal reference. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence. 1. First, FEI must transition to FBE mode: a. C2 = 0x1C * C2[RANGE0] set to 2'b01 because the frequency of 4 MHz is within the high frequency range. * C2[HGO0] set to 1 to configure the crystal oscillator for high gain operation. * C2[EREFS0] set to 1, because a crystal is being used. b. C1 = 0x90 * C1[CLKS] set to 2'b10 to select external reference clock as system clock source * C1[FRDIV] set to 3'b010, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL * C1[IREFS] cleared to 0, selecting the external reference clock and enabling the external oscillator. c. Loop until S[OSCINIT0] is 1, indicating the crystal selected by C2[EREFS0] has been initialized. d. Loop until S[IREFST] is 0, indicating the external reference is the current source for the reference clock. e. Loop until S[CLKST] is 2'b10, indicating that the external reference clock is selected to feed MCGOUTCLK. 2. Then, transition to BLPE: a. Set C2[LP] to 1. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 365 Initialization / Application information START IN FEI MODE C2 = 0x1C C1 = 0x40 NO CHECK S[OSCINIT0] = 1? YES CHECK S[IREFST] = 0? NO YES CHECK NO S[CLKST] = %10? YES C2 = 0x1E (C2[LP] = 1) Continue in BLPE mode Figure 24-12. Flowchart of FEI to BLPE mode transition using a 4 MHz crystal KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 366 Freescale Semiconductor, Inc. Chapter 24 Multipurpose Clock Generator (MCG) 24.5.3.2 Example 2: Moving from BLPE to BLPI mode: MCGOUTCLK frequency = 2 MHz In this example, the MCG will move through the proper operational modes from BLPE mode with a 4 MHz crystal configured for a 4 MHz MCGOUTCLK frequency (see previous example) to BLPI mode with a 2 MHz MCGOUTCLK frequency. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence. 1. First, BLPE must transition to FBE mode: a. Clear C2[LP] to 0 here to switch to FBE mode. 2. Next, FBE mode transitions into FBI mode: a. C1 = 0x54 * C1[CLKS] set to 2'b01 to switch the system clock to the internal reference clock. * C1[IREFS] set to 1 to select the internal reference clock as the reference clock source. * C1[FRDIV] remain unchanged because the reference divider does not affect the internal reference. b. Loop until S[IREFST] is 1, indicating the internal reference clock has been selected as the reference clock source. c. Loop until S[CLKST] are 2'b01, indicating that the internal reference clock is selected to feed MCGOUTCLK. 3. Lastly, FBI transitions into BLPI mode with IRCS selecting Fast Internal Reference Clock. a. C2 = 0x03 * C2[IRCS] is 1 * C2[LP] is 1 * C2[RANGE0], C2[HGO0], C2[EREFS0], C1[IRCLKEN], and C1[IREFSTEN] bits are ignored when the C1[IREFS] bit is set. They can remain set, or be cleared at this point. b. Loop until S[IRCST] is 1, indicating the internal reference clock is the fast clock. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 367 Initialization / Application information START IN BLPE MODE C2 = 0x1C (C2[LP] = 0) C1 = 0x64 CHECK S[IREFST] = 0? NO YES CHECK S[CLKST] = %01? NO YES C2 = 0x23 CHECK S[IRCST] = 1? NO YES CONTINUE IN BLPI MODE Figure 24-13. Flowchart of BLPE to BLPI mode transition using an 4 MHz crystal KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 368 Freescale Semiconductor, Inc. Chapter 24 Multipurpose Clock Generator (MCG) 24.5.3.3 Example 3: Moving from BLPI to FEE mode In this example, the MCG will move through the proper operational modes from BLPI mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz MCGOUTCLK frequency. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence. 1. First, BLPI must transition to FBI mode. a. C2 = 0x00 * C2[LP] is 0 2. Next, FBI will transition to FEE mode. a. C2 = 0x1C * C2[RANGE0] set to 2'b01 because the frequency of 4 MHz is within the high frequency range. * C2[HGO0] set to 1 to configure the crystal oscillator for high gain operation. * C2[EREFS0] set to 1, because a crystal is being used. b. C1 = 0x10 * C1[CLKS] set to 2'b00 to select the output of the FLL as system clock source. * C1[FRDIV] remain at 3'b010, or divide-by-128 for a reference of 4 MHz / 128 = 31.25 kHz. * C1[IREFS] cleared to 0, selecting the external reference clock. c. Loop until S[OSCINIT0] is 1, indicating the crystal selected by the C2[EREFS0] bit has been initialized. d. Loop until S[IREFST] is 0, indicating the external reference clock is the current source for the reference clock. e. Loop until S[CLKST] are 2'b00, indicating that the output of the FLL is selected to feed MCGOUTCLK. f. Now, with a 31.25 kHz reference frequency, a fixed DCO multiplier of 640, MCGOUTCLK = 31.25 kHz * 640 / 1 = 20 MHz. g. At this point, by default, the C4[DRST_DRS] bits are set to 2'b00 and C4[DMX32] is cleared to 0. If the MCGOUTCLK frequency of 40 MHz is desired instead, set the C4[DRST_DRS] bits to 0x01 to switch the FLL KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 369 Initialization / Application information multiplication factor from 640 to 1280. To return the MCGOUTCLK frequency to 20 MHz, set C4[DRST_DRS] bits to 2'b00 again, and the FLL multiplication factor will switch back to 640. START IN BLPI MODE CHECK NO S[IREFST] = 0? C2 =0x00 YES C2 = 0x1C NO CHECK S[CLKST] = %00? C1 =0x10 YES CONTINUE CHECK S[OSCINIT] = 1 ? NO IN FEE MODE YES Figure 24-14. Flowchart of BLPI to FEE mode transition using an 4 MHz crystal KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 370 Freescale Semiconductor, Inc. Chapter 25 Oscillator (OSC) 25.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 25.2 Features and Modes Key features of the module are: * Supports 32 kHz crystals (Low Range mode) * Voltage and frequency filtering to guarantee clock frequency and stability * Optionally external input bypass clock from EXTAL signal directly * One clock for MCU clock system * Two clocks for on-chip peripherals that can work in Stop modes Functional Description describes the module's operation in more detail. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 371 Block Diagram 25.3 Block Diagram The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals. Three clocks are output from OSC module: OSCCLK for MCU system, OSCERCLK for on-chip peripherals, and OSC32KCLK. The OSCCLK can only work in run mode. OSCERCLK and OSC32KCLK can work in low power modes. For the clock source assignments, refer to the clock distribution information of this MCU. Refer to the chip configuration chapter for the external reference clock source in this MCU. The following figure shows the block diagram of the OSC module. EXTAL XTAL OSC_CLK_OUT Mux OSC Clock Enable ERCLKEN XTL_CLK Oscillator Circuits OSCERCLK EN OSC32KCLK ERCLKEN OSC clock selection EREFSTEN OSC_EN 4096 Counter CNT_DONE_4096 Control and Decoding logic OSCCLK STOP Figure 25-1. OSC Module Block Diagram 25.4 OSC Signal Descriptions The following table shows the user-accessible signals available for the OSC module. Refer to signal multiplexing information for this MCU for more details. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 372 Freescale Semiconductor, Inc. Chapter 25 Oscillator (OSC) Table 25-1. OSC Signal Descriptions Signal Description EXTAL External clock/Oscillator input I Oscillator output O XTAL I/O 25.5 External Crystal / Resonator Connections The connections for a crystal/resonator frequency reference are shown in the following figures. When using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself. In the other oscillator modes, load capacitors (Cx, Cy) and feedback resistor (RF) are required. The following table shows all possible connections. Table 25-2. External Caystal/Resonator Connections Oscillator Mode Connections Low-frequency (32 kHz), low-power Connection 11 Low-frequency (32 kHz), high-gain Connection 2/Connection 32 High-frequency (3~32 MHz), low-power Connection 31 High-frequency (3~32 MHz), high-gain Connection 3 1. With the low-power mode, the oscillator has the internal feedback resistor RF. Therefore, the feedback resistor must not be externally with the Connection 3. 2. When the load capacitors (Cx, Cy) are greater than 30 pF, use Connection 3. OSC XTAL VSS EXTAL Crystal or Resonator Figure 25-2. Crystal/Ceramic Resonator Connections - Connection 1 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 373 External Clock Connections OSC XTAL EXTAL VSS RF Crystal or Resonator Figure 25-3. Crystal/Ceramic Resonator Connections - Connection 2 NOTE Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits. OSC XTAL EXTAL VSS Cx Cy RF Crystal or Resonator Figure 25-4. Crystal/Ceramic Resonator Connections - Connection 3 25.6 External Clock Connections In external clock mode, the pins can be connected as shown below. NOTE XTAL can be used as a GPIO when the GPIO alternate function is configured for it. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 374 Freescale Semiconductor, Inc. Chapter 25 Oscillator (OSC) OSC XTAL EXTAL VSS Clock Input I/O Figure 25-5. External Clock Connections 25.7 Memory Map/Register Definitions Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM. 25.7.1 OSC Memory Map/Register Definition OSC memory map Absolute address (hex) 4006_5000 Width Access (in bits) Register name OSC Control Register (OSC0_CR) 8 Reset value Section/ page 00h 25.71.1/375 R/W 25.71.1 OSC Control Register (OSCx_CR) NOTE After OSC is enabled and starts generating the clocks, the configurations such as low power and frequency range, must not be changed. Address: 4006_5000h base + 0h offset = 4006_5000h Bit Read Write Reset 7 6 ERCLKEN 0 0 0 5 3 2 1 0 EREFSTEN 0 4 SC2P SC4P SC8P SC16P 0 0 0 0 0 0 OSCx_CR field descriptions Field 7 ERCLKEN Description External Reference Enable Enables external reference clock (OSCERCLK). Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 375 Functional Description OSCx_CR field descriptions (continued) Field Description 0 1 6 Reserved 5 EREFSTEN This field is reserved. This read-only field is reserved and always has the value 0. External Reference Stop Enable Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode. 0 1 4 Reserved 3 SC2P Oscillator 2 pF Capacitor Load Configure Configures the oscillator load. Configures the oscillator load. Disable the selection. Add 4 pF capacitor to the oscillator load. Oscillator 8 pF Capacitor Load Configure Configures the oscillator load. 0 1 0 SC16P Disable the selection. Add 2 pF capacitor to the oscillator load. Oscillator 4 pF Capacitor Load Configure 0 1 1 SC8P External reference clock is disabled in Stop mode. External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. This field is reserved. This read-only field is reserved and always has the value 0. 0 1 2 SC4P External reference clock is inactive. External reference clock is enabled. Disable the selection. Add 8 pF capacitor to the oscillator load. Oscillator 16 pF Capacitor Load Configure Configures the oscillator load. 0 1 Disable the selection. Add 16 pF capacitor to the oscillator load. 25.8 Functional Description This following sections provide functional details of the module. 25.8.1 OSC Module States The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 376 Freescale Semiconductor, Inc. Chapter 25 Oscillator (OSC) Off Oscillator OFF OSC_CLK_OUT = Static OSCCLK not requested OSCCLK requested OSCCLK requested && && Select OSC internal clock Select clock from EXTAL signal Start-Up External Clock Mode Oscillator ON, not yet stable OSC_CLK_OUT = Static Oscillator ON OSC_CLK_OUT = EXTAL CNT_DONE_4096 Stable Oscillator ON, Stable OSC_CLK_OUT = XTL_CLK Figure 25-8. OSC Module State Diagram NOTE XTL_CLK is the clock generated internally from OSC circuits. 25.8.1.1 Off The OSC enters the Off state when the system does not require OSC clocks. Upon entering this state, XTL_CLK is static unless OSC is configured to select the clock from the EXTAL pad by clearing the external reference clock selection bit. For details regarding the external reference clock source in this MCU, refer to the chip configuration chapter. The EXTAL and XTAL pins are also decoupled from all other oscillator circuitry in this state. The OSC module circuitry is configured to draw minimal current. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 377 Functional Description 25.8.1.2 Oscillator Start-Up The OSC enters start-up state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized. When the oscillation amplitude becomes large enough to pass through the input buffer, XTL_CLK begins clocking the counter. When the counter reaches 4096 cycles of XTL_CLK, the oscillator is considered stable and XTL_CLK is passed to the output clock OSC_CLK_OUT. 25.8.1.3 Oscillator Stable The OSC enters stable state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit and the counter reaches 4096 cycles of XTL_CLK (when CNT_DONE_4096 is high). In this state, the OSC module is producing a stable output clock on OSC_CLK_OUT. Its frequency is determined by the external components being used. 25.8.1.4 External Clock Mode The OSC enters external clock state when it is enabled and external reference clock selection bit is cleared. For details regarding external reference clock source in this MCU, refer to the chip configuration chapter. In this state, the OSC module is set to buffer (with hysteresis) a clock from EXTAL onto the OSC_CLK_OUT. Its frequency is determined by the external clock being supplied. 25.8.2 OSC Module Modes The OSC is a Pierce-type oscillator that supports external crystals or resonators operating over the frequency ranges shown in Table 25-7. These modes assume the following conditions: OSC is enabled to generate clocks (OSC_EN=1), configured to generate clocks internally (MCG_C2[EREFS] = 1), and some or one of the other peripherals (MCG, Timer, and so on) is configured to use the oscillator output clock (OSC_CLK_OUT). Table 25-7. Oscillator Modes Mode Frequency Range Low-frequency, low-power (VLP) fosc_lo (1 kHz) up to fosc_lo (32.768 kHz) KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 378 Freescale Semiconductor, Inc. Chapter 25 Oscillator (OSC) NOTE For information about low power modes of operation used in this chip and their alignment with some OSC modes, refer to the chip's Power Management details. 25.8.2.1 Low-Frequency, Low-Power Mode In low-frequency, low-power mode, the oscillator uses a gain control loop to minimize power consumption. As the oscillation amplitude increases, the amplifier current is reduced. This continues until a desired amplitude is achieved at steady-state. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used, the internal feedback resistor is connected, and no external resistor should be used. In this mode, the amplifier inputs, gain-control input, and input buffer input are all capacitively coupled for leakage tolerance (not sensitive to the DC level of EXTAL). Also in this mode, all external components except for the resonator itself are integrated, which includes the load capacitors and feeback resistor that biases EXTAL. 25.8.3 Counter The oscillator output clock (OSC_CLK_OUT) is gated off until the counter has detected 4096 cycles of its input clock (XTL_CLK). After 4096 cycles are completed, the counter passes XTL_CLK onto OSC_CLK_OUT. This counting time-out is used to guarantee output clock stability. 25.8.4 Reference Clock Pin Requirements The OSC module requires use of both the EXTAL and XTAL pins to generate an output clock in Oscillator mode, but requires only the EXTAL pin in External clock mode. The EXTAL and XTAL pins are available for I/O. For the implementation of these pins on this device, refer to the Signal Multiplexing chapter. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 379 Reset 25.9 Reset There is no reset state associated with the OSC module. The counter logic is reset when the OSC is not configured to generate clocks. There are no sources of reset requests for the OSC module. 25.10 Low Power Modes Operation When the MCU enters Stop modes, the OSC is functional depending on ERCLKEN and EREFSETN bit settings. If both these bits are set, the OSC is in operation. In Low Leakage Stop (LLS) modes, the OSC holds all register settings. If ERCLKEN and EREFSTEN bits are set before entry to Low Leakage Stop modes, the OSC is still functional in these modes. After waking up from Very Low Leakage Stop (VLLSx) modes, all OSC register bits are reset and initialization is required through software. 25.11 Interrupts The OSC module does not generate any interrupts. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 380 Freescale Semiconductor, Inc. Chapter 26 Flash Memory Controller (FMC) 26.1 Introduction The Flash Memory Controller (FMC) is a memory acceleration unit that provides: * an interface between bus masters and the 32-bit program flash memory. * a buffer and a cache that can accelerate program flash memory data transfers. 26.1.1 Overview The Flash Memory Controller manages the interface between bus masters and the 32-bit program flash memory. The FMC receives status information detailing the configuration of the flash memory and uses this information to ensure a proper interface. The FMC supports 8-bit, 16-bit, and 32-bit read operations from the program flash memory. A write operation to program flash memory results in a bus error. In addition, the FMC provides two separate mechanisms for accelerating the interface between bus masters and program flash memory. A 32-bit speculation buffer can prefetch the next 32-bit flash memory location, and a 4-way, 4-set program flash memory cache can store previously accessed program flash memory data for quick access times. 26.1.2 Features The FMC's features include: * Interface between bus masters and the 32-bit program flash memory: * 8-bit, 16-bit, and 32-bit read operations to nonvolatile flash memory. * Acceleration of data transfer from the program flash memory to the device: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 381 Modes of operation * 32-bit prefetch speculation buffer for program flash accesses with controls for instruction/data access * 4-way, 4-set, 32-bit line size program flash memory cache for a total of sixteen 32-bit entries with invalidation control 26.2 Modes of operation The FMC operates only when a bus master accesses the program flash memory. In terms of chip power modes: * The FMC operates only in run and wait modes, including VLPR and VLPW modes. * For any power mode where the program flash memory cannot be accessed, the FMC is disabled. 26.3 External signal description The FMC has no external (off-chip) signals. 26.4 Memory map and register descriptions The MCM's programming model provides control and configuration of the FMC's features. For details, see the description of the MCM's Platform Control Register (PLACR). 26.5 Functional description The FMC is a flash acceleration unit with flexible buffers for user configuration. Besides managing the interface between bus masters and the program flash memory, the FMC can be used to customize the program flash memory cache and buffer to provide single-cycle system clock data access times. Whenever a hit occurs for the prefetch speculation buffer or the cache (when enabled), the requested data is transferred within a single system clock. Upon system reset, the FMC is configured as follows: * Flash cache is enabled * Instruction speculation and caching are enabled KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 382 Freescale Semiconductor, Inc. Chapter 26 Flash Memory Controller (FMC) * Data speculation is disabled * Data caching is enabled Though the default configuration provides flash acceleration, advanced users may desire to customize the FMC buffer configurations to maximize throughput for their use cases. For example, the user may adjust the controls to enable buffering per access type (data or instruction). NOTE When reconfiguring the FMC, do not program the control and configuration inputs to the FMC while the program flash memory is being accessed. Instead, change them with a routine executing from RAM in supervisor mode. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 383 Functional description KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 384 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) 27.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The flash memory module includes the following accessible memory regions: * Program flash memory for vector space and code store Flash memory is ideal for single-supply applications, permitting in-the-field erase and reprogramming operations without the need for any external high voltage power sources. The flash memory module includes a memory controller that executes commands to modify flash memory contents. An erased bit reads '1' and a programmed bit reads '0'. The programming operation is unidirectional; it can only move bits from the '1' state (erased) to the '0' state (programmed). Only the erase operation restores bits from '0' to '1'; bits cannot be programmed from a '0' to a '1'. CAUTION A flash memory location must be in the erased state before being programmed. Cumulative programming of bits (back-toback program operations without an intervening erase) within a flash memory location is not allowed. Re-programming of existing 0s to 0 is not allowed as this overstresses the device. The standard shipping condition for flash memory is erased with security disabled. Data loss over time may occur due to degradation of the erased ('1') states and/or programmed ('0') states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 385 Introduction 27.1.1 Features The flash memory module includes the following features. NOTE See the device's Chip Configuration details for the exact amount of flash memory available on your device. 27.1.1.1 Program Flash Memory Features * Sector size of 1 Kbyte * Program flash protection scheme prevents accidental program or erase of stored data * Automated, built-in, program and erase algorithms with verify 27.1.1.2 Other Flash Memory Module Features * Internal high-voltage supply generator for flash memory program and erase operations * Optional interrupt generation upon flash command completion * Supports MCU security mechanisms which prevent unauthorized access to the flash memory contents 27.1.2 Block Diagram The block diagram of the flash memory module is shown in the following figure. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 386 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) Interrupt Status registers Register access Memory controller Program flash 0 Control registers To MCU's flash controller Figure 27-1. Flash Block Diagram 27.1.3 Glossary Command write sequence -- A series of MCU writes to the flash FCCOB register group that initiates and controls the execution of flash algorithms that are built into the flash memory module. Endurance -- The number of times that a flash memory location can be erased and reprogrammed. FCCOB (Flash Common Command Object) -- A group of flash registers that are used to pass command, address, data, and any associated parameters to the memory controller in the flash memory module. Flash block -- A macro within the flash memory module which provides the nonvolatile memory storage. Flash Memory Module -- All flash blocks plus a flash management unit providing high-level control and an interface to MCU buses. IFR -- Nonvolatile information register found in each flash block, separate from the main memory array. NVM -- Nonvolatile memory. A memory technology that maintains stored data during power-off. The flash array is an NVM using NOR-type flash memory technology. NVM Normal Mode -- An NVM mode that provides basic user access to flash memory module resources. The CPU or other bus masters initiate flash program and erase operations (or other flash commands) using writes to the FCCOB register group in the flash memory module. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 387 External Signal Description NVM Special Mode -- An NVM mode enabling external, off-chip access to the memory resources in the flash memory module. A reduced flash command set is available when the MCU is secured. See the Chip Configuration details for information on when this mode is used. Longword -- 32 bits of data with an aligned longword having byte-address[1:0] = 00. Word -- 16 bits of data with an aligned word having byte-address[0] = 0. Program flash -- The program flash memory provides nonvolatile storage for vectors and code store. Program flash Sector -- The smallest portion of the program flash memory (consecutive addresses) that can be erased. Retention -- The length of time that data can be kept in the NVM without experiencing errors upon readout. Since erased (1) states are subject to degradation just like programmed (0) states, the data retention limit may be reached from the last erase operation (not from the programming time). RWW-- Read-While-Write. The ability to simultaneously read from one memory resource while commanded operations are active in another memory resource. Secure -- An MCU state conveyed to the flash memory module as described in the Chip Configuration details for this device. In the secure state, reading and changing NVM contents is restricted. 27.2 External Signal Description The flash memory module contains no signals that connect off-chip. 27.3 Memory Map and Registers This section describes the memory map and registers for the flash memory module. Data read from unimplemented memory space in the flash memory module is undefined. Writes to unimplemented or reserved memory space (registers) in the flash memory module are ignored. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 388 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) 27.3.1 Flash Configuration Field Description The program flash memory contains a 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the flash memory module. Flash Configuration Field Byte Address Size (Bytes) Field Description 0x0_0400 - 0x0_0407 8 Backdoor Comparison Key. Refer to Verify Backdoor Access Key Command and Unsecuring the Chip Using Backdoor Key Access. 0x0_0408 - 0x0_040B 4 Program flash protection bytes. Refer to the description of the Program Flash Protection Registers (FPROT0-3). 0x0_040F 1 Reserved 0x0_040E 1 Reserved 0x0_040D 1 Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT). 0x0_040C 1 Flash security byte. Refer to the description of the Flash Security Register (FSEC). 27.3.2 Program Flash IFR Map The program flash IFR is nonvolatile information memory that can be read freely, but the user has no erase and limited program capabilities (see the Read Once, Program Once, and Read Resource commands in Read Once Command, Program Once Command and Read Resource Command). The contents of the program flash IFR are summarized in the following table and further described in the subsequent paragraphs. The program flash IFR is located within the program flash 0 memory block. Address Range Size (Bytes) Field Description 0x00 - 0xBF 192 Reserved 0xC0 - 0xFF 64 Program Once Field 27.3.2.1 Program Once Field The Program Once Field in the program flash IFR provides 64 bytes of user data storage separate from the program flash main array. The user can program the Program Once Field one time only as there is no program flash IFR erase mechanism available to the KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 389 Memory Map and Registers user. The Program Once Field can be read any number of times. This section of the program flash IFR is accessed in 4-Byte records using the Read Once and Program Once commands (see Read Once Command and Program Once Command). 27.3.3 Register Descriptions The flash memory module contains a set of memory-mapped control and status registers. NOTE While a command is running (FSTAT[CCIF]=0), register writes are not accepted to any register except FCNFG and FSTAT. The no-write rule is relaxed during the start-up reset sequence, prior to the initial rise of CCIF. During this initialization period the user may write any register. All register writes are also disabled (except for registers FCNFG and FSTAT) whenever an erase suspend request is active (FCNFG[ERSSUSP]=1). FTFA memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_0000 Flash Status Register (FTFA_FSTAT) 8 R/W 00h 27.33.1/391 4002_0001 Flash Configuration Register (FTFA_FCNFG) 8 R/W 00h 27.33.2/392 4002_0002 Flash Security Register (FTFA_FSEC) 8 R Undefined 27.33.3/394 4002_0003 Flash Option Register (FTFA_FOPT) 8 R Undefined 27.33.4/395 4002_0004 Flash Common Command Object Registers (FTFA_FCCOB3) 8 R/W 00h 27.33.5/396 4002_0005 Flash Common Command Object Registers (FTFA_FCCOB2) 8 R/W 00h 27.33.5/396 4002_0006 Flash Common Command Object Registers (FTFA_FCCOB1) 8 R/W 00h 27.33.5/396 4002_0007 Flash Common Command Object Registers (FTFA_FCCOB0) 8 R/W 00h 27.33.5/396 4002_0008 Flash Common Command Object Registers (FTFA_FCCOB7) 8 R/W 00h 27.33.5/396 4002_0009 Flash Common Command Object Registers (FTFA_FCCOB6) 8 R/W 00h 27.33.5/396 4002_000A Flash Common Command Object Registers (FTFA_FCCOB5) 8 R/W 00h 27.33.5/396 4002_000B Flash Common Command Object Registers (FTFA_FCCOB4) 8 R/W 00h 27.33.5/396 4002_000C Flash Common Command Object Registers (FTFA_FCCOBB) 8 R/W 00h 27.33.5/396 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 390 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) FTFA memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4002_000D Flash Common Command Object Registers (FTFA_FCCOBA) 8 R/W 00h 27.33.5/396 4002_000E Flash Common Command Object Registers (FTFA_FCCOB9) 8 R/W 00h 27.33.5/396 4002_000F Flash Common Command Object Registers (FTFA_FCCOB8) 8 R/W 00h 27.33.5/396 4002_0010 Program Flash Protection Registers (FTFA_FPROT3) 8 R/W Undefined 27.33.6/397 4002_0011 Program Flash Protection Registers (FTFA_FPROT2) 8 R/W Undefined 27.33.6/397 4002_0012 Program Flash Protection Registers (FTFA_FPROT1) 8 R/W Undefined 27.33.6/397 4002_0013 Program Flash Protection Registers (FTFA_FPROT0) 8 R/W Undefined 27.33.6/397 27.33.1 Flash Status Register (FTFA_FSTAT) The FSTAT register reports the operational status of the flash memory module. The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. NOTE When set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this register prevent the launch of any more commands until the flag is cleared (by writing a one to it). Address: 4002_0000h base + 0h offset = 4002_0000h Bit 7 6 5 4 3 Read CCIF RDCOLERR ACCERR FPVIOL Write w1c w1c w1c w1c Reset 0 0 0 0 2 1 0 0 0 0 MGSTAT0 0 0 FTFA_FSTAT field descriptions Field 7 CCIF Description Command Complete Interrupt Flag The CCIF flag indicates that a flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command, and CCIF stays low until command completion or command violation. The CCIF bit is reset to 0 but is set to 1 by the memory controller at the end of the reset initialization sequence. Depending on how quickly the read occurs after reset release, the user may or may not see the 0 hardware reset value. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 391 Memory Map and Registers FTFA_FSTAT field descriptions (continued) Field Description 0 1 6 RDCOLERR Flash Read Collision Error Flag The RDCOLERR error bit indicates that the MCU attempted a read from a flash memory resource that was being manipulated by a flash command (CCIF=0). Any simultaneous access is detected as a collision error by the block arbitration logic. The read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by writing a 1 to it. Writing a 0 to RDCOLERR has no effect. 0 1 5 ACCERR No collision error detected Collision error detected Flash Access Error Flag The ACCERR error bit indicates an illegal access has occurred to a flash memory resource caused by a violation of the command write sequence or issuing an illegal flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the ACCERR bit has no effect. 0 1 4 FPVIOL Flash command in progress Flash command has completed No access error detected Access error detected Flash Protection Violation Flag The FPVIOL error bit indicates an attempt was made to program or erase an address in a protected area of program flash memory during a command write sequence . While FPVIOL is set, the CCIF flag cannot be cleared to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a 0 to the FPVIOL bit has no effect. 0 1 No protection violation detected Protection violation detected 3-1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 MGSTAT0 Memory Controller Command Completion Status Flag The MGSTAT0 status flag is set if an error is detected during execution of a flash command or during the flash reset sequence. As a status flag, this bit cannot (and need not) be cleared by the user like the other error flags in this register. The value of the MGSTAT0 bit for "command-N" is valid only at the end of the "command-N" execution when CCIF=1 and before the next command has been launched. At some point during the execution of "command-N+1," the previous result is discarded and any previous error is cleared. 27.33.2 Flash Configuration Register (FTFA_FCNFG) This register provides information on the current functional state of the flash memory module. The erase control bits (ERSAREQ and ERSSUSP) have write restrictions. The unassigned bits read as noted and are not writable. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 392 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) Address: 4002_0000h base + 1h offset = 4002_0001h Bit Read Write Reset 7 6 5 CCIE RDCOLLIE 0 0 ERSAREQ 0 4 ERSSUSP 0 3 2 1 0 0 0 0 0 0 0 0 0 FTFA_FCNFG field descriptions Field 7 CCIE Description Command Complete Interrupt Enable The CCIE bit controls interrupt generation when a flash command completes. 0 1 6 RDCOLLIE Read Collision Error Interrupt Enable The RDCOLLIE bit controls interrupt generation when a flash memory read collision error occurs. 0 1 5 ERSAREQ Command complete interrupt disabled Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. Read collision error interrupt disabled Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]). Erase All Request This bit issues a request to the memory controller to execute the Erase All Blocks command and release security. ERSAREQ is not directly writable but is under indirect user control. Refer to the device's Chip Configuration details on how to request this command. The ERSAREQ bit sets when an erase all request is triggered external to the flash memory module and CCIF is set (no command is currently being executed). ERSAREQ is cleared by the flash memory module when the operation completes. 0 1 4 ERSSUSP No request or request complete Request to: 1. run the Erase All Blocks command, 2. verify the erased state, 3. program the security byte in the Flash Configuration Field to the unsecure state, and 4. release MCU security by setting the FSEC[SEC] field to the unsecure state. Erase Suspend The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector command while it is executing. 0 1 No suspend requested Suspend the current Erase Flash Sector command execution. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 393 Memory Map and Registers 27.33.3 Flash Security Register (FTFA_FSEC) This read-only register holds all bits associated with the security of the MCU and flash memory module. During the reset sequence, the register is loaded with the contents of the flash security byte in the Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value. Address: 4002_0000h base + 2h offset = 4002_0002h Bit 7 Read 6 5 KEYEN 4 3 MEEN 2 1 FSLACC 0 SEC Write Reset x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. FTFA_FSEC field descriptions Field 7-6 KEYEN Description Backdoor Key Security Enable These bits enable and disable backdoor key access to the flash memory module. 00 01 10 11 5-4 MEEN Mass Erase Enable Bits Enables and disables mass erase capability of the flash memory module. The state of the MEEN bits is only relevant when the SEC bits are set to secure outside of NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does not matter. 00 01 10 11 3-2 FSLACC Backdoor key access disabled Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) Backdoor key access enabled Backdoor key access disabled Mass erase is enabled Mass erase is enabled Mass erase is disabled Mass erase is enabled Freescale Failure Analysis Access Code These bits enable or disable access to the flash memory contents during returned part failure analysis at Freescale. When SEC is secure and FSLACC is denied, access to the program flash contents is denied and any failure analysis performed by Freescale factory test must begin with a full erase to unsecure the part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is granted), Freescale factory testing has visibility of the current flash contents. The state of the FSLACC bits is only relevant when the SEC bits are set to secure. When the SEC field is set to unsecure, the FSLACC setting does not matter. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 394 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) FTFA_FSEC field descriptions (continued) Field Description 00 01 10 11 1-0 SEC Freescale factory access granted Freescale factory access denied Freescale factory access denied Freescale factory access granted Flash Security These bits define the security state of the MCU. In the secure state, the MCU limits access to flash memory module resources. The limitations are defined per device and are detailed in the Chip Configuration details. If the flash memory module is unsecured using backdoor key access, the SEC bits are forced to 10b. 00 01 10 11 MCU security status is secure MCU security status is secure MCU security status is unsecure (The standard shipping condition of the flash memory module is unsecure.) MCU security status is secure 27.33.4 Flash Option Register (FTFA_FOPT) The flash option register allows the MCU to customize its operations by examining the state of these read-only bits, which are loaded from NVM at reset. The function of the bits is defined in the device's Chip Configuration details. All bits in the register are read-only . During the reset sequence, the register is loaded from the flash nonvolatile option byte in the Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value. Address: 4002_0000h base + 3h offset = 4002_0003h Bit 7 6 5 4 Read 3 2 1 0 x* x* x* x* OPT Write Reset x* x* x* x* * Notes: * x = Undefined at reset. FTFA_FOPT field descriptions Field 7-0 OPT Description Nonvolatile Option These bits are loaded from flash to this register at reset. Refer to the device's Chip Configuration details for the definition and use of these bits. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 395 Memory Map and Registers 27.33.5 Flash Common Command Object Registers (FTFA_FCCOBn) The FCCOB register group provides 12 bytes for command codes and parameters. The individual bytes within the set append a 0-B hex identifier to the FCCOB register name: FCCOB0, FCCOB1, ..., FCCOBB. Address: 4002_0000h base + 4h offset + (1d x i), where i=0d to 11d Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 CCOBn 0 0 0 0 FTFA_FCCOBn field descriptions Field Description 7-0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller. The individual registers that compose the FCCOB data set can be written in any order, but you must provide all needed values, which vary from command to command. First, set up all required FCCOB fields and then initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed by the user until the command completes (CCIF returns to 1). No command buffering or queueing is provided; the next command can be loaded only after the current command completes. Some commands return information to the FCCOB registers. Any values returned to FCCOB are available for reading after the FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a generic flash command format. The first FCCOB register, FCCOB0, always contains the command code. This 8-bit value defines the command to be executed. The command code is followed by the parameters required for this specific flash command, typically an address and/or data values. NOTE: The command parameter table is written in terms of FCCOB Number (which is equivalent to the byte number). This number is a reference to the FCCOB register name and is not the register address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 396 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) FTFA_FCCOBn field descriptions (continued) Field Description FCCOB Number Typical Command Parameter Contents [7:0] A Data Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access : The FCCOB register group uses a big endian addressing convention. For all command parameter fields larger than 1 byte, the most significant data resides in the lowest FCCOB register number. The FCCOB register group may be read and written as individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes). 27.33.6 Program Flash Protection Registers (FTFA_FPROTn) The FPROT registers define which logical program flash regions are protected from program and erase operations. Protected flash regions cannot have their content changed; that is, these regions cannot be programmed and cannot be erased by any flash command. Unprotected regions can be changed by program and erase operations. The four FPROT registers allow up to 32 protectable regions. Each bit protects a 1/32 region of the program flash memory except for memory configurations with less than 32 Kbytes of program flash where each assigned bit protects 1 Kbyte . For configurations with 24 Kbytes of program flash memory or less, FPROT0 is not used. For configurations with 16 Kbytes of program flash memory or less, FPROT1 is not used. For configurations with 8 Kbytes of program flash memory, FPROT2 is not used. The bitfields are defined in each register as follows: Program flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the FPROT registers are loaded with the contents of the program flash protection bytes in the Flash Configuration Field as indicated in the following table. Program flash protection register Flash Configuration Field offset address FPROT0 0x000B FPROT1 0x000A Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 397 Functional Description Program flash protection register Flash Configuration Field offset address FPROT2 0x0009 FPROT3 0x0008 To change the program flash protection that is loaded during the reset sequence, unprotect the sector of program flash memory that contains the Flash Configuration Field. Then, reprogram the program flash protection byte. Address: 4002_0000h base + 10h offset + (1d x i), where i=0d to 3d Bit Read Write Reset 7 6 5 4 3 2 1 0 x* x* x* x* PROT x* x* x* x* * Notes: * x = Undefined at reset. FTFA_FPROTn field descriptions Field 7-0 PROT Description Program Flash Region Protect Each program flash region can be protected from program and erase operations by setting the associated PROT bit. In NVM Normal mode: The protection can only be increased, meaning that currently unprotected memory can be protected, but currently protected memory cannot be unprotected. Since unprotected regions are marked with a 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are writable without restriction. Unprotected areas can be protected and protected areas can be unprotected. Restriction: The user must never write to any FPROT register while a command is running (CCIF=0). Trying to alter data in any protected area in the program flash memory results in a protection violation error and sets the FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible if it contains any protected region. Each bit in the 32-bit protection register represents 1/32 of the total program flash except for configurations where program flash memory is less than 32 Kbytes. For configurations with less than 32 Kbytes of program flash memory, each assigned bit represents 1 Kbyte. 0 1 Program flash region is protected. Program flash region is not protected 27.4 Functional Description The following sections describe functional details of the flash memory module. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 398 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) 27.4.1 Flash Protection Individual regions within the flash memory can be protected from program and erase operations. Protection is controlled by the following registers: * FPROTn -- Four registers that protect 32 regions of the program flash memory as shown in the following figure Program flash 0x0_0000 Last program flash address Program flash size / 32 FPROT3[PROT0] Program flash size / 32 FPROT3[PROT1] Program flash size / 32 FPROT3[PROT2] Program flash size / 32 FPROT3[PROT3] Program flash size / 32 FPROT0[PROT29] Program flash size / 32 FPROT0[PROT30] Program flash size / 32 FPROT0[PROT31] Figure 27-24. Program flash protection 27.4.2 Interrupts The flash memory module can generate interrupt requests to the MCU upon the occurrence of various flash events. These interrupt events and their associated status and control bits are shown in the following table. Table 27-24. Flash Interrupt Sources Flash Event Readable Interrupt Status Bit Enable Bit Flash Command Complete FSTAT[CCIF] FCNFG[CCIE] Flash Read Collision Error FSTAT[RDCOLERR] FCNFG[RDCOLLIE] KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 399 Functional Description Note Vector addresses and their relative interrupt priority are determined at the MCU level. Some devices also generate a bus error response as a result of a Read Collision Error event. See the chip configuration information to determine if a bus error response is also supported. 27.4.3 Flash Operation in Low-Power Modes 27.4.3.1 Wait Mode When the MCU enters wait mode, the flash memory module is not affected. The flash memory module can recover the MCU from wait via the command complete interrupt (see Interrupts). 27.4.3.2 Stop Mode When the MCU requests stop mode, if a flash command is active (CCIF = 0) the command execution completes before the MCU is allowed to enter stop mode. CAUTION The MCU should never enter stop mode while any flash command is running (CCIF = 0). NOTE While the MCU is in very-low-power modes (VLPR, VLPW, VLPS), the flash memory module does not accept flash commands. 27.4.4 Functional Modes of Operation The flash memory module has two operating modes: NVM Normal and NVM Special. The operating mode affects the command set availability (see Table 27-25). Refer to the Chip Configuration details of this device for how to activate each mode. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 400 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) 27.4.5 Flash Reads and Ignored Writes The flash memory module requires only the flash address to execute a flash memory read. The MCU must not read from the flash memory while commands are running (as evidenced by CCIF=0) on that block. Read data cannot be guaranteed from a flash block while any command is processing within that block. The block arbitration logic detects any simultaneous access and reports this as a read collision error (see the FSTAT[RDCOLERR] bit). 27.4.6 Read While Write (RWW) The following simultaneous accesses are not allowed: * Reading from program flash memory space while a flash command is active (CCIF=0). 27.4.7 Flash Program and Erase All flash functions except read require the user to setup and launch a flash command through a series of peripheral bus writes. The user cannot initiate any further flash commands until notified that the current command has completed. The flash command structure and operation are detailed in Flash Command Operations. 27.4.8 Flash Command Operations Flash command operations are typically used to modify flash memory contents. The next sections describe: * The command write sequence used to set flash command parameters and launch execution * A description of all flash commands available KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 401 Functional Description 27.4.8.1 Command Write Sequence Flash commands are specified using a command write sequence illustrated in Figure 27-25. The flash memory module performs various checks on the command (FCCOB) content and continues with command execution if all requirements are fulfilled. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be zero and the CCIF flag must read 1 to verify that any previous command has completed. If CCIF is zero, the previous command execution is still active, a new command write sequence cannot be started, and all writes to the FCCOB registers are ignored. 27.4.8.1.1 Load the FCCOB Registers The user must load the FCCOB registers with all parameters required by the desired flash command. The individual registers that make up the FCCOB data set can be written in any order. 27.4.8.1.2 Launch the Command by Clearing CCIF Once all relevant command parameters have been loaded, the user launches the command by clearing the FSTAT[CCIF] bit by writing a '1' to it. The CCIF flag remains zero until the flash command completes. The FSTAT register contains a blocking mechanism that prevents a new command from launching (can't clear CCIF) if the previous command resulted in an access error (FSTAT[ACCERR]=1) or a protection violation (FSTAT[FPVIOL]=1). In error scenarios, two writes to FSTAT are required to initiate the next command: the first write clears the error flags, the second write clears CCIF. 27.4.8.1.3 Command Execution and Error Reporting The command processing has several steps: 1. The flash memory module reads the command code and performs a series of parameter checks and protection checks, if applicable, which are unique to each command. If the parameter check fails, the FSTAT[ACCERR] (access error) flag is set. ACCERR reports invalid instruction codes and out-of bounds addresses. Usually, access errors suggest that the command was not set-up with valid parameters in the FCCOB register group. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 402 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) Program and erase commands also check the address to determine if the operation is requested to execute on protected areas. If the protection check fails, the FSTAT[FPVIOL] (protection error) flag is set. Command processing never proceeds to execution when the parameter or protection step fails. Instead, command processing is terminated after setting the FSTAT[CCIF] bit. 2. If the parameter and protection checks pass, the command proceeds to execution. Run-time errors, such as failure to erase verify, may occur during the execution phase. Run-time errors are reported in the FSTAT[MGSTAT0] bit. A command may have access errors, protection errors, and run-time errors, but the run-time errors are not seen until all access and protection errors have been corrected. 3. Command execution results, if applicable, are reported back to the user via the FCCOB and FSTAT registers. 4. The flash memory module sets the FSTAT[CCIF] bit signifying that the command has completed. The flow for a generic command write sequence is illustrated in the following figure. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 403 Functional Description START Read: FSTAT register FCCOB Availability Check no CCIF = `1'? Previous command complete? yes Access Error and Protection Violation Check Results from previous command yes ACCERR/ FPVIOL Set? Clear the old errors Write 0x30 to FSTAT register no Write to the FCCOB registers to load the required command parameter. More Parameters? yes no Clear the CCIF to launch the command Write 0x80 to FSTAT register EXIT Figure 27-25. Generic Flash Command Write Sequence Flowchart 27.4.8.2 Flash Commands The following table summarizes the function of all flash commands. FCMD Command Program flash Function 0x01 Read 1s Section x Verify that a given number of program flash locations from a starting address are erased. 0x02 Program Check x Tests previously-programmed locations at margin read levels. 0x03 Read Resource IFR, ID Read 4 bytes from program flash IFR or version ID. 0x06 Program Longword x Program 4 bytes in a program flash block. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 404 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) FCMD Command Program flash Function 0x09 Erase Flash Sector x Erase all bytes in a program flash sector. 0x40 Read 1s All Blocks x Verify that the program flash block is erased then release MCU security. 0x41 Read Once IFR Read 4 bytes of a dedicated 64 byte field in the program flash 0 IFR. 0x43 Program Once IFR One-time program of 4 bytes of a dedicated 64-byte field in the program flash 0 IFR. 0x44 Erase All Blocks x Erase the program flash block, verify-erase and release MCU security. NOTE: 0x45 Verify Backdoor Access Key x An erase is only possible when all memory locations are unprotected. Release MCU security after comparing a set of usersupplied security keys to those stored in the program flash. 27.4.8.3 Flash Commands by Mode The following table shows the flash commands that can be executed in each flash operating mode. Table 27-25. Flash Commands by Mode FCMD Command 0x01 NVM Normal NVM Special Unsecure Secure MEEN=10 Unsecure Secure MEEN=10 Read 1s Section x x x x -- -- 0x02 Program Check x x x x -- -- 0x03 Read Resource x x x x -- -- 0x06 Program Longword x x x x -- -- 0x09 Erase Flash Sector x x x x -- -- 0x40 Read 1s All Blocks x x x x x -- 0x41 Read Once x x x x -- -- 0x43 Program Once x x x x -- -- 0x44 Erase All Blocks x x x x x -- 0x45 Verify Backdoor Access Key x x x x -- -- KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 405 Functional Description 27.4.9 Margin Read Commands The Read-1s commands (Read 1s All Blocks and Read 1s Section) and the Program Check command have a margin choice parameter that allows the user to apply nonstandard read reference levels to the program flash array reads performed by these commands. Using the preset 'user' and 'factory' margin levels, these commands perform their associated read operations at tighter tolerances than a 'normal' read. These nonstandard read levels are applied only during the command execution. All simple (uncommanded) flash array reads to the MCU always use the standard, un-margined, read reference level. Only the 'normal' read level should be employed during normal flash usage. The nonstandard, 'user' and 'factory' margin levels should be employed only in special cases. They can be used during special diagnostic routines to gain confidence that the device is not suffering from the end-of-life data loss customary of flash memory devices. Erased ('1') and programmed ('0') bit states can degrade due to elapsed time and data cycling (number of times a bit is erased and re-programmed). The lifetime of the erased states is relative to the last erase operation. The lifetime of the programmed states is measured from the last program time. The 'user' and 'factory' levels become, in effect, a minimum safety margin; i.e. if the reads pass at the tighter tolerances of the 'user' and 'factory' margins, then the 'normal' reads have at least this much safety margin before they experience data loss. The 'user' margin is a small delta to the normal read reference level. 'User' margin levels can be employed to check that flash memory contents have adequate margin for normal level read operations. If unexpected read results are encountered when checking flash memory contents at the 'user' margin levels, loss of information might soon occur during 'normal' readout. The 'factory' margin is a bigger deviation from the norm, a more stringent read criteria that should only be attempted immediately (or very soon) after completion of an erase or program command, early in the cycling life. 'Factory' margin levels can be used to check that flash memory contents have adequate margin for long-term data retention at the normal level setting. If unexpected results are encountered when checking flash memory contents at 'factory' margin levels, the flash memory contents should be erased and reprogrammed. CAUTION Factory margin levels must only be used during verify of the initial factory programming. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 406 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) 27.4.10 Flash Command Description This section describes all flash commands that can be launched by a command write sequence. The flash memory module sets the FSTAT[ACCERR] bit and aborts the command execution if any of the following illegal conditions occur: * There is an unrecognized command code in the FCCOB FCMD field. * There is an error in a FCCOB field for the specific commands. Refer to the error handling table provided for each command. Ensure that the ACCERR and FPVIOL bits in the FSTAT register are cleared prior to starting the command write sequence. As described in Launch the Command by Clearing CCIF, a new command cannot be launched while these error flags are set. Do not attempt to read a flash block while the flash memory module is running a command (CCIF = 0) on that same block. The flash memory module may return invalid data to the MCU with the collision error flag (FSTAT[RDCOLERR]) set. CAUTION Flash data must be in the erased state before being programmed. Cumulative programming of bits (adding more zeros) is not allowed. 27.4.10.1 Read 1s Section Command The Read 1s Section command checks if a section of program flash memory is erased to the specified read margin level. The Read 1s Section command defines the starting address and the number of longwords to be verified. Table 27-26. Read 1s Section Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x01 (RD1SEC) 1 Flash address [23:16] of the first longword to be verified 2 Flash address [15:8] of the first longword to be verified 3 Flash address [7:0]1 of the first longword to be verified 4 Number of longwords to be verified [15:8] 5 Number of longwords to be verified [7:0] 6 Read-1 Margin Choice 1. Must be longword aligned (Flash address [1:0] = 00). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 407 Functional Description Upon clearing CCIF to launch the Read 1s Section command, the flash memory module sets the read margin for 1s according to Table 27-27 and then reads all locations within the specified section of flash memory. If the flash memory module fails to read all 1s (i.e. the flash section is not erased), the FSTAT[MGSTAT0] bit is set. The CCIF flag sets after the Read 1s Section operation completes. Table 27-27. Margin Level Choices for Read 1s Section Read Margin Choice Margin Level Description 0x00 Use the 'normal' read level for 1s 0x01 Apply the 'User' margin to the normal read-1 level 0x02 Apply the 'Factory' margin to the normal read-1 level Table 27-28. Read 1s Section Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin code is supplied FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] The requested section crosses a Flash block boundary FSTAT[ACCERR] The requested number of longwords is zero FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] 27.4.10.2 Program Check Command The Program Check command tests a previously programmed program flash longword to see if it reads correctly at the specified margin level. Table 27-29. Program Check Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x02 (PGMCHK) 1 Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0]1 4 Margin Choice 8 Byte 0 expected data 9 Byte 1 expected data A Byte 2 expected data B Byte 3 expected data 1. Must be longword aligned (Flash address [1:0] = 00). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 408 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) Upon clearing CCIF to launch the Program Check command, the flash memory module sets the read margin for 1s according to Table 27-30, reads the specified longword, and compares the actual read data to the expected data provided by the FCCOB. If the comparison at margin-1 fails, the FSTAT[MGSTAT0] bit is set. The flash memory module then sets the read margin for 0s, re-reads, and compares again. If the comparison at margin-0 fails, the FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Program Check operation completes. The supplied address must be longword aligned (the lowest two bits of the byte address must be 00): * Byte 3 data is written to the supplied byte address ('start'), * Byte 2 data is programmed to byte address start+0b01, * Byte 1 data is programmed to byte address start+0b10, * Byte 0 data is programmed to byte address start+0b11. NOTE See the description of margin reads, Margin Read Commands Table 27-30. Margin Level Choices for Program Check Read Margin Choice Margin Level Description 0x01 Read at 'User' margin-1 and 'User' margin-0 0x02 Read at 'Factory' margin-1 and 'Factory' margin-0 Table 27-31. Program Check Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] An invalid margin choice is supplied FSTAT[ACCERR] Either of the margin reads does not match the expected data FSTAT[MGSTAT0] 27.4.10.3 Read Resource Command The Read Resource command allows the user to read data from special-purpose memory resources located within the flash memory module. The special-purpose memory resources available include program flash IFR space and the Version ID field. Each resource is assigned a select code as shown in Table 27-33. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 409 Functional Description Table 27-32. Read Resource Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x03 (RDRSRC) 1 Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0]1 Returned Values 4 Read Data [31:24] 5 Read Data [23:16] 6 Read Data [15:8] 7 Read Data [7:0] User-provided values 8 Resource Select Code (see Table 27-33) 1. Must be longword aligned (Flash address [1:0] = 00). Table 27-33. Read Resource Select Codes Resource Select Code Description Resource Size Local Address Range 0x00 Program Flash 0 IFR 256 Bytes 0x00_0000 - 0x00_00FF 0x011 Version ID 8 Bytes 0x00_0000 - 0x00_0007 1. Located in program flash 0 reserved space. After clearing CCIF to launch the Read Resource command, four consecutive bytes are read from the selected resource at the provided relative address and stored in the FCCOB register. The CCIF flag sets after the Read Resource operation completes. The Read Resource command exits with an access error if an invalid resource code is provided or if the address for the applicable area is out-of-range. Table 27-34. Read Resource Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid resource code is entered FSTAT[ACCERR] Flash address is out-of-range for the targeted resource. FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] 27.4.10.4 Program Longword Command The Program Longword command programs four previously-erased bytes in the program flash memory using an embedded algorithm. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 410 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) CAUTION A flash memory location must be in the erased state before being programmed. Cumulative programming of bits (back-toback program operations without an intervening erase) within a flash memory location is not allowed. Re-programming of existing 0s to 0 is not allowed as this overstresses the device. Table 27-35. Program Longword Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x06 (PGM4) 1 Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0]1 4 Byte 0 program value 5 Byte 1 program value 6 Byte 2 program value 7 Byte 3 program value 1. Must be longword aligned (Flash address [1:0] = 00). Upon clearing CCIF to launch the Program Longword command, the flash memory module programs the data bytes into the flash using the supplied address. The targeted flash locations must be currently unprotected (see the description of the FPROT registers) to permit execution of the Program Longword operation. The programming operation is unidirectional. It can only move NVM bits from the erased state ('1') to the programmed state ('0'). Erased bits that fail to program to the '0' state are flagged as errors in FSTAT[MGSTAT0]. The CCIF flag is set after the Program Longword operation completes. The supplied address must be longword aligned (flash address [1:0] = 00): * * * * Byte 3 data is written to the supplied byte address ('start'), Byte 2 data is programmed to byte address start+0b01, Byte 1 data is programmed to byte address start+0b10, and Byte 0 data is programmed to byte address start+0b11. Table 27-36. Program Longword Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] Flash address points to a protected area FSTAT[FPVIOL] Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 411 Functional Description Table 27-36. Program Longword Command Error Handling (continued) Error Condition Error Bit Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 27.4.10.5 Erase Flash Sector Command The Erase Flash Sector operation erases all addresses in a flash sector. Table 27-37. Erase Flash Sector Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x09 (ERSSCR) 1 Flash address [23:16] in the flash sector to be erased 2 Flash address [15:8] in the flash sector to be erased 3 Flash address [7:0]1 in the flash sector to be erased 1. Must be longword aligned (flash address [1:0] = 00). After clearing CCIF to launch the Erase Flash Sector command, the flash memory module erases the selected program flash sector and then verifies that it is erased. The Erase Flash Sector command aborts if the selected sector is protected (see the description of the FPROT registers). If the erase-verify fails the FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Erase Flash Sector operation completes. The Erase Flash Sector command is suspendable (see the FCNFG[ERSSUSP] bit and Figure 27-26). Table 27-38. Erase Flash Sector Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid Flash address is supplied FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] The selected program flash sector is protected Any errors have been encountered during the verify FSTAT[FPVIOL] operation1 FSTAT[MGSTAT0] 1. User margin read may be run using the Read 1s Section command to verify all bits are erased. 27.4.10.5.1 Suspending an Erase Flash Sector Operation To suspend an Erase Flash Sector operation set the FCNFG[ERSSUSP] bit (see Flash Configuration Field Description) when CCIF is clear and the CCOB command field holds the code for the Erase Flash Sector command. During the Erase Flash Sector operation (see Erase Flash Sector Command), the flash memory module samples the state of the ERSSUSP bit at convenient points. If the flash memory module detects that the KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 412 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) ERSSUSP bit is set, the Erase Flash Sector operation is suspended and the flash memory module sets CCIF. While ERSSUSP is set, all writes to flash registers are ignored except for writes to the FSTAT and FCNFG registers. If an Erase Flash Sector operation effectively completes before the flash memory module detects that a suspend request has been made, the flash memory module clears the ERSSUSP bit prior to setting CCIF. When an Erase Flash Sector operation has been successfully suspended, the flash memory module sets CCIF and leaves the ERSSUSP bit set. While CCIF is set, the ERSSUSP bit can only be cleared to prevent the withdrawal of a suspend request before the flash memory module has acknowledged it. 27.4.10.5.2 Resuming a Suspended Erase Flash Sector Operation If the ERSSUSP bit is still set when CCIF is cleared to launch the next command, the previous Erase Flash Sector operation resumes. The flash memory module acknowledges the request to resume a suspended operation by clearing the ERSSUSP bit. A new suspend request can then be made by setting ERSSUSP. A single Erase Flash Sector operation can be suspended and resumed multiple times. There is a minimum elapsed time limit between the request to resume the Erase Flash Sector operation (CCIF is cleared) and the request to suspend the operation again (ERSSUSP is set). This minimum time period is required to ensure that the Erase Flash Sector operation will eventually complete. If the minimum period is continually violated, i.e. the suspend requests come repeatedly and too quickly, no forward progress is made by the Erase Flash Sector algorithm. The resume/suspend sequence runs indefinitely without completing the erase. 27.4.10.5.3 Aborting a Suspended Erase Flash Sector Operation The user may choose to abort a suspended Erase Flash Sector operation by clearing the ERSSUSP bit prior to clearing CCIF for the next command launch. When a suspended operation is aborted, the flash memory module starts the new command using the new FCCOB contents. Note Aborting the erase leaves the bitcells in an indeterminate, partially-erased state. Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 413 Functional Description Enter with CCIF = 1 Command Initiation ERSSCR Command (Write FCCOB) Memory Controller Command Processing Launch/Resume Command (Clear CCIF) Yes SUSPACK=1 Next Command (Write FCCOB) Yes CCIF = 1? No No Interrupt? Yes Request Suspend (Set ERSSUSP) Start New No Restore Erase Algo Clear SUSPACK = 0 Execute Yes DONE? No ERSSUSP=1? No CCIF = 1? Resume ERSSCR No Yes Save Erase Algo Clear ERSSUSP Yes Service Interrupt (Read Flash) ERSSCR Suspended ERSSUSP=1 ERSSCR Completed Yes ERSSUSP=0? ERSSCR Suspended Yes Set SUSPACK = 1 ERSSCR Completed ERSSUSP=0 Set CCIF No Resume Erase? No, Abort ERSSUSP: Bit in FCNFG register SUSPACK: Internal Suspend Acknowledge Clear ERSSUSP User Cmd Interrupt/Suspend Figure 27-26. Suspend and Resume of Erase Flash Sector Operation KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 414 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) 27.4.10.6 Read 1s All Blocks Command The Read 1s All Blocks command checks if the program flash blocks have been erased to the specified read margin level, if applicable, and releases security if the readout passes, i.e. all data reads as '1'. Table 27-39. Read 1s All Blocks Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x40 (RD1ALL) 1 Read-1 Margin Choice After clearing CCIF to launch the Read 1s All Blocks command, the flash memory module : * sets the read margin for 1s according to Table 27-40, * checks the contents of the program flash are in the erased state. If the flash memory module confirms that these memory resources are erased, security is released by setting the FSEC[SEC] field to the unsecure state. The security byte in the flash configuration field (see Flash Configuration Field Description) remains unaffected by the Read 1s All Blocks command. If the read fails, i.e. all memory resources are not in the fully erased state, the FSTAT[MGSTAT0] bit is set. The CCIF flag sets after the Read 1s All Blocks operation has completed. Table 27-40. Margin Level Choices for Read 1s All Blocks Read Margin Choice Margin Level Description 0x00 Use the 'normal' read level for 1s 0x01 Apply the 'User' margin to the normal read-1 level 0x02 Apply the 'Factory' margin to the normal read-1 level Table 27-41. Read 1s All Blocks Command Error Handling Error Condition Error Bit An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 415 Functional Description 27.4.10.7 Read Once Command The Read Once command provides read access to a reserved 64-byte field located in the program flash 0 IFR (see Program Flash IFR Map and Program Once Field). Access to this field is via 16 records, each 4 bytes long. The Read Once field is programmed using the Program Once command described in Program Once Command. Table 27-42. Read Once Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x41 (RDONCE) 1 Read Once record index (0x00 - 0x0F) 2 Not used 3 Not used Returned Values 4 Read Once byte 0 value 5 Read Once byte 1 value 6 Read Once byte 2 value 7 Read Once byte 3 value After clearing CCIF to launch the Read Once command, a 4-byte Read Once record is read from the program flash IFR and stored in the FCCOB register. The CCIF flag is set after the Read Once operation completes. Valid record index values for the Read Once command range from 0x00 to 0x0F. During execution of the Read Once command, any attempt to read addresses within the program flash block containing this 64-byte field returns invalid data. The Read Once command can be executed any number of times. Table 27-43. Read Once Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] 27.4.10.8 Program Once Command The Program Once command enables programming to a reserved 64-byte field in the program flash 0 IFR (see Program Flash IFR Map and Program Once Field). Access to the Program Once field is via 16 records, each 4 bytes long. The Program Once field can be read using the Read Once command (see Read Once Command) or using the Read Resource command (see Read Resource Command). Each Program Once record can be programmed only once since the program flash 0 IFR cannot be erased. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 416 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) Table 27-44. Program Once Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x43 (PGMONCE) 1 Program Once record index (0x00 - 0x0F) 2 Not Used 3 Not Used 4 Program Once Byte 0 value 5 Program Once Byte 1 value 6 Program Once Byte 2 value 7 Program Once Byte 3 value After clearing CCIF to launch the Program Once command, the flash memory module first verifies that the selected record is erased. If erased, then the selected record is programmed using the values provided. The Program Once command also verifies that the programmed values read back correctly. The CCIF flag is set after the Program Once operation has completed. The reserved program flash 0 IFR location accessed by the Program Once command cannot be erased and any attempt to program one of these records when the existing value is not Fs (erased) is not allowed. Valid record index values for the Program Once command range from 0x00 to 0x0F. During execution of the Program Once command, any attempt to read addresses within the program flash block containing this 64-byte field returns invalid data. Table 27-45. Program Once Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied The requested record has already been programmed to a non-FFFF FSTAT[ACCERR] value1 Any errors have been encountered during the verify operation FSTAT[ACCERR] FSTAT[MGSTAT0] 1. If a Program Once record is initially programmed to 0xFFFF_FFFF, the Program Once command is allowed to execute again on that same record. 27.4.10.9 Erase All Blocks Command The Erase All Blocks operation erases all flash memory, verifies all memory contents, and releases MCU security. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 417 Functional Description Table 27-46. Erase All Blocks Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x44 (ERSALL) After clearing CCIF to launch the Erase All Blocks command, the flash memory module erases all program flash memory, then verifies that all are erased. If the flash memory module verifies that all flash memories were properly erased, security is released by setting the FSEC[SEC] field to the unsecure state. The Erase All Blocks command aborts if any flash region is protected. The security byte and all other contents of the flash configuration field (see Flash Configuration Field Description) are erased by the Erase All Blocks command. If the erase-verify fails, the FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Erase All Blocks operation completes. Table 27-47. Erase All Blocks Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] Any region of the program flash memory is protected Any errors have been encountered during the verify FSTAT[FPVIOL] operation1 FSTAT[MGSTAT0] 1. User margin read may be run using the Read 1s All Blocks command to verify all bits are erased. 27.4.10.9.1 Triggering an Erase All External to the Flash Memory Module The functionality of the Erase All Blocks command is also available in an uncommanded fashion outside of the flash memory. Refer to the device's Chip Configuration details for information on this functionality. Before invoking the external erase all function, the FSTAT[ACCERR and PVIOL] flags must be cleared and the FCCOB0 register must not contain 0x44. When invoked, the erase-all function erases all program flash memory regardless of the protection settings. If the post-erase verify passes, the routine then releases security by setting the FSEC[SEC] field register to the unsecure state. The security byte in the Flash Configuration Field is also programmed to the unsecure state. The status of the erase-all request is reflected in the FCNFG[ERSAREQ] bit. The FCNFG[ERSAREQ] bit is cleared once the operation completes and the normal FSTAT error reporting is available as described in Erase All Blocks Command. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 418 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) 27.4.10.10 Verify Backdoor Access Key Command The Verify Backdoor Access Key command only executes if the mode and security conditions are satisfied (see Flash Commands by Mode). Execution of the Verify Backdoor Access Key command is further qualified by the FSEC[KEYEN] bits. The Verify Backdoor Access Key command releases security if user-supplied keys in the FCCOB match those stored in the Backdoor Comparison Key bytes of the Flash Configuration Field (see Flash Configuration Field Description). The column labelled Flash Configuration Field offset address shows the location of the matching byte in the Flash Configuration Field. Table 27-48. Verify Backdoor Access Key Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x45 (VFYKEY) Flash Configuration Field Offset Address 1-3 Not Used 4 Key Byte 0 0x0_0000 5 Key Byte 1 0x0_0001 6 Key Byte 2 0x0_0002 7 Key Byte 3 0x0_0003 8 Key Byte 4 0x0_0004 9 Key Byte 5 0x0_0005 A Key Byte 6 0x0_0006 B Key Byte 7 0x0_0007 After clearing CCIF to launch the Verify Backdoor Access Key command, the flash memory module checks the FSEC[KEYEN] bits to verify that this command is enabled. If not enabled, the flash memory module sets the FSTAT[ACCERR] bit and terminates. If the command is enabled, the flash memory module compares the key provided in FCCOB to the backdoor comparison key in the Flash Configuration Field. If the backdoor keys match, the FSEC[SEC] field is changed to the unsecure state and security is released. If the backdoor keys do not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are immediately aborted and the FSTAT[ACCERR] bit is (again) set to 1 until a reset of the flash memory module module occurs. If the entire 8-byte key is all zeros or all ones, the Verify Backdoor Access Key command fails with an access error. The CCIF flag is set after the Verify Backdoor Access Key operation completes. Table 27-49. Verify Backdoor Access Key Command Error Handling Error Condition Error Bit The supplied key is all-0s or all-Fs FSTAT[ACCERR] An incorrect backdoor key is supplied FSTAT[ACCERR] Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 419 Functional Description Table 27-49. Verify Backdoor Access Key Command Error Handling (continued) Error Condition Error Bit Backdoor key access has not been enabled (see the description of the FSEC register) FSTAT[ACCERR] This command is launched and the backdoor key has mismatched since the last power down reset FSTAT[ACCERR] 27.4.11 Security The flash memory module provides security information to the MCU based on contents of the FSEC security register. The MCU then limits access to flash memory resources as defined in the device's Chip Configuration details. During reset, the flash memory module initializes the FSEC register using data read from the security byte of the Flash Configuration Field (see Flash Configuration Field Description). The following fields are available in the FSEC register. The settings are described in the Flash Security Register (FTFA_FSEC) details. Table 27-50. FSEC register fields FSEC field Description KEYEN Backdoor Key Access MEEN Mass Erase Capability FSLACC Freescale Factory Access SEC MCU security 27.4.11.1 Flash Memory Access by Mode and Security The following table summarizes how access to the flash memory module is affected by security and operating mode. Table 27-51. Flash Memory Access Summary Operating Mode Chip Security State Unsecure NVM Normal NVM Special Secure Full command set Full command set Only the Erase All Blocks and Read 1s All Blocks commands. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 420 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Module (FTFA) 27.4.11.2 Changing the Security State The security state out of reset can be permanently changed by programming the security byte of the flash configuration field. This assumes that you are starting from a mode where the necessary program flash erase and program commands are available and that the region of the program flash containing the flash configuration field is unprotected. If the flash security byte is successfully programmed, its new value takes affect after the next chip reset. 27.4.11.2.1 Unsecuring the Chip Using Backdoor Key Access The chip can be unsecured by using the backdoor key access feature, which requires knowledge of the contents of the 8-byte backdoor key value stored in the Flash Configuration Field (see Flash Configuration Field Description). If the FSEC[KEYEN] bits are in the enabled state, the Verify Backdoor Access Key command (see Verify Backdoor Access Key Command) can be run; it allows the user to present prospective keys for comparison to the stored keys. If the keys match, the FSEC[SEC] bits are changed to unsecure the chip. The entire 8-byte key cannot be all 0s or all 1s; that is, 0000_0000_0000_0000h and FFFF_FFFF_FFFF_FFFFh are not accepted by the Verify Backdoor Access Key command as valid comparison values. While the Verify Backdoor Access Key command is active, program flash memory is not available for read access and returns invalid data. The user code stored in the program flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN bits are in the enabled state, the chip can be unsecured by the following backdoor key access sequence: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Verify Backdoor Access Key Command 2. If the Verify Backdoor Access Key command is successful, the chip is unsecured and the FSEC[SEC] bits are forced to the unsecure state An illegal key provided to the Verify Backdoor Access Key command prohibits further use of the Verify Backdoor Access Key command. A reset of the chip is the only method to re-enable the Verify Backdoor Access Key command when a comparison fails. After the backdoor keys have been correctly matched, the chip is unsecured by changing the FSEC[SEC] bits. A successful execution of the Verify Backdoor Access Key command changes the security in the FSEC register only. It does not alter the security byte or the keys stored in the Flash Configuration Field (Flash Configuration Field Description). After the next reset of the chip, the security state of the flash memory KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 421 Functional Description module reverts back to the flash security byte in the Flash Configuration Field. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the program flash protection registers. If the backdoor keys successfully match, the unsecured chip has full control of the contents of the Flash Configuration Field. The chip may erase the sector containing the Flash Configuration Field and reprogram the flash security byte to the unsecure state and change the backdoor keys to any desired value. 27.4.12 Reset Sequence On each system reset the flash memory module executes a sequence which establishes initial values for the flash block configuration parameters, FPROT, FOPT, and FSEC registers. FSTAT[CCIF] is cleared throughout the reset sequence. The flash memory module holds off CPU access during the reset sequence. Flash reads are possible when the hold is removed. Completion of the reset sequence is marked by setting CCIF which enables flash user commands. If a reset occurs while any flash command is in progress, that command is immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. Commands and operations do not automatically resume after exiting reset. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 422 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) 28.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The 12-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE For the chip specific modes of operation, see the power management information of the device. 28.1.1 Features Features of the ADC module include: * Linear successive approximation algorithm with up to 12-bit resolution * Up to 24 single-ended external analog inputs * Output modes: * single-ended 12-bit, 10-bit, and 8-bit modes * Output in right-justified unsigned format for single-ended * Single or continuous conversion, that is, automatic return to idle after single conversion * Configurable sample time and conversion speed/power * Conversion complete/hardware average complete flag and interrupt KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 423 Introduction * Input clock selectable from up to four sources * Operation in Low-Power modes for lower noise * Asynchronous clock source for lower noise operation with option to output the clock * Selectable hardware conversion trigger with hardware channel select * Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value * Temperature sensor * Hardware average function * Selectable voltage reference: external or alternate * Self-Calibration mode 28.1.2 Block diagram The following figure is the ADC module block diagram. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 424 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) ADHWTSA SC1A Conversion trigger control ADHWTSn ADHWT SC1n ADTRG Control Registers (SC2, CFG1, CFG2) ADACKEN Interrupt ADCK ADACK Clock divide Bus clock 2 ALTCLK abort transfer convert initialize AD0 sample Control sequencer MCU STOP Async Clock Gen A D IC L K A D IV ADLPC/ADHSC ADLSMP/ADLSTS ADCO MODE trig g e r c o m p le te AIEN COCO ADCH C o m p a re tru e 1 PG, MG A D V IN AD23 Temp PG, MG CLPx SAR converter CLPx CLM x Offset subtractor CLMx OFS ADCOFS Calibration CALF CAL AVGE, AVGS V REFSH Averager MODE Formatting V REFH SC3 CFG1,2 D RA VALTH V REFSL tra n s fe r V REFL Rn Compare logic VALTL C V1 ACFE ACFGT, ACREN Compare true SC2 1 CV2 CV1:CV2 Figure 28-1. ADC block diagram 28.2 ADC Signal Descriptions The ADC module supports up to 24 single-ended inputs. The ADC also requires four supply/reference/ground connections. NOTE Refer to ADC configuration section in chip configuration chapter for the number of channels supported on this device. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 425 ADC Signal Descriptions Table 28-1. ADC Signal Descriptions Signal ADn Description I/O Single-Ended Analog Channel Inputs I VREFSH Voltage Reference Select High I VREFSL Voltage Reference Select Low I VDDA Analog Power Supply I VSSA Analog Ground I 28.2.1 Analog Power (VDDA) The ADC analog portion uses VDDA as its power connection. In some packages, VDDA is connected internally to VDD. If externally available, connect the VDDA pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDA for good results. 28.2.2 Analog Ground (VSSA) The ADC analog portion uses VSSA as its ground connection. In some packages, VSSA is connected internally to VSS. If externally available, connect the VSSA pin to the same voltage potential as VSS. 28.2.3 Voltage Reference Select VREFSH and VREFSL are the high and low reference voltages for the ADC module. The ADC can be configured to accept one of two voltage reference pairs for VREFSH and VREFSL. Each pair contains a positive reference that must be between the minimum Ref Voltage High and VDDA, and a ground reference that must be at the same potential as VSSA. The two pairs are external (VREFH and VREFL) and alternate (VALTH and VALTL). These voltage references are selected using SC2[REFSEL]. The alternate VALTH and VALTL voltage reference pair may select additional external pins or internal sources depending on MCU configuration. See the chip configuration information on the Voltage References specific to this MCU. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 426 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) In some packages, VREFH is connected in the package to VDDA and VREFL to VSSA. If externally available, the positive reference(s) may be connected to the same potential as VDDA or may be driven by an external source to a level between the minimum Ref Voltage High and the VDDA potential. VREFH must never exceed VDDA. Connect the ground references to the same voltage potential as VSSA. 28.2.4 Analog Channel Inputs (ADx) The ADC module supports up to 24 single-ended analog inputs. A single-ended input is selected for conversion through the SC1[ADCH] channel select bits. 28.3 Register definition This section describes the ADC registers. ADC memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_B000 ADC Status and Control Registers 1 (ADC0_SC1A) 32 R/W 0000_001Fh 28.3.1/428 4003_B004 ADC Status and Control Registers 1 (ADC0_SC1B) 32 R/W 0000_001Fh 28.3.1/428 4003_B008 ADC Configuration Register 1 (ADC0_CFG1) 32 R/W 0000_0000h 28.3.2/431 4003_B00C ADC Configuration Register 2 (ADC0_CFG2) 32 R/W 0000_0000h 28.3.3/433 4003_B010 ADC Data Result Register (ADC0_RA) 32 R 0000_0000h 28.3.4/434 4003_B014 ADC Data Result Register (ADC0_RB) 32 R 0000_0000h 28.3.4/434 4003_B018 Compare Value Registers (ADC0_CV1) 32 R/W 0000_0000h 28.3.5/435 4003_B01C Compare Value Registers (ADC0_CV2) 32 R/W 0000_0000h 28.3.5/435 4003_B020 Status and Control Register 2 (ADC0_SC2) 32 R/W 0000_0000h 28.3.6/436 4003_B024 Status and Control Register 3 (ADC0_SC3) 32 R/W 0000_0000h 28.3.7/438 4003_B028 ADC Offset Correction Register (ADC0_OFS) 32 R/W 0000_0004h 28.3.8/439 28.3.9/440 4003_B02C ADC Plus-Side Gain Register (ADC0_PG) 32 R/W 0000_8200h 4003_B034 ADC Plus-Side General Calibration Value Register (ADC0_CLPD) 32 R/W 0000_000Ah 28.3.10/440 4003_B038 ADC Plus-Side General Calibration Value Register (ADC0_CLPS) 32 R/W 0000_0020h 28.3.11/441 4003_B03C ADC Plus-Side General Calibration Value Register (ADC0_CLP4) 32 R/W 0000_0200h 28.3.12/441 4003_B040 ADC Plus-Side General Calibration Value Register (ADC0_CLP3) 32 R/W 0000_0100h 28.3.13/442 4003_B044 ADC Plus-Side General Calibration Value Register (ADC0_CLP2) 32 R/W 0000_0080h 28.3.14/442 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 427 Register definition ADC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_B048 ADC Plus-Side General Calibration Value Register (ADC0_CLP1) 32 R/W 0000_0040h 28.3.15/443 4003_B04C ADC Plus-Side General Calibration Value Register (ADC0_CLP0) 32 R/W 0000_0020h 28.3.16/443 28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n) SC1A is used for both software and hardware trigger modes of operation. To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more then one status and control register: one for each conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers for use only in hardware trigger mode. See the chip configuration information about the number of SC1n registers specific to this device. The SC1n registers have identical fields, and are used in a "pingpong" approach to control ADC operation. At any one point in time, only one of the SC1n registers is actively controlling ADC conversions. Updating SC1A while SC1n is actively controlling a conversion is allowed, and vice-versa for any of the SC1n registers specific to this MCU. Writing SC1A while SC1A is actively controlling a conversion aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0, writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a value other than all 1s. Writing any of the SC1n registers while that specific SC1n register is actively controlling a conversion aborts the current conversion. None of the SC1B-SC1n registers are used for software trigger operation and therefore writes to the SC1B-SC1n registers do not initiate a new conversion. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 428 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) Address: 4003_B000h base + 0h offset + (4d x i), where i=0d to 1d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AIEN 0 0 1 1 COCO Reset Reserved W 0 R ADCH W Reset 0 0 0 0 0 0 0 0 0 1 1 1 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 429 Register definition ADCx_SC1n field descriptions Field 31-8 Reserved 7 COCO Description This field is reserved. This read-only field is reserved and always has the value 0. Conversion Complete Flag This is a read-only field that is set each time a conversion is completed when the compare function is disabled, or SC2[ACFE]=0 and the hardware average function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare result is true. When the hardware average function is enabled, or SC3[AVGE]=1, COCO is set upon completion of the selected number of conversions (determined by AVGS). COCO in SC1A is also set at the completion of a calibration sequence. COCO is cleared when the respective SC1n register is written or when the respective Rn register is read. 0 1 6 AIEN Interrupt Enable Enables conversion complete interrupts. When COCO becomes set while the respective AIEN is high, an interrupt is asserted. 0 1 5 Reserved 4-0 ADCH Conversion is not completed. Conversion is completed. Conversion complete interrupt is disabled. Conversion complete interrupt is enabled. This field is reserved. This reserved bit should not be changed. Input channel select Selects one of the input channels. NOTE: Some of the input channel options in the bitfield-setting descriptions might not be available for your device. For the actual ADC channel assignments for your device, see the Chip Configuration details. The successive approximation converter subsystem is turned off when the channel select bits are all set, that is, ADCH = 11111. This feature allows explicit disabling of the ADC and isolation of the input channel from all sources. Terminating continuous conversions this way prevents an additional single conversion from being performed. It is not necessary to set ADCH to all 1s to place the ADC in a low-power state when continuous conversions are not enabled because the module automatically enters a low-power state when a conversion completes. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 AD0 is selected as input. AD1 is selected as input. AD2 is selected as input. AD3 is selected as input. AD4 is selected as input. AD5 is selected as input. AD6 is selected as input. AD7 is selected as input. AD8 is selected as input. AD9 is selected as input. AD10 is selected as input. AD11 is selected as input. AD12 is selected as input. AD13 is selected as input. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 430 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) ADCx_SC1n field descriptions (continued) Field Description 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 AD14 is selected as input. AD15 is selected as input. AD16 is selected as input. AD17 is selected as input. AD18 is selected as input. AD19 is selected as input. AD20 is selected as input. AD21 is selected as input. AD22 is selected as input. AD23 is selected as input. Reserved. Reserved. Temp Sensor (single-ended) is selected as input. Bandgap (single-ended) is selected as input. Reserved. VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]. VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]. Module is disabled. 28.3.2 ADC Configuration Register 1 (ADCx_CFG1) The configuration Register 1 (CFG1) selects the mode of operation, clock source, clock divide, and configuration for low power or long sample time. Address: 4003_B000h base + 8h offset = 4003_B008h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADLPC 0 R W Reset 0 0 0 0 0 0 0 0 0 ADLSMP Reset ADIV 0 0 0 MODE 0 0 ADICLK 0 0 ADCx_CFG1 field descriptions Field 31-8 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 431 Register definition ADCx_CFG1 field descriptions (continued) Field 7 ADLPC Description Low-Power Configuration Controls the power configuration of the successive approximation converter. This optimizes power consumption when higher sample rates are not required. 0 1 6-5 ADIV Clock Divide Select ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK. 00 01 10 11 4 ADLSMP ADLSMP selects between different sample times based on the conversion mode selected. This bit adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall power consumption if continuous conversions are enabled and high conversion rates are not required. When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the extent of the long sample time. Short sample time. Long sample time. Conversion mode selection Selects the ADC resolution mode. 00 01 10 11 1-0 ADICLK The divide ratio is 1 and the clock rate is input clock. The divide ratio is 2 and the clock rate is (input clock)/2. The divide ratio is 4 and the clock rate is (input clock)/4. The divide ratio is 8 and the clock rate is (input clock)/8. Sample time configuration 0 1 3-2 MODE Normal power configuration. Low-power configuration. The power is reduced at the expense of maximum clock speed. It is single-ended 8-bit conversion. It is single-ended 12-bit conversion . It is single-ended 10-bit conversion . Reserved. Do not set the bitfield to this value. Input Clock Select Selects the input clock source to generate the internal clock, ADCK. Note that when the ADACK clock source is selected, it is not required to be active prior to conversion start. When it is selected and it is not active prior to a conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at the start of a conversion and deactivated when conversions are terminated. In this case, there is an associated clock startup delay each time the clock source is re-activated. 00 01 10 11 Bus clock (Bus clock)/2 Alternate clock (ALTCLK) Asynchronous clock (ADACK) KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 432 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) 28.3.3 ADC Configuration Register 2 (ADCx_CFG2) Configuration Register 2 (CFG2) selects the special high-speed configuration for very high speed conversions and selects the long sample time duration during long sample mode. Address: 4003_B000h base + Ch offset = 4003_B00Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MUXSEL ADACKEN ADHSC W 0 0 0 0 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 ADLSTS 0 0 ADCx_CFG2 field descriptions Field Description 31-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7-5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 MUXSEL ADC Mux Select Changes the ADC mux setting to select between alternate sets of ADC channels. 0 1 3 ADACKEN Asynchronous Clock Output Enable Enables the asynchronous clock source and the clock source output regardless of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the asynchronous clock may be used by other modules. See chip configuration information. Setting this field allows the clock to be used even while the ADC is idle or operating from a different clock source. Also, latency of initiating a single or first-continuous conversion with the asynchronous clock selected is reduced because the ADACK clock is already operational. 0 1 2 ADHSC ADxxa channels are selected. ADxxb channels are selected. Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. Asynchronous clock and clock output is enabled regardless of the state of the ADC. High-Speed Configuration Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 433 Register definition ADCx_CFG2 field descriptions (continued) Field Description Configures the ADC for very high-speed operation. The conversion sequence is altered with 2 ADCK cycles added to the conversion time to allow higher speed conversion clocks. 0 1 1-0 ADLSTS Normal conversion sequence selected. High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. Long Sample Time Select Selects between the extended sample times when long sample time is selected, that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if high conversion rates are not required. 00 01 10 11 Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. 12 extra ADCK cycles; 16 ADCK cycles total sample time. 6 extra ADCK cycles; 10 ADCK cycles total sample time. 2 extra ADCK cycles; 6 ADCK cycles total sample time. 28.3.4 ADC Data Result Register (ADCx_Rn) The data result registers (Rn) contain the result of an ADC conversion of the channel selected by the corresponding status and channel control register (SC1A:SC1n). For every status and channel control register, there is a corresponding data result register. Unused bits in R n are cleared in unsigned right-justified modes and carry the sign bit (MSB) in sign-extended 2's complement modes. The following table describes the behavior of the data result registers in the different modes of operation. Table 28-35. Data result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Format 12-bit singleended 0 0 0 0 D D D D D D D D D D D D Unsigned rightjustified 10-bit singleended 0 0 0 0 0 0 D D D D D D D D D D Unsigned rightjustified 8-bit singleended 0 0 0 0 0 0 0 0 D D D D D D D D Unsigned rightjustified NOTE S: Sign bit or sign bit extension; D: Data, which is 2's complement data if indicated KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 434 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) Address: 4003_B000h base + 10h offset + (4d x i), where i=0d to 1d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 0 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 D W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCx_Rn field descriptions Field Description 31-16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15-0 D Data result 28.3.5 Compare Value Registers (ADCx_CVn) The compare value registers (CV1 and CV2) contain a compare value used to compare the conversion result when the compare function is enabled, that is, SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in different modes of operation for both bit position definition and value format using unsigned or sign-extended 2's complement. Therefore, the compare function uses only the CVn fields that are related to the ADC mode of operation. The compare value 2 register (CV2) is used only when the compare range function is enabled, that is, SC2[ACREN]=1. Address: 4003_B000h base + 18h offset + (4d x i), where i=0d to 1d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 CV W Reset 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCx_CVn field descriptions Field 31-16 Reserved 15-0 CV Description This field is reserved. This read-only field is reserved and always has the value 0. Compare Value. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 435 Register definition 28.3.6 Status and Control Register 2 (ADCx_SC2) The status and control register 2 (SC2) contains the conversion active, hardware/software trigger select, compare function, and voltage reference select of the ADC module. Address: 4003_B000h base + 20h offset = 4003_B020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACFE ACFGT ACREN DMAEN 0 0 0 0 0 ADACT Reset ADTRG W 0 R REFSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 ADCx_SC2 field descriptions Field 31-8 Reserved 7 ADACT Description This field is reserved. This read-only field is reserved and always has the value 0. Conversion Active Indicates that a conversion or hardware averaging is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted. 0 1 6 ADTRG Conversion not in progress. Conversion in progress. Conversion Trigger Select Selects the type of trigger used for initiating a conversion. Two types of trigger are selectable: Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 436 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) ADCx_SC2 field descriptions (continued) Field Description * Software trigger: When software trigger is selected, a conversion is initiated following a write to SC1A. * Hardware trigger: When hardware trigger is selected, a conversion is initiated following the assertion of the ADHWT input after a pulse of the ADHWTSn input. 0 1 5 ACFE Compare Function Enable Enables the compare function. 0 1 4 ACFGT Compare function disabled. Compare function enabled. Compare Function Greater Than Enable Configures the compare function to check the conversion result relative to the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to have any effect. 0 1 3 ACREN Software trigger selected. Hardware trigger selected. Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2. Compare Function Range Enable Configures the compare function to check if the conversion result of the input being monitored is either between or outside the range formed by CV1 and CV2 determined by the value of ACFGT. ACFE must be set for ACFGT to have any effect. 0 1 Range function disabled. Only CV1 is compared. Range function enabled. Both CV1 and CV2 are compared. 2 DMAEN DMA Enable 1-0 REFSEL Voltage Reference Selection 0 1 DMA is disabled. DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted. Selects the voltage reference source used for conversions. 00 01 10 11 Default voltage reference pin pair, that is, external pins VREFH and VREFL Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU Reserved Reserved KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 437 Register definition 28.3.7 Status and Control Register 3 (ADCx_SC3) The Status and Control Register 3 (SC3) controls the calibration, continuous convert, and hardware averaging functions of the ADC module. Address: 4003_B000h base + 24h offset = 4003_B024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AVGE 0 0 CALF Reset ADCO W 0 R 0 CAL AVGS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCx_SC3 field descriptions Field 31-8 Reserved 7 CAL 6 CALF Description This field is reserved. This read-only field is reserved and always has the value 0. Calibration Begins the calibration sequence when set. This field stays set while the calibration is in progress and is cleared when the calibration sequence is completed. CALF must be checked to determine the result of the calibration sequence. Once started, the calibration routine cannot be interrupted by writes to the ADC registers or the results will be invalid and CALF will set. Setting CAL will abort any current conversion. Calibration Failed Flag Displays the result of the calibration sequence. The calibration sequence will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is entered before the calibration sequence completes. Writing 1 to CALF clears it. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 438 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) ADCx_SC3 field descriptions (continued) Field Description 0 1 5-4 Reserved Calibration completed normally. Calibration failed. ADC accuracy specifications are not guaranteed. This field is reserved. This read-only field is reserved and always has the value 0. 3 ADCO Continuous Conversion Enable Enables continuous conversions. 0 1 2 AVGE One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. Hardware Average Enable Enables the hardware average function of the ADC. 0 1 1-0 AVGS Hardware average function disabled. Hardware average function enabled. Hardware Average Select Determines how many ADC conversions will be averaged to create the ADC average result. 00 01 10 11 4 samples averaged. 8 samples averaged. 16 samples averaged. 32 samples averaged. 28.3.8 ADC Offset Correction Register (ADCx_OFS) The ADC Offset Correction Register (OFS) contains the user-selected or calibrationgenerated offset error correction value. This register is a 2's complement, left-justified, 16-bit value . The value in OFS is subtracted from the conversion and the result is transferred into the result registers, Rn. If the result is greater than the maximum or less than the minimum result value, it is forced to the appropriate limit for the current mode of operation. Address: 4003_B000h base + 28h offset = 4003_B028h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 OFS W Reset 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 439 Register definition ADCx_OFS field descriptions Field Description 31-16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15-0 OFS Offset Error Correction Value 28.3.9 ADC Plus-Side Gain Register (ADCx_PG) The Plus-Side Gain Register (PG) contains the gain error correction for the overall conversion in single-ended mode. PG, a 16-bit real number in binary format, is the gain adjustment factor, with the radix point fixed between ADPG15 and ADPG14. This register must be written by the user with the value described in the calibration procedure. Otherwise, the gain error specifications may not be met. Address: 4003_B000h base + 2Ch offset = 4003_B02Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PG W Reset 8 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 ADCx_PG field descriptions Field 31-16 Reserved 15-0 PG Description This field is reserved. This read-only field is reserved and always has the value 0. Plus-Side Gain 28.3.10 ADC Plus-Side General Calibration Value Register (ADCx_CLPD) The Plus-Side General Calibration Value Registers (CLPx) contain calibration information that is generated by the calibration function. These registers contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0], CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set when the selfcalibration sequence is done, that is, CAL is cleared. If these registers are written by the user after calibration, the linearity error specifications may not be met. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 440 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) Address: 4003_B000h base + 34h offset = 4003_B034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 CLPD W Reset 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 4 3 2 1 0 ADCx_CLPD field descriptions Field Description 31-6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5-0 CLPD Calibration Value 28.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPS) For more information, see CLPD register description. Address: 4003_B000h base + 38h offset = 4003_B038h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 0 R CLPS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 4 3 2 1 0 0 0 0 0 ADCx_CLPS field descriptions Field Description 31-6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5-0 CLPS Calibration Value 28.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLP4) For more information, see CLPD register description. Address: 4003_B000h base + 3Ch offset = 4003_B03Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 0 R CLP4 W Reset 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 441 Register definition ADCx_CLP4 field descriptions Field Description 31-10 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 9-0 CLP4 Calibration Value 28.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP3) For more information, see CLPD register description. Address: 4003_B000h base + 40h offset = 4003_B040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 0 R 0 0 0 0 0 0 0 0 0 0 0 3 2 1 0 0 0 0 0 0 4 3 2 1 0 0 0 0 CLP3 W Reset 4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 ADCx_CLP3 field descriptions Field Description 31-9 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 8-0 CLP3 Calibration Value 28.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP2) For more information, see CLPD register description. Address: 4003_B000h base + 44h offset = 4003_B044h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 0 R CLP2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 ADCx_CLP2 field descriptions Field 31-8 Reserved 7-0 CLP2 Description This field is reserved. This read-only field is reserved and always has the value 0. Calibration Value KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 442 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) 28.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP1) For more information, see CLPD register description. Address: 4003_B000h base + 48h offset = 4003_B048h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 0 R 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 CLP1 W Reset 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 4 3 2 1 0 0 0 ADCx_CLP1 field descriptions Field Description 31-7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6-0 CLP1 Calibration Value 28.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP0) For more information, see CLPD register description. Address: 4003_B000h base + 4Ch offset = 4003_B04Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 0 R CLP0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 ADCx_CLP0 field descriptions Field 31-6 Reserved 5-0 CLP0 Description This field is reserved. This read-only field is reserved and always has the value 0. Calibration Value KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 443 Functional description 28.4 Functional description The ADC module is disabled during reset, in Low-Power Stop mode, or when SC1n[ADCH] are all high; see the power management information for details. The module is idle when a conversion has completed and another conversion has not been initiated. When it is idle and the asynchronous clock output enable is disabled, or CFG2[ADACKEN]= 0, the module is in its lowest power state. The ADC can perform an analog-to-digital conversion on any of the software selectable channels. All modes perform conversion by a successive approximation algorithm. To meet accuracy specifications, the ADC module must be calibrated using the on-chip calibration function. See Calibration function for details on how to perform calibration. When the conversion is completed, the result is placed in the Rn data registers. The respective SC1n[COCO] is then set and an interrupt is generated if the respective conversion complete interrupt has been enabled, or, when SC1n[AIEN]=1. The ADC module has the capability of automatically comparing the result of a conversion with the contents of the CV1 and CV2 registers. The compare function is enabled by setting SC2[ACFE] and operates in any of the conversion modes and configurations. The ADC module has the capability of automatically averaging the result of multiple conversions. The hardware average function is enabled by setting SC3[AVGE] and operates in any of the conversion modes and configurations. NOTE For the chip specific modes of operation, see the power management information of this MCU. 28.4.1 Clock select and divide control One of four clock sources can be selected as the clock source for the ADC module. This clock source is then divided by a configurable value to generate the input clock ADCK, to the module. The clock is selected from one of the following sources by means of CFG1[ADICLK]. * Bus clock. This is the default selection following reset. * Bus clock divided by two. For higher bus clock rates, this allows a maximum divideby-16 of the bus clock using CFG1[ADIV]. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 444 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) * ALTCLK: As defined for this MCU. See the chip configuration information. * Asynchronous clock (ADACK): This clock is generated from a clock source within the ADC module. When the ADACK clock source is selected, it is not required to be active prior to conversion start. When it is selected and it is not active prior to a conversion start CFG2[ADACKEN]=0, ADACK is activated at the start of a conversion and deactivated when conversions are terminated. In this case, there is an associated clock startup delay each time the clock source is re-activated. To avoid the conversion time variability and latency associated with the ADACK clock startup, set CFG2[ADACKEN]=1 and wait the worst-case startup time of 5 s prior to initiating any conversions using the ADACK clock source. Conversions are possible using ADACK as the input clock source while the MCU is in Normal Stop mode. See Power Control for more information. Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the available clocks are too slow, the ADC may not perform according to specifications. If the available clocks are too fast, the clock must be divided to the appropriate frequency. This divider is specified by CFG1[ADIV] and can be divide-by 1, 2, 4, or 8. 28.4.2 Voltage reference selection The ADC can be configured to accept one of the two voltage reference pairs as the reference voltage (VREFSH and VREFSL) used for conversions. Each pair contains a positive reference that must be between the minimum Ref Voltage High and VDDA, and a ground reference that must be at the same potential as VSSA. The two pairs are external (VREFH and VREFL) and alternate (VALTH and VALTL). These voltage references are selected using SC2[REFSEL]. The alternate (VALTH and VALTL) voltage reference pair may select additional external pins or internal sources depending on MCU configuration. See the chip configuration information on the voltage references specific to this MCU. 28.4.3 Hardware trigger and channel selects The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT, that is enabled when SC2[ADTRG] is set and a hardware trigger select event, ADHWTSn, has occurred. This source is not available on all MCUs. See the Chip Configuration chapter for information on the ADHWT source and the ADHWTSn configurations specific to this MCU. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 445 Functional description When an ADHWT source is available and hardware trigger is enabled, that is SC2[ADTRG]=1, a conversion is initiated on the rising-edge of ADHWT after a hardware trigger select event, that is, ADHWTSn, has occurred. If a conversion is in progress when a rising-edge of a trigger occurs, the rising-edge is ignored. In continuous convert configuration, only the initial rising-edge to launch continuous conversions is observed, and until conversion is aborted, the ADC continues to do conversions on the same SCn register that initiated the conversion. The hardware trigger function operates in conjunction with any of the conversion modes and configurations. The hardware trigger select event, that is, ADHWTSn, must be set prior to the receipt of the ADHWT signal. If these conditions are not met, the converter may ignore the trigger or use the incorrect configuration. If a hardware trigger select event is asserted during a conversion, it must stay asserted until the end of current conversion and remain set until the receipt of the ADHWT signal to trigger a new conversion. The channel and status fields selected for the conversion depend on the active trigger select signal: * ADHWTSA active selects SC1A * ADHWTSn active selects SC1n Note Asserting more than one hardware trigger select signal (ADHWTSn) at the same time results in unknown results. To avoid this, select only one hardware trigger select signal (ADHWTSn) prior to the next intended conversion. When the conversion is completed, the result is placed in the Rn registers associated with the ADHWTSn received. For example: * ADHWTSA active selects RA register * ADHWTSn active selects Rn register The conversion complete flag associated with the ADHWTSn received, that is, SC1n[COCO], is then set and an interrupt is generated if the respective conversion complete interrupt has been enabled, that is, SC1[AIEN]=1. 28.4.4 Conversion control Conversions can be performed as determined by CFG1[MODE] as shown in the description of CFG1[MODE]. Conversions can be initiated by a software or hardware trigger. In addition, the ADC module can be configured for: * Low-power operation * Long sample time KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 446 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) * Continuous conversion * Hardware average * Automatic compare of the conversion result to a software determined compare value 28.4.4.1 Initiating conversions A conversion is initiated: * Following a write to SC1A, with SC1n[ADCH] not all 1's, if software triggered operation is selected, that is, when SC2[ADTRG]=0. * Following a hardware trigger, or ADHWT event, if hardware triggered operation is selected, that is, SC2[ADTRG]=1, and a hardware trigger select event, ADHWTSn, has occurred. The channel and status fields selected depend on the active trigger select signal: * ADHWTSA active selects SC1A * ADHWTSn active selects SC1n * if neither is active, the off condition is selected Note Selecting more than one ADHWTSn prior to a conversion completion will result in unknown results. To avoid this, select only one ADHWTSn prior to a conversion completion. * Following the transfer of the result to the data registers when continuous conversion is enabled, that is, when ADCO=1. If continuous conversions are enabled, a new conversion is automatically initiated after the completion of the current conversion, by:. In software triggered operation, that is, when ADTRG=0, continuous conversions begin after SC1A is written and continue until aborted. In hardware triggered operation, that is, when ADTRG=1 and one ADHWTSn event has occurred, continuous conversions begin after a hardware trigger event and continue until aborted. If hardware averaging is enabled, a new conversion is automatically initiated after the completion of the current conversion until the correct number of conversions are completed. In software triggered operation, conversions begin after SC1A is written. In hardware triggered operation, conversions begin after a hardware trigger. If continuous conversions are also enabled, a new set of conversions to be averaged are initiated following the last of the selected number of conversions. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 447 Functional description 28.4.4.2 Completing conversions A conversion is completed when the result of the conversion is transferred into the data result registers, Rn. If the compare functions are disabled, this is indicated by setting of SC1n[COCO]. If hardware averaging is enabled, the respective SC1n[COCO] sets only if the last of the selected number of conversions is completed. If the compare function is enabled, the respective SC1n[COCO] sets and conversion result data is transferred only if the compare condition is true. If both hardware averaging and compare functions are enabled, then the respective SC1n[COCO] sets only if the last of the selected number of conversions is completed and the compare condition is true. An interrupt is generated if the respective SC1n[AIEN] is high at the time that the respective SC1n[COCO] is set. 28.4.4.3 Aborting conversions Any conversion in progress is aborted when: * Writing to SC1A while it is actively controlling a conversion, aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0, a write to SC1A initiates a new conversion if SC1A[ADCH] is equal to a value other than all 1s. Writing to any of the SC1B-SC1n registers while that specific SC1B-SC1n register is actively controlling a conversion aborts the current conversion. The SC1(B-n) registers are not used for software trigger operation and therefore writes to the SC1(B-n) registers do not initiate a new conversion. * A write to any ADC register besides the SC1A-SC1n registers occurs. This indicates that a change in mode of operation has occurred and the current conversion is therefore invalid. * The MCU is reset or enters Low-Power Stop modes. * The MCU enters Normal Stop mode with ADACK not enabled. When a conversion is aborted, the contents of the data registers, Rn, are not altered. The data registers continue to be the values transferred after the completion of the last successful conversion. If the conversion was aborted by a reset or Low-Power Stop modes, RA and Rn return to their reset states. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 448 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) 28.4.4.4 Power control The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the conversion clock source, but the asynchronous clock output is disabled, that is CFG2[ADACKEN]=0, the ADACK clock generator also remains in its idle state (disabled) until a conversion is initiated. If the asynchronous clock output is enabled, that is, CFG2[ADACKEN]=1, it remains active regardless of the state of the ADC or the MCU power mode. Power consumption when the ADC is active can be reduced by setting CFG1[ADLPC]. This results in a lower maximum value for fADCK. 28.4.4.5 Sample time and total conversion time For short sample, that is, when CFG1[ADLSMP]=0, there is a 2-cycle adder for first conversion over the base sample time of four ADCK cycles. For high speed conversions, that is, when CFG2[ADHSC]=1, there is an additional 2-cycle adder on any conversion. The table below summarizes sample times for the possible ADC configurations. ADC configuration Sample time (ADCK cycles) CFG1[ADLSMP] CFG2[ADLSTS] CFG2[ADHSC] First or Single Subsequent 0 X 0 6 4 1 00 0 24 1 01 0 16 1 10 0 10 1 11 0 6 0 X 1 1 00 1 26 1 01 1 18 1 10 1 12 1 11 1 8 8 6 The total conversion time depends upon: * The sample time as determined by CFG1[ADLSMP] and CFG2[ADLSTS] * The MCU bus frequency * The conversion mode, as determined by CFG1[MODE] * The high speed configuration, that is, CFG2[ADHSC] * The frequency of the conversion clock, that is, fADCK. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 449 Functional description CFG2[ADHSC] is used to configure a higher clock input frequency. This will allow faster overall conversion times. To meet internal ADC timing requirements, CFG2[ADHSC] adds additional ADCK cycles. Conversions with CFG2[ADHSC]=1 take two more ADCK cycles. CFG2[ADHSC] must be used when the ADCLK exceeds the limit for CFG2[ADHSC]=0. After the module becomes active, sampling of the input begins. 1. CFG1[ADLSMP] and CFG2[ADLSTS] select between sample times based on the conversion mode that is selected. 2. When sampling is completed, the converter is isolated from the input channel and a successive approximation algorithm is applied to determine the digital value of the analog signal. 3. The result of the conversion is transferred to Rn upon completion of the conversion algorithm. If the bus frequency is less than fADCK, precise sample time for continuous conversions cannot be guaranteed when short sample is enabled, that is, when CFG1[ADLSMP]=0. The maximum total conversion time is determined by the clock source chosen and the divide ratio selected. The clock source is selectable by CFG1[ADICLK], and the divide ratio is specified by CFG1[ADIV]. The maximum total conversion time for all configurations is summarized in the equation below. See the following tables for the variables referenced in the equation. Figure 28-46. Conversion time equation Table 28-54. Single or first continuous time adder (SFCAdder) CFG1[AD LSMP] CFG2[AD ACKEN] CFG1[ADICLK] Single or first continuous time adder (SFCAdder) 1 x 0x, 10 3 ADCK cycles + 5 bus clock cycles 1 1 11 3 ADCK cycles + 5 bus clock cycles1 1 0 11 5 s + 3 ADCK cycles + 5 bus clock cycles 0 x 0x, 10 5 ADCK cycles + 5 bus clock cycles 0 1 11 5 ADCK cycles + 5 bus clock cycles1 0 0 11 5 s + 5 ADCK cycles + 5 bus clock cycles 1. To achieve this time, CFG2[ADACKEN] must be 1 for at least 5 s prior to the conversion is initiated. Table 28-55. Average number factor (AverageNum) SC3[AVGE] SC3[AVGS] Average number factor (AverageNum) 0 xx 1 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 450 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) Table 28-55. Average number factor (AverageNum) (continued) SC3[AVGE] SC3[AVGS] Average number factor (AverageNum) 1 00 4 1 01 8 1 10 16 1 11 32 Table 28-56. Base conversion time (BCT) Mode Base conversion time (BCT) 8b single-ended 17 ADCK cycles 10b single-ended 20 ADCK cycles 12b single-ended 20 ADCK cycles Table 28-57. Long sample time adder (LSTAdder) CFG1[ADLSMP] CFG2[ADLSTS] Long sample time adder (LSTAdder) 0 xx 0 ADCK cycles 1 00 20 ADCK cycles 1 01 12 ADCK cycles 1 10 6 ADCK cycles 1 11 2 ADCK cycles Table 28-58. High-speed conversion time adder (HSCAdder) CFG2[ADHSC] High-speed conversion time adder (HSCAdder) 0 0 ADCK cycles 1 2 ADCK cycles Note The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specifications. 28.4.4.6 Conversion time examples The following examples use the Figure 28-46, and the information provided in Table 28-54 through Table 28-58. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 451 Functional description 28.4.4.6.1 Typical conversion time configuration A typical configuration for ADC conversion is: * 10-bit mode, with the bus clock selected as the input clock source * The input clock divide-by-1 ratio selected * Bus frequency of 8 MHz * Long sample time disabled * High-speed conversion disabled The conversion time for a single conversion is calculated by using the Figure 28-46, and the information provided in Table 28-54 through Table 28-58. The table below lists the variables of Figure 28-46. Table 28-59. Typical conversion time Variable Time SFCAdder 5 ADCK cycles + 5 bus clock cycles AverageNum 1 BCT 20 ADCK cycles LSTAdder 0 HSCAdder 0 The resulting conversion time is generated using the parameters listed in the preceding table. Therefore, for a bus clock and an ADCK frequency equal to 8 MHz, the resulting conversion time is 3.75 s. 28.4.4.6.2 Short conversion time configuration A configuration for short ADC conversion is: * 8-bit Single-Ended mode with the bus clock selected as the input clock source * The input clock divide-by-1 ratio selected * Bus frequency of 20 MHz * Long sample time disabled * High-speed conversion enabled The conversion time for this conversion is calculated by using the Figure 28-46, and the information provided in Table 28-54 through Table 28-58. The table below lists the variables of Figure 28-46. Table 28-60. Typical conversion time Variable Time SFCAdder 5 ADCK cycles + 5 bus clock cycles AverageNum 1 BCT 17 ADCK cycles Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 452 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) Table 28-60. Typical conversion time (continued) Variable Time LSTAdder 0 ADCK cycles HSCAdder 2 The resulting conversion time is generated using the parameters listed in in the preceding table. Therefore, for bus clock and ADCK frequency equal to 20 MHz, the resulting conversion time is 1.45 s. 28.4.4.7 Hardware average function The hardware average function can be enabled by setting SC3[AVGE]=1 to perform a hardware average of multiple conversions. The number of conversions is determined by the AVGS[1:0] bits, which can select 4, 8, 16, or 32 conversions to be averaged. While the hardware average function is in progress, SC2[ADACT] will be set. After the selected input is sampled and converted, the result is placed in an accumulator from which an average is calculated once the selected number of conversions have been completed. When hardware averaging is selected, the completion of a single conversion will not set SC1n[COCO]. If the compare function is either disabled or evaluates true, after the selected number of conversions are completed, the average conversion result is transferred into the data result registers, Rn, and SC1n[COCO] is set. An ADC interrupt is generated upon the setting of SC1n[COCO] if the respective ADC interrupt is enabled, that is, SC1n[AIEN]=1. Note The hardware average function can perform conversions on a channel while the MCU is in Wait or Normal Stop modes. The ADC interrupt wakes the MCU when the hardware average is completed if SC1n[AIEN] was set. 28.4.5 Automatic compare function The compare function can be configured to check whether the result is less than or greater-than-or-equal-to a single compare value, or, if the result falls within or outside a range determined by two compare values. The compare mode is determined by SC2[ACFGT], SC2[ACREN], and the values in the compare value registers, CV1 and KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 453 Functional description CV2. After the input is sampled and converted, the compare values in CV1 and CV2 are used as described in the following table. There are six Compare modes as shown in the following table. Table 28-61. Compare modes SC2[AC FGT] SC2[AC REN] ADCCV1 relative to ADCCV2 0 0 1 Function Compare mode description -- Less than threshold Compare true if the result is less than the CV1 registers. 0 -- Greater than or equal to threshold Compare true if the result is greater than or equal to CV1 registers. 0 1 Less than or equal Outside range, not inclusive Compare true if the result is less than CV1 Or the result is greater than CV2. 0 1 Greater than Inside range, not inclusive Compare true if the result is less than CV1 And the result is greater than CV2. 1 1 Less than or equal Inside range, inclusive Compare true if the result is greater than or equal to CV1 And the result is less than or equal to CV2. 1 1 Greater than Outside range, inclusive Compare true if the result is greater than or equal to CV1 Or the result is less than or equal to CV2. With SC2[ACREN] =1, and if the value of CV1 is less than or equal to the value of CV2, then setting SC2[ACFGT] will select a trigger-if-inside-compare-range inclusive-ofendpoints function. Clearing SC2[ACFGT] will select a trigger-if-outside-comparerange, not-inclusive-of-endpoints function. If CV1 is greater than CV2, setting SC2[ACFGT] will select a trigger-if-outsidecompare-range, inclusive-of-endpoints function. Clearing SC2[ACFGT] will select a trigger-if-inside-compare-range, not-inclusive-of-endpoints function. If the condition selected evaluates true, SC1n[COCO] is set. Upon completion of a conversion while the compare function is enabled, if the compare condition is not true, SC1n[COCO] is not set and the conversion result data will not be transferred to the result register, Rn. If the hardware averaging function is enabled, the compare function compares the averaged result to the compare values. The same compare function definitions apply. An ADC interrupt is generated when SC1n[COCO] is set and the respective ADC interrupt is enabled, that is, SC1n[AIEN]=1. Note The compare function can monitor the voltage on a channel while the MCU is in Wait or Normal Stop modes. The ADC interrupt wakes the MCU when the compare condition is met. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 454 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) 28.4.6 Calibration function The ADC contains a self-calibration function that is required to achieve the specified accuracy. Calibration must be run, or valid calibration values written, after any reset and before a conversion is initiated. The calibration function sets the offset calibration value and the plus-side calibration values. The offset calibration value is automatically stored in the ADC offset correction register (OFS), and the plus-side calibration values are automatically stored in the ADC plus-side calibration registers, CLPx. The user must configure the ADC correctly prior to calibration, and must generate the plus-side gain calibration results and store them in the ADC plus-side gain register (PG) after the calibration function completes. Prior to calibration, the user must configure the ADC's clock source and frequency, low power configuration, voltage reference selection, sample time, and high speed configuration according to the application's clock source availability and needs. If the application uses the ADC in a wide variety of configurations, the configuration for which the highest accuracy is required should be selected, or multiple calibrations can be done for the different configurations. For best calibration results: * Set hardware averaging to maximum, that is, SC3[AVGE]=1 and SC3[AVGS]=11 for an average of 32 * Set ADC clock frequency fADCK less than or equal to 4 MHz * VREFH=VDDA * Calibrate at nominal voltage and temperature The input channel, conversion mode continuous function, compare function, resolution mode, and single-ended mode are all ignored during the calibration function. To initiate calibration, the user sets SC3[CAL] and the calibration will automatically begin if the SC2[ADTRG] is 0. If SC2[ADTRG] is 1, SC3[CAL] will not get set and SC3[CALF] will be set. While calibration is active, no ADC register can be written and no stop mode may be entered, or the calibration routine will be aborted causing SC3[CAL] to clear and SC3[CALF] to set. At the end of a calibration sequence, SC1n[COCO] will be set. SC1n[AIEN] can be used to allow an interrupt to occur at the end of a calibration sequence. At the end of the calibration routine, if SC3[CALF] is not set, the automatic calibration routine is completed successfully. To complete calibration, the user must generate the gain calibration values using the following procedure: 1. Initialize or clear a 16-bit variable in RAM. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 455 Functional description 2. Add the plus-side calibration results CLP0, CLP1, CLP2, CLP3, CLP4, and CLPS to the variable. 3. Divide the variable by two. 4. Set the MSB of the variable. 5. The previous two steps can be achieved by setting the carry bit, rotating to the right through the carry bit on the high byte and again on the low byte. 6. Store the value in the plus-side gain calibration register PG. When calibration is complete, the user may reconfigure and use the ADC as desired. A second calibration may also be performed, if desired, by clearing and again setting SC3[CAL]. Overall, the calibration routine may take as many as 14k ADCK cycles and 100 bus cycles, depending on the results and the clock source chosen. For an 8 MHz clock source, this length amounts to about 1.7 ms. To reduce this latency, the calibration values, which are offset, plus-side gain, and plus-side calibration values, may be stored in flash memory after an initial calibration and recovered prior to the first ADC conversion. This method can reduce the calibration latency to 20 register store operations on all subsequent power, reset, or Low-Power Stop mode recoveries. 28.4.7 User-defined offset function OFS contains the user-selected or calibration-generated offset error correction value. This register is a 2's complement, left-justified. The value in OFS is subtracted from the conversion and the result is transferred into the result registers, Rn. If the result is greater than the maximum or less than the minimum result value, it is forced to the appropriate limit for the current mode of operation. The formatting of the OFS is different from the data result register, Rn, to preserve the resolution of the calibration value regardless of the conversion mode selected. Lower order bits are ignored in lower resolution modes. For example, in 8-bit single-ended mode, OFS[14:7] are subtracted from D[7:0]; OFS[15] indicates the sign (negative numbers are effectively added to the result) and OFS[6:0] are ignored. OFS is automatically set according to calibration requirements once the self-calibration sequence is done, that is, SC3[CAL] is cleared. The user may write to OFS to override the calibration result if desired. If the OFS is written by the user to a value that is different from the calibration value, the ADC error specifications may not be met. Storing the value generated by the calibration function in memory before overwriting with a userspecified value is recommended. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 456 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) Note There is an effective limit to the values of offset that can be set by the user. If the magnitude of the offset is too high, the results of the conversions will cap off at the limits. The offset calibration function may be employed by the user to remove application offsets or DC bias values. OFS may be written with a number in 2's complement format and this offset will be subtracted from the result, or hardware averaged value. To add an offset, store the negative offset in 2's complement format and the effect will be an addition. An offset correction that results in an out-of-range value will be forced to the minimum or maximum value. The minimum value for single-ended conversions is 0x0000. To preserve accuracy, the calibrated offset value initially stored in OFS must be added to the user-defined offset. For applications that may change the offset repeatedly during operation, store the initial offset calibration value in flash so it can be recovered and added to any user offset adjustment value and the sum stored in OFS. 28.4.8 Temperature sensor The ADC module includes a temperature sensor whose output is connected to one of the ADC analog channel inputs. The following equation provides an approximate transfer function of the temperature sensor. m Figure 28-47. Approximate transfer function of the temperature sensor where: * VTEMP is the voltage of the temperature sensor channel at the ambient temperature. * VTEMP25 is the voltage of the temperature sensor channel at 25 C. * m is referred as temperature sensor slope in the device data sheet. It is the hot or cold voltage versus temperature slope in V/C. For temperature calculations, use the VTEMP25 and temperature sensor slope values from the ADC Electricals table. In application code, the user reads the temperature sensor channel, calculates VTEMP, and compares to VTEMP25. If VTEMP is greater than VTEMP25 the cold slope value is applied in the preceding equation. If VTEMP is less than VTEMP25, the hot slope value is applied in KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 457 Functional description the preceding equation. ADC Electricals table may only specify one temperature sensor slope value. In that case, the user could use the same slope for the calculation across the operational temperature range. For more information on using the temperature sensor, see the application note titled Temperature Sensor for the HCS08 Microcontroller Family (document AN3031). 28.4.9 MCU wait mode operation Wait mode is a lower-power consumption Standby mode from which recovery is fast because the clock sources remain active. If a conversion is in progress when the MCU enters Wait mode, it continues until completion. Conversions can be initiated while the MCU is in Wait mode by means of the hardware trigger or if continuous conversions are enabled. The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in Wait mode. The use of ALTCLK as the conversion clock source in Wait is dependent on the definition of ALTCLK for this MCU. See the Chip Configuration information on ALTCLK specific to this MCU. If the compare and hardware averaging functions are disabled, a conversion complete event sets SC1n[COCO] and generates an ADC interrupt to wake the MCU from Wait mode if the respective ADC interrupt is enabled, that is, when SC1n[AIEN]=1. If the hardware averaging function is enabled, SC1n[COCO] will set, and generate an interrupt if enabled, when the selected number of conversions are completed. If the compare function is enabled, SC1n[COCO] will set, and generate an interrupt if enabled, only if the compare conditions are met. If a single conversion is selected and the compare trigger is not met, the ADC will return to its idle state and cannot wake the MCU from Wait mode unless a new conversion is initiated by the hardware trigger. 28.4.10 MCU Normal Stop mode operation Stop mode is a low-power consumption Standby mode during which most or all clock sources on the MCU are disabled. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 458 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) 28.4.10.1 Normal Stop mode with ADACK disabled If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a stop instruction aborts the current conversion and places the ADC in its Idle state. The contents of the ADC registers, including Rn, are unaffected by Normal Stop mode. After exiting from Normal Stop mode, a software or hardware trigger is required to resume conversions. 28.4.10.2 Normal Stop mode with ADACK enabled If ADACK is selected as the conversion clock, the ADC continues operation during Normal Stop mode. See the chip configuration chapter for configuration information for this MCU. If a conversion is in progress when the MCU enters Normal Stop mode, it continues until completion. Conversions can be initiated while the MCU is in Normal Stop mode by means of the hardware trigger or if continuous conversions are enabled. If the compare and hardware averaging functions are disabled, a conversion complete event sets SC1n[COCO] and generates an ADC interrupt to wake the MCU from Normal Stop mode if the respective ADC interrupt is enabled, that is, when SC1n[AIEN]=1. The result register, Rn, will contain the data from the first completed conversion that occurred during Normal Stop mode. If the hardware averaging function is enabled, SC1n[COCO] will set, and generate an interrupt if enabled, when the selected number of conversions are completed. If the compare function is enabled, SC1n[COCO] will set, and generate an interrupt if enabled, only if the compare conditions are met. If a single conversion is selected and the compare is not true, the ADC will return to its Idle state and cannot wake the MCU from Normal Stop mode unless a new conversion is initiated by another hardware trigger. 28.4.11 MCU Low-Power Stop mode operation The ADC module is automatically disabled when the MCU enters Low-Power Stop mode. All module registers contain their reset values following exit from Low-Power Stop mode. Therefore, the module must be re-enabled and re-configured following exit from Low-Power Stop mode. NOTE For the chip specific modes of operation, see the power management information for the device. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 459 Initialization information 28.5 Initialization information This section gives an example that provides some basic direction on how to initialize and configure the ADC module. The user can configure the module for 12-bit, 10-bit, or 8-bit single-ended resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. For information used in this example, refer to Table 28-57, Table 28-58, and Table 28-59. Note Hexadecimal values are designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. 28.5.1 ADC module initialization example 28.5.1.1 Initialization sequence Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is: 1. Calibrate the ADC by following the calibration instructions in Calibration function. 2. Update CFG to select the input clock source and the divide ratio used to generate ADCK. This register is also used for selecting sample time and low-power configuration. 3. Update SC2 to select the conversion trigger, hardware or software, and compare function options, if enabled. 4. Update SC3 to select whether conversions will be continuous or completed only once (ADCO) and whether to perform hardware averaging. 5. Update SC1:SC1n registers to enable or disable conversion complete interrupts. Also, select the input channel which can be used to perform conversions. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 460 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) 28.5.1.2 Pseudo-code example In this example, the ADC module is set up with interrupts enabled to perform a single 10bit conversion at low-power with a long sample time on input channel 1, where ADCK is derived from the bus clock divided by 1. CFG1 = 0x98 (%10011000) Bit Bit Bit Bit Bit 7 ADLPC 1 6:5 ADIV 00 4 ADLSMP 1 3:2 MODE 10 1:0 ADICLK 00 Configures for low power, lowers maximum clock speed. Sets the ADCK to the input clock / 1. Configures for long sample time. Selects the single-ended 10-bit conversion. Selects the bus clock. SC2 = 0x00 (%00000000) Bit Bit Bit Bit Bit Bit Bit and VREFL). 7 6 5 4 3 2 1:0 ADACT ADTRG ACFE ACFGT ACREN DMAEN REFSEL 0 0 0 0 0 0 00 Flag indicates if a conversion is in progress. Software trigger selected. Compare function disabled. Not used in this example. Compare range disabled. DMA request disabled. Selects default voltage reference pin pair (External pins VREFH SC1A = 0x41 (%01000001) Bit 7 Bit 6 COCO AIEN Bit 4:0 ADCH 0 1 Read-only flag which is set when a conversion completes. Conversion complete interrupt enabled. 00001 Input channel 1 selected as ADC input channel. RA = 0xxx Holds results of conversion. CV = 0xxx Holds compare value when compare function enabled. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 461 Application information Reset Initialize ADC CFG1 = 0x98 SC2 = 0x00 SC1n = 0x41 Check No SC1n[COCO]=1? Yes Read Rn to clear SC1n[COCO] Continue Figure 28-48. Initialization flowchart example 28.6 Application information The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an ADC. 28.6.1 External pins and routing 28.6.1.1 Analog supply pins Depending on the device, the analog power and ground supplies, VDDA and VSSA, of the ADC module are available as: * VDDA and VSSA available as separate pins--When available on a separate pin, both VDDA and VSSA must be connected to the same voltage potential as their corresponding MCU digital supply, VDD and VSS, and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 462 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) * VSSA is shared on the same pin as the MCU digital VSS. * VSSA and VDDA are shared with the MCU digital supply pins--In these cases, there are separate pads for the analog supplies bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. If separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the VSSA pin. This must be the only ground connection between these supplies, if possible. VSSA makes a good single point ground location. 28.6.1.2 Analog voltage reference pins In addition to the analog supplies, the ADC module has connections for two reference voltage inputs used by the converter: * VREFSH is the high reference voltage for the converter. * VREFSL is the low reference voltage for the converter. The ADC can be configured to accept one of two voltage reference pairs for VREFSH and VREFSL. Each pair contains a positive reference and a ground reference. The two pairs are external, VREFH and VREFL and alternate, VALTH and VALTL. These voltage references are selected using SC2[REFSEL]. The alternate voltage reference pair, VALTH and VALTL, may select additional external pins or internal sources based on MCU configuration. See the chip configuration information on the voltage references specific to this MCU. In some packages, the external or alternate pairs are connected in the package to VDDA and VSSA, respectively. One of these positive references may be shared on the same pin as VDDA on some devices. One of these ground references may be shared on the same pin as VSSA on some devices. If externally available, the positive reference may be connected to the same potential as VDDA or may be driven by an external source to a level between the minimum Ref Voltage High and the VDDA potential. The positive reference must never exceed VDDA. If externally available, the ground reference must be connected to the same voltage potential as VSSA. The voltage reference pairs must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. AC current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the VREFH and VREFL loop. The best external component to meet this current demand is a 0.1 F capacitor with good high-frequency characteristics. This capacitor is connected between VREFH and VREFL and must be placed as near as possible to the package pins. Resistance in the path is not recommended because the current causes a voltage drop that could result in conversion errors. Inductance in this path must be minimum, that is, parasitic only. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 463 Application information 28.6.1.3 Analog input pins The external analog inputs are typically shared with digital I/O pins on MCU devices. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. Use of 0.01 F capacitors with good high-frequency characteristics is sufficient. These capacitors are not necessary in all cases, but when used, they must be placed as near as possible to the package pins and be referenced to VSSA. For proper conversion, the input voltage must fall between VREFH and VREFL. If the input is equal to or exceeds VREFH, the converter circuit converts the signal to 0xFFF, which is full scale 12-bit representation, 0x3FF, which is full scale 10-bit representation, or 0xFF, which is full scale 8-bit representation. If the input is equal to or less than VREFL, the converter circuit converts it to 0x000. Input voltages between VREFH and VREFL are straight-line linear conversions. There is a brief current associated with VREFL when the sampling capacitor is charging. For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins must not be transitioning during conversions. 28.6.2 Sources of error 28.6.2.1 Sampling error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. RAS + RADIN =SC / (FMAX * NUMTAU * CADIN) Figure 28-49. Sampling equation Where: RAS = External analog source resistance SC = Number of ADCK cycles used during sample window CADIN = Internal ADC input capacitance NUMTAU = -ln(LSBERR / 2N) KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 464 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) LSBERR = value of acceptable sampling error in LSBs N = 8 in 8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode Higher source resistances or higher-accuracy sampling is possible by setting CFG1[ADLSMP] and changing CFG2[ADLSTS] to increase the sample window, or decreasing ADCK frequency to increase sample time. 28.6.2.2 Pin leakage error Leakage on the I/O pins can cause conversion error if the external analog source resistance, RAS, is high. If this error cannot be tolerated by the application, keep RAS lower than VREFH / (4 x ILEAK x 2N) for less than 1/4 LSB leakage error, where N = 8 in 8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode. 28.6.2.3 Noise-induced errors System noise that occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are met: * There is a 0.1 F low-ESR capacitor from VREFH to VREFL. * There is a 0.1 F low-ESR capacitor from VDDA to VSSA. * If inductive isolation is used from the primary supply, an additional 1 F capacitor is placed from VDDA to VSSA. * VSSA, and VREFL, if connected, is connected to VSS at a quiet point in the ground plane. * Operate the MCU in Wait or Normal Stop mode before initiating (hardware-triggered conversions) or immediately after initiating (hardware- or software-triggered conversions) the ADC conversion. * For software triggered conversions, immediately follow the write to SC1 with a Wait instruction or Stop instruction. * For Normal Stop mode operation, select ADACK as the clock source. Operation in Normal Stop reduces VDD noise but increases effective conversion time due to stop recovery. * There is no I/O switching, input or output, on the MCU during the conversion. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 465 Application information There are some situations where external system activity causes radiated or conducted noise emissions or excessive VDD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in Wait or Normal Stop mode, or I/O activity cannot be halted, the following actions may reduce the effect of noise on the accuracy: * Place a 0.01 F capacitor (CAS) on the selected input channel to VREFL or VSSA. This improves noise issues, but affects the sample rate based on the external analog source resistance. * Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1 LSB, one-time error. * Reduce the effect of synchronous noise by operating off the asynchronous clock, that is, ADACK, and averaging. Noise that is synchronous to ADCK cannot be averaged out. 28.6.2.4 Code width and quantization error The ADC quantizes the ideal straight-line transfer function into 4096 steps in the 12-bit mode). Each step ideally has the same height, that is, 1 code, and width. The width is defined as the delta between the transition points to one code and the next. The ideal code width for an N-bit converter, where N can be 12, 10, or 8, defined as 1 LSB, is: LSB Figure 28-50. Ideal code width for an N-bit converter There is an inherent quantization error due to the digitization of the result. For 8-bit, 10bit, or 12-bit conversions, the code transitions when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function. Therefore, the quantization error will be 1/2 LSB in 8-bit, 10bit, or 12-bit modes. As a consequence, however, the code width of the first (0x000) conversion is only 1/2 LSB and the code width of the last (0xFF or 0x3FF) is 1.5 LSB. 28.6.2.5 Linearity errors The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors, but the system designers must be aware of these errors because they affect overall accuracy: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 466 Freescale Semiconductor, Inc. Chapter 28 Analog-to-Digital Converter (ADC) * Zero-scale error (EZS), sometimes called offset: This error is defined as the difference between the actual code width of the first conversion and the ideal code width. This is 1/2 LSB in 8-bit, 10-bit, or 12-bit modes. If the first conversion is 0x001, the difference between the actual 0x001 code width and its ideal (1 LSB) is used. * Full-scale error (EFS): This error is defined as the difference between the actual code width of the last conversion and the ideal code width. This is 1.5 LSB in 8-bit, 10-bit, or 12-bit modes. If the last conversion is 0x3FE, the difference between the actual 0x3FE code width and its ideal (1 LSB) is used. * Differential non-linearity (DNL): This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. * Integral non-linearity (INL): This error is defined as the highest-value or absolute value that the running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. * Total unadjusted error (TUE): This error is defined as the difference between the actual transfer function and the ideal straight-line transfer function and includes all forms of error. 28.6.2.6 Code jitter, non-monotonicity, and missing codes Analog-to-digital converters are susceptible to three special forms of error: * Code jitter: Code jitter is when, at certain points, a given input voltage converts to one of the two values when sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the converter yields the lower code, and vice-versa. However, even small amounts of system noise can cause the converter to be indeterminate, between two codes, for a range of input voltages around the transition voltage. This error may be reduced by repeatedly sampling the input and averaging the result. Additionally, the techniques discussed in Noise-induced errors reduces this error. * Non-monotonicity: Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. * Missing codes: Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 467 Application information KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 468 Freescale Semiconductor, Inc. Chapter 29 Comparator (CMP) 29.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The comparator (CMP) module provides a circuit for comparing two analog input voltages. The comparator circuit is designed to operate across the full range of the supply voltage, known as rail-to-rail operation. The Analog MUX (ANMUX) provides a circuit for selecting an analog input signal from eight channels. One signal is provided by the 6-bit digital-to-analog converter (DAC). The mux circuit is designed to operate across the full range of the supply voltage. The 6-bit DAC is 64-tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed. The 64-tap resistor ladder network divides the supply reference Vin into 64 voltage levels. A 6-bit digital signal input selects the output voltage level, which varies from Vin to Vin/64. Vin can be selected from two voltage sources, Vin1 and Vin2. The 6-bit DAC from a comparator is available as an on-chip internal signal only and is not available externally to a pin. 29.2 CMP features The CMP has the following features: * Operational over the entire supply range * Inputs may range from rail to rail * Programmable hysteresis control KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 469 6-bit DAC key features * Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator output * Selectable inversion on comparator output * Capability to produce a wide range of outputs such as: * Sampled * Windowed, which is ideal for certain PWM zero-crossing-detection applications * Digitally filtered: * Filter can be bypassed * Can be clocked via external SAMPLE signal or scaled bus clock * External hysteresis can be used at the same time that the output filter is used for internal functions * Two software selectable performance levels: * Shorter propagation delay at the expense of higher power * Low power, with longer propagation delay * DMA transfer support * A comparison event can be selected to trigger a DMA transfer * Functional in all modes of operation * The window and filter functions are not available in the following modes: * Stop * VLPS * LLS * VLLSx 29.3 6-bit DAC key features * * * * 6-bit resolution Selectable supply reference source Power Down mode to conserve power when not in use Option to route the output to internal comparator input KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 470 Freescale Semiconductor, Inc. Chapter 29 Comparator (CMP) 29.4 ANMUX key features * Two 8-to-1 channel mux * Operational over the entire supply range 29.5 CMP, DAC and ANMUX diagram The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 471 CMP block diagram VRSEL Vin1 Vin2 VOSEL[5:0] MUX DAC output MUX 64-level DACEN DAC PSEL[2:0] CMP MUX Reference Input 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Reference Input 5 Reference Input 6 INP Sample input CMP MUX ANMUX Window and filter control INM IRQ CMPO MSEL[2:0] Figure 29-1. CMP, DAC and ANMUX block diagram 29.6 CMP block diagram The following figure shows the block diagram for the CMP module. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 472 Freescale Semiconductor, Inc. Chapter 29 Comparator (CMP) Internal bus FILT_PER EN,PMODE,HYSCTRL[1:0] COS INV OPE WE FILTER_CNT SE COUT IER/F CFR/F INP + - CMPO Polarity select Window control Interrupt control Filter block INM IRQ COUT To other SOC functions WINDOW/SAMPLE bus clock Clock prescaler FILT_PER 1 0 0 divided bus clock COUTA CGMUX SE 1 CMPO to PAD COS Figure 29-2. Comparator module block diagram In the CMP block diagram: * The Window Control block is bypassed when CR1[WE] = 0 * If CR1[WE] = 1, the comparator output will be sampled on every bus clock when WINDOW=1 to generate COUTA. Sampling does NOT occur when WINDOW = 0. * The Filter block is bypassed when not in use. * The Filter block acts as a simple sampler if the filter is bypassed and CR0[FILTER_CNT] is set to 0x01. * The Filter block filters based on multiple samples when the filter is bypassed and CR0[FILTER_CNT] is set greater than 0x01. * If CR1[SE] = 1, the external SAMPLE input is used as sampling clock * IF CR1[SE] = 0, the divided bus clock is used as sampling clock KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 473 Memory map/register definitions * If enabled, the Filter block will incur up to one bus clock additional latency penalty on COUT due to the fact that COUT, which is crossing clock domain boundaries, must be resynchronized to the bus clock. * CR1[WE] and CR1[SE] are mutually exclusive. 29.7 Memory map/register definitions CMP memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_3000 CMP Control Register 0 (CMP0_CR0) 8 R/W 00h 29.7.1/474 4007_3001 CMP Control Register 1 (CMP0_CR1) 8 R/W 00h 29.7.2/475 4007_3002 CMP Filter Period Register (CMP0_FPR) 8 R/W 00h 29.7.3/477 4007_3003 CMP Status and Control Register (CMP0_SCR) 8 R/W 00h 29.7.4/477 4007_3004 DAC Control Register (CMP0_DACCR) 8 R/W 00h 29.7.5/478 4007_3005 MUX Control Register (CMP0_MUXCR) 8 R/W 00h 29.7.6/479 1 0 29.7.1 CMP Control Register 0 (CMPx_CR0) Address: 4007_3000h base + 0h offset = 4007_3000h Bit 7 Read Write Reset 0 0 6 5 4 FILTER_CNT 0 0 0 3 2 0 0 0 0 HYSTCTR 0 0 CMPx_CR0 field descriptions Field 7 Reserved 6-4 FILTER_CNT Description This field is reserved. This read-only field is reserved and always has the value 0. Filter Sample Count Represents the number of consecutive samples that must agree prior to the comparator ouput filter accepting a new output state. For information regarding filter programming and latency, see the Functional description. 000 001 010 011 100 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. One sample must agree. The comparator output is simply sampled. 2 consecutive samples must agree. 3 consecutive samples must agree. 4 consecutive samples must agree. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 474 Freescale Semiconductor, Inc. Chapter 29 Comparator (CMP) CMPx_CR0 field descriptions (continued) Field Description 101 110 111 5 consecutive samples must agree. 6 consecutive samples must agree. 7 consecutive samples must agree. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1-0 HYSTCTR Comparator hard block hysteresis control Defines the programmable hysteresis level. The hysteresis values associated with each level are devicespecific. See the Data Sheet of the device for the exact values. 00 01 10 11 Level 0 Level 1 Level 2 Level 3 29.7.2 CMP Control Register 1 (CMPx_CR1) Address: 4007_3000h base + 1h offset = 4007_3001h Bit Read Write Reset 7 6 5 4 3 2 1 0 SE WE TRIGM PMODE INV COS OPE EN 0 0 0 0 0 0 0 0 CMPx_CR1 field descriptions Field 7 SE Description Sample Enable At any given time, either SE or WE can be set. It is mandatory request to not set SE and WE both at a given time. 0 1 6 WE Windowing Enable At any given time, either SE or WE can be set. It is mandatory request to not set SE and WE both at a given time. 0 1 5 TRIGM Sampling mode is not selected. Sampling mode is selected. Windowing mode is not selected. Windowing mode is selected. Trigger Mode Enable CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to 1. In addition, the CMP should be enabled. If the DAC is to be used as a reference to the CMP, it should also be enabled. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 475 Memory map/register definitions CMPx_CR1 field descriptions (continued) Field Description CMP Trigger mode depends on an external timer resource to periodically enable the CMP and 6-bit DAC in order to generate a triggered compare. Upon setting TRIGM, the CMP and DAC are placed in a standby state until an external timer resource trigger is received. See the chip configuration chapter for details about the external timer resource. 0 1 4 PMODE Power Mode Select See the electrical specifications table in the device Data Sheet for details. 0 1 3 INV Trigger mode is disabled. Trigger mode is enabled. Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. Comparator INVERT Allows selection of the polarity of the analog comparator function. It is also driven to the COUT output, on both the device pin and as SCR[COUT], when OPE=0. 0 1 Does not invert the comparator output. Inverts the comparator output. 2 COS Comparator Output Select 1 OPE Comparator Output Pin Enable 0 1 0 1 Set the filtered comparator output (CMPO) to equal COUT. Set the unfiltered comparator output (CMPO) to equal COUTA. CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. 0 EN Comparator Module Enable Enables the Analog Comparator module. When the module is not enabled, it remains in the off state, and consumes no power. When the user selects the same input from analog mux to the positive and negative port, the comparator is disabled automatically. 0 1 Analog Comparator is disabled. Analog Comparator is enabled. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 476 Freescale Semiconductor, Inc. Chapter 29 Comparator (CMP) 29.7.3 CMP Filter Period Register (CMPx_FPR) Address: 4007_3000h base + 2h offset = 4007_3002h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 FILT_PER 0 0 0 0 CMPx_FPR field descriptions Field 7-0 FILT_PER Description Filter Sample Period Specifies the sampling period, in bus clock cycles, of the comparator output filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter programming and latency details appear in the Functional description. This field has no effect when CR1[SE]=1. In that case, the external SAMPLE signal is used to determine the sampling period. 29.7.4 CMP Status and Control Register (CMPx_SCR) Address: 4007_3000h base + 3h offset = 4007_3003h Bit 7 Read 0 6 DMAEN Write Reset 0 0 5 0 0 4 3 IER IEF 0 0 2 1 0 CFR CFF COUT w1c w1c 0 0 0 CMPx_SCR field descriptions Field 7 Reserved 6 DMAEN Description This field is reserved. This read-only field is reserved and always has the value 0. DMA Enable Control Enables the DMA transfer triggered from the CMP module. When this field is set, a DMA request is asserted when CFR or CFF is set. 0 1 5 Reserved 4 IER DMA is disabled. DMA is enabled. This field is reserved. This read-only field is reserved and always has the value 0. Comparator Interrupt Enable Rising Enables the CFR interrupt from the CMP. When this field is set, an interrupt will be asserted when CFR is set. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 477 Memory map/register definitions CMPx_SCR field descriptions (continued) Field Description 0 1 3 IEF Comparator Interrupt Enable Falling Enables the CFF interrupt from the CMP. When this field is set, an interrupt will be asserted when CFF is set. 0 1 2 CFR Detects a rising-edge on COUT, when set, during normal operation. CFR is cleared by writing 1 to it. During Stop modes, CFR is level sensitive . Rising-edge on COUT has not been detected. Rising-edge on COUT has occurred. Analog Comparator Flag Falling Detects a falling-edge on COUT, when set, during normal operation. CFF is cleared by writing 1 to it. During Stop modes, CFF is level senstive . 0 1 0 COUT Interrupt is disabled. Interrupt is enabled. Analog Comparator Flag Rising 0 1 1 CFF Interrupt is disabled. Interrupt is enabled. Falling-edge on COUT has not been detected. Falling-edge on COUT has occurred. Analog Comparator Output Returns the current value of the Analog Comparator output, when read. The field is reset to 0 and will read as CR1[INV] when the Analog Comparator module is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored. 29.7.5 DAC Control Register (CMPx_DACCR) Address: 4007_3000h base + 4h offset = 4007_3004h Bit Read Write Reset 7 6 DACEN VRSEL 0 0 5 4 3 2 1 0 0 0 0 VOSEL 0 0 0 CMPx_DACCR field descriptions Field 7 DACEN Description DAC Enable Enables the DAC. When the DAC is disabled, it is powered down to conserve power. 0 1 6 VRSEL DAC is disabled. DAC is enabled. Supply Voltage Reference Source Select Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 478 Freescale Semiconductor, Inc. Chapter 29 Comparator (CMP) CMPx_DACCR field descriptions (continued) Field Description 0 1 5-0 VOSEL V is selected as resistor ladder network supply reference V. in1in V is selected as resistor ladder network supply reference V. in2in DAC Output Voltage Select Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in . 29.7.6 MUX Control Register (CMPx_MUXCR) Address: 4007_3000h base + 5h offset = 4007_3005h Bit Read Write Reset 7 6 Reserved 0 0 0 5 4 3 2 PSEL 0 0 1 0 MSEL 0 0 0 0 CMPx_MUXCR field descriptions Field Description 7 Reserved Bit can be programmed to zero only . 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5-3 PSEL This field is reserved. Plus Input Mux Control Determines which input is selected for the plus input of the comparator. For INx inputs, see CMP, DAC, and ANMUX block diagrams. NOTE: When an inappropriate operation selects the same input for both muxes, the comparator automatically shuts down to prevent itself from becoming a noise generator. 000 001 010 011 100 101 110 111 2-0 MSEL IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 Minus Input Mux Control Determines which input is selected for the minus input of the comparator. For INx inputs, see CMP, DAC, and ANMUX block diagrams. NOTE: When an inappropriate operation selects the same input for both muxes, the comparator automatically shuts down to prevent itself from becoming a noise generator. 000 IN0 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 479 Functional description CMPx_MUXCR field descriptions (continued) Field Description 001 010 011 100 101 110 111 IN1 IN2 IN3 IN4 IN5 IN6 IN7 29.8 Functional description The CMP module can be used to compare two analog input voltages applied to INP and INM. CMPO is high when the non-inverting input is greater than the inverting input, and is low when the non-inverting input is less than the inverting input. This signal can be selectively inverted by setting CR1[INV] = 1. SCR[IER] and SCR[IEF] are used to select the condition which will cause the CMP module to assert an interrupt to the processor. SCR[CFF] is set on a falling-edge and SCR[CFR] is set on rising-edge of the comparator output. The optionally filtered CMPO can be read directly through SCR[COUT]. 29.8.1 CMP functional modes There are three main sub-blocks to the CMP module: * The comparator itself * The window function * The filter function The filter, CR0[FILTER_CNT], can be clocked from an internal or external clock source. The filter is programmable with respect to the number of samples that must agree before a change in the output is registered. In the simplest case, only one sample must agree. In this case, the filter acts as a simple sampler. The external sample input is enabled using CR1[SE]. When set, the output of the comparator is sampled only on rising edges of the sample input. The "windowing mode" is enabled by setting CR1[WE]. When set, the comparator output is sampled only when WINDOW=1. This feature can be used to ignore the comparator output during time periods in which the input voltages are not valid. This is especially useful when implementing zero-crossing-detection for certain PWM applications. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 480 Freescale Semiconductor, Inc. Chapter 29 Comparator (CMP) The comparator filter and sampling features can be combined as shown in the following table. Individual modes are discussed below. Table 29-15. Comparator sample/filter controls Mode # CR1[EN] CR1[WE] CR1[SE] CR0[FILTER_C NT] FPR[FILT_PER] Operation 1 0 X X X X Disabled See the Disabled mode (# 1). 2A 1 0 0 0x00 X Continuous Mode 2B 1 0 0 X 0x00 See the Continuous mode (#s 2A & 2B). 3A 1 0 1 0x01 X Sampled, Non-Filtered mode 3B 1 0 0 0x01 > 0x00 See the Sampled, Non-Filtered mode (#s 3A & 3B). 4A 1 0 1 > 0x01 X Sampled, Filtered mode 4B 1 0 0 > 0x01 > 0x00 See the Sampled, Filtered mode (#s 4A & 4B). 5A 1 1 0 0x00 X Windowed mode 5B 1 1 0 X 0x00 Comparator output is sampled on every rising bus clock edge when SAMPLE=1 to generate COUTA. See the Windowed mode (#s 5A & 5B). 6 1 1 0 0x01 0x01-0xFF Windowed/Resampled mode Comparator output is sampled on every rising bus clock edge when SAMPLE=1 to generate COUTA, which is then resampled on an interval determined by FILT_PER to generate COUT. See the Windowed/Resampled mode (# 6). 7 1 1 0 > 0x01 0x01-0xFF Windowed/Filtered mode Comparator output is sampled on every rising bus clock edge when SAMPLE=1 to generate COUTA, which is then resampled and filtered to generate COUT. See the Windowed/Filtered mode (#7). All other combinations of CR1[EN], CR1[WE], CR1[SE], CR0[FILTER_CNT], and FPR[FILT_PER] are illegal. For cases where a comparator is used to drive a fault input, for example, for a motorcontrol module such as FTM, it must be configured to operate in Continuous mode so that an external fault can immediately pass through the comparator to the target fault circuitry. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 481 Functional description Note Filtering and sampling settings must be changed only after setting CR1[SE]=0 and CR0[FILTER_CNT]=0x00. This resets the filter to a known state. 29.8.1.1 Disabled mode (# 1) In Disabled mode, the analog comparator is non-functional and consumes no power. CMPO is 0 in this mode. 29.8.1.2 Continuous mode (#s 2A & 2B) Internal bus EN,PMODE,HYSTCTR[1:0] FILT_PER INV COS WE OPE FILTER_CNT SE COUT IER/F CFR/F 0 INP + - CMPO Polarity select Window control INM Filter block Interrupt control IRQ COUT To other system functions WINDOW/SAMPLE bus clock FILT_PER Clock prescaler 1 0 0 divided bus clock COUTA CGMUX SE 1 CMPO to PAD COS Figure 29-15. Comparator operation in Continuous mode NOTE See the chip configuration section for the source of sample/ window input. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 482 Freescale Semiconductor, Inc. Chapter 29 Comparator (CMP) The analog comparator block is powered and active. CMPO may be optionally inverted, but is not subject to external sampling or filtering. Both window control and filter blocks are completely bypassed. SCR[COUT] is updated continuously. The path from comparator input pins to output pin is operating in combinational unclocked mode. COUT and COUTA are identical. For control configurations which result in disabling the filter block, see the Filter Block Bypass Logic diagram. 29.8.1.3 Sampled, Non-Filtered mode (#s 3A & 3B) Internal bus EN,PMODE,HYSTCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT 0x01 0 IER/F CFR/F 1 INP + - CMPO Polarity select Window control INM Filter block Interrupt control IRQ COUT To other SOC functions WINDOW/SAMPLE Clock prescaler bus clock FILT_PER 1 0 0 divided bus clock COUTA CGMUX SE=1 1 CMPO to PAD COS Figure 29-16. Sampled, Non-Filtered (# 3A): sampling point externally driven In Sampled, Non-Filtered mode, the analog comparator block is powered and active. The path from analog inputs to COUTA is combinational unclocked. Windowing control is completely bypassed. COUTA is sampled whenever a rising-edge is detected on the filter block clock input. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 483 Functional description The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Non-Filtered (# 3B) is in how the clock to the filter block is derived. In #3A, the clock to filter block is externally derived while in #3B, the clock to filter block is internally derived. The comparator filter has no other function than sample/hold of the comparator output in this mode (# 3B). Internal bus EN,PMODE,HYSTCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT 0 IER/F CFR/F 0 0x01 INP + - CMPO Polarity select Window control Filter block INM Interrupt control IRQ COUT WINDOW/SAMPLE bus clock FILT_PER Clock prescaler To other SOC functions 1 0 0 divided bus clock COUTA CGMUX SE=0 1 CMPO to PAD COS Figure 29-17. Sampled, Non-Filtered (# 3B): sampling interval internally derived 29.8.1.4 Sampled, Filtered mode (#s 4A & 4B) In Sampled, Filtered mode, the analog comparator block is powered and active. The path from analog inputs to COUTA is combinational unclocked. Windowing control is completely bypassed. COUTA is sampled whenever a rising edge is detected on the filter block clock input. The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Filtered (# 4A) is that, now, CR0[FILTER_CNT]>1, which activates filter operation. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 484 Freescale Semiconductor, Inc. Chapter 29 Comparator (CMP) Internal bus EN, PMODE, HYSTCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT > 0x01 0 INP + - CMPO Polarity select Window control INM IER/F CFR/F 1 Interrupt control Filter block IRQ COUT To other SOC functions WINDOW/SAMPLE bus clock Clock prescaler FILT_PER 1 0 0 divided bus clock COUTA CGMUX SE=1 1 CMPO to PAD COS Figure 29-18. Sampled, Filtered (# 4A): sampling point externally driven KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 485 Functional description Internal bus OPE FILT_PER EN, PMODE,HYSTCTR[1:0] COS INV WE FILTER_CNT SE COUT IER/F CFR/F >0x01 0 0 INP + - Polarity CMPO select Window control INM Filter block Interrupt control IRQ COUT WINDOW/SAMPLE bus clock FILT_PER Clock prescaler To other SOC functions 1 0 0 divided bus clock COUTA CGMUX SE=0 1 CMPO to PAD COS Figure 29-19. Sampled, Filtered (# 4B): sampling point internally derived The only difference in operation between Sampled, Non-Filtered (# 3B) and Sampled, Filtered (# 4B) is that now, CR0[FILTER_CNT]>1, which activates filter operation. 29.8.1.5 Windowed mode (#s 5A & 5B) The following figure illustrates comparator operation in the Windowed mode, ignoring latency of the analog comparator, polarity select, and window control block. It also assumes that the polarity select is set to non-inverting state. NOTE The analog comparator output is passed to COUTA only when the WINDOW signal is high. In actual operation, COUTA may lag the analog inputs by up to one bus clock cycle plus the combinational path delay through the comparator and polarity select logic. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 486 Freescale Semiconductor, Inc. Chapter 29 Comparator (CMP) WI NDOW Plus input Minus input CMPO COUTA Figure 29-20. Windowed mode operation Internal bus EN, PMODE,HYSCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT 0x01 IER/F CFR/F 0 INP + - CMPO Polarity select Window control Interrupt control Filter block INM IRQ COUT To other SOC functions WINDOW/SAMPLE bus clock Clock prescaler FILT_PER 1 0 0 divided bus clock COUTA CGMUX SE=0 1 CMPO to PAD COS Figure 29-21. Windowed mode For control configurations which result in disabling the filter block, see Filter Block Bypass Logic diagram. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 487 Functional description When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. 29.8.1.6 Windowed/Resampled mode (# 6) The following figure uses the same input stimulus shown in Figure 29-20, and adds resampling of COUTA to generate COUT. Samples are taken at the time points indicated by the arrows in the figure. Again, prop delays and latency are ignored for the sake of clarity. This example was generated solely to demonstrate operation of the comparator in windowed/resampled mode, and does not reflect any specific application. Depending upon the sampling rate and window placement, COUT may not see zero-crossing events detected by the analog comparator. Sampling period and/or window placement must be carefully considered for a given application. WI NDOW Plus input Minus input CMPO COUTA COUT Figure 29-22. Windowed/resampled mode operation This mode of operation results in an unfiltered string of comparator samples where the interval between the samples is determined by FPR[FILT_PER] and the bus clock rate. Configuration for this mode is virtually identical to that for the Windowed/Filtered Mode shown in the next section. The only difference is that the value of CR0[FILTER_CNT] must be 1. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 488 Freescale Semiconductor, Inc. Chapter 29 Comparator (CMP) 29.8.1.7 Windowed/Filtered mode (#7) This is the most complex mode of operation for the comparator block, as it uses both windowing and filtering features. It also has the highest latency of any of the modes. This can be approximated: up to 1 bus clock synchronization in the window function + ((CR0[FILTER_CNT] * FPR[FILT_PER]) + 1) * bus clock for the filter function. When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. Internal bus EN, PMODE,HYSCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT > 0x01 1 INP + Polarity CMPO select - Window control IER/F CFR/F 0 Interrupt control Filter block INM IRQ COUT To other SOC functions WINDOW/SAMPLE bus clock Clock prescaler FILT_PER 1 0 0 divided bus clock COUTA CGMUX SE=0 1 CMPO to PAD COS Figure 29-23. Windowed/Filtered mode 29.8.2 Power modes 29.8.2.1 Wait mode operation During Wait and VLPW modes, the CMP, if enabled, continues to operate normally and a CMP interrupt can wake the MCU. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 489 Functional description 29.8.2.2 Stop mode operation Depending on clock restrictions related to the MCU core or core peripherals, the MCU is brought out of stop when a compare event occurs and the corresponding interrupt is enabled. Similarly, if CR1[OPE] is enabled, the comparator output operates as in the normal operating mode and comparator output is placed onto the external pin. In Stop modes, the comparator can be operational in both: * High-Speed (HS) Comparison mode when CR1[PMODE] = 1 * Low-Speed (LS) Comparison mode when CR1[PMODE] = 0 It is recommended to use the LS mode to minimize power consumption. If stop is exited with a reset, all comparator registers are put into their reset state. 29.8.2.3 Background Debug Mode Operation When the microcontroller is in active background debug mode, the CMP continues to operate normally. 29.8.3 Startup and operation A typical startup sequence is as follows. The time required to stabilize COUT will be the power-on delay of the comparators plus the largest propagation delay from a selected analog source through the analog comparator, windowing function and filter. See the Data Sheets for power-on delays of the comparators. The windowing function has a maximum of one bus clock period delay. The filter delay is specified in the Low-pass filter. During operation, the propagation delay of the selected data paths must always be considered. It may take many bus clock cycles for COUT and SCR[CFR]/SCR[CFF] to reflect an input change or a configuration change to one of the components involved in the data path. When programmed for filtering modes, COUT will initially be equal to 0, until sufficient clock cycles have elapsed to fill all stages of the filter. This occurs even if COUTA is at a logic 1. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 490 Freescale Semiconductor, Inc. Chapter 29 Comparator (CMP) 29.8.4 Low-pass filter The low-pass filter operates on the unfiltered and unsynchronized and optionally inverted comparator output COUTA and generates the filtered and synchronized output COUT. Both COUTA and COUT can be configured as module outputs and are used for different purposes within the system. Synchronization and edge detection are always used to determine status register bit values. They also apply to COUT for all sampling and windowed modes. Filtering can be performed using an internal timebase defined by FPR[FILT_PER], or using an external SAMPLE input to determine sample time. The need for digital filtering and the amount of filtering is dependent on user requirements. Filtering can become more useful in the absence of an external hysteresis circuit. Without external hysteresis, high-frequency oscillations can be generated at COUTA when the selected INM and INP input voltages differ by less than the offset voltage of the differential comparator. 29.8.4.1 Enabling filter modes Filter modes can be enabled by: * Setting CR0[FILTER_CNT] > 0x01 and * Setting FPR[FILT_PER] to a nonzero value or setting CR1[SE]=1 If using the divided bus clock to drive the filter, it will take samples of COUTA every FPR[FILT_PER] bus clock cycles. The filter output will be at logic 0 when first initalized, and will subsequently change when all the consecutive CR0[FILTER_CNT] samples agree that the output value has changed. In other words, SCR[COUT] will be 0 for some initial period, even when COUTA is at logic 1. Setting both CR1[SE] and FPR[FILT_PER] to 0 disables the filter and eliminates switching current associated with the filtering process. Note Always switch to this setting prior to making any changes in filter parameters. This resets the filter to a known state. Switching CR0[FILTER_CNT] on the fly without this intermediate step can result in unexpected behavior. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 491 Functional description If CR1[SE]=1, the filter takes samples of COUTA on each positive transition of the sample input. The output state of the filter changes when all the consecutive CR0[FILTER_CNT] samples agree that the output value has changed. 29.8.4.2 Latency issues The value of FPR[FILT_PER] or SAMPLE period must be set such that the sampling period is just longer than the period of the expected noise. This way a noise spike will corrupt only one sample. The value of CR0[FILTER_CNT] must be chosen to reduce the probability of noisy samples causing an incorrect transition to be recognized. The probability of an incorrect transition is defined as the probability of an incorrect sample raised to the power of CR0[FILTER_CNT]. The values of FPR[FILT_PER] or SAMPLE period and CR0[FILTER_CNT] must also be traded off against the desire for minimal latency in recognizing actual comparator output transitions. The probability of detecting an actual output change within the nominal latency is the probability of a correct sample raised to the power of CR0[FILTER_CNT]. The following table summarizes maximum latency values for the various modes of operation in the absence of noise. Filtering latency is restarted each time an actual output transition is masked by noise. Table 29-16. Comparator sample/filter maximum latencies Mode # CR1[ EN] CR1[ WE] CR1[ SE] CR0[FILTER _CNT] FPR[FILT_P ER] Operation Maximum latency1 1 0 X X X X Disabled N/A 2A 1 0 0 0x00 X Continuous Mode TPD 2B 1 0 0 X 0x00 3A 1 0 1 0x01 X Sampled, Non-Filtered mode TPD + TSAMPLE + Tper 3B 1 0 0 0x01 > 0x00 4A 1 0 1 > 0x01 X 4B 1 0 0 > 0x01 > 0x00 5A 1 1 0 0x00 X 5B 1 1 0 X 0x00 6 1 1 0 0x01 0x01 - 0xFF Windowed / Resampled mode TPD + (FPR[FILT_PER] * Tper) + 2Tper 7 1 1 0 > 0x01 0x01 - 0xFF Windowed / Filtered mode TPD + (CR0[FILTER_CNT] * FPR[FILT_PER] x Tper) + 2Tper TPD + (FPR[FILT_PER] * Tper) + Tper Sampled, Filtered mode TPD + (CR0[FILTER_CNT] * TSAMPLE) + Tper TPD + (CR0[FILTER_CNT] * FPR[FILT_PER] x Tper) + Tper Windowed mode TPD + Tper TPD + Tper KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 492 Freescale Semiconductor, Inc. Chapter 29 Comparator (CMP) 1. TPD represents the intrinsic delay of the analog component plus the polarity select logic. TSAMPLE is the clock period of the external sample clock. Tper is the period of the bus clock. 29.9 CMP interrupts The CMP module is capable of generating an interrupt on either the rising- or fallingedge of the comparator output, or both. The following table gives the conditions in which the interrupt request is asserted and deasserted. When Then SCR[IER] and SCR[CFR] are set The interrupt request is asserted SCR[IEF] and SCR[CFF] are set The interrupt request is asserted SCR[IER] and SCR[CFR] are cleared for a rising-edge interrupt The interrupt request is deasserted SCR[IEF] and SCR[CFF] are cleared for a falling-edge interrupt The interrupt request is deasserted 29.10 DMA support Normally, the CMP generates a CPU interrupt if there is a change on the COUT. When DMA support is enabled by setting SCR[DMAEN] and the interrupt is enabled by setting SCR[IER], SCR[IEF], or both, the corresponding change on COUT forces a DMA transfer request rather than a CPU interrupt instead. When the DMA has completed the transfer, it sends a transfer completing indicator that deasserts the DMA transfer request and clears the flag to allow a subsequent change on comparator output to occur and force another DMA request. The comparator can remain functional in STOP modes. When DMA support is enabled by setting SCR[DMAEN] and the interrupt is enabled by setting SCR[IER], SCR[IEF], or both, the corresponding change on COUT forces a DMA transfer request to wake up the system from STOP modes. After the data transfer has finished, system will go back to STOP modes. Refer to DMA chapters in the device reference manual for the asynchronous DMA function for details. 29.11 CMP Asyncrhonous DMA support The comparator can remain functional in STOP modes. When DMA support is enabled by setting SCR[DMAEN] and the interrupt is enabled by setting SCR[IER], SCR[IEF], or both, the corresponding change on COUT forces a DMA transfer request to wake up the KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 493 Digital-to-analog converter system from STOP modes. After the data transfer has finished, system will go back to STOP modes. Refer to DMA chapters in the device reference manual for the asynchronous DMA function for details. 29.12 Digital-to-analog converter The following figure shows the block diagram of the DAC module. It contains a 64-tap resistor ladder network and a 64-to-1 multiplexer, which selects an output voltage from one of 64 distinct levels that outputs from DACO. It is controlled through the DAC Control Register (DACCR). Its supply reference source can be selected from two sources Vin1 and Vin2. The module can be powered down or disabled when not in use. When in Disabled mode, DACO is connected to the analog ground. Vin1 VRSEL Vin2 MUX DACEN VOSEL[5:0] Vin MUX DACO Figure 29-24. 6-bit DAC block diagram 29.13 DAC functional description This section provides DAC functional description. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 494 Freescale Semiconductor, Inc. Chapter 29 Comparator (CMP) 29.13.1 Voltage reference source select * Vin1 connects to the primary voltage source as supply reference of 64 tap resistor ladder * Vin2 connects to an alternate voltage source 29.14 DAC resets This module has a single reset input, corresponding to the chip-wide peripheral reset. 29.15 DAC clocks This module has a single clock input, the bus clock. 29.16 DAC interrupts This module has no interrupts. 29.17 CMP Trigger Mode CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to 1. In addition, the CMP must be enabled. If the DAC is to be used as a reference to the CMP, it must also be enabled. CMP Trigger mode depends on an external timer resource to periodically enable the CMP and 6-bit DAC in order to generate a triggered compare. Upon setting TRIGM, the CMP and DAC are placed in a standby state until an external timer resource trigger is received. See the chip configuration chapter for details about the external timer resource. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 495 CMP Trigger Mode KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 496 Freescale Semiconductor, Inc. Chapter 30 12-bit Digital-to-Analog Converter (DAC) 30.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The 12-bit digital-to-analog converter (DAC) is a low-power, general-purpose DAC. The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator, op-amps, or ADC. 30.2 Features The features of the DAC module include: * On-chip programmable reference generator output. The voltage output range is from 14096 Vin to Vin, and the step is 14096 Vin, where Vin is the input voltage. * Vin can be selected from two reference sources * Static operation in Normal Stop mode * 2-word data buffer supported with multiple operation modes * DMA support 30.3 Block diagram The block diagram of the DAC module is as follows: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 497 Memory map/register definition DACREF_1 DACREF_2 DACRFS MUX AMP buffer Vin DACEN MUX 4096-level VDD - LPEN Vo Vout + DACDAT[11:0] 12 Hardware trigger DACBFWMF DACSWTRG DACBFWM DACBFEN DACBFUP DACBFRP Data Buffer DACBWIEN & DACBFRPTF DACBTIEN & dac_interrupt OR DACBFRPBF DACBBIEN & DACBFMD DACTRGSE Figure 30-1. DAC block diagram 30.4 Memory map/register definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 498 Freescale Semiconductor, Inc. Chapter 30 12-bit Digital-to-Analog Converter (DAC) DAC memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4003_F000 DAC Data Low Register (DAC0_DAT0L) 8 R/W 00h 30.4.1/499 4003_F001 DAC Data High Register (DAC0_DAT0H) 8 R/W 00h 30.4.2/499 4003_F002 DAC Data Low Register (DAC0_DAT1L) 8 R/W 00h 30.4.1/499 4003_F003 DAC Data High Register (DAC0_DAT1H) 8 R/W 00h 30.4.2/499 4003_F020 DAC Status Register (DAC0_SR) 8 R/W 02h 30.4.3/500 4003_F021 DAC Control Register (DAC0_C0) 8 R/W 00h 30.4.4/500 4003_F022 DAC Control Register 1 (DAC0_C1) 8 R/W 00h 30.4.5/502 4003_F023 DAC Control Register 2 (DAC0_C2) 8 R/W 01h 30.4.6/502 30.4.1 DAC Data Low Register (DACx_DATnL) Address: 4003_F000h base + 0h offset + (2d x i), where i=0d to 1d Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 DATA0 0 0 0 0 DACx_DATnL field descriptions Field 7-0 DATA0 Description When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA is mapped to the 16-word buffer. 30.4.2 DAC Data High Register (DACx_DATnH) Address: 4003_F000h base + 1h offset + (2d x i), where i=0d to 1d Bit Read Write Reset 7 6 5 4 3 2 0 0 0 1 0 0 0 DATA1 0 0 0 0 DACx_DATnH field descriptions Field 7-4 Reserved 3-0 DATA1 Description This field is reserved. This read-only field is reserved and always has the value 0. When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 499 Memory map/register definition 30.4.3 DAC Status Register (DACx_SR) If DMA is enabled, the flags can be cleared automatically by DMA when the DMA request is done. Writing 0 to a field clears it whereas writing 1 has no effect. After reset, DACBFRPTF is set and can be cleared by software, if needed. The flags are set only when the data buffer status is changed. NOTE Do not use 32/16-bit accesses to this register. Address: 4003_F000h base + 20h offset = 4003_F020h Bit Read Write Reset 7 6 5 4 3 2 0 0 0 0 1 0 DACBFRPT DACBFRPB F F 0 0 0 1 0 2 1 0 DACBTIEN DACBBIEN 0 0 DACx_SR field descriptions Field 7-2 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 1 DACBFRPTF DAC Buffer Read Pointer Top Position Flag 0 DACBFRPBF DAC Buffer Read Pointer Bottom Position Flag 0 1 0 1 The DAC buffer read pointer is not zero. The DAC buffer read pointer is zero. The DAC buffer read pointer is not equal to C2[DACBFUP]. The DAC buffer read pointer is equal to C2[DACBFUP]. 30.4.4 DAC Control Register (DACx_C0) NOTE Do not use 32- or 16-bit accesses to this register. Address: 4003_F000h base + 21h offset = 4003_F021h Bit Read Write Reset 7 6 DACEN DACRFS 0 0 5 4 0 DACTRGSE L DACSWTRG 0 0 3 LPEN 0 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 500 Freescale Semiconductor, Inc. Chapter 30 12-bit Digital-to-Analog Converter (DAC) DACx_C0 field descriptions Field 7 DACEN Description DAC Enable Starts the Programmable Reference Generator operation. 0 1 6 DACRFS The DAC system is disabled. The DAC system is enabled. DAC Reference Select 0 1 The DAC selects DACREF_1 as the reference voltage. The DAC selects DACREF_2 as the reference voltage. 5 DACTRGSEL DAC Trigger Select 4 DACSWTRG DAC Software Trigger 0 1 Active high. This is a write-only field, which always reads 0. If DAC software trigger is selected and buffer is enabled, writing 1 to this field will advance the buffer read pointer once. 0 1 3 LPEN The DAC hardware trigger is selected. The DAC software trigger is selected. The DAC soft trigger is not valid. The DAC soft trigger is valid. DAC Low Power Control NOTE: See the 12-bit DAC electrical characteristics of the device data sheet for details on the impact of the modes below. 0 1 2 Reserved High-Power mode Low-Power mode This field is reserved. This read-only field is reserved and always has the value 0. 1 DACBTIEN DAC Buffer Read Pointer Top Flag Interrupt Enable 0 DACBBIEN DAC Buffer Read Pointer Bottom Flag Interrupt Enable 0 1 0 1 The DAC buffer read pointer top flag interrupt is disabled. The DAC buffer read pointer top flag interrupt is enabled. The DAC buffer read pointer bottom flag interrupt is disabled. The DAC buffer read pointer bottom flag interrupt is enabled. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 501 Memory map/register definition 30.4.5 DAC Control Register 1 (DACx_C1) NOTE Do not use 32- or 16-bit accesses to this register. Address: 4003_F000h base + 22h offset = 4003_F022h Bit Read Write Reset 7 6 5 DMAEN 0 4 3 0 0 0 0 2 1 0 DACBFMD 0 DACBFEN 0 0 0 0 DACx_C1 field descriptions Field 7 DMAEN 6-3 Reserved 2 DACBFMD Description DMA Enable Select 0 1 DMA is disabled. DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time. This field is reserved. This read-only field is reserved and always has the value 0. DAC Buffer Work Mode Select 0 1 Normal mode One-Time Scan mode 1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 DACBFEN DAC Buffer Enable 0 1 Buffer read pointer is disabled. The converted data is always the first word of the buffer. Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. 30.4.6 DAC Control Register 2 (DACx_C2) NOTE Do not use 32- or 16-bit accesses to this register. Address: 4003_F000h base + 23h offset = 4003_F023h Bit Read Write Reset 7 6 5 0 0 0 4 3 DACBFRP 0 0 2 1 0 0 0 DACBFUP 0 0 1 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 502 Freescale Semiconductor, Inc. Chapter 30 12-bit Digital-to-Analog Converter (DAC) DACx_C2 field descriptions Field Description 7-5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 DACBFRP DAC Buffer Read Pointer 3-1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 DACBFUP DAC Buffer Upper Limit Keeps the current value of the buffer read pointer. Selects the upper limit of the DAC buffer. The buffer read pointer cannot exceed it. 30.5 Functional description The 12-bit DAC module can select one of the two reference inputs--DACREF_1 and DACREF_2 as the DAC reference voltage, Vin by C0[DACRFS]. See the module introduction for information on the source for DACREF_1 and DACREF_2. When the DAC is enabled, it converts the data in DACDAT0[11:0] or the data from the DAC data buffer to a stepped analog output voltage. The output voltage range is from Vin to Vin4096, and the step is Vin4096. 30.5.1 DAC data buffer operation When the DAC is enabled and the buffer is not enabled, the DAC module always converts the data in DAT0 to analog output voltage. When both the DAC and the buffer are enabled, the DAC converts the data in the data buffer to analog output voltage. The data buffer read pointer advances to the next word whenever any hardware or software trigger event occurs. Refer to Introduction for the hardware trigger connection. The data buffer can be configured to operate in Normal mode, Swing mode, or One-Time Scan mode. When the buffer operation is switched from one mode to another, the read pointer does not change. The read pointer can be set to any value between 0 and C2[DACBFUP] by writing C2[DACBFRP]. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 503 Functional description 30.5.1.1 DAC data buffer interrupts There are several interrupts and associated flags that can be configured for the DAC buffer. SR[DACBFRPBF] is set when the DAC buffer read pointer reaches the DAC buffer upper limit, that is, C2[DACBFRP] = C2[DACBFUP]. SR[DACBFRPTF] is set when the DAC read pointer is equal to the start position, 0. 30.5.1.2 Modes of DAC data buffer operation The following table describes the different modes of data buffer operation for the DAC module. Table 30-23. Modes of DAC data buffer operation Modes Description Buffer Normal mode This is the default mode. The buffer works as a circular buffer. The read pointer increases by one, every time the trigger occurs. When the read pointer reaches the upper limit, it goes to 0 directly in the next trigger event. Buffer One-time Scan mode The read pointer increases by 1 every time the trigger occurs. When it reaches the upper limit, it stops there. If read pointer is reset to the address other than the upper limit, it will increase to the upper address and stop there again. NOTE: If the software set the read pointer to the upper limit, the read pointer will not advance in this mode. 30.5.2 DMA operation When DMA is enabled, DMA requests are generated instead of interrupt requests. The DMA Done signal clears the DMA request. The status register flags are still set and are cleared automatically when the DMA completes. 30.5.3 Resets During reset, the DAC is configured in the default mode and is disabled. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 504 Freescale Semiconductor, Inc. Chapter 30 12-bit Digital-to-Analog Converter (DAC) 30.5.4 Low-Power mode operation The following table shows the wait mode and the stop mode operation of the DAC module. Table 30-24. Modes of operation Modes of operation Description Wait mode The DAC will operate normally, if enabled. Stop mode If enabled, the DAC module continues to operate in Normal Stop mode and the output voltage will hold the value before stop. In low-power stop modes, the DAC is fully shut down. NOTE The assignment of module modes to core modes is chipspecific. For module-to-core mode assignments, see the chapter that describes how modules are configured. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 505 Functional description KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 506 Freescale Semiconductor, Inc. Chapter 31 Timer/PWM Module (TPM) 31.1 Introduction The TPM (Timer/PWM Module) is a two to eight channel timer which supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications. The counter, compare and capture registers are clocked by an asynchronous clock that can remain enabled in low power modes. 31.1.1 TPM Philosophy The TPM is built upon a very simple timer (HCS08 Timer PWM Module - TPM) used for many years on Freescale's 8-bit microcontrollers. The TPM extends the functionality to support operation in low power modes by clocking the counter, compare and capture registers from an asynchronous clock that can remain functional in low power modes. 31.1.2 Features The TPM features include: * TPM clock mode is selectable * Can increment on every edge of the asynchronous counter clock * Can increment on rising edge of an external clock input synchronized to the asynchronous counter clock * Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 * TPM includes a 16-bit counter KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 507 Introduction * It can be a free-running counter or modulo counter * The counting can be up or up-down * Includes 6 channels that can be configured for input capture, output compare, or edge-aligned PWM mode * In input capture mode the capture can occur on rising edges, falling edges or both edges * In output compare mode the output signal can be set, cleared, pulsed, or toggled on match * All channels can be configured for center-aligned PWM mode * Support the generation of an interrupt and/or DMA request per channel * Support the generation of an interrupt and/or DMA request when the counter overflows * Support selectable trigger input to optionally reset or cause the counter to start incrementing. * The counter can also optionally stop incrementing on counter overflow * Support the generation of hardware triggers when the counter overflows and per channel 31.1.3 Modes of Operation During debug mode, the TPM can can be configured to temporarily pause all counting until the core returns to normal user operating mode or to operate normally. When the counter is paused, trigger inputs and input capture events are ignored. During doze mode, the TPM can be configured to operate normally or to pause all counting for the duration of doze mode. When the counter is paused, trigger inputs and input capture events are ignored. During stop mode, the TPM counter clock can remain functional and the TPM can generate an asynchronous interrupt to exit the MCU from stop mode. 31.1.4 Block Diagram The TPM uses one input/output (I/O) pin per channel, CHn (TPM channel (n)) where n is the channel number. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 508 Freescale Semiconductor, Inc. Chapter 31 Timer/PWM Module (TPM) The following figure shows the TPM structure. The central component of the TPM is the 16-bit counter with programmable final value and its counting can be up or up-down. CMOD no clock selected (counter disable) module clock PS external clock prescaler synchronizer 3 (1, 2, 4, 8, 16, 32, 64 or 128) CPWMS Module counter TOIE MOD CH0IE CH0F input capture mode logic channel 0 interrupt output modes logic (generation of channel 0 outputs signals in output compare, EPWM and CPWM modes) C0V channel 0 output signal Channel N MSNB:MSNA ELSNB:ELSNA CHNIE CHNF channel N input timer overflow interrupt Channel 0 MS0B:MS0A ELS0B:ELS0A channel 0 input TOF input capture mode logic CNV channel N interrupt output modes logic (generation of channel N outputs signals in output compare, EPWM and CPWM modes) channel N output signal Figure 31-1. TPM block diagram 31.2 TPM Signal Descriptions Table 31-1 shows the user-accessible signals for the TPM. Table 31-1. TPM signal descriptions Signal TPM_EXTCLK TPM_CHn Description External clock. TPM external clock can be selected to increment the TPM counter on every rising edge synchronized to the counter clock. TPM channel (n = 5 to 0) I/O I I/O KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 509 Memory Map and Register Definition 31.2.1 TPM_EXTCLK -- TPM External Clock The rising edge of the external input signal is used to increment the TPM counter if selected by CMOD[1:0] bits in the SC register. This input signal must be less than half of the TPM counter clock frequency. The TPM counter prescaler selection and settings are also used when an external input is selected. 31.2.2 TPM_CHn -- TPM Channel (n) I/O Pin Each TPM channel can be configured to operate either as input or output. The direction associated with each channel, input or output, is selected according to the mode assigned for that channel. 31.3 Memory Map and Register Definition This section provides a detailed description of all TPM registers. Attempting to access a reserved register location in the TPM memory map will generate a bus error. TPM memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_8000 Status and Control (TPM0_SC) 32 R/W 0000_0000h 31.3.1/512 4003_8004 Counter (TPM0_CNT) 32 R/W 0000_0000h 31.3.2/513 4003_8008 Modulo (TPM0_MOD) 32 R/W 0000_FFFFh 31.3.3/514 4003_800C Channel (n) Status and Control (TPM0_C0SC) 32 R/W 0000_0000h 31.3.4/515 4003_8010 Channel (n) Value (TPM0_C0V) 32 R/W 0000_0000h 31.3.5/517 4003_8014 Channel (n) Status and Control (TPM0_C1SC) 32 R/W 0000_0000h 31.3.4/515 4003_8018 Channel (n) Value (TPM0_C1V) 32 R/W 0000_0000h 31.3.5/517 4003_801C Channel (n) Status and Control (TPM0_C2SC) 32 R/W 0000_0000h 31.3.4/515 4003_8020 Channel (n) Value (TPM0_C2V) 32 R/W 0000_0000h 31.3.5/517 4003_8024 Channel (n) Status and Control (TPM0_C3SC) 32 R/W 0000_0000h 31.3.4/515 4003_8028 Channel (n) Value (TPM0_C3V) 32 R/W 0000_0000h 31.3.5/517 4003_802C Channel (n) Status and Control (TPM0_C4SC) 32 R/W 0000_0000h 31.3.4/515 4003_8030 Channel (n) Value (TPM0_C4V) 32 R/W 0000_0000h 31.3.5/517 4003_8034 Channel (n) Status and Control (TPM0_C5SC) 32 R/W 0000_0000h 31.3.4/515 4003_8038 Channel (n) Value (TPM0_C5V) 32 R/W 0000_0000h 31.3.5/517 4003_8050 Capture and Compare Status (TPM0_STATUS) 32 R/W 0000_0000h 31.3.6/517 4003_8084 Configuration (TPM0_CONF) 32 R/W 0000_0000h 31.3.7/519 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 510 Freescale Semiconductor, Inc. Chapter 31 Timer/PWM Module (TPM) TPM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_9000 Status and Control (TPM1_SC) 32 R/W 0000_0000h 31.3.1/512 4003_9004 Counter (TPM1_CNT) 32 R/W 0000_0000h 31.3.2/513 4003_9008 Modulo (TPM1_MOD) 32 R/W 0000_FFFFh 31.3.3/514 4003_900C Channel (n) Status and Control (TPM1_C0SC) 32 R/W 0000_0000h 31.3.4/515 4003_9010 Channel (n) Value (TPM1_C0V) 32 R/W 0000_0000h 31.3.5/517 4003_9014 Channel (n) Status and Control (TPM1_C1SC) 32 R/W 0000_0000h 31.3.4/515 4003_9018 Channel (n) Value (TPM1_C1V) 32 R/W 0000_0000h 31.3.5/517 4003_901C Channel (n) Status and Control (TPM1_C2SC) 32 R/W 0000_0000h 31.3.4/515 4003_9020 Channel (n) Value (TPM1_C2V) 32 R/W 0000_0000h 31.3.5/517 4003_9024 Channel (n) Status and Control (TPM1_C3SC) 32 R/W 0000_0000h 31.3.4/515 4003_9028 Channel (n) Value (TPM1_C3V) 32 R/W 0000_0000h 31.3.5/517 4003_902C Channel (n) Status and Control (TPM1_C4SC) 32 R/W 0000_0000h 31.3.4/515 4003_9030 Channel (n) Value (TPM1_C4V) 32 R/W 0000_0000h 31.3.5/517 4003_9034 Channel (n) Status and Control (TPM1_C5SC) 32 R/W 0000_0000h 31.3.4/515 4003_9038 Channel (n) Value (TPM1_C5V) 32 R/W 0000_0000h 31.3.5/517 4003_9050 Capture and Compare Status (TPM1_STATUS) 32 R/W 0000_0000h 31.3.6/517 4003_9084 Configuration (TPM1_CONF) 32 R/W 0000_0000h 31.3.7/519 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 511 Memory Map and Register Definition 31.3.1 Status and Control (TPMx_SC) SC contains the overflow status flag and control bits used to configure the interrupt enable, module configuration and prescaler factor. These controls relate to all channels within this module. Address: Base address + 0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOIE 0 0 TOF Reset CPWMS W 0 R DMA PS w1c W Reset CMOD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPMx_SC field descriptions Field 31-9 Reserved 8 DMA Description This field is reserved. This read-only field is reserved and always has the value 0. DMA Enable Enables DMA transfers for the overflow flag. 0 1 7 TOF Disables DMA transfers. Enables DMA transfers. Timer Overflow Flag Set by hardware when the LPTPM counter equals the value in the MOD register and increments. The TOF bit is cleared by writing a 1 to TOF bit. Writing a 0 to TOF has no effect. If another LPTPM overflow occurs between the flag setting and the flag clearing, the write operation has no effect; therefore, TOF remains set indicating another overflow has occurred. In this case a TOF interrupt request is not lost due to a delay in clearing the previous TOF. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 512 Freescale Semiconductor, Inc. Chapter 31 Timer/PWM Module (TPM) TPMx_SC field descriptions (continued) Field Description 0 1 6 TOIE Timer Overflow Interrupt Enable Enables LPTPM overflow interrupts. 0 1 5 CPWMS LPTPM counter has not overflowed. LPTPM counter has overflowed. Disable TOF interrupts. Use software polling or DMA request. Enable TOF interrupts. An interrupt is generated when TOF equals one. Center-aligned PWM Select Selects CPWM mode. This mode configures the LPTPM to operate in up-down counting mode. This field is write protected. It can be written only when the counter is disabled. 0 1 4-3 CMOD Clock Mode Selection Selects the LPTPM counter clock modes. When disabling the counter, this field remain set until acknolwedged in the LPTPM clock domain. 00 01 10 11 2-0 PS LPTPM counter operates in up counting mode. LPTPM counter operates in up-down counting mode. LPTPM counter is disabled LPTPM counter increments on every LPTPM counter clock LPTPM counter increments on rising edge of LPTPM_EXTCLK synchronized to the LPTPM counter clock Reserved Prescale Factor Selection Selects one of 8 division factors for the clock mode selected by CMOD. This field is write protected. It can be written only when the counter is disabled. 000 001 010 011 100 101 110 111 Divide by 1 Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 Divide by 128 31.3.2 Counter (TPMx_CNT) The CNT register contains the LPTPM counter value. Reset clears the CNT register. Writing any value to COUNT also clears the counter. When debug is active, the LPTPM counter does not increment unless configured otherwise. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 513 Memory Map and Register Definition Reading the CNT register adds two wait states to the register access due to synchronization delays. Address: Base address + 4h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 COUNT W Reset 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPMx_CNT field descriptions Field Description 31-16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15-0 COUNT Counter value 31.3.3 Modulo (TPMx_MOD) The Modulo register contains the modulo value for the LPTPM counter. When the LPTPM counter reaches the modulo value and increments, the overflow flag (TOF) is set and the next value of LPTPM counter depends on the selected counting method (see Counter ). Writing to the MOD register latches the value into a buffer. The MOD register is updated with the value of its write buffer according to MOD Register Update . It is recommended to initialize the LPTPM counter (write to CNT) before writing to the MOD register to avoid confusion about when the first counter overflow will occur. Address: Base address + 8h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 MOD W Reset 8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 TPMx_MOD field descriptions Field 31-16 Reserved 15-0 MOD Description This field is reserved. This read-only field is reserved and always has the value 0. Modulo value When writing this field, all bytes must be written at the same time. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 514 Freescale Semiconductor, Inc. Chapter 31 Timer/PWM Module (TPM) 31.3.4 Channel (n) Status and Control (TPMx_CnSC) CnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. When switching from one channel mode to a different channel mode, the channel must first be disabled and this must be acknowledged in the LPTPM counter clock domain. Table 31-34. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration X 00 00 None Channel disabled X 01/10/11 00 Software compare Pin not used for LPTPM 0 00 01 Input capture Capture on Rising Edge Only 01 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge 01 10 Output compare Toggle Output on match 10 Clear Output on match 11 Set Output on match 10 Edge-aligned PWM High-true pulses (clear Output on match, set Output on reload) X1 11 Low-true pulses (set Output on match, clear Output on reload) 10 Output compare Pulse Output low on match X1 1 10 Pulse Output high on match 10 Center-aligned PWM High-true pulses (clear Output on match-up, set Output on matchdown) X1 Low-true pulses (set Output on match-up, clear Output on matchdown) Address: Base address + Ch offset + (8d x i), where i=0d to 5d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 R W Reset 0 0 0 0 0 0 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 515 Memory Map and Register Definition Bit 15 14 13 12 11 10 9 8 0 R CHF w1c W Reset 7 0 0 0 0 0 0 0 0 0 6 5 CHIE MSB 0 0 4 3 2 MSA ELSB ELSA 0 0 0 1 0 0 0 DMA 0 TPMx_CnSC field descriptions Field 31-8 Reserved 7 CHF Description This field is reserved. This read-only field is reserved and always has the value 0. Channel Flag Set by hardware when an event occurs on the channel. CHF is cleared by writing a 1 to the CHF bit. Writing a 0 to CHF has no effect. If another event occurs between the CHF sets and the write operation, the write operation has no effect; therefore, CHF remains set indicating another event has occurred. In this case a CHF interrupt request is not lost due to the delay in clearing the previous CHF. 0 1 6 CHIE No channel event has occurred. A channel event has occurred. Channel Interrupt Enable Enables channel interrupts. 0 1 Disable channel interrupts. Enable channel interrupts. 5 MSB Channel Mode Select 4 MSA Channel Mode Select 3 ELSB Edge or Level Select 2 ELSA Edge or Level Select 1 Reserved 0 DMA Used for further selections in the channel logic. Its functionality is dependent on the channel mode. When a channel is disabled, this bit will not change state until acknowledged in the LPTPM counter clock domain. Used for further selections in the channel logic. Its functionality is dependent on the channel mode. When a channel is disabled, this bit will not change state until acknowledged in the LPTPM counter clock domain. The functionality of ELSB and ELSA depends on the channel mode. When a channel is disabled, this bit will not change state until acknowledged in the LPTPM counter clock domain. The functionality of ELSB and ELSA depends on the channel mode. When a channel is disabled, this bit will not change state until acknowledged in the LPTPM counter clock domain. This field is reserved. This read-only field is reserved and always has the value 0. DMA Enable Enables DMA transfers for the channel. 0 1 Disable DMA transfers. Enable DMA transfers. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 516 Freescale Semiconductor, Inc. Chapter 31 Timer/PWM Module (TPM) 31.3.5 Channel (n) Value (TPMx_CnV) These registers contain the captured LPTPM counter value for the input modes or the match value for the output modes. In input capture mode, any write to a CnV register is ignored. In compare modes, writing to a CnV register latches the value into a buffer. A CnV register is updated with the value of its write buffer according to CnV Register Update . Address: Base address + 10h offset + (8d x i), where i=0d to 5d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 VAL W Reset 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPMx_CnV field descriptions Field 31-16 Reserved 15-0 VAL Description This field is reserved. This read-only field is reserved and always has the value 0. Channel Value Captured LPTPM counter value of the input modes or the match value for the output modes. When writing this field, all bytes must be written at the same time. 31.3.6 Capture and Compare Status (TPMx_STATUS) The STATUS register contains a copy of the status flag CHnF bit (in CnSC) for each LPTPM channel, as well as the TOF bit (in SC), for software convenience. Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be checked using only one read of STATUS. All CHnF bits can be cleared by writing all ones to STATUS. Hardware sets the individual channel flags when an event occurs on the channel. CHF is cleared by writing a 1 to the CHF bit. Writing a 0 to CHF has no effect. If another event occurs between the flag setting and the write operation, the write operation has no effect; therefore, CHF remains set indicating another event has occurred. In this case a CHF interrupt request is not lost due to the clearing sequence for a previous CHF. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 517 Memory Map and Register Definition Address: Base address + 50h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R w1c W Reset 0 0 0 0 0 0 0 0 0 0 0 CH0F 0 CH1F 0 CH2F 0 CH3F 0 CH4F 0 CH5F 0 TOF Reset w1c w1c w1c w1c w1c w1c 0 0 0 0 0 0 TPMx_STATUS field descriptions Field 31-9 Reserved 8 TOF Description This field is reserved. This read-only field is reserved and always has the value 0. Timer Overflow Flag See register description 0 1 7-6 Reserved 5 CH5F This field is reserved. This read-only field is reserved and always has the value 0. Channel 5 Flag See the register description. 0 1 4 CH4F No channel event has occurred. A channel event has occurred. Channel 4 Flag See the register description. 0 1 3 CH3F LPTPM counter has not overflowed. LPTPM counter has overflowed. No channel event has occurred. A channel event has occurred. Channel 3 Flag See the register description. 0 1 No channel event has occurred. A channel event has occurred. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 518 Freescale Semiconductor, Inc. Chapter 31 Timer/PWM Module (TPM) TPMx_STATUS field descriptions (continued) Field Description 2 CH2F Channel 2 Flag See the register description. 0 1 1 CH1F No channel event has occurred. A channel event has occurred. Channel 1 Flag See the register description. 0 1 0 CH0F No channel event has occurred. A channel event has occurred. Channel 0 Flag See the register description. 0 1 No channel event has occurred. A channel event has occurred. 31.3.7 Configuration (TPMx_CONF) This register selects the behavior in debug and wait modes and the use of an external global time base. Address: Base address + 84h offset Bit 31 30 29 28 27 26 25 24 23 22 0 20 19 CSOT 16 CSOO 17 CROT 0 18 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GTBEEN R 21 0 0 0 0 0 TRGSEL W W Reset 0 0 0 0 0 0 DBGMODE 0 0 0 DOZEEN 0 R 0 0 0 0 TPMx_CONF field descriptions Field 31-28 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 519 Memory Map and Register Definition TPMx_CONF field descriptions (continued) Field Description 27-24 TRGSEL Trigger Select 23-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18 CROT Selects the input trigger to use for starting the counter and/or reloading the counter. This field should only be changed when the LPTPM counter is disabled. See Chip configuration section for available options. Counter Reload On Trigger When set, the LPTPM counter will reload with zero (and initialize PWM outputs to their default value) when a rising edge is detected on the selected trigger input. The trigger input is ignored if the LPTPM counter is paused during debug mode or doze mode. This field should only be changed when the LPTPM counter is disabled. 0 1 17 CSOO Counter is not reloaded due to a rising edge on the selected input trigger Counter is reloaded when a rising edge is detected on the selected input trigger Counter Stop On Overflow When set, the LPTPM counter will stop incrementing once the counter equals the MOD value and incremented (this also sets the TOF). Reloading the counter with zero due to writing to the counter register or due to a trigger input does not cause the counter to stop incrementing. Once the counter has stopped incrementing, the counter will not start incrementing unless it is disabled and then enabled again, or a rising edge on the selected trigger input is detected when CSOT set. This field should only be changed when the LPTPM counter is disabled. 0 1 16 CSOT LPTPM counter continues incrementing or decrementing after overflow LPTPM counter stops incrementing or decrementing after overflow. Counter Start on Trigger When set, the LPTPM counter will not start incrementing after it is enabled until a rising edge on the selected trigger input is detected. If the LPTPM counter is stopped due to an overflow, a rising edge on the selected trigger input will also cause the LPTPM counter to start incrementing again. The trigger input is ignored if the LPTPM counter is paused during debug mode or doze mode. This field should only be changed when the LPTPM counter is disabled. 0 1 LPTPM counter starts to increment immediately, once it is enabled. LPTPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. 15-10 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 9 GTBEEN Global time base enable Configures the LPTPM to use an externally generated global time base counter. When an externally generated timebase is used, the internal LPTPM counter is not used by the channels but can be used to generate a periodic interrupt or DMA request using the Modulo register and timer overflow flag. 0 1 8 Reserved 7-6 DBGMODE All channels use the internally generated LPTPM counter as their timebase All channels use an externally generated global timebase as their timebase This field is reserved. This read-only field is reserved and always has the value 0. Debug Mode Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 520 Freescale Semiconductor, Inc. Chapter 31 Timer/PWM Module (TPM) TPMx_CONF field descriptions (continued) Field Description Configures the LPTPM behavior in debug mode. All other configurations are reserved. 00 11 5 DOZEEN Doze Enable Configures the LPTPM behavior in wait mode. 0 1 4-0 Reserved LPTPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. LPTPM counter continues in debug mode. Internal LPTPM counter continues in Doze mode. Internal LPTPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. This field is reserved. This read-only field is reserved and always has the value 0. 31.4 Functional Description The following sections describe the TPM features. 31.4.1 Clock Domains The TPM module supports two clock domains. The bus clock domain is used by the register interface and for synchronizing interrupts and DMA requests. The TPM counter clock domain is used to clock the counter and prescaler along with the output compare and input capture logic. The TPM counter clock is considered asynchronous to the bus clock, can be a higher or lower frequency than the bus clock and can remain operational in Stop mode. Multiple TPM instances are all clocked by the same TPM counter clock in support of the external timebase feature. 31.4.1.1 Counter Clock Mode The CMOD[1:0] bits in the SC register either disable the TPM counter or select one of two possible clock modes for the TPM counter. After any reset, CMOD[1:0] = 0:0 so the TPM counter is disabled. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 521 Functional Description The CMOD[1:0] bits may be read or written at any time. Disabling the TPM counter by writing zero to the CMOD[1:0] bits does not affect the TPM counter value or other registers, but must be acknowledged by the TPM counter clock domain before they read as zero. The external clock input passes through a synchronizer clocked by the TPM counter clock to assure that counter transitions are properly aligned to counter clock transitions. Therefore, to meet Nyquist criteria considering also jitter, the frequency of the external clock source must be less than half of the counter clock frequency. 31.4.2 Prescaler The selected counter clock source passes through a prescaler that is a 7-bit counter. The value of the prescaler is selected by the PS[2:0] bits. The following figure shows an example of the prescaler counter and TPM counter. timer module counting is up. PS[2:0] = 001 CNTIN = 0x0000 selected input clock prescaler counter 1 timer module counter 0 0 1 1 0 1 2 0 1 0 3 1 0 0 1 1 0 1 2 0 1 3 0 1 0 0 1 Figure 31-59. Example of the Prescaler Counter 31.4.3 Counter The TPM has a 16-bit counter that is used by the channels either for input or output modes. The counter updates from the selected clock divided by the prescaler. The TPM counter has these modes of operation: * up counting (see Up Counting) * up-down counting (see Up-Down Counting) 31.4.3.1 Up Counting Up counting is selected when (CPWMS = 0) KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 522 Freescale Semiconductor, Inc. Chapter 31 Timer/PWM Module (TPM) The value of zero is loaded into the TPM counter, and the counter increments until the value of MOD is reached, at which point the counter is reloaded with zero. The TPM period when using up counting is (MOD + 0x0001) x period of the TPM counter clock. The TOF bit is set when the TPM counter changes from MOD to zero. MOD = 0x0004 timer module counter 3 4 0 1 2 3 4 0 1 2 3 0 4 1 2 TOF bit set TOF bit set TOF bit set TOF bit period of timer module counter clock period of counting = (MOD + 0x0001) x period of timer module counter clock Figure 31-60. Example of TPM Up Counting Note * MOD = 0000 is a redundant condition. In this case, the TPM counter is always equal to MOD and the TOF bit is set in each rising edge of the TPM counter clock. 31.4.3.2 Up-Down Counting Up-down counting is selected when (CPWMS = 1). When configured for up-down counting, configuring MOD to less than 2 is not supported. The value of zero is loaded into the TPM counter, and the counter increments until the value of MOD is reached, at which point the counter is decremented until it returns to zero and the up-down counting restarts. The TPM period when using up-down counting is 2 x MOD x period of the TPM counter clock. The TOF bit is set when the TPM counter changes from MOD to (MOD - 1). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 523 Functional Description MOD = 0x0004 Timer module counter 0 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 0 1 2 3 4 TOF bit set TOF bit set TOF bit period of timer module counter clock period of counting = 2 x MOD x period of timer module counter clock Figure 31-61. Example of Up-Down Counting 31.4.3.3 Counter Reset Any write to CNT resets the TPM counter and the channel outputs to their initial values (except for channels in output compare mode). 31.4.4 Input Capture Mode The input capture mode is selected when (CPWMS = 0), (MSnB:MSnA = 0:0), and (ELSnB:ELSnA 0:0). When a selected edge occurs on the channel input, the current value of the TPM counter is captured into the CnV register, at the same time the CHnF bit is set and the channel interrupt is generated if enabled by CHnIE = 1 (see the following figure). When a channel is configured for input capture, the TPM_CHn pin is an edge-sensitive input. ELSnB:ELSnA control bits determine which edge, falling or rising, triggers inputcapture event. Note that the maximum frequency for the channel input signal to be detected correctly is counter clock divided by 4, which is required to meet Nyquist criteria for signal sampling. Writes to the CnV register are ignored in input capture mode. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 524 Freescale Semiconductor, Inc. Chapter 31 Timer/PWM Module (TPM) was rising edge selected? 0 synchronizer channel (n) input timer module clock D Q CLK D rising edge Q CLK 0 CHnIE channel (n) interrupt CHnF 1 edge detector CnV falling edge 0 1 0 was falling edge selected? timer module counter Figure 31-62. Input capture mode The CHnF bit is set on the third rising edge of the counter clock after a valid edge occurs on the channel input. 31.4.5 Output Compare Mode The output compare mode is selected when (CPWMS = 0), and (MSnB:MSnA = 0:1). In output compare mode, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter matches the value in the CnV register of an output compare channel, the channel (n) output can be set, cleared, or toggled. When a channel is initially configured to output compare mode, the channel output updates with its negated value (logic 0 for set/toggle/pulse high and logic one for clear/ pulse low). The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the channel (n) match (TPM counter = CnV). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 525 Functional Description MOD = 0x0005 CnV = 0x0003 channel (n) match counter overflow CNT ... 2 1 0 channel (n) output previous value CHnF bit previous value 4 3 channel (n) match counter overflow 5 1 0 2 counter overflow 4 3 5 1 0 ... TOF bit Figure 31-63. Example of the output compare mode when the match toggles the channel output MOD = 0x0005 CnV = 0x0003 CNT channel (n) output CHnF bit ... 0 counter overflow channel (n) match counter overflow 2 1 3 4 5 0 counter overflow channel (n) match 1 2 3 4 5 0 1 ... previous value previous value TOF bit Figure 31-64. Example of the output compare mode when the match clears the channel output MOD = 0x0005 CnV = 0x0003 channel (n) match counter overflow CNT channel (n) output CHnF bit ... 0 1 2 3 counter overflow 4 5 0 channel (n) match 1 2 3 counter overflow 4 5 0 1 ... previous value previous value TOF bit Figure 31-65. Example of the output compare mode when the match sets the channel output It is possible to use the output compare mode with (ELSnB:ELSnA = 0:0). In this case, when the counter reaches the value in the CnV register, the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the channel (n) output is not modified and controlled by TPM. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 526 Freescale Semiconductor, Inc. Chapter 31 Timer/PWM Module (TPM) 31.4.6 Edge-Aligned PWM (EPWM) Mode The edge-aligned mode is selected when (CPWMS = 0), and (MSnB:MSnA = 1:0). The EPWM period is determined by (MOD + 0x0001) and the pulse width (duty cycle) is determined by CnV. The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the channel (n) match (TPM counter = CnV), that is, at the end of the pulse width. This type of PWM signal is called edge-aligned because the leading edges of all PWM signals are aligned with the beginning of the period, which is the same for all channels within an TPM. counter overflow counter overflow counter overflow period pulse width channel (n) output channel (n) match channel (n) match channel (n) match Figure 31-66. EPWM period and pulse width with ELSnB:ELSnA = 1:0 If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnV register, the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the channel (n) output is not controlled by TPM. If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the counter overflow (when the zero is loaded into the TPM counter), and it is forced low at the channel (n) match (TPM counter = CnV) (see the following figure). MOD = 0x0008 CnV = 0x0005 counter overflow CNT ... 0 channel (n) match 1 2 3 4 5 counter overflow 6 7 8 0 1 2 ... channel (n) output CHnF bit previous value TOF bit Figure 31-67. EPWM signal with ELSnB:ELSnA = 1:0 If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the counter overflow (when zero is loaded into the TPM counter), and it is forced high at the channel (n) match (TPM counter = CnV) (see the following figure). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 527 Functional Description MOD = 0x0008 CnV = 0x0005 counter overflow CNT ... 0 channel (n) match 1 2 3 4 5 counter overflow 6 7 8 0 1 2 ... channel (n) output CHnF bit previous value TOF bit Figure 31-68. EPWM signal with ELSnB:ELSnA = X:1 If (CnV = 0x0000), then the channel (n) output is a 0% duty cycle EPWM signal. If (CnV > MOD), then the channel (n) output is a 100% duty cycle EPWM signal and CHnF bit is not set since there is never a channel (n) match. Therefore, MOD must be less than 0xFFFF in order to get a 100% duty cycle EPWM signal. 31.4.7 Center-Aligned PWM (CPWM) Mode The center-aligned mode is selected when (CPWMS = 1) and (MSnB:MSnA = 1:0). The CPWM pulse width (duty cycle) is determined by 2 x CnV and the period is determined by 2 x MOD (see the following figure). MOD must be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results. In the CPWM mode, the TPM counter counts up until it reaches MOD and then counts down until it reaches zero. The CHnF bit is set and channel (n) interrupt is generated (if CHnIE = 1) at the channel (n) match (TPM counter = CnV) when the TPM counting is down (at the begin of the pulse width) and when the TPM counting is up (at the end of the pulse width). This type of PWM signal is called center-aligned because the pulse width centers for all channels are when the TPM counter is zero. The other channel modes are not designed to be used with the up-down counter (CPWMS = 1). Therefore, all TPM channels should be used in CPWM mode when (CPWMS = 1). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 528 Freescale Semiconductor, Inc. Chapter 31 Timer/PWM Module (TPM) timer module counter = 0 channel (n) match (timer module counting is down) counter overflow timer module counter = MOD channel (n) match counter overflow (timer module counting timer module counter = is up) MOD channel (n) output pulse width (2 x CnV) period (2 x MOD) Figure 31-69. CPWM period and pulse width with ELSnB:ELSnA = 1:0 If (ELSnB:ELSnA = 0:0) when the TPM counter reaches the value in the CnV register, the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the channel (n) output is not controlled by TPM. If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the channel (n) match (TPM counter = CnV) when counting down, and it is forced low at the channel (n) match when counting up (see the following figure). counter overflow channel (n) match in down counting MOD = 0x0008 CnV = 0x0005 CNT ... 7 8 7 6 5 4 3 counter overflow channel (n) match in down counting channel (n) match in up counting 2 1 0 1 2 3 4 5 6 7 8 7 6 5 ... channel (n) output previous value CHnF bit TOF bit Figure 31-70. CPWM signal with ELSnB:ELSnA = 1:0 If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n) match (TPM counter = CnV) when counting down, and it is forced high at the channel (n) match when counting up (see the following figure). counter overflow counter overflow MOD = 0x0008 CnV = 0x0005 channel (n) match in down counting CNT ... 7 8 7 6 5 4 3 channel (n) match in up counting 2 1 0 1 2 3 4 5 6 channel (n) match in down counting 7 8 7 6 5 ... channel (n) output CHnF bit previous value TOF bit Figure 31-71. CPWM signal with ELSnB:ELSnA = X:1 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 529 Functional Description If (CnV = 0x0000) then the channel (n) output is a 0% duty cycle CPWM signal. If (CnV > MOD), then the channel (n) output is a 100% duty cycle CPWM signal, although the CHnF bit is set when the counter changes from incrementing to decrementing. Therefore, MOD must be less than 0xFFFF in order to get a 100% duty cycle CPWM signal. 31.4.8 Registers Updated from Write Buffers 31.4.8.1 MOD Register Update If (CMOD[1:0] = 0:0) then MOD register is updated when MOD register is written. If (CMOD[1:0] 0:0), then MOD register is updated according to the CPWMS bit, that is: * If the selected mode is not CPWM then MOD register is updated after MOD register was written and the TPM counter changes from MOD to zero. * If the selected mode is CPWM then MOD register is updated after MOD register was written and the TPM counter changes from MOD to (MOD - 1). 31.4.8.2 CnV Register Update If (CMOD[1:0] = 0:0) then CnV register is updated when CnV register is written. If (CMOD[1:0] 0:0), then CnV register is updated according to the selected mode, that is: * If the selected mode is output compare then CnV register is updated on the next TPM counter increment (end of the prescaler counting) after CnV register was written. * If the selected mode is EPWM then CnV register is updated after CnV register was written and the TPM counter changes from MOD to zero. * If the selected mode is CPWM then CnV register is updated after CnV register was written and the TPM counter changes from MOD to (MOD - 1). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 530 Freescale Semiconductor, Inc. Chapter 31 Timer/PWM Module (TPM) 31.4.9 DMA The channel generates a DMA transfer request according to DMA and CHnIE bits (see the following table). Table 31-83. Channel DMA Transfer Request DMA CHnIE Channel DMA Transfer Request Channel Interrupt 0 0 The channel DMA transfer request is not generated. The channel interrupt is not generated. 0 1 The channel DMA transfer request is not generated. The channel interrupt is generated if (CHnF = 1). 1 0 The channel DMA transfer request is generated if The channel interrupt is not generated. (CHnF = 1). 1 1 The channel DMA transfer request is generated if The channel interrupt is generated if (CHnF = 1). (CHnF = 1). If DMA = 1, the CHnF bit can be cleared either by channel DMA transfer done or writing a one to CHnF bit (see the following table). Table 31-84. Clear CHnF Bit DMA How CHnF Bit Can Be Cleared 0 CHnF bit is cleared by writing a 1 to CHnF bit. 1 CHnF bit is cleared either when the channel DMA transfer is done or by writing a 1 to CHnF bit. 31.4.10 Reset Overview The TPM is reset whenever any chip reset occurs. When the TPM exits from reset: * the TPM counter and the prescaler counter are zero and are stopped (CMOD[1:0] = 0:0); * the timer overflow interrupt is zero; * the channels interrupts are zero; * the channels are in input capture mode; * the channels outputs are zero; * the channels pins are not controlled by TPM (ELS(n)B:ELS(n)A = 0:0). 31.4.11 TPM Interrupts This section describes TPM interrupts. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 531 Functional Description 31.4.11.1 Timer Overflow Interrupt The timer overflow interrupt is generated when (TOIE = 1) and (TOF = 1). 31.4.11.2 Channel (n) Interrupt The channel (n) interrupt is generated when (CHnIE = 1) and (CHnF = 1). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 532 Freescale Semiconductor, Inc. Chapter 32 Periodic Interrupt Timer (PIT-RTI) 32.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels. 32.1.1 Block diagram The following figure shows the block diagram of the PIT-RTI module. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 533 Signal description PIT Peripheral bus PIT registers load_value Timer 1 Iinterrupts Triggers Timer n Peripheral bus clock Figure 32-1. Block diagram of the PIT NOTE See the chip configuration details for the number of PIT channels used in this MCU. 32.1.2 Features The main features of this block are: * Ability of timers to generate DMA trigger pulses * Ability of timers to generate interrupts * Maskable interrupts * Independent timeout periods for each timer 32.2 Signal description The PIT module has no external pins. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 534 Freescale Semiconductor, Inc. Chapter 32 Periodic Interrupt Timer (PIT-RTI) 32.3 Memory map/register description This section provides a detailed description of all registers accessible in the PIT module. NOTE * Reserved registers will read as 0, writes will have no effect. * See the chip configuration details for the number of PIT channels used in this MCU. Table 32-2. Timer Channel n Address Offset Use Access Channel + 0x00 Timer Load Value Register R/W Channel + 0x04 Current Timer Value Register R Channel + 0x08 Timer Control Register R/W Channel + 0x0C Timer Flag Register R/W PIT memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_7000 PIT Module Control Register (PIT_MCR) 32 R/W 0000_0002h 32.3.1/535 4003_70E0 PIT Upper Lifetime Timer Register (PIT_LTMR64H) 32 R 0000_0000h 32.3.2/537 4003_70E4 PIT Lower Lifetime Timer Register (PIT_LTMR64L) 32 R 0000_0000h 32.3.3/537 4003_7100 Timer Load Value Register (PIT_LDVAL0) 32 R/W 0000_0000h 32.3.4/538 4003_7104 Current Timer Value Register (PIT_CVAL0) 32 R 0000_0000h 32.3.5/538 4003_7108 Timer Control Register (PIT_TCTRL0) 32 R/W 0000_0000h 32.3.6/539 4003_710C Timer Flag Register (PIT_TFLG0) 32 R/W 0000_0000h 32.3.7/540 4003_7110 Timer Load Value Register (PIT_LDVAL1) 32 R/W 0000_0000h 32.3.4/538 4003_7114 Current Timer Value Register (PIT_CVAL1) 32 R 0000_0000h 32.3.5/538 4003_7118 Timer Control Register (PIT_TCTRL1) 32 R/W 0000_0000h 32.3.6/539 4003_711C Timer Flag Register (PIT_TFLG1) 32 R/W 0000_0000h 32.3.7/540 32.3.1 PIT Module Control Register (PIT_MCR) This register enables or disables the PIT timer clocks and controls the timers when the PIT enters the Debug mode. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 535 Memory map/register description Address: 4003_7000h base + 0h offset = 4003_7000h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MDIS FRZ 1 0 Reserved Reset 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIT_MCR field descriptions Field Description 0-28 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 29 Reserved This field is reserved. 30 MDIS Module Disable - (PIT section) Disables the standard timers. This field must be enabled before any other setup is done. 0 1 31 FRZ Clock for standard PIT timers is enabled. Clock for standard PIT timers is disabled. Freeze Allows the timers to be stopped when the device enters the Debug mode. 0 1 Timers continue to run in Debug mode. Timers are stopped in Debug mode. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 536 Freescale Semiconductor, Inc. Chapter 32 Periodic Interrupt Timer (PIT-RTI) 32.3.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H) This register is intended for applications that chain timer 0 and timer 1 to build a 64-bit lifetimer. Address: 4003_7000h base + E0h offset = 4003_70E0h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTH R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIT_LTMR64H field descriptions Field Description 0-31 LTH Life Timer value Shows the timer value of timer 1. If this register is read at a time t1, LTMR64L shows the value of timer 0 at time t1. 32.3.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L) This register is intended for applications that chain timer 0 and timer 1 to build a 64-bit lifetimer. To use LTMR64H and LTMR64L, timer 0 and timer 1 need to be chained. To obtain the correct value, first read LTMR64H and then LTMR64L. LTMR64H will have the value of CVAL1 at the time of the first access, LTMR64L will have the value of CVAL0 at the time of the first access, therefore the application does not need to worry about carry-over effects of the running counter. Address: 4003_7000h base + E4h offset = 4003_70E4h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTL R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIT_LTMR64L field descriptions Field 0-31 LTL Description Life Timer value Shows the value of timer 0 at the time LTMR64H was last read. It will only update if LTMR64H is read. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 537 Memory map/register description 32.3.4 Timer Load Value Register (PIT_LDVALn) These registers select the timeout period for the timer interrupts. Address: 4003_7000h base + 100h offset + (16d x i), where i=0d to 1d Bit R W 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIT_LDVALn field descriptions Field Description 0-31 TSV Timer Start Value Sets the timer start value. The timer will count down until it reaches 0, then it will generate an interrupt and load this register value again. Writing a new value to this register will not restart the timer; instead the value will be loaded after the timer expires. To abort the current cycle and start a timer period with the new value, the timer must be disabled and enabled again. 32.3.5 Current Timer Value Register (PIT_CVALn) These registers indicate the current timer position. Address: 4003_7000h base + 104h offset + (16d x i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TVL R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIT_CVALn field descriptions Field 0-31 TVL Description Current Timer Value Represents the current timer value, if the timer is enabled. NOTE: * If the timer is disabled, do not use this field as its value is unreliable. * The timer uses a downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 538 Freescale Semiconductor, Inc. Chapter 32 Periodic Interrupt Timer (PIT-RTI) 32.3.6 Timer Control Register (PIT_TCTRLn) These register contain the control bits for each timer. Address: 4003_7000h base + 108h offset + (16d x i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CHN TIE TEN 0 0 0 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 PIT_TCTRLn field descriptions Field 0-28 Reserved 29 CHN Description This field is reserved. This read-only field is reserved and always has the value 0. Chain Mode When activated, Timer n-1 needs to expire before timer n can decrement by 1. Timer 0 can not be changed. 0 1 30 TIE Timer Interrupt Enable When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt will immediately cause an interrupt event. To avoid this, the associated TFLGn[TIF] must be cleared first. 0 1 31 TEN Timer is not chained. Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. Interrupt requests from Timer n are disabled. Interrupt will be requested whenever TIF is set. Timer Enable Enables or disables the timer. 0 1 Timer n is disabled. Timer n is enabled. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 539 Functional description 32.3.7 Timer Flag Register (PIT_TFLGn) These registers hold the PIT interrupt flags. Address: 4003_7000h base + 10Ch offset + (16d x i), where i=0d to 1d Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 R TIF w1c W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIT_TFLGn field descriptions Field 0-30 Reserved 31 TIF Description This field is reserved. This read-only field is reserved and always has the value 0. Timer Interrupt Flag Sets to 1 at the end of the timer period. Writing 1 to this flag clears it. Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an interrupt request. 0 1 Timeout has not yet occurred. Timeout has occurred. 32.4 Functional description This section provides the functional description of the module. 32.4.1 General operation This section gives detailed information on the internal operation of the module. Each timer can be used to generate trigger pulses and interrupts. Each interrupt is available on a separate interrupt line. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 540 Freescale Semiconductor, Inc. Chapter 32 Periodic Interrupt Timer (PIT-RTI) 32.4.1.1 Timers The timers generate triggers at periodic intervals, when enabled. The timers load the start values as specified in their LDVAL registers, count down to 0 and then load the respective start value again. Each time a timer reaches 0, it will generate a trigger pulse and set the interrupt flag. All interrupts can be enabled or masked by setting TCTRLn[TIE]. A new interrupt can be generated only after the previous one is cleared. If desired, the current counter value of the timer can be read via the CVAL registers. The counter period can be restarted, by first disabling, and then enabling the timer with TCTRLn[TEN]. See the following figure. Disable timer Timer enabled Start value = p1 Re-enable timer Trigger event p1 p1 p1 p1 Figure 32-17. Stopping and starting a timer The counter period of a running timer can be modified, by first disabling the timer, setting a new load value, and then enabling the timer again. See the following figure. Timer enabled Start value = p1 Trigger event Re-enable Disable timer, Set new load value timer p2 p1 p2 p2 p1 Figure 32-18. Modifying running timer period It is also possible to change the counter period without restarting the timer by writing LDVAL with the new load value. This value will then be loaded after the next trigger event. See the following figure. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 541 Initialization and application information Timer enabled Start value = p1 New start Value p2 set Trigger event p1 p1 p1 p2 p2 Figure 32-19. Dynamically setting a new load value 32.4.1.2 Debug mode In Debug mode, the timers will be frozen based on MCR[FRZ]. This is intended to aid software development, allowing the developer to halt the processor, investigate the current state of the system, for example, the timer values, and then continue the operation. 32.4.2 Interrupts All the timers support interrupt generation. See the MCU specification for related vector addresses and priorities. Timer interrupts can be enabled by setting TCTRLn[TIE]. TFLGn[TIF] are set to 1 when a timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to the corresponding TFLGn[TIF]. 32.4.3 Chained timers When a timer has chain mode enabled, it will only count after the previous timer has expired. So if timer n-1 has counted down to 0, counter n will decrement the value by one. This allows to chain some of the timers together to form a longer timer. The first timer (timer 0) cannot be chained to any other timer. 32.5 Initialization and application information In the example configuration: * The PIT clock has a frequency of 50 MHz. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 542 Freescale Semiconductor, Inc. Chapter 32 Periodic Interrupt Timer (PIT-RTI) * Timer 1 creates an interrupt every 5.12 ms. * Timer 3 creates a trigger event every 30 ms. The PIT module must be activated by writing a 0 to MCR[MDIS]. The 50 MHz clock frequency equates to a clock period of 20 ns. Timer 1 needs to trigger every 5.12 ms/20 ns = 256,000 cycles and Timer 3 every 30 ms/20 ns = 1,500,000 cycles. The value for the LDVAL register trigger is calculated as: LDVAL trigger = (period / clock period) -1 This means LDVAL1 and LDVAL3 must be written with 0x0003E7FF and 0x0016E35F respectively. The interrupt for Timer 1 is enabled by setting TCTRL1[TIE]. The timer is started by writing 1 to TCTRL1[TEN]. Timer 3 shall be used only for triggering. Therefore, Timer 3 is started by writing a 1 to TCTRL3[TEN]. TCTRL3[TIE] stays at 0. The following example code matches the described setup: // turn on PIT PIT_MCR = 0x00; // Timer 1 PIT_LDVAL1 = 0x0003E7FF; // setup timer 1 for 256000 cycles PIT_TCTRL1 = TIE; // enable Timer 1 interrupts PIT_TCTRL1 |= TEN; // start Timer 1 // Timer 3 PIT_LDVAL3 = 0x0016E35F; // setup timer 3for 1500000 cycles PIT_TCTRL3 |= TEN; // start Timer 3 32.6 Example configuration for chained timers In the example configuration: * The PIT clock has a frequency of 100 MHz. * Timers 1 and 2 are available. * An interrupt shall be raised every 1 hour. The PIT module needs to be activated by writing a 0 to MCR[MDIS]. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 543 Example configuration for the lifetime timer The 100 MHz clock frequency equates to a clock period of 10 ns, so the PIT needs to count for 6000 million cycles, which is more than a single timer can do. So, Timer 1 is set up to trigger every 6 s (600 million cycles). Timer 2 is chained to Timer 1 and programmed to trigger 10 times. The value for the LDVAL register trigger is calculated as number of cycles-1, so LDVAL1 receives the value 0x23C345FF and LDVAL2 receives the value 0x00000009. The interrupt for Timer 2 is enabled by setting TCTRL2[TIE], the Chain mode is activated by setting TCTRL2[CHN], and the timer is started by writing a 1 to TCTRL2[TEN]. TCTRL1[TEN] needs to be set, and TCTRL1[CHN] and TCTRL1[TIE] are cleared. The following example code matches the described setup: // turn on PIT PIT_MCR = 0x00; // Timer 2 PIT_LDVAL2 PIT_TCTRL2 PIT_TCTRL2 PIT_TCTRL2 = 0x00000009; // = TIE; // enable |= CHN; // chain |= TEN; // start setup Timer Timer Timer Timer 2 for 10 counts 2 interrupt 2 to Timer 1 2 // Timer 1 PIT_LDVAL1 = 0x23C345FF; // setup Timer 1 for 600 000 000 cycles PIT_TCTRL1 = TEN; // start Timer 1 32.7 Example configuration for the lifetime timer To configure the lifetimer timer, channels 0 and 1 need to be chained together. First the PIT module needs to be activated by writing a 0 to the MDIS bit in the CTRL register, then the LDVAL registers need to be set to the maximum value. The timer is a downcounter. The following example code matches the described setup: // turn on PIT PIT_MCR = 0x00; // Timer 1 PIT_LDVAL1 PIT_TCTRL1 PIT_TCTRL1 PIT_TCTRL1 = 0xFFFFFFFF; // setup timer 1 for maximum counting period = 0x0; // disable timer 1 interrupts |= CHN; // chain timer 1 to timer 0 |= TEN; // start timer 1 // Timer 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 544 Freescale Semiconductor, Inc. Chapter 32 Periodic Interrupt Timer (PIT-RTI) PIT_LDVAL0 = 0xFFFFFFFF; // setup timer 0 for maximum counting period PIT_TCTRL0 = TEN; // start timer 0 To access the lifetime, read first LTMR64H and then LTMR64L. current_uptime = PIT_LTMR64H<<32; current_uptime = current_uptime + PIT_LTMR64L; KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 545 Example configuration for the lifetime timer KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 546 Freescale Semiconductor, Inc. Chapter 33 Low-Power Timer (LPTMR) 33.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter. 33.1.1 Features The features of the LPTMR module include: * 16-bit time counter or pulse counter with compare * Optional interrupt can generate asynchronous wakeup from any low-power mode * Hardware trigger output * Counter supports free-running mode or reset on compare * Configurable clock source for prescaler/glitch filter * Configurable input source for pulse counter * Rising-edge or falling-edge 33.1.2 Modes of operation The following table describes the operation of the LPTMR module in various modes. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 547 LPTMR signal descriptions Table 33-1. Modes of operation Modes Description Run The LPTMR operates normally. Wait The LPTMR continues to operate normally and may be configured to exit the low-power mode by generating an interrupt request. Stop The LPTMR continues to operate normally and may be configured to exit the low-power mode by generating an interrupt request. Low-Leakage The LPTMR continues to operate normally and may be configured to exit the low-power mode by generating an interrupt request. Debug The LPTMR operates normally in Pulse Counter mode, but counter does not increment in Time Counter mode. 33.2 LPTMR signal descriptions Table 33-2. LPTMR signal descriptions Signal I/O LPTMR_ALTn I Description Pulse Counter Input pin 33.2.1 Detailed signal descriptions Table 33-3. LPTMR interface--detailed signal descriptions Signal I/O LPTMR_ALTn I Description Pulse Counter Input The LPTMR can select one of the input pins to be used in Pulse Counter mode. State meaning Assertion--If configured for pulse counter mode with active-high input, then assertion causes the CNR to increment. Deassertion--If configured for pulse counter mode with active-low input, then deassertion causes the CNR to increment. Timing Assertion or deassertion may occur at any time; input may assert asynchronously to the bus clock. 33.3 Memory map and register definition KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 548 Freescale Semiconductor, Inc. Chapter 33 Low-Power Timer (LPTMR) LPTMR memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4004_0000 Low Power Timer Control Status Register (LPTMR0_CSR) 32 R/W 0000_0000h 33.3.1/549 4004_0004 Low Power Timer Prescale Register (LPTMR0_PSR) 32 R/W 0000_0000h 33.3.2/550 4004_0008 Low Power Timer Compare Register (LPTMR0_CMR) 32 R/W 0000_0000h 33.3.3/552 4004_000C Low Power Timer Counter Register (LPTMR0_CNR) 32 R 0000_0000h 33.3.4/552 33.3.1 Low Power Timer Control Status Register (LPTMRx_CSR) Address: 4004_0000h base + 0h offset = 4004_0000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPP TFC TMS TEN 0 0 0 0 0 R TCF w1c W Reset 0 0 0 0 0 0 0 0 0 TIE 0 TPS 0 0 LPTMRx_CSR field descriptions Field 31-8 Reserved 7 TCF Description This field is reserved. This read-only field is reserved and always has the value 0. Timer Compare Flag TCF is set when the LPTMR is enabled and the CNR equals the CMR and increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it. 0 1 6 TIE Timer Interrupt Enable When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set. 0 1 5-4 TPS The value of CNR is not equal to CMR and increments. The value of CNR is equal to CMR and increments. Timer interrupt disabled. Timer interrupt enabled. Timer Pin Select Configures the input source to be used in Pulse Counter mode. TPS must be altered only when the LPTMR is disabled. The input connections vary by device. See the chip configuration details for information on the connections to these inputs. 00 Pulse counter input 0 is selected. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 549 Memory map and register definition LPTMRx_CSR field descriptions (continued) Field Description 01 10 11 3 TPP Pulse counter input 1 is selected. Pulse counter input 2 is selected. Pulse counter input 3 is selected. Timer Pin Polarity Configures the polarity of the input source in Pulse Counter mode. TPP must be changed only when the LPTMR is disabled. 0 1 2 TFC Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. Timer Free-Running Counter When clear, TFC configures the CNR to reset whenever TCF is set. When set, TFC configures the CNR to reset on overflow. TFC must be altered only when the LPTMR is disabled. 0 1 1 TMS CNR is reset whenever TCF is set. CNR is reset on overflow. Timer Mode Select Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is disabled. 0 1 0 TEN Time Counter mode. Pulse Counter mode. Timer Enable When TEN is clear, it resets the LPTMR internal logic, including the CNR and TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field, CSR[5:1] must not be altered. 0 1 LPTMR is disabled and internal logic is reset. LPTMR is enabled. 33.3.2 Low Power Timer Prescale Register (LPTMRx_PSR) Address: 4004_0000h base + 4h offset = 4004_0004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R PRESCALE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 PBYP 0 0 PCS 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 550 Freescale Semiconductor, Inc. Chapter 33 Low-Power Timer (LPTMR) LPTMRx_PSR field descriptions Field 31-7 Reserved 6-3 PRESCALE Description This field is reserved. This read-only field is reserved and always has the value 0. Prescale Value Configures the size of the Prescaler in Time Counter mode or width of the glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR is disabled. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 2 PBYP Prescaler Bypass When PBYP is set, the selected prescaler clock in Time Counter mode or selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP must be altered only when the LPTMR is disabled. 0 1 1-0 PCS Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. Prescaler/glitch filter is enabled. Prescaler/glitch filter is bypassed. Prescaler Clock Select Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must be altered only when the LPTMR is disabled. The clock connections vary by device. NOTE: See the chip configuration details for information on the connections to these inputs. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 551 Memory map and register definition LPTMRx_PSR field descriptions (continued) Field Description 00 01 10 11 Prescaler/glitch filter clock 0 selected. Prescaler/glitch filter clock 1 selected. Prescaler/glitch filter clock 2 selected. Prescaler/glitch filter clock 3 selected. 33.3.3 Low Power Timer Compare Register (LPTMRx_CMR) Address: 4004_0000h base + 8h offset = 4004_0008h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 R 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 COMPARE W Reset 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPTMRx_CMR field descriptions Field Description 31-16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15-0 COMPARE Compare Value When the LPTMR is enabled and the CNR equals the value in the CMR and increments, TCF is set and the hardware trigger asserts until the next time the CNR increments. If the CMR is 0, the hardware trigger will remain asserted until the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only when TCF is set. 33.3.4 Low Power Timer Counter Register (LPTMRx_CNR) Address: 4004_0000h base + Ch offset = 4004_000Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 COUNTER W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPTMRx_CNR field descriptions Field 31-16 Reserved 15-0 COUNTER Description This field is reserved. This read-only field is reserved and always has the value 0. Counter Value KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 552 Freescale Semiconductor, Inc. Chapter 33 Low-Power Timer (LPTMR) 33.4 Functional description 33.4.1 LPTMR power and reset The LPTMR remains powered in all power modes, including low-leakage modes. If the LPTMR is not required to remain operating during a low-power mode, then it must be disabled before entering the mode. The LPTMR is reset only on global Power On Reset (POR) or Low Voltage Detect (LVD). When configuring the LPTMR registers, the CSR must be initially written with the timer disabled, before configuring the PSR and CMR. Then, CSR[TIE] must be set as the last step in the initialization. This ensures the LPTMR is configured correctly and the LPTMR counter is reset to zero following a warm reset. 33.4.2 LPTMR clocking The LPTMR prescaler/glitch filter can be clocked by one of the four clocks. The clock source must be enabled before the LPTMR is enabled. NOTE The clock source selected may need to be configured to remain enabled in low-power modes, otherwise the LPTMR will not operate during low-power modes. In Pulse Counter mode with the prescaler/glitch filter bypassed, the selected input source directly clocks the CNR and no other clock source is required. To minimize power in this case, configure the prescaler clock source for a clock that is not toggling. NOTE The clock source or pulse input source selected for the LPTMR should not exceed the frequency fLPTMR defined in the device datasheet. 33.4.3 LPTMR prescaler/glitch filter The LPTMR prescaler and glitch filter share the same logic which operates as a prescaler in Time Counter mode and as a glitch filter in Pulse Counter mode. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 553 Functional description NOTE The prescaler/glitch filter configuration must not be altered when the LPTMR is enabled. 33.4.3.1 Prescaler enabled In Time Counter mode, when the prescaler is enabled, the output of the prescaler directly clocks the CNR. When the LPTMR is enabled, the CNR will increment every 22 to 216 prescaler clock cycles. After the LPTMR is enabled, the first increment of the CNR will take an additional one or two prescaler clock cycles due to synchronization logic. 33.4.3.2 Prescaler bypassed In Time Counter mode, when the prescaler is bypassed, the selected prescaler clock increments the CNR on every clock cycle. When the LPTMR is enabled, the first increment will take an additional one or two prescaler clock cycles due to synchronization logic. 33.4.3.3 Glitch filter In Pulse Counter mode, when the glitch filter is enabled, the output of the glitch filter directly clocks the CNR. When the LPTMR is first enabled, the output of the glitch filter is asserted, that is, logic 1 for active-high and logic 0 for active-low. The following table shows the change in glitch filter output with the selected input source. If The selected input source remains deasserted for at least to 215 consecutive prescaler clock rising edges Then 21 The selected input source remains asserted for at least 21 to 215 consecutive prescaler clock rising-edges The glitch filter output will also deassert. The glitch filter output will also assert. NOTE The input is only sampled on the rising clock edge. The CNR will increment each time the glitch filter output asserts. In Pulse Counter mode, the maximum rate at which the CNR can increment is once every 22 to 216 prescaler clock edges. When first enabled, the glitch filter will wait an additional one or two prescaler clock edges due to synchronization logic. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 554 Freescale Semiconductor, Inc. Chapter 33 Low-Power Timer (LPTMR) 33.4.3.4 Glitch filter bypassed In Pulse Counter mode, when the glitch filter is bypassed, the selected input source increments the CNR every time it asserts. Before the LPTMR is first enabled, the selected input source is forced to be asserted. This prevents the CNR from incrementing if the selected input source is already asserted when the LPTMR is first enabled. 33.4.4 LPTMR compare When the CNR equals the value of the CMR and increments, the following events occur: * * * * CSR[TCF] is set. LPTMR interrupt is generated if CSR[TIE] is also set. LPTMR hardware trigger is generated. CNR is reset if CSR[TFC] is clear. When the LPTMR is enabled, the CMR can be altered only when CSR[TCF] is set. When updating the CMR, the CMR must be written and CSR[TCF] must be cleared before the LPTMR counter has incremented past the new LPTMR compare value. 33.4.5 LPTMR counter The CNR increments by one on every: * * * * Prescaler clock in Time Counter mode with prescaler bypassed Prescaler output in Time Counter mode with prescaler enabled Input source assertion in Pulse Counter mode with glitch filter bypassed Glitch filter output in Pulse Counter mode with glitch filter enabled The CNR is reset when the LPTMR is disabled or if the counter register overflows. If CSR[TFC] is cleared, then the CNR is also reset whenever CSR[TCF] is set. The CNR continues incrementing when the core is halted in Debug mode when configured for Pulse Counter mode, the CNR will stop incrementing when the core is halted in Debug mode when configured for Time Counter mode. The CNR cannot be initialized, but can be read at any time. On each read of the CNR, software must first write to the CNR with any value. This will synchronize and register the current value of the CNR into a temporary register. The contents of the temporary register are returned on each read of the CNR. When reading the CNR, the bus clock must be at least two times faster than the rate at which the LPTMR counter is incrementing, otherwise incorrect data may be returned. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 555 Functional description 33.4.6 LPTMR hardware trigger The LPTMR hardware trigger asserts at the same time the CSR[TCF] is set and can be used to trigger hardware events in other peripherals without software intervention. The hardware trigger is always enabled. When Then The CMR is set to 0 with CSR[TFC] clear The LPTMR hardware trigger will assert on the first compare and does not deassert. The CMR is set to a nonzero value, or, if CSR[TFC] is set The LPTMR hardware trigger will assert on each compare and deassert on the following increment of the CNR. 33.4.7 LPTMR interrupt The LPTMR interrupt is generated whenever CSR[TIE] and CSR[TCF] are set. CSR[TCF] is cleared by disabling the LPTMR or by writing a logic 1 to it. CSR[TIE] can be altered and CSR[TCF] can be cleared while the LPTMR is enabled. The LPTMR interrupt is generated asynchronously to the system clock and can be used to generate a wakeup from any low-power mode, including the low-leakage modes, provided the LPTMR is enabled as a wakeup source. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 556 Freescale Semiconductor, Inc. Chapter 34 Real Time Clock (RTC) 34.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. 34.1.1 Features The RTC module features include: * 32-bit seconds counter with roll-over protection and 32-bit alarm * 16-bit prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm * Register write protection * Lock register requires POR or software reset to enable write access * 1 Hz square wave output 34.1.2 Modes of operation The RTC remains functional in all low power modes and can generate an interrupt to exit any low power mode. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 557 Register definition 34.1.3 RTC Signal Descriptions Table 34-1. RTC signal descriptions Signal Description RTC_CLKOUT I/O 1 Hz square-wave output O 34.1.3.1 RTC clock output The clock to the seconds counter is available on the RTC_CLKOUT signal. It is a 1 Hz square wave output. 34.2 Register definition All registers must be accessed using 32-bit writes and all register accesses incur three wait states. Write accesses to any register by non-supervisor mode software, when the supervisor access bit in the control register is clear, will terminate with a bus error. Read accesses by non-supervisor mode software complete as normal. Writing to a register protected by the lock register does not generate a bus error, but the write will not complete. RTC memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_D000 RTC Time Seconds Register (RTC_TSR) 32 R/W 0000_0000h 34.2.1/559 4003_D004 RTC Time Prescaler Register (RTC_TPR) 32 R/W 0000_0000h 34.2.2/559 4003_D008 RTC Time Alarm Register (RTC_TAR) 32 R/W 0000_0000h 34.2.3/560 4003_D00C RTC Time Compensation Register (RTC_TCR) 32 R/W 0000_0000h 34.2.4/560 4003_D010 RTC Control Register (RTC_CR) 32 R/W 0000_0000h 34.2.5/561 4003_D014 RTC Status Register (RTC_SR) 32 R/W 0000_0001h 34.2.6/563 4003_D018 RTC Lock Register (RTC_LR) 32 R/W 0000_00FFh 34.2.7/564 32 R/W 0000_0007h 34.2.8/565 4003_D01C RTC Interrupt Enable Register (RTC_IER) KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 558 Freescale Semiconductor, Inc. Chapter 34 Real Time Clock (RTC) 34.2.1 RTC Time Seconds Register (RTC_TSR) Address: 4003_D000h base + 0h offset = 4003_D000h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_TSR field descriptions Field Description 31-0 TSR Time Seconds Register When the time counter is enabled, the TSR is read only and increments once a second provided SR[TOF] or SR[TIF] are not set. The time counter will read as zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the TSR can be read or written. Writing to the TSR when the time counter is disabled will clear the SR[TOF] and/or the SR[TIF]. Writing to TSR with zero is supported, but not recommended because TSR will read as zero when SR[TIF] or SR[TOF] are set (indicating the time is invalid). 34.2.2 RTC Time Prescaler Register (RTC_TPR) Address: 4003_D000h base + 4h offset = 4003_D004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TPR W Reset 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_TPR field descriptions Field 31-16 Reserved 15-0 TPR Description This field is reserved. This read-only field is reserved and always has the value 0. Time Prescaler Register When the time counter is enabled, the TPR is read only and increments every 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the TPR can be read or written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one to a logic zero. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 559 Register definition 34.2.3 RTC Time Alarm Register (RTC_TAR) Address: 4003_D000h base + 8h offset = 4003_D008h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_TAR field descriptions Field Description 31-0 TAR Time Alarm Register When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR clears the SR[TAF]. 34.2.4 RTC Time Compensation Register (RTC_TCR) Address: 4003_D000h base + Ch offset = 4003_D00Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 CIC R 19 18 17 16 15 14 13 TCV 0 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 CIR W Reset 12 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 TCR 0 0 0 0 0 0 0 0 RTC_TCR field descriptions Field Description 31-24 CIC Compensation Interval Counter 23-16 TCV Time Compensation Value 15-8 CIR Compensation Interval Register 7-0 TCR Time Compensation Register Current value of the compensation interval counter. If the compensation interval counter equals zero then it is loaded with the contents of the CIR. If the CIC does not equal zero then it is decremented once a second. Current value used by the compensation logic for the present second interval. Updated once a second if the CIC equals 0 with the contents of the TCR field. If the CIC does not equal zero then it is loaded with zero (compensation is not enabled for that second increment). Configures the compensation interval in seconds from 1 to 256 to control how frequently the TCR should adjust the number of 32.768 kHz cycles in each second. The value written should be one less than the number of seconds. For example, write zero to configure for a compensation interval of one second. This register is double buffered and writes do not take affect until the end of the current compensation interval. Configures the number of 32.768 kHz clock cycles in each second. This register is double buffered and writes do not take affect until the end of the current compensation interval. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 560 Freescale Semiconductor, Inc. Chapter 34 Real Time Clock (RTC) RTC_TCR field descriptions (continued) Field Description 80h ... FFh 00h 01h ... 7Fh Time Prescaler Register overflows every 32896 clock cycles. ... Time Prescaler Register overflows every 32769 clock cycles. Time Prescaler Register overflows every 32768 clock cycles. Time Prescaler Register overflows every 32767 clock cycles. ... Time Prescaler Register overflows every 32641 clock cycles. 34.2.5 RTC Control Register (RTC_CR) Address: 4003_D000h base + 10h offset = 4003_D010h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 Reserved W UM SUP 0 0 OSCE 0 0 0 WPE SWR 0 W Reset CLKO SC2P SC4P SC8P SC16P 0 0 0 0 0 0 0 0 0 0 0 0 RTC_CR field descriptions Field 31-15 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 561 Register definition RTC_CR field descriptions (continued) Field Description 14 Reserved This field is reserved. It must always be written to 0. 13 SC2P Oscillator 2pF Load Configure 12 SC4P Oscillator 4pF Load Configure 11 SC8P Oscillator 8pF Load Configure 10 SC16P Oscillator 16pF Load Configure 9 CLKO Clock Output 8 OSCE Oscillator Enable 7-4 Reserved 3 UM 0 1 0 1 0 1 0 1 0 1 0 1 Disable the load. Enable the additional load. Disable the load. Enable the additional load. Disable the load. Enable the additional load. Disable the load. Enable the additional load. The 32 kHz clock is output to other peripherals. The 32 kHz clock is not output to other peripherals. 32.768 kHz oscillator is disabled. 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize. This field is reserved. This read-only field is reserved and always has the value 0. Update Mode Allows SR[TCE] to be written even when the Status Register is locked. When set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if the SR[TCE] is clear. 0 1 Registers cannot be written when locked. Registers can be written when locked under limited conditions. 2 SUP Supervisor Access 1 WPE Wakeup Pin Enable 0 1 The wakeup pin is optional and not available on all devices. 0 1 0 SWR Non-supervisor mode write accesses are not supported and generate a bus error. Non-supervisor mode write accesses are supported. Wakeup pin is disabled. Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on. Software Reset Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 562 Freescale Semiconductor, Inc. Chapter 34 Real Time Clock (RTC) RTC_CR field descriptions (continued) Field Description 0 1 No effect. Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it. 34.2.6 RTC Status Register (RTC_SR) Address: 4003_D000h base + 14h offset = 4003_D014h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 TAF TOF TIF 0 0 0 1 0 R TCE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 RTC_SR field descriptions Field 31-5 Reserved 4 TCE Description This field is reserved. This read-only field is reserved and always has the value 0. Time Counter Enable When time counter is disabled the TSR register and TPR register are writeable, but do not increment. When time counter is enabled the TSR register and TPR register are not writeable, but increment. 0 1 3 Reserved 2 TAF This field is reserved. This read-only field is reserved and always has the value 0. Time Alarm Flag Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] increments. This bit is cleared by writing the TAR register. 0 1 1 TOF Time counter is disabled. Time counter is enabled. Time alarm has not occurred. Time alarm has occurred. Time Overflow Flag Time overflow flag is set when the time counter is enabled and overflows. The TSR and TPR do not increment and read as zero when this bit is set. This bit is cleared by writing the TSR register when the time counter is disabled. 0 1 Time overflow has not occurred. Time overflow has occurred and time counter is read as zero. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 563 Register definition RTC_SR field descriptions (continued) Field Description 0 TIF Time Invalid Flag The time invalid flag is set on POR or software reset. The TSR and TPR do not increment and read as zero when this bit is set. This bit is cleared by writing the TSR register when the time counter is disabled. 0 1 Time is valid. Time is invalid and time counter is read as zero. 34.2.7 RTC Lock Register (RTC_LR) Address: 4003_D000h base + 18h offset = 4003_D018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 R W Reset 0 0 0 0 Bit 15 14 13 12 0 0 0 0 11 10 9 8 0 R 1 LRL SRL CRL TCL 1 1 1 1 1 W Reset 0 0 0 0 0 0 0 0 1 1 1 1 RTC_LR field descriptions Field Description 31-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 6 LRL Lock Register Lock After being cleared, this bit can be set only by POR or software reset. 0 1 5 SRL Status Register Lock After being cleared, this bit can be set only by POR or software reset. 0 1 4 CRL Lock Register is locked and writes are ignored. Lock Register is not locked and writes complete as normal. Status Register is locked and writes are ignored. Status Register is not locked and writes complete as normal. Control Register Lock After being cleared, this bit can only be set by POR. 0 1 Control Register is locked and writes are ignored. Control Register is not locked and writes complete as normal. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 564 Freescale Semiconductor, Inc. Chapter 34 Real Time Clock (RTC) RTC_LR field descriptions (continued) Field Description 3 TCL Time Compensation Lock After being cleared, this bit can be set only by POR or software reset. 0 1 2-0 Reserved Time Compensation Register is locked and writes are ignored. Time Compensation Register is not locked and writes complete as normal. This field is reserved. This read-only field is reserved and always has the value 1. 34.2.8 RTC Interrupt Enable Register (RTC_IER) Address: 4003_D000h base + 1Ch offset = 4003_D01Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSIE Reserved W TAIE TOIE TIIE 0 0 1 1 1 WPON 0 R W Reset 0 0 0 0 0 0 0 0 0 Reserved 0 0 RTC_IER field descriptions Field 31-8 Reserved 7 WPON Description This field is reserved. This read-only field is reserved and always has the value 0. Wakeup Pin On The wakeup pin is optional and not available on all devices. Whenever the wakeup pin is enabled and this bit is set, the wakeup pin will assert. 0 1 6-5 Reserved 4 TSIE No effect. If the wakeup pin is enabled, then the wakeup pin will assert. This field is reserved. Time Seconds Interrupt Enable The seconds interrupt is an edge-sensitive interrupt with a dedicated interrupt vector. It is generated once a second and requires no software overhead (there is no corresponding status flag to clear). Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 565 Functional description RTC_IER field descriptions (continued) Field Description 0 1 3 Reserved Seconds interrupt is disabled. Seconds interrupt is enabled. This field is reserved. 2 TAIE Time Alarm Interrupt Enable 1 TOIE Time Overflow Interrupt Enable 0 TIIE Time Invalid Interrupt Enable 0 1 0 1 0 1 Time alarm flag does not generate an interrupt. Time alarm flag does generate an interrupt. Time overflow flag does not generate an interrupt. Time overflow flag does generate an interrupt. Time invalid flag does not generate an interrupt. Time invalid flag does generate an interrupt. 34.3 Functional description 34.3.1 Power, clocking, and reset The RTC is an always powered block that remains active in all low power modes. The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an external crystal using the oscillator. The power-on-reset signal initializes all RTC registers to their default state. A software reset bit can also initialize all RTC registers. 34.3.1.1 Oscillator control The 32.768 kHz crystal oscillator is disabled at POR and must be enabled by software. After enabling the cystal oscillator, wait the oscillator startup time before setting SR[TCE] or using the oscillator clock external to the RTC. The crystal oscillator includes tunable capacitors that can be configured by software. Do not change the capacitance unless the oscillator is disabled. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 566 Freescale Semiconductor, Inc. Chapter 34 Real Time Clock (RTC) 34.3.1.2 Software reset Writing one to the CR[SWR] forces the equivalent of a POR to the rest of the RTC module. The CR[SWR] is not affected by the software reset and must be cleared by software. 34.3.1.3 Supervisor access When the supervisor access control bit is clear, only supervisor mode software can write to the RTC registers, non-supervisor mode software will generate a bus error. Both supervisor and non-supervisor mode software can always read the RTC registers. 34.3.2 Time counter The time counter consists of a 32-bit seconds counter that increments once every second and a 16-bit prescaler register that increments once every 32.768 kHz clock cycle. The time seconds register and time prescaler register can be written only when SR[TCE] is clear. Always write to the prescaler register before writing to the seconds register, because the seconds register increments on the falling edge of bit 14 of the prescaler register. The time prescaler register increments provided SR[TCE] is set, SR[TIF] is clear, SR[TOF] is clear, and the 32.768 kHz clock source is present. After enabling the oscillator, wait the oscillator startup time before setting SR[TCE] to allow time for the oscillator clock output to stabilize. If the time seconds register overflows then the SR[TOF] will set and the time prescaler register will stop incrementing. Clear SR[TOF] by initializing the time seconds register. The time seconds register and time prescaler register read as zero whenever SR[TOF] is set. SR[TIF] is set on POR and software reset and is cleared by initializing the time seconds register. The time seconds register and time prescaler register read as zero whenever SR[TIF] is set. 34.3.3 Compensation The compensation logic provides an accurate and wide compensation range and can correct errors as high as 3906 ppm and as low as 0.12 ppm. The compensation factor must be calculated externally to the RTC and supplied by software to the compensation KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 567 Functional description register. The RTC itself does not calculate the amount of compensation that is required, although the 1 Hz clock is output to an external pin in support of external calibration logic. Crystal compensation can be supported by using firmware and crystal characteristics to determine the compensation amount. Temperature compensation can be supported by firmware that periodically measures the external temperature via ADC and updates the compensation register based on a look-up table that specifies the change in crystal frequency over temperature. The compensation logic alters the number of 32.768 kHz clock cycles it takes for the prescaler register to overflow and increment the time seconds counter. The time compensation value is used to adjust the number of clock cycles between -127 and +128. Cycles are added or subtracted from the prescaler register when the prescaler register equals 0x3FFF and then increments. The compensation interval is used to adjust the frequency at which the time compensation value is used, that is, from once a second to once every 256 seconds. Updates to the time compensation register will not take effect until the next time the time seconds register increments and provided the previous compensation interval has expired. When the compensation interval is set to other than once a second then the compensation is applied in the first second interval and the remaining second intervals receive no compensation. Compensation is disabled by configuring the time compensation register to zero. 34.3.4 Time alarm The time alarm register, SR[TAF], and IER[TAIE] allow the RTC to generate an interrupt at a predefined time. The 32-bit time alarm register is compared with the 32-bit time seconds register each time it increments. The SR[TAF] will set when the time alarm register equals the time seconds register and the time seconds register increments. The time alarm flag is cleared by writing the time alarm register. This will usually be the next alarm value, although writing a value that is less than the time seconds register, such as zero, will prevent the time alarm flag from setting again. The time alarm flag cannot otherwise be disabled, although the interrupt it generates is enabled or disabled by IER[TAIE]. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 568 Freescale Semiconductor, Inc. Chapter 34 Real Time Clock (RTC) 34.3.5 Update mode The Update Mode bit in the Control register (CR[UM]) configures software write access to the Time Counter Enable (SR[TCE]) bit. When CR[UM] is clear, SR[TCE] can be written only when the LR[SRL] bit is set. When CR[UM] is set, the SR[TCE] can also be written when SR[TCE] is clear or when SR[TIF] or SR[TOF] are set. This allows the time seconds and prescaler registers to be initialized whenever time is invalidated, while preventing the time seconds and prescaler registers from being changed on the fly. When LR[SRL] is set, CR[UM] has no effect on SR[TCE]. 34.3.6 Register lock The lock register can be used to block write accesses to certain registers until the next POR or software reset. Locking the control register will disable the software reset. Locking the lock register will block future updates to the lock register. Write accesses to a locked register are ignored and do not generate a bus error. 34.3.7 Interrupt The RTC interrupt is asserted whenever a status flag and the corresponding interrupt enable bit are both set. It is always asserted on POR, and software reset. The RTC interrupt is enabled at the chip level by enabling the chip-specific RTC clock gate control bit. The RTC interrupt can be used to wakeup the chip from any low-power mode. The optional RTC seconds interrupt is an edge-sensitive interrupt with a dedicated interrupt vector that is generated once a second and requires no software overhead (there is no corresponding status flag to clear). It is enabled in the RTC by the time seconds interrupt enable bit and enabled at the chip level by setting the chip-specific RTC clock gate control bit. This interrupt is optional and may not be implemented on all devices. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 569 Functional description KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 570 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) 35.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial communication between the MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, and memories, among others. The SPI runs at a baud rate up to the bus clock divided by two in master mode and up to the bus clock divided by four in slave mode. Software can poll the status flags, or SPI operation can be interrupt driven. NOTE For the actual maximum SPI baud rate, refer to the Chip Configuration details and to the device's Data Sheet. The SPI also includes a hardware match feature for the receive data buffer. The SPI includes an internal DMA interface to support continuous SPI transmission through an on-chip DMA controller instead of through the CPU. This feature decreases CPU loading, allowing CPU time to be used for other work. 35.1.1 Features The SPI includes these distinctive features: * Master mode or slave mode operation * Full-duplex or single-wire bidirectional mode KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 571 Introduction * Programmable transmit bit rate * Double-buffered transmit and receive data register * Serial clock phase and polarity options * Slave select output * Mode fault error flag with CPU interrupt capability * Control of SPI operation during wait mode * Selectable MSB-first or LSB-first shifting * Receive data buffer hardware match feature * Support transmission of both Transmit and Receive by DMA 35.1.2 Modes of Operation The SPI functions in three modes, run, wait, and stop. * Run Mode This is the basic mode of operation. * Wait Mode SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPIx_C2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in Run Mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock generation turned off. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU enters run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. * Stop Mode To reduce power consumption, the SPI is inactive in stop modes where the peripheral bus clock is stopped but internal logic states are retained. If the SPI is configured as a master, any transmission in progress stops, but is resumed after the CPU enters run mode. If the SPI is configured as a slave, reception and transmission of a data continues, so that the slave stays synchronized to the master. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 572 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) The SPI is completely disabled in stop modes where the peripheral bus clock is stopped and internal logic states are not retained. When the CPU wakes from these stop modes, all SPI register content is reset. Detailed descriptions of operating modes appear in Low Power Mode Options. 35.1.3 Block Diagrams This section includes block diagrams showing SPI system connections, the internal organization of the SPI module, and the SPI clock dividers that control the master mode bit rate. 35.1.3.1 SPI System Block Diagram The following figure shows the SPI modules of two MCUs connected in a master-slave arrangement. The master device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock output from the master and an input to the slave. The slave device must be selected by a low level on the slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave select output. SLAVE MASTER MOSI MOSI SPI SHIFTER 8 BITS SPI SHIFTER MISO SPSCK CLOCK GENERATOR SS MISO 8 BITS SPSCK SS Figure 35-1. SPI System Connections KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 573 Introduction 35.1.3.2 SPI Module Block Diagram The following is a block diagram of the SPI module. The central element of the SPI is the SPI shift register. Data is written to the double-buffered transmitter (write to SPIx_D) and gets transferred to the SPI shift register at the start of a data transfer. After shifting in 8 bits of data, the data is transferred into the double-buffered receiver where it can be read from SPIx_D. Pin multiplexing logic controls connections between MCU pins and the SPI module. When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the shifter output is routed to MOSI, and the shifter input is routed from the MISO pin. When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter output is routed to MISO, and the shifter input is routed from the MOSI pin. In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all MOSI pins together. Peripheral devices often use slightly different names for these pins. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 574 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) PIN CONTROL M SPE MOSI (MOMI) S Tx BUFFER (WRITE SPIxD) ENABLE SPI SYSTEM M SPI SHIFT REGISTER SHIFT OUT SHIFT IN Rx BUFFER (READ SPIxD) MISO (SISO) S SPC0 BIDIROE LSBFE SHIFT DIRECTION Rx BUFFER Tx BUFFER SHIFT FULL CLOCK EMPTY MASTER CLOCK BUS RATE CLOCK CLOCK LOGIC SPIBR CLOCK GENERATOR MSTR SLAVE CLOCK MASTER/SLAVE M SPSCK S MASTER/ SLAVE MODE SELECT MODSSOE MODE FAULT DETECTION RX DMA DONE SPRF Rx_DMA REQ 8-BIT COMPARATOR RXDMAE SPIxM TX DMA DONE SS SPMF SPMIE SPTEF TX DMA REQ TXDMAE SPTIE MODF SPIE INTERRUPT REQUEST Figure 35-2. SPI Module Block Diagram without FIFO 35.2 External Signal Description The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits. When the SPI is disabled (SPE = 0), these four pins revert to other functions that are not controlled by the SPI (based on chip configuration). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 575 External Signal Description 35.2.1 SPSCK -- SPI Serial Clock When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master, this pin is the serial clock output. 35.2.2 MOSI -- Master Data Out, Slave Data In When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data output. When the SPI is enabled as a slave and SPC0 is 0, this pin is the serial data input. If SPC0 is 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes the bidirectional data I/O pin (MOMI). Also, the bidirectional mode output enable bit determines whether the pin acts as an input (BIDIROE is 0) or an output (BIDIROE is 1). If SPC0 is 1 and slave mode is selected, this pin is not used by the SPI and reverts to other functions (based on chip configuration). 35.2.3 MISO -- Master Data In, Slave Data Out When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data input. When the SPI is enabled as a slave and SPC0 is 0, this pin is the serial data output. If SPC0 is 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes the bidirectional data I/ O pin (SISO), and the bidirectional mode output enable bit determines whether the pin acts as an input (BIDIROE is 0) or an output (BIDIROE is 1). If SPC0 is 1 and master mode is selected, this pin is not used by the SPI and reverts to other functions (based on chip configuration). 35.2.4 SS -- Slave Select When the SPI is enabled as a slave, this pin is the low-true slave select input. When the SPI is enabled as a master and mode fault enable is off (MODFEN is 0), this pin is not used by the SPI and reverts to other functions (based on chip configuration). When the SPI is enabled as a master and MODFEN is 1, the slave select output enable bit determines whether this pin acts as the mode fault input (SSOE is 0) or as the slave select output (SSOE is 1). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 576 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) 35.3 Memory Map and Register Descriptions The SPI has 8-bit registers to select SPI options, to control baud rate, to report SPI status, to hold an SPI data match value, and for transmit/receive data. SPI memory map Address offset (hex) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 0 4007_6000 SPI control register 1 (SPI0_C1) 8 R/W 04h 35.3.1/577 1 4007_6001 SPI control register 2 (SPI0_C2) 8 R/W 00h 35.3.2/579 2 4007_6002 SPI baud rate register (SPI0_BR) 8 R/W 00h 35.3.3/580 3 4007_6003 SPI status register (SPI0_S) 8 R 20h 35.3.4/581 5 4007_6005 SPI data register (SPI0_D) 8 R/W 00h 35.3.5/582 7 4007_6007 SPI match register (SPI0_M) 8 R/W 00h 35.3.6/583 35.3.1 SPI control register 1 (SPIx_C1) This read/write register includes the SPI enable control, interrupt enables, and configuration options. Address: 4007_6000h base + 0h offset = 4007_6000h Bit Read Write Reset 7 6 5 4 3 2 1 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0 0 0 0 0 1 0 0 SPI0_C1 field descriptions Field 7 SPIE Description SPI interrupt enable: for SPRF and MODF This bit enables the interrupt for SPI receive buffer full (SPRF) and mode fault (MODF) events. 0 1 6 SPE Interrupts from SPRF and MODF are inhibited--use polling Request a hardware interrupt when SPRF or MODF is 1 SPI system enable This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, the SPI is disabled and forced into an idle state, and all status bits in the S register are reset. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 577 Memory Map and Register Descriptions SPI0_C1 field descriptions (continued) Field Description 0 1 5 SPTIE SPI transmit interrupt enable This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). An interrupt occurs when the SPI transmit buffer is empty (SPTEF is set). 0 1 4 MSTR Interrupts from SPTEF inhibited (use polling) When SPTEF is 1, hardware interrupt requested Master/slave mode select This bit selects master or slave mode operation. 0 1 3 CPOL SPI system inactive SPI system enabled SPI module configured as a slave SPI device SPI module configured as a master SPI device Clock polarity This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values. This bit effectively places an inverter in series with the clock signal either from a master SPI device or to a slave SPI device. Refer to the description of "SPI Clock Formats" for details. 0 1 2 CPHA Clock phase This bit selects one of two clock formats for different kinds of synchronous serial peripheral devices. Refer to the description of "SPI Clock Formats" for details. 0 1 1 SSOE Active-high SPI clock (idles low) Active-low SPI clock (idles high) First edge on SPSCK occurs at the middle of the first cycle of a data transfer First edge on SPSCK occurs at the start of the first cycle of a data transfer Slave select output enable This bit is used in combination with the mode fault enable (MODFEN) bit in the C2 register and the master/ slave (MSTR) control bit to determine the function of the SS pin. 0 1 When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input. When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input. 0 LSBFE LSB first (shifter direction) This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register always have the MSB in bit 7. 0 1 SPI serial data transfers start with most significant bit SPI serial data transfers start with least significant bit KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 578 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) 35.3.2 SPI control register 2 (SPIx_C2) This read/write register is used to control optional features of the SPI system. Bit 6 is not implemented and always reads 0. Address: 4007_6000h base + 1h offset = 4007_6001h Bit Read Write Reset 7 6 5 4 3 2 1 0 SPMIE Reserved TXDMAE MODFEN BIDIROE RXDMAE SPISWAI SPC0 0 0 0 0 0 0 0 0 SPI0_C2 field descriptions Field 7 SPMIE Description SPI match interrupt enable This is the interrupt enable bit for the SPI receive data buffer hardware match (SPMF) function. 0 1 Interrupts from SPMF inhibited (use polling) When SPMF is 1, requests a hardware interrupt 6 Reserved This field is reserved. Do not write to this reserved bit. 5 TXDMAE Transmit DMA enable This bit enables a transmit DMA request. When this bit is set to 1, a transmit DMA request is asserted when both SPTEF and SPE are set, and the interrupt from SPTEF is disabled. 0 1 4 MODFEN Master mode-fault function enable When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used. For details, refer to the description of the SSOE bit in the C1 register. 0 1 3 BIDIROE Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output Bidirectional mode output enable When bidirectional mode is enabled because SPI pin control 0 (SPC0) is set to 1, the BIDIROE bit determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending on whether the SPI is configured as a master or a slave, it uses the MOSI (MOMI) or MISO (SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 is 0, BIDIROE has no meaning or effect. 0 1 2 RXDMAE DMA request for transmit is disabled and interrupt from SPTEF is allowed DMA request for transmit is enabled and interrupt from SPTEF is disabled Output driver disabled so SPI data I/O pin acts as an input SPI I/O pin enabled as an output Receive DMA enable This is the enable bit for a receive DMA request. When this bit is set to 1, a receive DMA request is asserted when both SPRF and SPE are set, and the interrupt from SPRF is disabled. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 579 Memory Map and Register Descriptions SPI0_C2 field descriptions (continued) Field Description 0 1 1 SPISWAI SPI stop in wait mode This bit is used for power conservation while the device is in wait mode. 0 1 0 SPC0 DMA request for receive is disabled and interrupt from SPRF is allowed DMA request for receive is enabled and interrupt from SPRF is disabled SPI clocks continue to operate in wait mode SPI clocks stop when the MCU enters wait mode SPI pin control 0 This bit enables bidirectional pin configurations. 0 SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. 1 In slave mode of operation: MISO is slave out and MOSI is slave in. SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI. 35.3.3 SPI baud rate register (SPIx_BR) Use this register to set the prescaler and bit rate divisor for an SPI master. This register may be read or written at any time. Address: 4007_6000h base + 2h offset = 4007_6002h Bit 7 Read Write Reset 0 0 6 5 4 3 2 SPPR[2:0] 0 0 1 0 0 0 SPR[3:0] 0 0 0 SPI0_BR field descriptions Field Description 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6-4 SPPR[2:0] SPI baud rate prescale divisor This 3-bit field selects one of eight divisors for the SPI baud rate prescaler. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler drives the input of the SPI baud rate divider. Refer to the description of "SPI Baud Rate Generation" for details. 000 Baud rate prescaler divisor is 1 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 580 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) SPI0_BR field descriptions (continued) Field Description 001 010 011 100 101 110 111 3-0 SPR[3:0] Baud rate prescaler divisor is 2 Baud rate prescaler divisor is 3 Baud rate prescaler divisor is 4 Baud rate prescaler divisor is 5 Baud rate prescaler divisor is 6 Baud rate prescaler divisor is 7 Baud rate prescaler divisor is 8 SPI baud rate divisor This 4-bit field selects one of nine divisors for the SPI baud rate divider. The input to this divider comes from the SPI baud rate prescaler. Refer to the description of "SPI Baud Rate Generation" for details. 0000 0001 0010 0011 0100 0101 0110 0111 1000 All others Baud rate divisor is 2 Baud rate divisor is 4 Baud rate divisor is 8 Baud rate divisor is 16 Baud rate divisor is 32 Baud rate divisor is 64 Baud rate divisor is 128 Baud rate divisor is 256 Baud rate divisor is 512 Reserved 35.3.4 SPI status register (SPIx_S) This register contains read-only status bits. Writes have no meaning or effect. NOTE Bits 3 through 0 are not implemented and always read 0. Address: 4007_6000h base + 3h offset = 4007_6003h Bit Read 7 6 5 4 SPRF SPMF SPTEF MODF 0 0 1 0 3 2 1 0 0 0 0 Write Reset 0 0 SPI0_S field descriptions Field 7 SPRF Description SPI read buffer full flag SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data (D) register. When the receive DMA request is disabled (RXDMAE is 0), SPRF is cleared by reading SPRF while it is set and then reading the SPI data register. When the receive DMA request is enabled (RXDMAE is 1), SPRF is automatically cleared when the DMA transfer for the receive DMA request is completed (RX DMA Done is asserted). Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 581 Memory Map and Register Descriptions SPI0_S field descriptions (continued) Field Description 0 1 6 SPMF Data available in the receive data buffer SPI match flag SPMF is set after SPRF is 1 when the value in the receive data buffer matches the value in the M register. To clear the flag, read SPMF when it is set and then write a 1 to it. 0 1 5 SPTEF No data available in the receive data buffer Value in the receive data buffer does not match the value in the M register Value in the receive data buffer matches the value in the M register SPI transmit buffer empty flag This bit is set when the transmit data buffer is empty. When the transmit DMA request is disabled (TXDMAE is 0), SPTEF is cleared by reading the S register with SPTEF set and then writing a data value to the transmit buffer at D. The S register must be read with SPTEF set to 1 before writing data to the D register; otherwise, the D write is ignored. When the transmit DMA request is enabled (TXDMAE is 1), SPTEF is automatically cleared when the DMA transfer for the transmit DMA request is completed (TX DMA Done is asserted). SPTEF is automatically set when all data from the transmit buffer transfers into the transmit shift register. For an idle SPI, data written to D is transferred to the shifter almost immediately so that SPTEF is set within two bus cycles, allowing a second set of data to be queued into the transmit buffer. After completion of the transfer of the data in the shift register, the queued data from the transmit buffer automatically moves to the shifter, and SPTEF is set to indicate that room exists for new data in the transmit buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no data moves from the buffer to the shifter. If a transfer does not stop, the last data that was transmitted is sent out again. 0 1 4 MODF SPI transmit buffer empty Master mode fault flag MODF is set if the SPI is configured as a master and the slave select input goes low, indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input only when MSTR is 1, MODFEN is 1, and SSOE is 0; otherwise, MODF will never be set. MODF is cleared by reading MODF while it is 1 and then writing to the SPI control register 1 (C1). 0 1 3-0 Reserved SPI transmit buffer not empty No mode fault error Mode fault error detected This field is reserved. This read-only field is reserved and always has the value 0. 35.3.5 SPI data register (SPIx_D) This register is both the input and output register for SPI data. A write to the register writes to the transmit data buffer, allowing data to be queued and transmitted. When the SPI is configured as a master, data queued in the transmit data buffer is transmitted immediately after the previous transmission has completed. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 582 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) The SPTEF bit in the S register indicates when the transmit data buffer is ready to accept new data. When the transmit DMA request is disabled (TXDMAE is 0): The S register must be read when SPTEF is set before writing to the SPI data register; otherwise, the write is ignored. When the transmit DMA request is enabled (TXDMAE is 1) when SPTEF is set, the SPI data register can be written automatically by DMA without reading the S register first. Data may be read from the SPI data register any time after SPRF is set and before another transfer is finished. Failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition, and the data from the new transfer is lost. The new data is lost because the receive buffer still held the previous character and was not ready to accept the new data. There is no indication for a receive overrun condition, so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated. Address: 4007_6000h base + 5h offset = 4007_6005h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 Bits[7:0] 0 0 0 0 SPI0_D field descriptions Field 7-0 Bits[7:0] Description Data (low byte) 35.3.6 SPI match register (SPIx_M) This register contains the hardware compare value. When the value received in the SPI receive data buffer equals this hardware compare value, the SPI match flag (SPMF) sets. Address: 4007_6000h base + 7h offset = 4007_6007h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 Bits[7:0] 0 0 0 0 SPI0_M field descriptions Field 7-0 Bits[7:0] Description Hardware compare value (low byte) KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 583 Functional Description 35.4 Functional Description This section provides the functional description of the module. 35.4.1 General The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1. While the SPE bit is set, the four associated SPI port pins are dedicated to the SPI function as: * Slave select (SS) * Serial clock (SPSCK) * Master out/slave in (MOSI) * Master in/slave out (MISO) An SPI transfer is initiated in the master SPI device by reading the SPI status register (SPIx_S) when SPTEF = 1 and then writing data to the transmit data buffer (write to SPIxD ). When a transfer is complete, received data is moved into the receive data buffer. The SPIxD register acts as the SPI receive data buffer for reads and as the SPI transmit data buffer for writes. The clock phase control bit (CPHA) and clock polarity control bit (CPOL) in the SPI Control Register 1 (SPIx_C1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered SPSCK edges or on even numbered SPSCK edges. The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI Control Register 1 is set, master mode is selected; when the MSTR bit is clear, slave mode is selected. 35.4.2 Master Mode The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by reading the SPIx_S register while SPTEF = 1 and writing to the master SPI data registers. If the shift register is empty, the byte immediately transfers to the shift register. The data begins shifting out on the MOSI pin under the control of the serial clock. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 584 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) * SPSCK * The SPR3, SPR2, SPR1, and SPR0 baud rate selection bits in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI Baud Rate register control the baud rate generator and determine the speed of the transmission. The SPSCK pin is the SPI clock output. Through the SPSCK pin, the baud rate generator of the master controls the shift register of the slave peripheral. * MOSI, MISO pin * In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and BIDIROE control bits. * SS pin * If MODFEN and SSOE bit are set, the SS pin is configured as slave select output. The SS output becomes low during each transmission and is high when the SPI is in idle state. If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input becomes low this indicates a mode fault error where another master tries to drive the MOSI and SPSCK lines. In this case, the SPI immediately switches to slave mode by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). As a result, all outputs are disabled, and SPSCK, MOSI and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state. This mode fault error also sets the mode fault (MODF) flag in the SPI Status Register (SPIx_S). If the SPI interrupt enable bit (SPIE) is set when the MODF flag gets set, then an SPI interrupt sequence is also requested. When a write to the SPI Data Register in the master occurs, there is a half SPSCK-cycle delay. After the delay, SPSCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI Control Register 1 (see SPI Clock Formats). Note A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR3SPR0 in master mode abort a transmission in progress and force the SPI into idle state. The remote slave cannot detect this, therefore the master has to ensure that the remote slave is set back to idle state. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 585 Functional Description 35.4.3 Slave Mode The SPI operates in slave mode when the MSTR bit in SPI Control Register1 is clear. * SPSCK In slave mode, SPSCK is the SPI clock input from the master. * MISO, MOSI pin In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI Control Register 2. * SS pin The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is forced into an idle state. The SS input also controls the serial data output pin. If SS is high (not selected), the serial data output pin is high impedance. If SS is low, the first bit in the SPI Data Register is driven out of the serial data output pin. Also, if the slave is not selected (SS is high), then the SPSCK input is ignored and no internal shifting of the SPI shift register occurs. Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. Note When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave's serial data output line. As long as no more than one slave device drives the system slave's serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. If the CPHA bit in SPI Control Register 1 is clear, odd numbered edges on the SPSCK input cause the data at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 586 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) If the CPHA bit is set, even numbered edges on the SPSCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the eighth shift, the transfer is considered complete and the received data is transferred into the SPI Data register. To indicate transfer is complete, the SPRF flag in the SPI Status Register is set. Note A change of the bits BIDIROE with SPC0 set, CPOL, CPHA, SSOE, LSBFE, MODFEN, and SPC0 in slave mode will corrupt a transmission in progress and must be avoided. 35.4.4 SPI Transmission by DMA SPI supports both Transmit and Receive by DMA. The basic flow of SPI transmission by DMA is as below. RESET Configure DMA Controller for SPI Transmission Configure SPI before Transmission Set TXDMAE/RXDMAE=1 to enable Transmit/Receive by DMA Set SPE=1 to start transmission in master mode or enable SPI for transmission in slave moe Wait for interrupt(s) of DMA Controller indicating end of SPI transmission Figure 35-15. Basic Flow of SPI Transmission by DMA KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 587 Functional Description 35.4.4.1 Transmit by DMA Transmit by DMA is supported only when TXDMAE is set. A transmit DMA request is asserted when both SPE and SPTEF are set. Then the on-chip DMA controller detects this request and transfers data from memory into the SPI data register. After that, TX DMA DONE is asserted to clear SPTEF automatically. This process repeats until all data for transmission (the number is decided by the configuration register[s] of the DMA controller) is sent. After DMA transfers the first byte to the SPI data register, the SPI pushes this data into the shifter, thereby making SPTEF high again. This generates another DMA request immediately, but the CPU lacks enough time to service the first DMA interrupt service request (ISR). The subsequent DMA request is paced at the SPI transfer rate. Manage this behavior during the first byte transfer through the DMA channel. Write the first byte to the SPI data register via the CPU. The other bytes are transmitted by the DMA. RESET Configure DMA Controller for SPI transmission Configure SPI before Transmission Set SPE=1 to start transmission in master mode or enable SPI for transmission in slave mode Read SPI status register Write the first byte to SPI data register via CPU Set TXDMAE to enable Transmit by DMA Wait for interrupt(s) of DMA Controller indicating end of SPI transmission Figure 35-16. Recommended startup of SPI transmit by DMA KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 588 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) 35.4.4.2 Receive by DMA Receive by DMA is supported only when RXDMAE is set. A receive DMA request is asserted when both SPE and SPRF are set. Then the on-chip DMA controller detects this request and transfers data from the SPI data register into memory. After that, RX DMA DONE is asserted to clear SPRF automatically. This process repeats until all data to be received (the number is decided by configuration register[s] of the DMA controller) is received or no receive DMA request is generated again because the SPI transmission is finished. 35.4.5 SPI Clock Formats To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses between two different clock phase relationships between the clock and data. The following figure shows the clock formats when CPHA = 1. At the top of the figure, the eight bit times are shown for reference with bit 1 starting at the first SPSCK edge and bit 8 ending one-half SPSCK cycle after the eighth SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 589 Functional Description BIT TIME # (REFERENCE) 1 2 ... 6 8 7 SPSCK (CPOL = 0) SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST LSB FIRST BIT 7 BIT 0 BIT 6 BIT 1 ... ... BIT 2 BIT 5 BIT 1 BIT 6 BIT 0 BIT 7 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure 35-17. SPI Clock Formats (CPHA = 1) When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low, but the data is not defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled, and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When CPHA = 1, the slave's SS input is not required to go to its inactive high level between transfers. In this clock format, a back-to-back transmission can occur, as follows: 1. A transmission is in progress. 2. A new data byte is written to the transmit buffer before the in-progress transmission is complete. 3. When the in-progress transmission is complete, the new, ready data byte is transmitted immediately. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 590 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) Between these two successive transmissions, no pause is inserted; the SS pin remains low. The following figure shows the clock formats when CPHA = 0. At the top of the figure, the eight bit times are shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low at the start of the first bit time of the transfer and goes back high one-half SPSCK cycle after the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ... 6 7 8 SPSCK (CPOL = 0) SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) BIT 7 BIT 0 MSB FIRST LSB FIRST BIT 6 BIT 1 ... ... BIT 2 BIT 5 BIT 1 BIT 6 BIT 0 BIT 7 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure 35-18. SPI Clock Formats (CPHA = 0) KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 591 Functional Description When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When CPHA = 0, the slave's SS input must go to its inactive high level between transfers. 35.4.6 SPI Baud Rate Generation As shown in the following figure, the clock source for the SPI baud rate generator is the bus clock. The three prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate select bits (SPR3:SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, 256, or 512 to get the internal SPI master mode bit-rate clock. The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current. The baud rate divisor equation is as follows (except those reserved combinations in the SPI Baud Rate Divisor table). BaudRateDivisor = (SPPR + 1) x 2(SPR + 1) The baud rate can be calculated with the following equation: BaudRate = BusClock / BaudRateDivisor BUS CLOCK PRESCALER BAUD RATE DIVIDER DIVIDE BY 1, 2, 3, 4, 5, 6, 7, or 8 DIVIDE BY 2, 4, 8, 16, 32, 64, 128, 256, or 512 SPPR2:SPPR1:SPPR0 SPR3:SPR2:SPR1:SPR0 MASTER SPI BIT RATE Figure 35-19. SPI Baud Rate Generation 35.4.7 Special Features The following section shows the module special features. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 592 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) 35.4.7.1 SS Output The SS output feature automatically drives the SS pin low during transmission to select external devices and drives the SS pin high during idle to deselect external devices. When the SS output is selected, the SS output pin is connected to the SS input pin of the external device. The SS output is available only in master mode during normal SPI operation by asserting the SSOE and MODFEN bits as shown in the description of the C1[SSOE] bit. The mode fault feature is disabled while SS output is enabled. Note Be careful when using the SS output feature in a multimaster system because the mode fault feature is not available for detecting system errors between masters. 35.4.7.2 Bidirectional Mode (MOMI or SISO) The bidirectional mode is selected when the SPC0 bit is set in SPI Control Register 2 (see the following table). In this mode, the SPI uses only one serial data pin for the interface with one or more external devices. The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI. Table 35-15. Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Serial Out Normal Mode Slave Mode MSTR = 0 MOSI SPI SPC0 = 0 Bidirectional Mode SPC0 = 1 SPI Serial In MISO Serial Out Serial Out MOMI Serial In SPI Serial In MOSI Serial In BIDIROE SPI MISO BIDIROE Serial Out SISO The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register. The SPSCK is an output for the master mode and an input for the slave mode. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 593 Functional Description SS is the input or output for the master mode, and it is always the input for the slave mode. The bidirectional mode does not affect SPSCK and SS functions. Note In bidirectional master mode, with the mode fault feature enabled, both data pins MISO and MOSI can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode and MISO is not used by the SPI. If a mode fault occurs, the SPI is automatically switched to slave mode. In this case, MISO becomes occupied by the SPI and MOSI is not used. Consider this scenario if the MISO pin is used for another purpose. 35.4.8 Error Conditions The SPI module has one error condition: the mode fault error. 35.4.8.1 Mode Fault Error If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SPSCK lines simultaneously. This condition is not permitted in normal operation, and it sets the MODF bit in the SPI status register automatically provided that the MODFEN bit is set. In the special case where the SPI is in master mode and the MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. If the SPI system is configured as a slave, the SS pin is a dedicated input pin. A mode fault error does not occur in slave mode. If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So the SPSCK, MISO and MOSI pins are forced to be high impedance inputs to avoid any possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state. If the mode fault error occurs in the bidirectional mode for an SPI system configured in master mode, the output enable of MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for the SPI system configured in slave mode. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 594 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) The mode fault flag is cleared automatically by a read of the SPI Status Register (with MODF set) followed by a write to SPI Control Register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again. 35.4.9 Low Power Mode Options This section describes the low power mode options. 35.4.9.1 SPI in Run Mode In run mode, with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers can still be accessed, but clocks to the core of this module are disabled. 35.4.9.2 SPI in Wait Mode SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI Control Register 2. * If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode. * If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. * If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry. The transmission and reception resumes when the SPI exits wait mode. * If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SPSCK continues to be driven from the master. This keeps the slave synchronized to the master and the SPSCK. If the master transmits data while the slave is in wait mode, the slave continues to send data consistent with the operation mode at the start of wait mode (that is, if the slave is currently sending its SPIx_D to the master, it continues to send the same byte. Otherwise, if the slave is currently sending the last data received byte from the master, it continues to send each previously received data from the master byte). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 595 Functional Description Note Care must be taken when expecting data from a master while the slave is in a wait mode or a stop mode where the peripheral bus clock is stopped but internal logic states are retained. Even though the shift register continues to operate, the rest of the SPI is shut down (that is, an SPRF interrupt is not generated until an exit from stop or wait mode). Also, the data from the shift register is not copied into the SPIx_D registers until after the slave SPI has exited wait or stop mode. An SPRF flag and SPIx_D copy is only generated if wait mode is entered or exited during a transmission. If the slave enters wait mode in idle mode and exits wait mode in idle mode, neither an SPRF nor a SPIx_D copy occurs. 35.4.9.3 SPI in Stop Mode Operation in a stop mode where the peripheral bus clock is stopped but internal logic states are retained depends on the SPI system. The stop mode does not depend on the SPISWAI bit. Upon entry to this type of stop mode, the SPI module clock is disabled (held high or low). * If the SPI is in master mode and exchanging data when the CPU enters the stop mode, the transmission is frozen until the CPU exits stop mode. After the exit from stop mode, data to and from the external SPI is exchanged correctly. * In slave mode, the SPI remains synchronized with the master. The SPI is completely disabled in a stop mode where the peripheral bus clock is stopped and internal logic states are not retained. After an exit from this type of stop mode, all registers are reset to their default values, and the SPI module must be re-initialized. 35.4.10 Reset The reset values of registers and signals are described in the Memory Map and Register Descriptions content, which details the registers and their bitfields. * If a data transmission occurs in slave mode after a reset without a write to SPIx_D, the transmission consists of "garbage" or the data last received from the master before the reset. * Reading from SPIx_D after reset always returns zeros. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 596 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) 35.4.11 Interrupts The SPI originates interrupt requests only when the SPI is enabled (the SPE bit in the SPIx_C1 register is set). The following is a description of how the SPI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent. Four flag bits, three interrupt mask bits, and one interrupt vector are associated with the SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF). The SPI match interrupt enable mask bit (SPIMIE) enables interrupts from the SPI match flag (SPMF). When one of the flag bits is set, and the associated interrupt mask bit is set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can poll the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should check the flag bits to determine which event caused the interrupt. The service routine should also clear the flag bit(s) before returning from the ISR (usually near the beginning of the ISR). 35.4.11.1 MODF MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see the description of the C1[SSOE] bit). Once MODF is set, the current transfer is aborted and the master (MSTR) bit in the SPIx_C1 register resets to 0. The MODF interrupt is reflected in the status register's MODF flag. Clearing the flag also clears the interrupt. This interrupt stays active while the MODF flag is set. MODF has an automatic clearing process that is described in the SPI Status Register. 35.4.11.2 SPRF SPRF occurs when new data has been received and copied to the SPI receive data buffer. After SPRF is set, it does not clear until it is serviced. SPRF has an automatic clearing process that is described in the SPI Status Register details. If the SPRF is not serviced before the end of the next transfer (that is, SPRF remains active throughout another transfer), the subsequent transfers are ignored and no new data is copied into the Data register. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 597 Initialization/Application Information 35.4.11.3 SPTEF SPTEF occurs when the SPI transmit buffer is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process that is described in the SPI Status Register details. 35.4.11.4 SPMF SPMF occurs when the data in the receive data buffer is equal to the data in the SPI match register. 35.4.11.5 Asynchronous interrupt in low power modes When the CPU is in wait mode or stop mode and the SPI module receives a transmission, the SPI module can generate an asynchronous interrupt to wake the CPU from the low power mode. The module generates the asynchronous interrupt only when all of the following conditions apply: 1. The C1[SPIE] bit is set to 1. 2. The CPU is in wait mode--in which case the C2[SPISWAI] bit must be 1--or in stop mode where the peripheral bus clock is stopped but internal logic states are retained. 3. The SPI module is in slave mode. 4. The received transmission ends. After the interrupt wakes the CPU and the peripheral bus clock is active again, the SPI module copies the received data from the shifter into the Data register and generates flags or DMA request signals. During the wakeup phase, a continuous transmission from a master would destroy the first received data. 35.5 Initialization/Application Information This section discusses an example of how to initialize and use the SPI. 35.5.1 Initialization Sequence Before the SPI module can be used for communication, an initialization procedure must be carried out, as follows: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 598 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) 1. Update control register 1 (SPIx_C1) to enable the SPI and to control interrupt enables. This register also sets the SPI as master or slave, determines clock phase and polarity, and configures the main SPI options. 2. Update control register 2 (SPIx_C2) to enable additional SPI functions such as the SPI match interrupt feature, the master mode-fault function, and bidirectional mode output as well as to control and other optional features. 3. Update the baud rate register (SPIx_BR) to set the prescaler and bit rate divisor for an SPI master. 4. Update the hardware match register (SPIx_M) with the value to be compared to the receive data register for triggering an interrupt if hardware match interrupts are enabled. 5. In the master, read SPIx_S while SPTEF = 1, and then write to the transmit data register (SPIx_D) to begin transfer. 35.5.2 Pseudo-Code Example In this example, the SPI module is set up for master mode with only hardware match interrupts enabled. The SPI runs at a maximum baud rate of bus clock divided by 2. Clock phase and polarity are set for an active-high SPI clock where the first edge on SPSCK occurs at the start of the first cycle of a data transfer. SPIx_C1=0x54(%01010100) Bit 7 SPIE = 0 Disables receive and mode fault interrupts Bit 6 SPE = 1 Enables the SPI system Bit 5 SPTIE = 0 Disables SPI transmit interrupts Bit 4 MSTR = 1 Sets the SPI module as a master SPI device Bit 3 CPOL = 0 Configures SPI clock as active-high Bit 2 CPHA = 1 First edge on SPSCK at start of first data transfer cycle Bit 1 SSOE = 0 Determines SS pin function when mode fault enabled Bit 0 LSBFE = 0 SPI serial data transfers start with most significant bit SPMIE = 1 SPI hardware match interrupt enabled = 0 Unimplemented SPIx_C2 = 0x80(%10000000) Bit 7 Bit 6 Bit 5 TXDMAE = 0 DMA request disabled Bit 4 MODFEN = 0 Disables mode fault function Bit 3 BIDIROE = 0 SPI data I/O pin acts as input Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 599 Initialization/Application Information SPIx_C2 = 0x80(%10000000) Bit 2 RXDMAE = 0 DMA request disabled Bit 1 SPISWAI = 0 SPI clocks operate in wait mode Bit 0 SPC0 = 0 uses separate pins for data input and output Bit 7 = 0 Reserved Bit 6:4 = 000 Sets prescale divisor to 1 Bit 3:0 = 0000 Sets baud rate divisor to 2 SPIx_BR = 0x00(%00000000) SPIx_S = 0x00(%00000000) Bit 7 SPRF = 0 Flag is set when receive data buffer is full Bit 6 SPMF = 0 Flag is set when SPIx_M = receive data buffer Bit 5 SPTEF = 0 Flag is set when transmit data buffer is empty Bit 4 MODF = 0 Mode fault flag for master mode = 0 Reserved Bit 3:0 SPIx_M = 0xXX Holds bits 0-7 of the hardware match buffer. SPIx_D = 0xxx Holds bits 0-7 of the data to be transmitted by the transmit buffer and received by the receive buffer. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 600 Freescale Semiconductor, Inc. Chapter 35 Serial Peripheral Interface (SPI) RESET INITIALIZE SPI SPIxC1 = 0x54 SPIxC2 = 0x80 SPIxBR = 0x00 YES SPTEF = 1 ? NO YES WRITE TO SPIxD SPRF = 1 ? NO YES READ SPIxD SPMF = 1 ? NO YES READ SPMF WHILE SET TO CLEAR FLAG, THEN WRITE A 1 TO IT CONTINUE Figure 35-20. Initialization Flowchart Example for SPI Master Device KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 601 Initialization/Application Information KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 602 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) 36.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The inter-integrated circuit (I2C, I2C, or IIC) module provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbit/s with maximum bus loading and timing. The I2C device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF. The I2C module also complies with the System Management Bus (SMBus) Specification, version 2. 36.1.1 Features The I2C module has the following features: * * * * * * * * * * * * Compatible with The I2C-Bus Specification Multimaster operation Software programmable for one of 64 different serial clock frequencies Software-selectable acknowledge bit Interrupt-driven byte-by-byte data transfer Arbitration-lost interrupt with automatic mode switching from master to slave Calling address identification interrupt START and STOP signal generation and detection Repeated START signal generation and detection Acknowledge bit generation and detection Bus busy detection General call recognition KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 603 Introduction * * * * * * 10-bit address extension Support for System Management Bus (SMBus) Specification, version 2 Programmable glitch input filter Low power mode wakeup on slave address match Range slave address support DMA support 36.1.2 Modes of operation The I2C module's operation in various low power modes is as follows: * Run mode: This is the basic mode of operation. To conserve power in this mode, disable the module. * Wait mode: The module continues to operate when the core is in Wait mode and can provide a wakeup interrupt. * Stop mode: The module is inactive in Stop mode for reduced power consumption, except that address matching is enabled in Stop mode. The STOP instruction does not affect the I2C module's register states. 36.1.3 Block diagram The following figure is a functional block diagram of the I2C module. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 604 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) Address Module Enable Write/Read Interrupt ADDR_DECODE DATA_MUX CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync START STOP Arbitration Control Clock Control In/Out Data Shift Register Address Compare SDA SCL Figure 36-1. I2C Functional block diagram 36.2 I2C signal descriptions The signal properties of I2C are shown in the following table. Table 36-1. I2C signal descriptions Signal SCL SDA Description I/O Bidirectional serial clock line of the Bidirectional serial data line of the I2C I2C system. system. I/O I/O 36.3 Memory map and register descriptions This section describes in detail all I2C registers accessible to the end user. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 605 Memory map and register descriptions I2C memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4006_6000 I2C Address Register 1 (I2C0_A1) 8 R/W 00h 36.3.1/606 4006_6001 I2C Frequency Divider register (I2C0_F) 8 R/W 00h 36.3.2/607 4006_6002 I2C Control Register 1 (I2C0_C1) 8 R/W 00h 36.3.3/608 4006_6003 I2C Status register (I2C0_S) 8 R/W 80h 36.3.4/609 4006_6004 I2C Data I/O register (I2C0_D) 8 R/W 00h 36.3.5/611 4006_6005 I2C Control Register 2 (I2C0_C2) 8 R/W 00h 36.3.6/612 4006_6006 I2C Programmable Input Glitch Filter register (I2C0_FLT) 8 R/W 00h 36.3.7/613 4006_6007 I2C Range Address register (I2C0_RA) 8 R/W 00h 36.3.8/614 4006_6008 I2C SMBus Control and Status register (I2C0_SMB) 8 R/W 00h 36.3.9/615 4006_6009 I2C Address Register 2 (I2C0_A2) 8 R/W C2h 36.3.10/ 616 4006_600A I2C SCL Low Timeout Register High (I2C0_SLTH) 8 R/W 00h 36.3.11/ 617 4006_600B I2C SCL Low Timeout Register Low (I2C0_SLTL) 8 R/W 00h 36.3.12/ 617 36.3.1 I2C Address Register 1 (I2Cx_A1) This register contains the slave address to be used by the I2C module. Address: 4006_6000h base + 0h offset = 4006_6000h Bit Read Write Reset 7 6 5 4 3 2 1 AD[7:1] 0 0 0 0 0 0 0 0 0 0 I2Cx_A1 field descriptions Field 7-1 AD[7:1] 0 Reserved Description Address Contains the primary slave address used by the I2C module when it is addressed as a slave. This field is used in the 7-bit address scheme and the lower seven bits in the 10-bit address scheme. This field is reserved. This read-only field is reserved and always has the value 0. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 606 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) 36.3.2 I2C Frequency Divider register (I2Cx_F) Address: 4006_6000h base + 1h offset = 4006_6001h Bit Read Write Reset 7 6 5 4 3 MULT 0 2 1 0 0 0 0 ICR 0 0 0 0 I2Cx_F field descriptions Field 7-6 MULT Description The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to generate the I2C baud rate. 00 01 10 11 5-0 ICR mul = 1 mul = 2 mul = 4 Reserved ClockRate Prescales the bus clock for bit rate selection. This field and the MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold time, and the SCL stop hold time. For a list of values corresponding to each ICR setting, see I2C divider and hold values. The SCL divider multiplied by multiplier factor (mul) determines the I2C baud rate. I2C baud rate = bus speed (Hz)/(mul x SCL divider) The SDA hold time is the delay from the falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time = bus period (s) x mul x SDA hold value The SCL start hold time is the delay from the falling edge of SDA (I2C data) while SCL is high (start condition) to the falling edge of SCL (I2C clock). SCL start hold time = bus period (s) x mul x SCL start hold value The SCL stop hold time is the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C data) while SCL is high (stop condition). SCL stop hold time = bus period (s) x mul x SCL stop hold value For example, if the bus speed is 8 MHz, the following table shows the possible hold time values with different ICR and MULT selections to achieve an I2C baud rate of 100 kbps. MULT ICR 2h Hold times (s) SDA SCL Start SCL Stop 00h 3.500 3.000 5.500 1h 07h 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h 1.125 4.750 5.125 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 607 Memory map and register descriptions 36.3.3 I2C Control Register 1 (I2Cx_C1) Address: 4006_6000h base + 2h offset = 4006_6002h Bit Read Write Reset 7 6 5 4 3 IICEN IICIE MST TX TXAK 0 0 0 0 0 2 0 RSTA 0 1 0 WUEN DMAEN 0 0 I2Cx_C1 field descriptions Field 7 IICEN Description I2C Enable Enables I2C module operation. 0 1 6 IICIE I2C Interrupt Enable Enables I2C interrupt requests. 0 1 5 MST When the MST bit is changed from a 0 to a 1, a START signal is generated on the bus and master mode is selected. When this bit changes from a 1 to a 0, a STOP signal is generated and the mode of operation changes from master to slave. Slave mode Master mode Transmit Mode Select Selects the direction of master and slave transfers. In master mode this bit must be set according to the type of transfer required. Therefore, for address cycles, this bit is always set. When addressed as a slave this bit must be set by software according to the SRW bit in the status register. 0 1 3 TXAK Disabled Enabled Master Mode Select 0 1 4 TX Disabled Enabled Receive Transmit Transmit Acknowledge Enable Specifies the value driven onto the SDA during data acknowledge cycles for both master and slave receivers. The value of the FACK bit affects NACK/ACK generation. NOTE: SCL is held low until TXAK is written. 0 1 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 608 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) I2Cx_C1 field descriptions (continued) Field Description 2 RSTA Repeat START 1 WUEN Wakeup Enable Writing a one to this bit generates a repeated START condition provided it is the current master. This bit will always be read as zero. Attempting a repeat at the wrong time results in loss of arbitration. The I2C module can wake the MCU from low power mode with no peripheral bus running when slave address matching occurs. 0 1 0 DMAEN Normal operation. No interrupt generated when address matching in low power mode. Enables the wakeup function in low power mode. DMA Enable The DMAEN bit enables or disables the DMA function. 0 1 All DMA signalling disabled. DMA transfer is enabled and the following conditions trigger the DMA request: * While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) * While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. 36.3.4 I2C Status register (I2Cx_S) Address: 4006_6000h base + 3h offset = 4006_6003h Bit Read 7 6 TCF IAAS Write Reset 1 0 5 4 BUSY ARBL w1c 0 0 3 RAM 0 2 1 0 SRW IICIF RXAK w1c 0 0 0 I2Cx_S field descriptions Field 7 TCF Description Transfer Complete Flag This bit sets on the completion of a byte and acknowledge bit transfer. This bit is valid only during or immediately following a transfer to or from the I2C module. The TCF bit is cleared by reading the I2C data register in receive mode or by writing to the I2C data register in transmit mode. 0 1 Transfer in progress Transfer complete Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 609 Memory map and register descriptions I2Cx_S field descriptions (continued) Field 6 IAAS Description Addressed As A Slave This bit is set by one of the following conditions: * The calling address matches the programmed slave primary address in the A1 register or range address in the RA register (which must be set to a nonzero value). * GCAEN is set and a general call is received. * SIICAEN is set and the calling address matches the second programmed slave address. * ALERTEN is set and an SMBus alert response address is received * RMEN is set and an address is received that is within the range between the values of the A1 and RA registers. This bit sets before the ACK bit. The CPU must check the SRW bit and set TX/RX accordingly. Writing the C1 register with any value clears this bit. 0 1 5 BUSY Bus Busy Indicates the status of the bus regardless of slave or master mode. This bit is set when a START signal is detected and cleared when a STOP signal is detected. 0 1 4 ARBL Bus is idle Bus is busy Arbitration Lost This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by software, by writing a one to it. 0 1 3 RAM Not addressed Addressed as a slave Standard bus operation. Loss of arbitration. Range Address Match This bit is set to 1 by any of the following conditions: * Any nonzero calling address is received that matches the address in the RA register. * The RMEN bit is set and the calling address is within the range of values of the A1 and RA registers. NOTE: For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1. Writing the C1 register with any value clears this bit to 0. 0 1 2 SRW Slave Read/Write When addressed as a slave, SRW indicates the value of the R/W command bit of the calling address sent to the master. 0 1 1 IICIF Not addressed Addressed as a slave Slave receive, master writing to slave Slave transmit, master reading from slave Interrupt Flag This bit sets when an interrupt is pending. This bit must be cleared by software by writing a 1 to it, such as in the interrupt routine. One of the following events can set this bit: Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 610 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) I2Cx_S field descriptions (continued) Field Description * One byte transfer, including ACK/NACK bit, completes if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK after this bit is set in receive mode. * One byte transfer, excluding ACK/NACK bit, completes if FACK is 1. * Match of slave address to calling address including primary slave address, range slave address, alert response address, second slave address, or general call address. * Arbitration lost * In SMBus mode, any timeouts except SCL and SDA high timeouts * I2C bus stop detection if the STOPIE bit in the Input Glitch Filter register is 1 NOTE: 0 1 0 RXAK To clear the I2C bus stop detection interrupt: In the interrupt service routine, first clear the STOPF bit in the Input Glitch Filter register by writing 1 to it, and then clear the IICIF bit. If this sequence is reversed, the IICIF bit is asserted again. No interrupt pending Interrupt pending Receive Acknowledge 0 1 Acknowledge signal was received after the completion of one byte of data transmission on the bus No acknowledge signal detected 36.3.5 I2C Data I/O register (I2Cx_D) Address: 4006_6000h base + 4h offset = 4006_6004h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 DATA 0 0 0 0 I2Cx_D field descriptions Field 7-0 DATA Description Data In master transmit mode, when data is written to this register, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data. NOTE: When making the transition out of master receive mode, switch the I2C mode before reading the Data register to prevent an inadvertent initiation of a master receive data transfer. In slave mode, the same functions are available after an address match occurs. The C1[TX] bit must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. For example, if the I2C module is configured for master transmit but a master receive is desired, reading the Data register does not initiate the receive. Reading the Data register returns the last byte received while the I2C module is configured in master receive or slave receive mode. The Data register does not reflect every byte that is transmitted on the I2C bus, and neither can software verify that a byte has been written to the Data register correctly by reading it back. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 611 Memory map and register descriptions I2Cx_D field descriptions (continued) Field Description In master transmit mode, the first byte of data written to the Data register following assertion of MST (start bit) or assertion of RSTA (repeated start bit) is used for the address transfer and must consist of the calling address (in bits 7-1) concatenated with the required R/W bit (in position bit 0). 36.3.6 I2C Control Register 2 (I2Cx_C2) Address: 4006_6000h base + 5h offset = 4006_6005h Bit Read Write Reset 7 6 5 4 3 GCAEN ADEXT HDRS SBRC RMEN 0 0 0 0 0 2 1 0 AD[10:8] 0 0 0 I2Cx_C2 field descriptions Field 7 GCAEN Description General Call Address Enable Enables general call address. 0 1 6 ADEXT Address Extension Controls the number of bits used for the slave address. 0 1 5 HDRS Controls the drive capability of the I2C pads. Normal drive mode High drive mode Slave Baud Rate Control Enables independent slave mode baud rate at maximum frequency, which forces clock stretching on SCL in very fast I2C modes. To a slave, an example of a "very fast" mode is when the master transfers at 40 kbps but the slave can capture the master's data at only 10 kbps. 0 1 3 RMEN 7-bit address scheme 10-bit address scheme High Drive Select 0 1 4 SBRC Disabled Enabled The slave baud rate follows the master baud rate and clock stretching may occur Slave baud rate is independent of the master baud rate Range Address Matching Enable This bit controls slave address matching for addresses between the values of the A1 and RA registers. When this bit is set, a slave address match occurs for any address greater than the value of the A1 register and less than or equal to the value of the RA register. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 612 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) I2Cx_C2 field descriptions (continued) Field Description 0 1 2-0 AD[10:8] Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers. Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. Slave Address Contains the upper three bits of the slave address in the 10-bit address scheme. This field is valid only while the ADEXT bit is set. 36.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT) Address: 4006_6000h base + 6h offset = 4006_6006h Bit Read Write Reset 7 6 5 STOPF SHEN 3 STOPIE w1c 0 4 0 0 2 1 0 0 0 FLT 0 0 0 I2Cx_FLT field descriptions Field 7 SHEN Description Stop Hold Enable Set this bit to hold off entry to stop mode when any data transmission or reception is occurring. The following scenario explains the holdoff functionality: 1. The I2C module is configured for a basic transfer, and the SHEN bit is set to 1. 2. A transfer begins. 3. The MCU signals the I2C module to enter stop mode. 4. The byte currently being transferred, including both address and data, completes its transfer. 5. The I2C slave or master acknowledges that the in-transfer byte completed its transfer and acknowledges the request to enter stop mode. 6. After receiving the I2C module's acknowledgment of the request to enter stop mode, the MCU determines whether to shut off the I2C module's clock. If the SHEN bit is set to 1 and the I2C module is in an idle or disabled state when the MCU signals to enter stop mode, the module immediately acknowledges the request to enter stop mode. If SHEN is cleared to 0 and the overall data transmission or reception that was suspended by stop mode entry was incomplete: To resume the overall transmission or reception after the MCU exits stop mode, software must reinitialize the transfer by resending the address of the slave. If the I2C Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode, system software will receive the interrupt triggered by the I2C Status Register's TCF bit after the MCU wakes from the stop mode. 0 1 6 STOPF Stop holdoff is disabled. The MCU's entry to stop mode is not gated. Stop holdoff is enabled. I2C Bus Stop Detect Flag Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 613 Memory map and register descriptions I2Cx_FLT field descriptions (continued) Field Description Hardware sets this bit when the I2C bus's stop status is detected. The STOPF bit must be cleared by writing 1 to it. 0 1 5 STOPIE No stop happens on I2C bus Stop detected on I2C bus I2C Bus Stop Interrupt Enable This bit enables the interrupt for I2C bus stop detection. NOTE: To clear the I2C bus stop detection interrupt: In the interrupt service routine, first clear the STOPF bit by writing 1 to it, and then clear the IICIF bit in the status register. If this sequence is reversed, the IICIF bit is asserted again. 0 1 4-0 FLT Stop detection interrupt is disabled Stop detection interrupt is enabled I2C Programmable Filter Factor Controls the width of the glitch, in terms of bus clock cycles, that the filter must absorb. For any glitch whose size is less than or equal to this width setting, the filter does not allow the glitch to pass. 00h 01-1Fh No filter/bypass Filter glitches up to width of n bus clock cycles, where n=1-31d 36.3.8 I2C Range Address register (I2Cx_RA) Address: 4006_6000h base + 7h offset = 4006_6007h Bit Read Write Reset 7 6 5 4 3 2 1 0 RAD 0 0 0 0 0 0 0 0 0 I2Cx_RA field descriptions Field 7-1 RAD 0 Reserved Description Range Slave Address This field contains the slave address to be used by the I2C module. The field is used in the 7-bit address scheme. Any nonzero write enables this register. This register's use is similar to that of the A1 register, but in addition this register can be considered a maximum boundary in range matching mode. This field is reserved. This read-only field is reserved and always has the value 0. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 614 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) 36.3.9 I2C SMBus Control and Status register (I2Cx_SMB) NOTE When the SCL and SDA signals are held high for a length of time greater than the high timeout period, the SHTF1 flag sets. Before reaching this threshold, while the system is detecting how long these signals are being held high, a master assumes that the bus is free. However, the SHTF1 bit rises in the bus transmission process with the idle bus state. NOTE When the TCKSEL bit is set, there is no need to monitor the SHTF1 bit because the bus speed is too high to match the protocol of SMBus. Address: 4006_6000h base + 8h offset = 4006_6008h Bit Read Write Reset 7 6 5 4 FACK ALERTEN SIICAEN TCKSEL 0 0 0 0 3 2 1 SLTF SHTF1 SHTF2 w1c 0 w1c 0 0 0 SHTF2IE 0 I2Cx_SMB field descriptions Field 7 FACK Description Fast NACK/ACK Enable For SMBus packet error checking, the CPU must be able to issue an ACK or NACK according to the result of receiving data byte. 0 1 6 ALERTEN An ACK or NACK is sent on the following receiving data byte Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. SMBus Alert Response Address Enable Enables or disables SMBus alert response address matching. NOTE: After the host responds to a device that used the alert response address, you must use software to put the device's address on the bus. The alert protocol is described in the SMBus specification. 0 1 5 SIICAEN SMBus alert response address matching is disabled SMBus alert response address matching is enabled Second I2C Address Enable Enables or disables SMBus device default address. 0 1 I2C address register 2 matching is disabled I2C address register 2 matching is enabled Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 615 Memory map and register descriptions I2Cx_SMB field descriptions (continued) Field 4 TCKSEL Description Timeout Counter Clock Select Selects the clock source of the timeout counter. 0 1 3 SLTF Timeout counter counts at the frequency of the bus clock / 64 Timeout counter counts at the frequency of the bus clock SCL Low Timeout Flag This bit is set when the SLT register (consisting of the SLTH and SLTL registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs. Software clears this bit by writing a logic 1 to it. NOTE: The low timeout function is disabled when the SLT register's value is zero. 0 1 2 SHTF1 SCL High Timeout Flag 1 This read-only bit sets when SCL and SDA are held high more than clock x LoValue / 512, which indicates the bus is free. This bit is cleared automatically. 0 1 1 SHTF2 No SCL high and SDA high timeout occurs SCL high and SDA high timeout occurs SCL High Timeout Flag 2 This bit sets when SCL is held high and SDA is held low more than clock x LoValue/512. Software clears this bit by writing a 1 to it. 0 1 0 SHTF2IE No low timeout occurs Low timeout occurs No SCL high and SDA low timeout occurs SCL high and SDA low timeout occurs SHTF2 Interrupt Enable Enables SCL high and SDA low timeout interrupt. 0 1 SHTF2 interrupt is disabled SHTF2 interrupt is enabled 36.3.10 I2C Address Register 2 (I2Cx_A2) Address: 4006_6000h base + 9h offset = 4006_6009h Bit Read Write Reset 7 6 5 4 3 2 1 0 SAD 1 1 0 0 0 0 0 1 0 I2Cx_A2 field descriptions Field 7-1 SAD Description SMBus Address Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 616 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) I2Cx_A2 field descriptions (continued) Field Description Contains the slave address used by the SMBus. This field is used on the device default address or other related addresses. 0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 36.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH) Address: 4006_6000h base + Ah offset = 4006_600Ah Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 SSLT[15:8] 0 0 0 0 I2Cx_SLTH field descriptions Field 7-0 SSLT[15:8] Description Most significant byte of SCL low timeout value that determines the timeout period of SCL low. 36.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL) Address: 4006_6000h base + Bh offset = 4006_600Bh Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 SSLT[7:0] 0 0 0 0 I2Cx_SLTL field descriptions Field 7-0 SSLT[7:0] Description Least significant byte of SCL low timeout value that determines the timeout period of SCL low. 36.4 Functional description This section provides a comprehensive functional description of the I2C module. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 617 Functional description 36.4.1 I2C protocol The I2C bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfers. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors depends on the system. Normally, a standard instance of communication is composed of four parts: 1. 2. 3. 4. START signal Slave address transmission Data transfer STOP signal The STOP signal should not be confused with the CPU STOP instruction. The following figure illustrates I2C bus system communication. M SB SCL SDA 1 SDA Start Signal 3 4 5 6 7 8 9 A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 R /W C a llin g A d d re s s Start Signal SCL M SB LSB 2 3 4 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 D a ta B y te 5 6 7 8 A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 R /W C a llin g A d d re s s 1 9 R e a d / Ack W rite Bit XX 9 No Stop Ack Signal Bit M SB LSB 2 2 R e a d / Ack W rite Bit M SB 1 XXX LSB 1 LSB 2 3 4 5 6 7 8 9 A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 R /W Repeated Start Signal N e w C a llin g A d d re s s Read/ W rite No Stop Ack Signal Bit Figure 36-26. I2C bus transmission signals 36.4.1.1 START signal The bus is free when no master device is engaging the bus (both SCL and SDA are high). When the bus is free, a master may initiate communication by sending a START signal. A START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer--each data transfer might contain several bytes of data--and brings all slaves out of their idle states. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 618 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) 36.4.1.2 Slave address transmission Immediately after the START signal, the first byte of a data transfer is the slave address transmitted by the master. This address is a 7-bit calling address followed by an R/W bit. The R/W bit tells the slave the desired direction of data transfer. * 1 = Read transfer: The slave transmits data to the master * 0 = Write transfer: The master transmits data to the slave Only the slave with a calling address that matches the one transmitted by the master responds by sending an acknowledge bit. The slave sends the acknowledge bit by pulling SDA low at the ninth clock. No two slaves in the system can have the same address. If the I2C module is the master, it must not transmit an address that is equal to its own slave address. The I2C module cannot be master and slave at the same time. However, if arbitration is lost during an address cycle, the I2C module reverts to slave mode and operates correctly even if it is being addressed by another master. 36.4.1.3 Data transfers When successful slave addressing is achieved, data transfer can proceed on a byte-bybyte basis in the direction specified by the R/W bit sent by the calling master. All transfers that follow an address cycle are referred to as data transfers, even if they carry subaddress information for the slave device. Each data byte is 8 bits long. Data may be changed only while SCL is low. Data must be held stable while SCL is high. There is one clock pulse on SCL for each data bit, and the MSB is transferred first. Each data byte is followed by a ninth (acknowledge) bit, which is signaled from the receiving device by pulling SDA low at the ninth clock. In summary, one complete data transfer needs nine clock pulses. If the slave receiver does not acknowledge the master in the ninth bit, the slave must leave SDA high. The master interprets the failed acknowledgement as an unsuccessful data transfer. If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets it as an end to data transfer and releases the SDA line. In the case of a failed acknowledgement by either the slave or master, the data transfer is aborted and the master does one of two things: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 619 Functional description * Relinquishes the bus by generating a STOP signal. * Commences a new call by generating a repeated START signal. 36.4.1.4 STOP signal The master can terminate the communication by generating a STOP signal to free the bus. A STOP signal is defined as a low-to-high transition of SDA while SCL is asserted. The master can generate a STOP signal even if the slave has generated an acknowledgement, at which point the slave must release the bus. 36.4.1.5 Repeated START signal The master may generate a START signal followed by a calling command without generating a STOP signal first. This action is called a repeated START. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. 36.4.1.6 Arbitration procedure The I2C bus is a true multimaster bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock. The bus clock's low period is equal to the longest clock low period, and the high period is equal to the shortest one among the masters. The relative priority of the contending masters is determined by a data arbitration procedure. A bus master loses arbitration if it transmits logic level 1 while another master transmits logic level 0. The losing masters immediately switch to slave receive mode and stop driving SDA output. In this case, the transition from master to slave mode does not generate a STOP condition. Meanwhile, hardware sets a status bit to indicate the loss of arbitration. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 620 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) 36.4.1.7 Clock synchronization Because wire AND logic is performed on SCL, a high-to-low transition on SCL affects all devices connected on the bus. The devices start counting their low period and, after a device's clock has gone low, that device holds SCL low until the clock reaches its high state. However, the change of low to high in this device clock might not change the state of SCL if another device clock is still within its low period. Therefore, the synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time; see the following diagram. When all applicable devices have counted off their low period, the synchronized clock SCL is released and pulled high. Afterward there is no difference between the device clocks and the state of SCL, and all devices start counting their high periods. The first device to complete its high period pulls SCL low again. D e la y S ta rt C o u n tin g H ig h P e rio d SCL1 SCL2 SCL In te rn a l C o u n te r R e s e t Figure 36-27. I2C clock synchronization 36.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfers. A slave device may hold SCL low after completing a single byte transfer (9 bits). In this case, it halts the bus clock and forces the master clock into wait states until the slave releases SCL. 36.4.1.9 Clock stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master drives SCL low, a slave can drive SCL low for the required period and then release it. If the slave's SCL low period is greater than the master's SCL KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 621 Functional description low period, the resulting SCL bus signal's low period is stretched. In other words, the SCL bus signal's low period is increased to be the same length as the slave's SCL low period. 36.4.1.10 I2C divider and hold values NOTE For some cases on some devices, the SCL divider value may vary by +/-2 or +/-4 when ICR's value ranges from 00h to 0Fh. These potentially varying SCL divider values are highlighted in the following table. For the actual SCL divider values for your device, see the chip-specific details about the I2C module. Table 36-28. I2C divider and hold values ICR SCL divider SDA hold value SCL hold (start) value SCL hold (stop) value SCL divider (clocks) SDA hold (clocks) SCL hold (start) value SCL hold (stop) value 00 20 7 6 11 20 160 17 78 81 01 22 7 7 12 21 192 17 94 97 02 24 8 8 13 22 224 33 110 113 03 26 8 9 14 23 256 33 126 129 04 28 9 10 15 24 288 49 142 145 05 06 30 9 11 16 25 320 49 158 161 34 10 13 18 26 384 65 190 193 07 40 10 16 21 27 480 65 238 241 08 28 7 10 15 28 320 33 158 161 09 32 7 12 17 29 384 33 190 193 0A 36 9 14 19 2A 448 65 222 225 0B 40 9 16 21 2B 512 65 254 257 0C 44 11 18 23 2C 576 97 286 289 0D 48 11 20 25 2D 640 97 318 321 0E 56 13 24 29 2E 768 129 382 385 0F 68 13 30 35 2F 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896 129 446 449 13 72 13 30 37 33 1024 129 510 513 14 80 17 34 41 34 1152 193 574 577 15 88 17 38 45 35 1280 193 638 641 16 104 21 46 53 36 1536 257 766 769 17 128 21 58 65 37 1920 257 958 961 (hex) ICR (hex) Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 622 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) Table 36-28. I2C divider and hold values (continued) ICR SCL divider SDA hold value SCL hold (start) value SCL hold (stop) value SCL divider (clocks) SDA hold (clocks) SCL hold (start) value SCL hold (stop) value 18 80 9 38 41 38 1280 129 638 641 19 96 9 46 49 39 1536 129 766 769 1A 112 17 54 57 3A 1792 257 894 897 1B 128 17 62 65 3B 2048 257 1022 1025 1C 1D 144 25 70 73 3C 2304 385 1150 1153 160 25 78 81 3D 2560 385 1278 1281 1E 192 33 94 97 3E 3072 513 1534 1537 1F 240 33 118 121 3F 3840 513 1918 1921 (hex) ICR (hex) 36.4.2 10-bit address For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. Various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 36.4.2.1 Master-transmitter addresses a slave-receiver The transfer direction is not changed. When a 10-bit address follows a START condition, each slave compares the first 7 bits of the first byte of the slave address (11110XX) with its own address and tests whether the eighth bit (R/W direction bit) is 0. It is possible that more than one device finds a match and generates an acknowledge (A1). Each slave that finds a match compares the 8 bits of the second byte of the slave address with its own address, but only one slave finds a match and generates an acknowledge (A2). The matching slave remains addressed by the master until it receives a STOP condition (P) or a repeated START condition (Sr) followed by a different slave address. Table 36-29. Master-transmitter addresses slave-receiver with a 10-bit address S Slave address first 7 bits 11110 + AD10 + AD9 R/W 0 A1 Slave address second byte AD[8:1] A2 Data A ... Data A/A P KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 623 Functional description After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an I2C interrupt. User software must ensure that for this interrupt, the contents of the Data register are ignored and not treated as valid data. 36.4.2.2 Master-receiver addresses a slave-transmitter The transfer direction is changed after the second R/W bit. Up to and including acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a slave-receiver. After the repeated START condition (Sr), a matching slave remembers that it was addressed before. This slave then checks whether the first seven bits of the first byte of the slave address following Sr are the same as they were after the START condition (S), and it tests whether the eighth (R/W) bit is 1. If there is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge A3. The slave-transmitter remains addressed until it receives a STOP condition (P) or a repeated START condition (Sr) followed by a different slave address. After a repeated START condition (Sr), all other slave devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are addressed because R/W = 1 (for 10-bit devices), or the 11110XX slave address (for 7-bit devices) does not match. Table 36-30. Master-receiver addresses a slave-transmitter with a 10-bit address S Slave address first 7 bits 11110 + AD10 + AD9 R/W 0 A1 Slave address second byte AD[8:1] A2 Sr Slave address first 7 bits 11110 + AD10 + AD9 R/W 1 A3 Data A ... Data A P After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter sees an I2C interrupt. User software must ensure that for this interrupt, the contents of the Data register are ignored and not treated as valid data. 36.4.3 Address matching All received addresses can be requested in 7-bit or 10-bit address format. * AD[7:1] in Address Register 1, which contains the I2C primary slave address, always participates in the address matching process. It provides a 7-bit address. * If the ADEXT bit is set, AD[10:8] in Control Register 2 participates in the address matching process. It extends the I2C primary slave address to a 10-bit address. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 624 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) Additional conditions that affect address matching include: * If the GCAEN bit is set, general call participates the address matching process. * If the ALERTEN bit is set, alert response participates the address matching process. * If the SIICAEN bit is set, Address Register 2 participates in the address matching process. * If the Range Address register is programmed to a nonzero value, the range address itself participates in the address matching process. * If the RMEN bit is set, any address within the range of values of Address Register 1 and the Range Address register participates in the address matching process. The Range Address register must be programmed to a value greater than the value of Address Register 1. When the I2C module responds to one of these addresses, it acts as a slave-receiver and the IAAS bit is set after the address cycle. Software must read the Data register after the first byte transfer to determine that the address is matched. 36.4.4 System management bus specification SMBus provides a control bus for system and power management related tasks. A system can use SMBus to pass messages to and from devices instead of tripping individual control lines. Removing the individual control lines reduces pin count. Accepting messages ensures future expandability. With the system management bus, a device can provide manufacturer information, tell the system what its model/part number is, save its state for a suspend event, report different types of errors, accept control parameters, and return its status. 36.4.4.1 Timeouts The TTIMEOUT,MIN parameter allows a master or slave to conclude that a defective device is holding the clock low indefinitely or a master is intentionally trying to drive devices off the bus. The slave device must release the bus (stop driving the bus and let SCL and SDA float high) when it detects any single clock held low longer than TTIMEOUT,MIN. Devices that have detected this condition must reset their communication and be able to receive a new START condition within the timeframe of TTIMEOUT,MAX. SMBus defines a clock low timeout, TTIMEOUT, of 35 ms, specifies TLOW:SEXT as the cumulative clock low extend time for a slave device, and specifies TLOW:MEXT as the cumulative clock low extend time for a master device. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 625 Functional description 36.4.4.1.1 SCL low timeout If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than a timeout value condition. Devices that have detected the timeout condition must reset the communication. When the I2C module is an active master, if it detects that SMBCLK low has exceeded the value of TTIMEOUT,MIN, it must generate a stop condition within or after the current data byte in the transfer process. When the I2C module is a slave, if it detects the TTIMEOUT,MIN condition, it resets its communication and is then able to receive a new START condition. 36.4.4.1.2 SCL high timeout When the I2C module has determined that the SMBCLK and SMBDAT signals have been high for at least THIGH:MAX, it assumes that the bus is idle. A HIGH timeout occurs after a START condition appears on the bus but before a STOP condition appears on the bus. Any master detecting this scenario can assume the bus is free when either of the following occurs: * SHTF1 rises. * The BUSY bit is high and SHTF1 is high. When the SMBDAT signal is low and the SMBCLK signal is high for a period of time, another kind of timeout occurs. The time period must be defined in software. SHTF2 is used as the flag when the time limit is reached. This flag is also an interrupt resource, so it triggers IICIF. 36.4.4.1.3 CSMBCLK TIMEOUT MEXT and CSMBCLK TIMEOUT SEXT The following figure illustrates the definition of the timeout intervals TLOW:SEXT and TLOW:MEXT. When in master mode, the I2C module must not cumulatively extend its clock cycles for a period greater than TLOW:MEXT within a byte, where each byte is defined as START-to-ACK, ACK-to-ACK, or ACK-to-STOP. When CSMBCLK TIMEOUT MEXT occurs, SMBus MEXT rises and also triggers the SLTF. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 626 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) Stop T LOW:SEXT Start T LOW:MEXT ClkAck T LOW:MEXT ClkAck T LOW:MEXT SCL SDA Figure 36-28. Timeout measurement intervals A master is allowed to abort the transaction in progress to any slave that violates the TLOW:SEXT or TTIMEOUT,MIN specifications. To abort the transaction, the master issues a STOP condition at the conclusion of the byte transfer in progress. When a slave, the I2C module must not cumulatively extend its clock cycles for a period greater than TLOW:SEXT during any message from the initial START to the STOP. When CSMBCLK TIMEOUT SEXT occurs, SEXT rises and also triggers SLTF. NOTE CSMBCLK TIMEOUT SEXT and CSMBCLK TIMEOUT MEXT are optional functions that are implemented in the second step. 36.4.4.2 FAST ACK and NACK To improve reliability and communication robustness, implementation of packet error checking (PEC) by SMBus devices is optional for SMBus devices but required for devices participating in and only during the address resolution protocol (ARP) process. The PEC is a CRC-8 error checking byte, calculated on all the message bytes. The PEC is appended to the message by the device that supplied the last data byte. If the PEC is present but not correct, a NACK is issued by the receiver. Otherwise an ACK is issued. To calculate the CRC-8 by software, this module can hold the SCL line low after receiving the eighth SCL (8th bit) if this byte is a data byte. So software can determine whether an ACK or NACK should be sent to the bus by setting or clearing the TXAK bit if the FACK (fast ACK/NACK enable) bit is enabled. SMBus requires a device always to acknowledge its own address, as a mechanism to detect the presence of a removable device (such as a battery or docking station) on the bus. In addition to indicating a slave device busy condition, SMBus uses the NACK mechanism to indicate the reception of an invalid command or invalid data. Because such a condition may occur on the last byte of the transfer, SMBus devices are required to KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 627 Functional description have the ability to generate the not acknowledge after the transfer of each byte and before the completion of the transaction. This requirement is important because SMBus does not provide any other resend signaling. This difference in the use of the NACK signaling has implications on the specific implementation of the SMBus port, especially in devices that handle critical system data such as the SMBus host and the SBS components. NOTE In the last byte of master receive slave transmit mode, the master must send a NACK to the bus, so FACK must be switched off before the last byte transmits. 36.4.5 Resets The I2C module is disabled after a reset. The I2C module cannot cause a core reset. 36.4.6 Interrupts The I2C module generates an interrupt when any of the events in the following table occur, provided that the IICIE bit is set. The interrupt is driven by the IICIF bit (of the I2C Status Register) and masked with the IICIE bit (of the I2C Control Register 1). The IICIF bit must be cleared (by software) by writing 1 to it in the interrupt routine. The SMBus timeouts interrupt is driven by SLTF and masked with the IICIE bit. The SLTF bit must be cleared by software by writing 1 to it in the interrupt routine. You can determine the interrupt type by reading the Status Register. NOTE In master receive mode, the FACK bit must be set to zero before the last byte transfer. Table 36-31. Interrupt summary Interrupt source Status Flag Local enable Complete 1-byte transfer TCF IICIF IICIE Match of received calling address IAAS IICIF IICIE Arbitration lost ARBL IICIF IICIE STOPF IICIF IICIE & STOPIE SMBus SCL low timeout SLTF IICIF IICIE SMBus SCL high SDA low timeout SHTF2 IICIF IICIE & SHTF2IE Wakeup from stop or wait mode IAAS IICIF IICIE & WUEN I2C bus stop detection KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 628 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) 36.4.6.1 Byte transfer interrupt The Transfer Complete Flag (TCF) bit is set at the falling edge of the ninth clock to indicate the completion of a byte and acknowledgement transfer. When FACK is enabled, TCF is then set at the falling edge of eighth clock to indicate the completion of byte. 36.4.6.2 Address detect interrupt When the calling address matches the programmed slave address (I2C Address Register) or when the GCAEN bit is set and a general call is received, the IAAS bit in the Status Register is set. The CPU is interrupted, provided the IICIE bit is set. The CPU must check the SRW bit and set its Tx mode accordingly. 36.4.6.3 Stop Detect Interrupt When the stop status is detected on the I2C bus, the STOPF bit is set to 1. The CPU is interrupted, provided the IICIE and STOPIE bits are both set to 1. 36.4.6.4 Exit from low-power/stop modes The slave receive input detect circuit and address matching feature are still active on low power modes (wait and stop). An asynchronous input matching slave address or general call address brings the CPU out of low power/stop mode if the interrupt is not masked. Therefore, TCF and IAAS both can trigger this interrupt. 36.4.6.5 Arbitration lost interrupt The I2C is a true multimaster bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, the relative priority of the contending masters is determined by a data arbitration procedure. The I2C module asserts the arbitration-lost interrupt when it loses the data arbitration process and the ARBL bit in the Status Register is set. Arbitration is lost in the following circumstances: 1. SDA is sampled as low when the master drives high during an address or data transmit cycle. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 629 Functional description 2. SDA is sampled as low when the master drives high during the acknowledge bit of a data receive cycle. 3. A START cycle is attempted when the bus is busy. 4. A repeated START cycle is requested in slave mode. 5. A STOP condition is detected when the master did not request it. The ARBL bit must be cleared (by software) by writing 1 to it. 36.4.6.6 Timeout interrupt in SMBus When the IICIE bit is set, the I2C module asserts a timeout interrupt (outputs SLTF and SHTF2) upon detection of any of the mentioned timeout conditions, with one exception. The SCL high and SDA high TIMEOUT mechanism must not be used to influence the timeout interrupt output, because this timeout indicates an idle condition on the bus. SHTF1 rises when it matches the SCL high and SDA high TIMEOUT and falls automatically just to indicate the bus status. The SHTF2's timeout period is the same as that of SHTF1, which is short compared to that of SLTF, so another control bit, SHTF2IE, is added to enable or disable it. 36.4.7 Programmable input glitch filter An I2C glitch filter has been added outside legacy I2C modules but within the I2C package. This filter can absorb glitches on the I2C clock and data lines for the I2C module. The width of the glitch to absorb can be specified in terms of the number of (half) bus clock cycles. A single Programmable Input Glitch Filter control register is provided. Effectively, any down-up-down or up-down-up transition on the data line that occurs within the number of clock cycles programmed in this register is ignored by the I2C module. The programmer must specify the size of the glitch (in terms of bus clock cycles) for the filter to absorb and not pass. Noise suppress circuits SCL, SDA internal signals SCL, SDA external signals DFF DFF DFF DFF Figure 36-29. Programmable input glitch filter diagram KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 630 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) 36.4.8 Address matching wakeup When a primary, range, or general call address match occurs when the I2C module is in slave receive mode, the MCU wakes from a low power mode with no peripheral bus running. Data sent on the bus that is the same as a target device address might also wake the target MCU. After the address matching IAAS bit is set, an interrupt is sent at the end of address matching to wake the core. The IAAS bit must be cleared after the clock recovery. NOTE After the system recovers and is in Run mode, restart the I2C module if it is needed to transfer packets. The SCL line is not held low until the I2C module resets after address matching. The main purpose of this feature is to wake the MCU from a low power mode where no peripheral bus is running. When the MCU is in such a mode: addressing as a slave, slave read/write, and sending an acknowledge bit are not fully supported. To avoid I2C transfer problems resulting from this situation, firmware should prevent the MCU execution of a STOP instruction when the I2C module is in the middle of a transfer unless the Stop mode holdoff feature is used during this period (set FLT[SHEN] to 1). 36.4.9 DMA support If the DMAEN bit is cleared and the IICIE bit is set, an interrupt condition generates an interrupt request. If the DMAEN bit is set and the IICIE bit is set, an interrupt condition generates a DMA request instead. DMA requests are generated by the transfer complete flag (TCF). If the DMAEN bit is set, the only arbitration lost is to another I2C module (error), and SCL low timeouts (error) generate CPU interrupts. All other events initiate a DMA transfer. NOTE Before the last byte of master receive mode, TXAK must be set to send a NACK after the last byte's transfer. Therefore, the DMA must be disabled before the last byte's transfer. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 631 Initialization/application information NOTE In 10-bit address mode transmission, the addresses to send occupy 2-3 bytes. During this transfer period, the DMA must be disabled because the C1 register is written to send a repeat start or to change the transfer direction. 36.5 Initialization/application information Module Initialization (Slave) 1. Write: Control Register 2 * to enable or disable general call * to select 10-bit or 7-bit addressing mode 2. Write: Address Register 1 to set the slave address 3. Write: Control Register 1 to enable the I2C module and interrupts 4. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data 5. Initialize RAM variables used to achieve the routine shown in the following figure Module Initialization (Master) 1. Write: Frequency Divider register to set the I2C baud rate (see example in description of ICR) 2. Write: Control Register 1 to enable the I2C module and interrupts 3. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data 4. Initialize RAM variables used to achieve the routine shown in the following figure 5. Write: Control Register 1 to enable TX 6. Write: Control Register 1 to enable MST (master mode) 7. Write: Data register with the address of the target slave (the LSB of this byte determines whether the communication is master receive or transmit) The routine shown in the following figure encompasses both master and slave I2C operations. For slave operation, an incoming I2C message that contains the proper address begins I2C communication. For master operation, communication must be initiated by writing the Data register. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 632 Freescale Semiconductor, Inc. Chapter 36 Inter-Integrated Circuit (I2C) Clear IICIF Y Tx Master mode? N Rx Y Tx/Rx? Last byte transmitted? Y Arbitration lost? N Clear ARBL N N Last byte to be read? RXAK=0? N End of address cycle (master Rx)? Y Y (read) 2nd to last byte to be read? Write next byte to Data reg Set TXACK Address transfer see note 1 N Data transfer see note 2 Tx/Rx? Tx Y Generate stop signal (MST=0) IIAAS=1? Rx SRW=1? N (write) N N Y IIAAS=1? Y N Y Y Y Set TX mode ACK from receiver? N Write data to Data reg Switch to Rx mode Dummy read from Data reg Generate stop signal (MST=0) Read data from Data reg and store Read data from Data reg and store Transmit next byte Set Rx mode Switch to Rx mode Dummy read from Data reg Dummy read from Data reg RTI Notes: 1. If general call is enabled, check to determine if the received address is a general call address (0x00). If the received address is a general call address, the general call must be handled by user software. 2. When 10-bit addressing addresses a slave, the slave sees an interrupt following the first byte of the extended address. Ensure that for this interrupt, the contents of the Data register are ignored and not treated as a valid data transfer. Figure 36-30. Typical I2C interrupt routine KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 633 Initialization/application information Y N SLTF or SHTF2=1? N FACK=1? See typical I2C interrupt routine flow chart Y Clear IICIF Y Tx Master mode? N Rx Y Tx/Rx? Last byte transmitted? Y Last byte to be read? Y N RXAK=0? 2nd to last byte to be read? N N Y N Clear IICIF Y (read) Delay (note 2) Read data and Soft CRC Set TXAK to proper value Delay (note 2) Set TXACK=1 Clear FACK=0 Write next byte to Data reg Switch to Rx mode Generate stop signal (MST=0) Y IAAS=1? Y Delay (note 2) Read data from Data reg and soft CRC End of address cycle (master Rx)? Dummy read from Data reg N Clear ARBL N N Y Y Arbitration lost? Address transfer see note 1 SRW=1? Rx N (write) N Tx/Rx? Tx Delay (note 2) Read data from Data reg and soft CRC Generate stop signal (MST=0) IAAS=1? ACK from receiver? N Set TXAK to proper value Set TXAK to proper value Clear IICIF Delay (note 2) Delay (note 2) Read data from Data reg and soft CRC Clear IICIF Delay (note 2) Set Tx mode Set TXAK to proper value Clear IICIF Delay (note 2) Switch to Rx mode Read data from Data reg and store Write data to Data reg Read data from Data reg and store Dummy read from Data reg Y Clear IICIF Transmit next byte RTI Notes: 1. If general call or SIICAEN is enabled, check to determine if the received address is a general call address (0x00) or an SMBus device default address. In either case, they must be handled by user software. 2. In receive mode, one bit time delay may be needed before the first and second data reading. Figure 36-31. Typical I2C SMBus interrupt routine KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 634 Freescale Semiconductor, Inc. Chapter 37 Universal Asynchronous Receiver/Transmitter (UART0) 37.1 Introduction 37.1.1 Features Features of the UART module include: * Full-duplex, standard non-return-to-zero (NRZ) format * Double-buffered transmitter and receiver with separate enables * Programmable baud rates (13-bit modulo divider) * Transmit and receive baud rate can operate asynchronous to the bus clock: * Baud rate can be configured independently of the bus clock frequency * Supports operation in Stop modes * Configurable receiver buad rate oversampling ratio from 4x to 32x * Interrupt, DMA or polled operation: * Transmit data register empty and transmission complete * Receive data register full * Receive overrun, parity error, framing error, and noise error * Idle receiver detect * Active edge on receive pin * Break detect supporting LIN * Hardware parity generation and checking * Programmable 8-bit, 9-bit or 10-bit character length * Programmable 1-bit or 2-bit stop bits * Receiver wakeup by idle-line, address-mark or address match * Optional 13-bit break character generation / 11-bit break character detection * Selectable transmitter output and receiver input polarity KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 635 Introduction 37.1.2 Modes of operation 37.1.2.1 Stop mode The UART will remain functional during Stop mode, provided the asynchronous transmit and receive clock remains enabled. The UART can generate an interrupt or DMA request to cause a wakeup from Stop mode. 37.1.2.2 Wait mode The UART can be configured to Stop in Wait modes, when the DOZEEN bit is set. The transmitter and receiver will finish transmitting/receiving the current word. 37.1.2.3 Debug mode The UART remains functional in debug mode. 37.1.3 Block diagram The following figure shows the transmitter portion of the UART. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 636 Freescale Semiconductor, Inc. Chapter 37 Universal Asynchronous Receiver/Transmitter (UART0) Internal Bus (Write-Only) LOOPS ASYNCH MODULE CLOCK UART_D - Tx Buffer Loop Control Stop M Start 11-BIT Transmit Shift Register H OSR Divider 8 7 6 5 4 3 2 1 0 To Receive Data In To TxD Pin L lsb BAUD Divider RSRC SHIFT DIRECTION PT Break (All 0s) Parity Generation Preamble (All 1s) PE Shift Enable T8 Load From UARTx_D TXINV UART Controls TxD TE SBK Transmit Control TXDIR TxD Direction TO TxD Pin Logic BRK13 TDRE TIE TC Tx Interrupt Request TCIE Figure 37-1. UART transmitter block diagram The following figure shows the receiver portion of the UART. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 637 Register definition INTERNAL BUS SBR12:0 ASYNCH MODULE CLOCK RE STOP BAUDRATE GENERATOR START DATA BUFFER VARIABLE 12-BIT RECEIVE SHIFT REGISTER M M10 LBKDE MSBF RXINV RECEIVE CONTROL RAF SHIFT DIRECTION RxD LOOPS RECEIVER SOURCE CONTROL RSRC PE RxD PARITY LOGIC PT From Transmitter WAKEUP LOGIC IRQ / DMA LOGIC ACTIVE EDGE DETECT DMA Requests IRQ Requests Figure 37-2. UART receiver block diagram 37.2 Register definition The UART includes registers to control baud rate, select UART options, report UART status, and for transmit/receive data. Accesses to address outside the valid memory map will generate a bus error. UART memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_A000 UART Baud Rate Register High (UART0_BDH) 8 R/W 00h 37.2.1/639 4006_A001 UART Baud Rate Register Low (UART0_BDL) 8 R/W 04h 37.2.2/640 4006_A002 UART Control Register 1 (UART0_C1) 8 R/W 00h 37.2.3/640 4006_A003 UART Control Register 2 (UART0_C2) 8 R/W 00h 37.2.4/642 4006_A004 UART Status Register 1 (UART0_S1) 8 R/W C0h 37.2.5/643 4006_A005 UART Status Register 2 (UART0_S2) 8 R/W 00h 37.2.6/645 4006_A006 UART Control Register 3 (UART0_C3) 8 R/W 00h 37.2.7/647 4006_A007 UART Data Register (UART0_D) 8 R/W 00h 37.2.8/648 4006_A008 UART Match Address Registers 1 (UART0_MA1) 8 R/W 00h 37.2.9/649 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 638 Freescale Semiconductor, Inc. Chapter 37 Universal Asynchronous Receiver/Transmitter (UART0) UART memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 8 R/W 00h 37.2.10/ 650 4006_A00A UART Control Register 4 (UART0_C4) 8 R/W 0Fh 37.2.11/ 650 4006_A00B UART Control Register 5 (UART0_C5) 8 R/W 00h 37.2.12/ 651 4006_A009 UART Match Address Registers 2 (UART0_MA2) 37.2.1 UART Baud Rate Register High (UARTx_BDH) This register, along with UART _BDL, controls the prescale divisor for UART baud rate generation. The 13-bit baud rate setting [SBR12:SBR0] should only be updated when the transmitter and receiver are both disabled. Address: 4006_A000h base + 0h offset = 4006_A000h Bit Read Write Reset 7 6 5 LBKDIE RXEDGIE SBNS 0 0 0 4 3 2 1 0 0 0 SBR 0 0 0 UARTx_BDH field descriptions Field 7 LBKDIE 6 RXEDGIE 5 SBNS Description LIN Break Detect Interrupt Enable (for LBKDIF) 0 1 RX Input Active Edge Interrupt Enable (for RXEDGIF) 0 1 Hardware interrupts from UART _S2[RXEDGIF] disabled (use polling). Hardware interrupt requested when UART _S2[RXEDGIF] flag is 1. Stop Bit Number Select SBNS determines whether data characters are one or two stop bits. This bit should only be changed when the transmitter and receiver are both disabled. 0 1 4-0 SBR Hardware interrupts from UART _S2[LBKDIF] disabled (use polling). Hardware interrupt requested when UART _S2[LBKDIF] flag is 1. One stop bit. Two stop bit. Baud Rate Modulo Divisor. The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the baud rate generator. When BR is 1 - 8191, the baud rate equals baud clock / ((OSR+1) x BR). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 639 Register definition 37.2.2 UART Baud Rate Register Low (UARTx_BDL) This register, along with UART _BDH, control the prescale divisor for UART baud rate generation. The 13-bit baud rate setting [SBR12:SBR0] can only be updated when the transmitter and receiver are both disabled. UART _BDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled; that is, UART _C2[RE] or UART _C2[TE] bits are written to 1. Address: 4006_A000h base + 1h offset = 4006_A001h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 1 0 0 SBR 0 0 0 0 UARTx_BDL field descriptions Field 7-0 SBR Description Baud Rate Modulo Divisor These 13 bits in SBR[12:0] are referred to collectively as BR. They set the modulo divide rate for the baud rate generator. When BR is 1 - 8191, the baud rate equals baud clock/((OSR+1) x BR). 37.2.3 UART Control Register 1 (UARTx_C1) This read/write register controls various optional features of the UART system. This register should only be altered when the transmitter and receiver are both disabled. Address: 4006_A000h base + 2h offset = 4006_A002h Bit Read Write Reset 7 6 5 4 3 2 1 0 LOOPS DOZEEN RSRC M WAKE ILT PE PT 0 0 0 0 0 0 0 0 UARTx_C1 field descriptions Field 7 LOOPS Description Loop Mode Select Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS is set, the transmitter output is internally connected to the receiver input. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 640 Freescale Semiconductor, Inc. Chapter 37 Universal Asynchronous Receiver/Transmitter (UART0) UARTx_C1 field descriptions (continued) Field Description 0 1 6 DOZEEN 5 RSRC Doze Enable 0 1 This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS is set, the receiver input is internally connected to the UART _TX pin and RSRC determines whether this connection is also connected to the transmitter output. 1 3 WAKE 2 ILT 0 1 Receiver and transmitter use 8-bit data characters. Receiver and transmitter use 9-bit data characters. Receiver Wakeup Method Select 0 1 Idle-line wakeup. Address-mark wakeup. Idle Line Type Select Setting this bit to 1 ensures that the stop bits and logic 1 bits at the end of a character do not count toward the 10 to 13 bit times of logic high level needed by the idle line detection logic. Idle character bit count starts after start bit. Idle character bit count starts after stop bit. Parity Enable Enables hardware parity generation and checking. When parity is enabled, the bit immediately before the stop bit is treated as the parity bit. 0 1 0 PT Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the UART _RX pins. Single-wire UART mode where the UART _TX pin is connected to the transmitter output and receiver input. 9-Bit or 8-Bit Mode Select 0 1 1 PE UART is enabled in Wait mode. UART is disabled in Wait mode. Receiver Source Select 0 4 M Normal operation - UART _RX and UART _TX use separate pins. Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) UART _RX pin is not used by UART . No hardware parity generation or checking. Parity enabled. Parity Type Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is even. 0 1 Even parity. Odd parity. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 641 Register definition 37.2.4 UART Control Register 2 (UARTx_C2) This register can be read or written at any time. Address: 4006_A000h base + 3h offset = 4006_A003h Bit Read Write Reset 7 6 5 4 3 2 1 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 UARTx_C2 field descriptions Field 7 TIE 6 TCIE Description Transmit Interrupt Enable for TDRE 0 1 Hardware interrupts from TDRE disabled; use polling. Hardware interrupt requested when TDRE flag is 1. Transmission Complete Interrupt Enable for TC 0 1 Hardware interrupts from TC disabled; use polling. Hardware interrupt requested when TC flag is 1. 5 RIE Receiver Interrupt Enable for RDRF 4 ILIE Idle Line Interrupt Enable for IDLE 3 TE Transmitter Enable 0 1 0 1 Hardware interrupts from RDRF disabled; use polling. Hardware interrupt requested when RDRF flag is 1. Hardware interrupts from IDLE disabled; use polling. Hardware interrupt requested when IDLE flag is 1. TE must be 1 to use the UART transmitter. When TE is set, the UART forces the UART _TX pin to act as an output for the UART system. When the UART is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of traffic on the single UART communication line ( UART _TX pin). TE can also queue an idle character by clearing TE then setting TE while a transmission is in progress. When TE is written to 0, the transmitter keeps control of the port UART _TX pin until any data, queued idle, or queued break character finishes transmitting before allowing the pin to tristate. 0 1 2 RE Transmitter disabled. Transmitter enabled. Receiver Enable When the UART receiver is off or LOOPS is set, the UART _RX pin is not used by the UART . When RE is written to 0, the receiver finishes receiving the current character (if any). 0 1 1 RWU Receiver disabled. Receiver enabled. Receiver Wakeup Control Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 642 Freescale Semiconductor, Inc. Chapter 37 Universal Asynchronous Receiver/Transmitter (UART0) UARTx_C2 field descriptions (continued) Field Description This bit can be written to 1 to place the UART receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is an idle line between messages, WAKE = 0, idle-line wakeup, or a logic 1 in the most significant data bit in a character, WAKE = 1, address-mark wakeup. Application software sets RWU and, normally, a selected hardware condition automatically clears RWU. 0 1 0 SBK Normal UART receiver operation. UART receiver in standby waiting for wakeup condition. Send Break Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break characters of 10 to 13, or 13 to 16 if BRK13 = 1, bit times of logic 0 are queued as long as SBK is set. Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a second break character may be queued before software clears SBK. 0 1 Normal transmitter operation. Queue break character(s) to be sent. 37.2.5 UART Status Register 1 (UARTx_S1) Address: 4006_A000h base + 4h offset = 4006_A004h Bit Read 7 6 5 4 3 2 1 0 TDRE TC RDRF IDLE OR NF FE PF w1c w1c w1c w1c w1c 0 0 0 0 0 Write Reset 1 1 0 UARTx_S1 field descriptions Field 7 TDRE Description Transmit Data Register Empty Flag TDRE is set out of reset and whenever there is room to write data to the transmit data buffer. To clear TDRE, write to the UART data register ( UART _D). 0 1 6 TC Transmit data buffer full. Transmit data buffer empty. Transmission Complete Flag TC is set out of reset and when TDRE is set and no data, preamble, or break character is being transmitted. TC is cleared automatically by one of the following: * Write to the UART data register ( UART _D) to transmit new data * Queue a preamble by changing TE from 0 to 1 * Queue a break character by writing 1 to UART _C2[SBK] 0 1 Transmitter active (sending data, a preamble, or a break). Transmitter idle (transmission activity complete). Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 643 Register definition UARTx_S1 field descriptions (continued) Field 5 RDRF Description Receive Data Register Full Flag RDRF becomes set whenever the receive data buffer is full. To clear RDRF, read the UART data register ( UART _D). 0 1 4 IDLE Receive data buffer empty. Receive data buffer full. Idle Line Flag IDLE is set when the UART receive line becomes idle for a full character time after a period of activity. When ILT is cleared, the receiver starts counting idle bit times after the start bit. If the receive character is all 1s, these bit times and the stop bits time count toward the full character time of logic high, 10 to 13 bit times, needed for the receiver to detect an idle line. When ILT is set, the receiver doesn't start counting idle bit times until after the stop bits. The stop bits and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line. To clear IDLE, write logic 1 to the IDLE flag. After IDLE has been cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE is set only once even if the receive line remains idle for an extended period. 0 1 3 OR Receiver Overrun Flag OR is set when a new serial character is ready to be transferred to the receive data buffer, but the previously received character has not been read from UART _D yet. In this case, the new character, and all associated error information, is lost because there is no room to move it into UART _D. To clear OR, write a logic 1 to the OR flag. 0 1 2 NF The advanced sampling technique used in the receiver takes three samples in each of the received bits. If any of these samples disagrees with the rest of the samples within any bit time in the frame, the flag NF is set at the same time as RDRF is set for the character. To clear NF, write logic one to the NF. No noise detected. Noise detected in the received character in UART _D. Framing Error Flag FE is set at the same time as RDRF when the receiver detects a logic 0 where a stop bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, write a logic one to the FE flag. 0 1 0 PF No overrun. Receive overrun (new UART data lost). Noise Flag 0 1 1 FE No idle line detected. Idle line was detected. No framing error detected. This does not guarantee the framing is correct. Framing error. Parity Error Flag PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received character does not agree with the expected parity value. To clear PF, write a logic one to the PF. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 644 Freescale Semiconductor, Inc. Chapter 37 Universal Asynchronous Receiver/Transmitter (UART0) UARTx_S1 field descriptions (continued) Field Description 0 1 No parity error. Parity error. 37.2.6 UART Status Register 2 (UARTx_S2) This register contains one read-only status flag. When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slave running 14% faster than the master. This would trigger normal break detection circuitry designed to detect a 10-bit break symbol. When the LBKDE bit is set, framing errors are inhibited and the break detection threshold increases, preventing false detection of a 0x00 data character as a LIN break symbol. Address: 4006_A000h base + 5h offset = 4006_A005h Bit Read Write Reset 7 6 5 4 3 2 1 LBKDIF RXEDGIF MSBF RXINV RWUID BRK13 LBKDE 0 0 0 0 0 0 0 0 RAF 0 UARTx_S2 field descriptions Field 7 LBKDIF Description LIN Break Detect Interrupt Flag LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break character is detected. LBKDIF is cleared by writing a 1 to it. 0 1 6 RXEDGIF UART _RX Pin Active Edge Interrupt Flag RXEDGIF is set when an active edge, falling if RXINV = 0, rising if RXINV=1, on the UART _RX pin occurs. RXEDGIF is cleared by writing a 1 to it. 0 1 5 MSBF No LIN break character has been detected. LIN break character has been detected. No active edge on the receive pin has occurred. An active edge on the receive pin has occurred. MSB First Setting this bit reverses the order of the bits that are transmitted and received on the wire. This bit does not affect the polarity of the bits, the location of the parity bit or the location of the start or stop bits. This bit should only be changed when the transmitter and receiver are both disabled. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 645 Register definition UARTx_S2 field descriptions (continued) Field Description 0 1 4 RXINV LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M], C1[PE] and C4[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE]. Receive Data Inversion Setting this bit reverses the polarity of the received data input. NOTE: Setting RXINV inverts the UART _RXD input for all cases: data bits, start and stop bits, break, and idle. 0 1 3 RWUID Receive Wake Up Idle Detect RWUID controls whether the idle character that wakes up the receiver sets the IDLE bit. This bit should only be changed when the receiver is disabled. 0 1 2 BRK13 BRK13 selects a longer transmitted break character length. Detection of a framing error is not affected by the state of this bit. This bit should only be changed when the transmitter is disabled. 1 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). LIN Break Detection Enable LBKDE selects a longer break character detection length. While LBKDE is set, framing error (FE) and receive data register full (RDRF) flags are prevented from setting. 0 1 0 RAF During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. Break Character Generation Length 0 1 LBKDE Receive data not inverted. Receive data inverted. Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). Receiver Active Flag RAF is set when the UART receiver detects the beginning of a valid start bit, and RAF is cleared automatically when the receiver detects an idle line. 0 1 UART receiver idle waiting for a start bit. UART receiver active ( UART _RXD input not idle). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 646 Freescale Semiconductor, Inc. Chapter 37 Universal Asynchronous Receiver/Transmitter (UART0) 37.2.7 UART Control Register 3 (UARTx_C3) Address: 4006_A000h base + 6h offset = 4006_A006h Bit Read Write Reset 7 6 5 4 3 2 1 0 R8T9 R9T8 TXDIR TXINV ORIE NEIE FEIE PEIE 0 0 0 0 0 0 0 0 UARTx_C3 field descriptions Field 7 R8T9 Description Receive Bit 8 / Transmit Bit 9 When the UART is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data bit to the left of the msb of the buffered data in the UART_D register. When reading 9-bit data, read R8 before reading UART_D because reading UART_D completes automatic flag clearing sequences that could allow R8 and UART_D to be overwritten with new data. When the UART is configured for 10-bit data (M10 = 1), T9 may be thought of as a tenth transmit data bit. When writing 10-bit data, the entire 10-bit value is transferred to the UART transmit buffer when UART_D is written so T9 and T8 should be written, if it needs to change from its previous value, before UART_D is written. If T9 and T8 do not need to change in the new value, such as when it is used to generate mark or space parity, they need not be written each time UART_D is written. 6 R9T8 Receive Bit 9 / Transmit Bit 8 When the UART is configured for 9-bit data (M = 1), T8 may be thought of as a ninth transmit data bit to the left of the msb of the data in the UART_D register. When writing 9-bit data, the entire 9-bit value is transferred to the UART transmit buffer after UART_D is written so T8 should be written, if it needs to change from its previous value, before UART_D is written. If T8 does not need to change in the new value, such as when it is used to generate mark or space parity, it need not be written each time UART_D is written. When the UART is configured for 10-bit data (M10 = 1), R9 can be thought of as a tenth receive data bit. When reading 10-bit data, read R9 and R8 before reading UART_D because reading UART_D completes automatic flag clearing sequences that could allow R8, R9 and UART_D to be overwritten with new data. 5 TXDIR UART _TX Pin Direction in Single-Wire Mode When the UART is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit determines the direction of data at the UART_TXD pin. When clearing TXDIR, the transmitter will finish receiving the current character (if any) before the receiver starts receiving data from the UART_TXD pin. 0 1 4 TXINV UART _TXD pin is an input in single-wire mode. UART _TXD pin is an output in single-wire mode. Transmit Data Inversion Setting this bit reverses the polarity of the transmitted data output. NOTE: Setting TXINV inverts the UART _TXD output for all cases: data bits, start and stop bits, break, and idle. 0 1 3 ORIE Transmit data not inverted. Transmit data inverted. Overrun Interrupt Enable This bit enables the overrun flag (OR) to generate hardware interrupt requests. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 647 Register definition UARTx_C3 field descriptions (continued) Field Description 0 1 2 NEIE Noise Error Interrupt Enable This bit enables the noise flag (NF) to generate hardware interrupt requests. 0 1 1 FEIE NF interrupts disabled; use polling. Hardware interrupt requested when NF is set. Framing Error Interrupt Enable This bit enables the framing error flag (FE) to generate hardware interrupt requests. 0 1 0 PEIE OR interrupts disabled; use polling. Hardware interrupt requested when OR is set. FE interrupts disabled; use polling. Hardware interrupt requested when FE is set. Parity Error Interrupt Enable This bit enables the parity error flag (PF) to generate hardware interrupt requests. 0 1 PF interrupts disabled; use polling). Hardware interrupt requested when PF is set. 37.2.8 UART Data Register (UARTx_D) This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms for some of the UART status flags. Address: 4006_A000h base + 7h offset = 4006_A007h Bit Read Write Reset 7 6 5 4 3 2 1 0 R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 0 0 0 0 0 0 0 0 UARTx_D field descriptions Field Description 7 R7T7 Read receive data buffer 7 or write transmit data buffer 7. 6 R6T6 Read receive data buffer 6 or write transmit data buffer 6. 5 R5T5 Read receive data buffer 5 or write transmit data buffer 5. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 648 Freescale Semiconductor, Inc. Chapter 37 Universal Asynchronous Receiver/Transmitter (UART0) UARTx_D field descriptions (continued) Field Description 4 R4T4 Read receive data buffer 4 or write transmit data buffer 4. 3 R3T3 Read receive data buffer 3 or write transmit data buffer 3. 2 R2T2 Read receive data buffer 2 or write transmit data buffer 2. 1 R1T1 Read receive data buffer 1 or write transmit data buffer 1. 0 R0T0 Read receive data buffer 0 or write transmit data buffer 0. 37.2.9 UART Match Address Registers 1 (UARTx_MA1) The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and the associated C4[MAEN] bit is set. If a match occurs, the following data is transferred to the data register. If a match fails, the following data is discarded. Software should only write a MA register when the associated C4[MAEN] bit is clear. Address: 4006_A000h base + 8h offset = 4006_A008h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 MA 0 0 0 0 UARTx_MA1 field descriptions Field 7-0 MA Description Match Address KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 649 Register definition 37.2.10 UART Match Address Registers 2 (UARTx_MA2) The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and the associated C4[MAEN] bit is set. If a match occurs, the following data is transferred to the data register. If a match fails, the following data is discarded. Software should only write a MA register when the associated C4[MAEN] bit is clear. Address: 4006_A000h base + 9h offset = 4006_A009h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 2 1 0 1 1 MA 0 0 0 0 UARTx_MA2 field descriptions Field 7-0 MA Description Match Address 37.2.11 UART Control Register 4 (UARTx_C4) Address: 4006_A000h base + Ah offset = 4006_A00Ah Bit Read Write Reset 7 6 5 MAEN1 MAEN2 M10 0 0 0 4 3 OSR 0 1 1 UARTx_C4 field descriptions Field 7 MAEN1 Description Match Address Mode Enable 1 Refer to Match address operation for more information. 0 1 6 MAEN2 All data received is transferred to the data buffer if MAEN2 is cleared. All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. Match Address Mode Enable 2 Refer to Match address operation for more information. 0 1 All data received is transferred to the data buffer if MAEN1 is cleared. All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 650 Freescale Semiconductor, Inc. Chapter 37 Universal Asynchronous Receiver/Transmitter (UART0) UARTx_C4 field descriptions (continued) Field 5 M10 Description 10-bit Mode select The M10 bit causes a tenth bit to be part of the serial transmission. This bit should only be changed when the transmitter and receiver are both disabled. 0 1 4-0 OSR Receiver and transmitter use 8-bit or 9-bit data characters. Receiver and transmitter use 10-bit data characters. Over Sampling Ratio This field configures the oversampling ratio for the receiver between 4x (00011) and 32x (11111). Writing an invalid oversampling ratio will default to an oversampling ratio of 16 (01111). This field should only be changed when the transmitter and receiver are both disabled. 37.2.12 UART Control Register 5 (UARTx_C5) Address: 4006_A000h base + Bh offset = 4006_A00Bh Bit Read Write Reset 7 6 5 0 TDMAE 0 4 0 2 0 RDMAE 0 3 0 0 1 0 BOTHEDGE RESYNCDI S 0 0 0 UARTx_C5 field descriptions Field 7 TDMAE Description Transmitter DMA Enable TDMAE configures the transmit data register empty flag, S1[TDRE], to generate a DMA request. 0 1 6 Reserved 5 RDMAE This field is reserved. This read-only field is reserved and always has the value 0. Receiver Full DMA Enable RDMAE configures the receiver data register full flag, S1[RDRF], to generate a DMA request. 0 1 4-2 Reserved 1 BOTHEDGE DMA request disabled. DMA request enabled. DMA request disabled. DMA request enabled. This field is reserved. This read-only field is reserved and always has the value 0. Both Edge Sampling Enables sampling of the received data on both edges of the baud rate clock, effectively doubling the number of times the receiver samples the input data for a given oversampling ratio. This bit must be set for oversampling ratios between x4 and x7 and is optional for higher oversampling ratios. This bit should only be changed when the receiver is disabled. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 651 Functional description UARTx_C5 field descriptions (continued) Field Description 0 1 0 RESYNCDIS Receiver samples input data using the rising edge of the baud rate clock. Receiver samples input data using the rising and falling edge of the baud rate clock. Resynchronization Disable When set, disables the resynchronization of the received data word when a data one followed by data zero transition is detected. This bit should only be changed when the receiver is disabled. 0 1 Resynchronization during received data word is supported Resynchronization during received data word is disabled 37.3 Functional description The UART supports full-duplex, asynchronous, NRZ serial communication and comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate independently, although they use the same baud rate generator. The following describes each of the blocks of the UART. 37.3.1 Baud rate generation A 13-bit modulus counter in the baud rate generator derive the baud rate for both the receiver and the transmitter. The value from 1 to 8191 written to SBR[12:0] determines the baud clock divisor for the asynchronous UART baud clock. The SBR bits are in the UART baud rate registers, BDH and BDL. The baud rate clock drives the receiver, while the transmitter is driven by the baud rate clock divided by the over sampling ratio. Depending on the over sampling ratio, the receiver has an acquisition rate of 4 to 32 samples per bit time. Figure 37-27. UART baud rate generation Baud rate generation is subject to two sources of error: * Integer division of the module clock may not give the exact target frequency. * Synchronization with the asynchronous UART baud clock can cause phase shift. 37.3.2 Transmitter functional description This section describes the overall block diagram for the UART transmitter, as well as specialized functions for sending break and idle characters. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 652 Freescale Semiconductor, Inc. Chapter 37 Universal Asynchronous Receiver/Transmitter (UART0) The transmitter output (UART_TX) idle state defaults to logic high, C3[TXINV] is cleared following reset. The transmitter output is inverted by setting C3[TXINV]. The transmitter is enabled by setting the C2[TE] bit. This queues a preamble character that is one full character frame of the idle state. The transmitter then remains idle until data is available in the transmit data buffer. Programs store data into the transmit data buffer by writing to the UART data register. The central element of the UART transmitter is the transmit shift register that is 10-bit to 13 bits long depending on the setting in the C1[M], C2[M10] and BDH[SBNS] control bits. For the remainder of this section, assume C1[M], C2[M10] and BDH[SBNS] are cleared, selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. When the transmit shift register is available for a new UART character, the value waiting in the transmit data register is transferred to the shift register, synchronized with the baud rate clock, and the transmit data register empty (S1[TDRE]) status flag is set to indicate another character may be written to the transmit data buffer at UART_D. If no new character is waiting in the transmit data buffer after a stop bit is shifted out the UART_TX pin, the transmitter sets the transmit complete flag and enters an idle mode, with UART_TX high, waiting for more characters to transmit. Writing 0 to C2[TE] does not immediately disable the transmitter. The current transmit activity in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters. 37.3.2.1 Send break and queued idle The UART_C2[SBK] bit sends break characters originally used to gain the attention of old teletype receivers. Break characters are a full character time of logic 0, 10-bit to 12bit times including the start and stop bits. A longer break of 13-bit times can be enabled by setting UART_S2[BRK13]. Normally, a program would wait for UART_S1[TDRE] to become set to indicate the last character of a message has moved to the transmit shifter, write 1, and then write 0 to the UART_C2[SBK] bit. This action queues a break character to be sent as soon as the shifter is available. If UART_C2[SBK] remains 1 when the queued break moves into the shifter, synchronized to the baud rate clock, an additional break character is queued. If the receiving device is another Freescale Semiconductor UART, the break characters are received as 0s in all data bits and a framing error (UART_S1[FE] = 1) occurs. When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. Normally, a program would wait for UART_S1[TDRE] to become set to indicate the last character of a message has moved to KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 653 Functional description the transmit shifter, then write 0 and then write 1 to the UART_C2[TE] bit. This action queues an idle character to be sent as soon as the shifter is available. As long as the character in the shifter does not finish whileUART_C2[TE] is cleared, the UART transmitter never actually releases control of the UART_TX pin. The length of the break character is affected by the UART_S2[BRK13], UART_C1[M] and UART_C4[M10] bits as shown below. Table 37-27. Break character length BRK13 M M10 SBNS Break character length 0 0 0 0 10 bit times 0 0 0 1 11 bit times 0 1 0 0 11 bit times 0 1 0 1 12 bit times 0 X 1 0 12 bit times 0 X 1 1 13 bit times 1 0 0 0 13 bit times 1 0 0 1 14 bit times 1 1 0 0 14 bit times 1 1 0 1 15 bit times 1 X 1 0 15 bit times 1 X 1 1 16 bit times 37.3.3 Receiver functional description In this section, the receiver block diagram is a guide for the overall receiver functional description. Next, the data sampling technique used to reconstruct receiver data is described in more detail. Finally, two variations of the receiver wakeup function are explained. The receiver input is inverted by setting UART_S2[RXINV]. The receiver is enabled by setting the UART_C2[RE] bit. Character frames consist of a start bit of logic 0, eight to ten data bits (msb or lsb first), and one or two stop bits of logic 1. For information about 9-bit or 10-bit data mode, refer to 8-bit, 9-bit and 10-bit data modes. For the remainder of this discussion, assume the UART is configured for normal 8-bit data mode. After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full (UART_S1[RDRF]) status flag is set. If UART_S1[RDRF] was already set indicating the receive data register (buffer) was already full, the overrun (OR) KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 654 Freescale Semiconductor, Inc. Chapter 37 Universal Asynchronous Receiver/Transmitter (UART0) status flag is set and the new data is lost. Because the UART receiver is double-buffered, the program has one full character time after UART_S1[RDRF] is set before the data in the receive data buffer must be read to avoid a receiver overrun. When a program detects that the receive data register is full (UART_S1[RDRF] = 1), it gets the data from the receive data register by reading UART_D. Refer to Interrupts and status flags for details about flag clearing. 37.3.3.1 Data sampling technique The UART receiver supports an oversampling rate of between 4x and 32x of the baud rate clock for sampling. The receiver starts by taking logic level samples at the oversampling rate times the baud rate to search for a falling edge on the UART_RX serial data input pin. A falling edge is defined as a logic 0 sample after three consecutive logic 1 samples. The oversampling baud rate clock divides the bit time into 4 to 32 segments from 1 to OSR (where OSR is the configured oversampling ratio). When a falling edge is located, three more samples are taken at (OSR/2), (OSR/2)+1, and (OSR/2)+2 to make sure this was a real start bit and not merely noise. If at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character. If another falling edge is detected before the receiver is considered synchronized, the receiver restarts the sampling from the first segment. The receiver then samples each bit time, including the start and stop bits, at (OSR/2), (OSR/2)+1, and (OSR/2)+2 to determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples taken during the bit time. If any sample in any bit time, including the start and stop bits, in a character frame fails to agree with the logic level for that bit, the noise flag (UART_S1[NF]) is set when the received character is transferred to the receive data buffer. When the UART receiver is configured to sample on both edges of the baud rate clock, the number of segments in each received bit is effectively doubled (from 1 to OSR*2). The start and data bits are then sampled at OSR, OSR+1 and OSR+2. Sampling on both edges of the clock must be enabled for oversampling rates of 4x to 7x and is optional for higher oversampling rates. The falling edge detection logic continuously looks for falling edges. If an edge is detected, the sample clock is resynchronized to bit times (unless resynchronization has been disabled). This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 655 Functional description In the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. 37.3.3.2 Receiver wakeup operation Receiver wakeup is a hardware mechanism that allows an UART receiver to ignore the characters in a message intended for a different UART receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up control bit(UART_C2[RWU]). When RWU bit is set, the status flags associated with the receiver, with the exception of the idle bit, IDLE, when UART_S2[RWUID] bit is set, are inhibited from setting, thus eliminating the software overhead for handling the unimportant message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force UART_C2[RWU] to 0 so all receivers wake up in time to look at the first character(s) of the next message. 37.3.3.2.1 Idle-line wakeup When wake is cleared, the receiver is configured for idle-line wakeup. In this mode, UART_C2[RWU] is cleared automatically when the receiver detects a full character time of the idle-line level. The UART_C1[M] and UART_C4[M10] control bit selects 8-bit to 10-bit data mode and the UART_BDH[SBNS] bit selects 1-bit or 2-bit stop bit number that determines how many bit times of idle are needed to constitute a full character time, 10 to 13 bit times because of the start and stop bits. When UART_C2[RWU] is one and UART_S2[RWUID] is zero, the idle condition that wakes up the receiver does not set the UART_S1[IDLE] flag. The receiver wakes up and waits for the first data character of the next message that sets the UART_S1[RDRF] flag and generates an interrupt if enabled. When UART_S2[RWUID] is one, any idle condition sets the UART_S1[IDLE] flag and generates an interrupt if enabled, regardless of whether UART_C2[RWU] is zero or one. The idle-line type (UART_C1[ILT]) control bit selects one of two ways to detect an idle line. When UART_C1[ILT] is cleared, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. When UART_C1[ILT] is set, the idle bit counter does not start until after the stop bit time, so the idle detection is not affected by the data in the last character of the previous message. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 656 Freescale Semiconductor, Inc. Chapter 37 Universal Asynchronous Receiver/Transmitter (UART0) 37.3.3.2.2 Address-mark wakeup When wake is set, the receiver is configured for address-mark wakeup. In this mode, UART_C2[RWU] is cleared automatically when the receiver detects a logic 1 in the most significant bit of a received character. Address-mark wakeup allows messages to contain idle characters, but requires the msb be reserved for use in address frames. The logic 1 in the msb of an address frame clears the UART_C2[RWU] bit before the stop bits are received and sets the UART_S1[RDRF] flag. In this case, the character with the msb set is received even though the receiver was sleeping during most of this character time. 37.3.3.2.3 Match address operation Match address operation is enabled when the UART_C4[MAEN1] or UART_C4[MAEN2] bit is set. In this function, a frame received by the UART_RX pin with a logic 1 in the bit position immediately preceding the stop bit is considered an address and is compared with the associated MA1 or MA2 register. The frame is only transferred to the receive buffer, and UART_S1[RDRF] is set, if the comparison matches. All subsequent frames received with a logic 0 in the bit position immediately preceding the stop bit are considered to be data associated with the address and are transferred to the receive data buffer. If no marked address match occurs then no transfer is made to the receive data buffer, and all following frames with logic zero in the bit position immediately preceding the stop bit are also discarded. If both the UART_C4[MAEN1] and UART_C4[MAEN2] bits are negated, the receiver operates normally and all data received is transferred to the receive data buffer. Match Address operation functions in the same way for both MA1 and MA2 registers. * If only one of UART_C4[MAEN1] and UART_C4[MAEN2] is asserted, a marked address is compared only with the associated match register and data is transferred to the receive data buffer only on a match. * If UART_C4[MAEN1] and UART_C4[MAEN2] are asserted, a marked address is compared with both match registers and data is transferred only on a match with either register. 37.3.4 Additional UART functions The following sections describe additional UART functions. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 657 Functional description 37.3.4.1 8-bit, 9-bit and 10-bit data modes The UART system, transmitter and receiver, can be configured to operate in 9-bit data mode by setting the UART_C1[M] or 10-bit data mode by setting UART_C4[M10]. In 9bit mode, there is a ninth data bit to the left of the msb of the UART data register, in 10bit mode there is a tenth data bit. For the transmit data buffer, these bits are stored in T8 and T9 in UART_C3. For the receiver, these bits are held in UART_C3[R8] and UART_C3[R9]. For coherent writes to the transmit data buffer, write to UART_C3[T8] and UART_C3[T9] before writing to UART_D. If the bit values to be transmitted as the ninth and tenth bit of a new character are the same as for the previous character, it is not necessary to write to T8 and T9 again. When data is transferred from the transmit data buffer to the transmit shifter, the value in T8 and T9 is copied at the same time data is transferred from UART_D to the shifter. The 9-bit data mode is typically used with parity to allow eight bits of data plus the parity in the ninth bit, or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. The 10-bit data mode is typically used with parity and address-mark wakeup so the ninth data bit can serve as the wakeup bit and the tenth bit as the parity bit. In custom protocols, the ninth and/or tenth bits can also serve as software-controlled markers. 37.3.4.2 Loop mode When UART_C1[LOOPS] is set, the UART_C1[RSRC] bit in the same register chooses between loop mode (UART_C1[RSRC] = 0) or single-wire mode (UART_C1[RSRC] = 1). Loop mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. In this mode, the transmitter output is internally connected to the receiver input and the UART_RX pin is not used by the UART. 37.3.4.3 Single-wire operation When UART_C1[LOOPS] is set, the RSRC bit in the same register chooses between loop mode (UART_C1[RSRC] = 0) or single-wire mode (UART_C1[RSRC] = 1). Single-wire mode implements a half-duplex serial connection. The receiver is internally connected to the transmitter output and to the UART_TX pin (the UART_RX pin is not used). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 658 Freescale Semiconductor, Inc. Chapter 37 Universal Asynchronous Receiver/Transmitter (UART0) In single-wire mode, the UART_C3[TXDIR] bit controls the direction of serial data on the UART_TX pin. When UART_C3[TXDIR] is cleared, the UART_TX pin is an input to the UART receiver and the transmitter is temporarily disconnected from the UART_TX pin so an external device can send serial data to the receiver. When UART_C3[TXDIR] is set, the UART_TXD pin is an output driven by the transmitter, the internal loop back connection is disabled, and as a result the receiver cannot receive characters that are sent out by the transmitter. 37.3.5 Interrupts and status flags The UART system generates three separate interrupts to reduce the amount of software needed to isolate the cause of the interrupt. One interrupt is associated with the transmitter for TDRE and TC events. Another interrupt is associated with the receiver for RDRF, IDLE, RXEDGIF, and LBKDIF events. A third interrupt is used for OR, NF, FE, and PF error conditions. Each of these ten interrupt sources can be separately masked by local interrupt enable masks. The flags can be polled by software when the local masks are cleared to disable generation of hardware interrupt requests. The UART transmitter has two status flags that can optionally generate hardware interrupt requests. Transmit data register empty (UART_S1[TDRE]) indicates when there is room in the transmit data buffer to write another transmit character to UART_D. If the transmit interrupt enable (UART_C2[TIE]) bit is set, a hardware interrupt is requested when UART_S1[TDRE] is set. Transmit complete (UART_S1[TC]) indicates that the transmitter is finished transmitting all data, preamble, and break characters and is idle with UART_TX at the inactive level. This flag is often used in systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt enable (UART_C2[TCIE]) bit is set, a hardware interrupt is requested when UART_S1[TC] is set. Instead of hardware interrupts, software polling may be used to monitor the UART_S1[TDRE] and UART_S1[TC] status flags if the corresponding UART_C2[TIE] or UART_C2[TCIE] local interrupt masks are cleared. When a program detects that the receive data register is full (UART_S1[RDRF] = 1), it gets the data from the receive data register by reading UART_D. The UART_S1[RDRF] flag is cleared by reading UART_D. The IDLE status flag includes logic that prevents it from getting set repeatedly when the UART_RX line remains idle for an extended period of time. IDLE is cleared by writing 1 to the UART_S1[IDLE] flag. After UART_S1[IDLE] has been cleared, it cannot become set again until the receiver has received at least one new character and has set UART_S1[RDRF]. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 659 Functional description If the associated error was detected in the received character that caused UART_S1[RDRF] to be set, the error flags - noise flag (UART_S1[NF]), framing error (UART_S1[FE]), and parity error flag (UART_S1[PF]) - are set at the same time as UART_S1[RDRF]. These flags are not set in overrun cases. If UART_S1[RDRF] was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun (UART_S1[OR]) flag is set instead of the data along with any associated NF, FE, or PF condition is lost. At any time, an active edge on the UART_RX serial data input pin causes the UART_S2[RXEDGIF] flag to set. The UART_S2[RXEDGIF] flag is cleared by writing a 1 to it. This function depends on the receiver being enabled (UART_C2[RE] = 1). KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 660 Freescale Semiconductor, Inc. Chapter 38 General-Purpose Input/Output (GPIO) 38.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The general-purpose input and output (GPIO) module communicates to the processor core via a zero wait state interface for maximum pin performance. The GPIO registers support 8-bit, 16-bit or 32-bit accesses. The GPIO data direction and output data registers control the direction and output data of each pin when the pin is configured for the GPIO function. The GPIO input data register displays the logic value on each pin when the pin is configured for any digital function, provided the corresponding Port Control and Interrupt module for that pin is enabled. Efficient bit manipulation of the general-purpose outputs is supported through the addition of set, clear, and toggle write-only registers for each port output data register. 38.1.1 Features * Features of the GPIO module include: * Pin input data register visible in all digital pin-multiplexing modes * Pin output data register with corresponding set/clear/toggle registers * Pin data direction register * Zero wait state access to GPIO registers through IOPORT NOTE GPIO module is clocked by system clock. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 661 Introduction 38.1.2 Modes of operation The following table depicts different modes of operation and the behavior of the GPIO module in these modes. Table 38-1. Modes of operation Modes of operation Description Run The GPIO module operates normally. Wait The GPIO module operates normally. Stop The GPIO module is disabled. Debug The GPIO module operates normally. 38.1.3 GPIO signal descriptions Table 38-2. GPIO signal descriptions GPIO signal descriptions Description I/O PORTA31-PORTA0 General-purpose input/output I/O PORTB31-PORTB0 General-purpose input/output I/O NOTE Not all pins within each port are implemented on each device. See the chapter on signal multiplexing for the number of GPIO ports available in the device. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 662 Freescale Semiconductor, Inc. Chapter 38 General-Purpose Input/Output (GPIO) 38.1.3.1 Detailed signal description Table 38-3. GPIO interface-detailed signal descriptions Signal I/O Description PORTA31-PORTA0 I/O General-purpose input/output State meaning PORTB31-PORTB0 Asserted: The pin is logic 1. Deasserted: The pin is logic 0. Timing Assertion: When output, this signal occurs on the risingedge of the system clock. For input, it may occur at any time and input may be asserted asynchronously to the system clock. Deassertion: When output, this signal occurs on the rising-edge of the system clock. For input, it may occur at any time and input may be asserted asynchronously to the system clock. 38.2 Memory map and register definition Any read or write access to the GPIO memory space that is outside the valid memory map results in a bus error. GPIO memory map Absolute address (hex) Register name Width Access (in bits) R/W Reset value Section/ page 0000_0000h 38.2.1/664 400F_F000 Port Data Output Register (GPIOA_PDOR) 32 400F_F004 Port Set Output Register (GPIOA_PSOR) 32 W (always 0000_0000h reads 0) 38.2.2/665 400F_F008 Port Clear Output Register (GPIOA_PCOR) 32 W (always 0000_0000h reads 0) 38.2.3/665 400F_F00C Port Toggle Output Register (GPIOA_PTOR) 32 W (always 0000_0000h reads 0) 38.2.4/666 400F_F010 Port Data Input Register (GPIOA_PDIR) 32 R 0000_0000h 38.2.5/666 400F_F014 Port Data Direction Register (GPIOA_PDDR) 32 R/W 0000_0000h 38.2.6/667 400F_F040 Port Data Output Register (GPIOB_PDOR) 32 R/W 0000_0000h 38.2.1/664 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 663 Memory map and register definition GPIO memory map (continued) Absolute address (hex) Width Access (in bits) Register name Section/ page Reset value 400F_F044 Port Set Output Register (GPIOB_PSOR) 32 W (always 0000_0000h reads 0) 38.2.2/665 400F_F048 Port Clear Output Register (GPIOB_PCOR) 32 W (always 0000_0000h reads 0) 38.2.3/665 400F_F04C Port Toggle Output Register (GPIOB_PTOR) 32 W (always 0000_0000h reads 0) 38.2.4/666 400F_F050 Port Data Input Register (GPIOB_PDIR) 32 R 0000_0000h 38.2.5/666 400F_F054 Port Data Direction Register (GPIOB_PDDR) 32 R/W 0000_0000h 38.2.6/667 38.2.1 Port Data Output Register (GPIOx_PDOR) This register configures the logic levels that are driven on each general-purpose output pins. NOTE Do not modify pin configuration registers associated with pins not available in your selected package. All un-bonded pins not available in your package will default to DISABLE state for lowest power consumption. Address: Base address + 0h offset Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_PDOR field descriptions Field 31-0 PDO Description Port Data Output Register bits for un-bonded pins return a undefined value when read. 0 1 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. Logic level 1 is driven on pin, provided pin is configured for general-purpose output. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 664 Freescale Semiconductor, Inc. Chapter 38 General-Purpose Input/Output (GPIO) 38.2.2 Port Set Output Register (GPIOx_PSOR) This register configures whether to set the fields of the PDOR. Address: Base address + 4h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R 0 W PTSO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_PSOR field descriptions Field Description 31-0 PTSO Port Set Output Writing to this register will update the contents of the corresponding bit in the PDOR as follows: 0 1 Corresponding bit in PDORn does not change. Corresponding bit in PDORn is set to logic 1. 38.2.3 Port Clear Output Register (GPIOx_PCOR) This register configures whether to clear the fields of PDOR. Address: Base address + 8h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R 0 W PTCO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_PCOR field descriptions Field 31-0 PTCO Description Port Clear Output Writing to this register will update the contents of the corresponding bit in the Port Data Output Register (PDOR) as follows: 0 1 Corresponding bit in PDORn does not change. Corresponding bit in PDORn is cleared to logic 0. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 665 Memory map and register definition 38.2.4 Port Toggle Output Register (GPIOx_PTOR) Address: Base address + Ch offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R 0 W PTTO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_PTOR field descriptions Field Description 31-0 PTTO Port Toggle Output Writing to this register will update the contents of the corresponding bit in the PDOR as follows: 0 1 Corresponding bit in PDORn does not change. Corresponding bit in PDORn is set to the inverse of its existing logic state. 38.2.5 Port Data Input Register (GPIOx_PDIR) NOTE Do not modify pin configuration registers associated with pins not available in your selected package. All un-bonded pins not available in your package will default to DISABLE state for lowest power consumption. Address: Base address + 10h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDI R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_PDIR field descriptions Field 31-0 PDI Description Port Data Input Reads 0 at the unimplemented pins for a particular device. Pins that are not configured for a digital function read 0. If the Port Control and Interrupt module is disabled, then the corresponding bit in PDIR does not update. 0 1 Pin logic level is logic 0, or is not configured for use by digital function. Pin logic level is logic 1. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 666 Freescale Semiconductor, Inc. Chapter 38 General-Purpose Input/Output (GPIO) 38.2.6 Port Data Direction Register (GPIOx_PDDR) The PDDR configures the individual port pins for input or output. Address: Base address + 14h offset Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_PDDR field descriptions Field 31-0 PDD Description Port Data Direction Configures individual port pins for input or output. 0 1 Pin is configured as general-purpose input, for the GPIO function. Pin is configured as general-purpose output, for the GPIO function. 38.3 FGPIO memory map and register definition Any read or write access to the FGPIO memory space that is outside the valid memory map results in a bus error. All register accesses complete with zero wait states, except error accesses which complete with one wait state. FGPIO memory map Absolute address (hex) Register name Width Access (in bits) R/W Reset value Section/ page 0000_0000h 38.3.1/668 F80F_F000 Port Data Output Register (FGPIOA_PDOR) 32 F80F_F004 Port Set Output Register (FGPIOA_PSOR) 32 W (always 0000_0000h reads 0) 38.3.2/668 F80F_F008 Port Clear Output Register (FGPIOA_PCOR) 32 W (always 0000_0000h reads 0) 38.3.3/669 F80F_F00C Port Toggle Output Register (FGPIOA_PTOR) 32 W (always 0000_0000h reads 0) 38.3.4/669 F80F_F010 Port Data Input Register (FGPIOA_PDIR) 32 R 0000_0000h 38.3.5/670 F80F_F014 Port Data Direction Register (FGPIOA_PDDR) 32 R/W 0000_0000h 38.3.6/670 F80F_F040 Port Data Output Register (FGPIOB_PDOR) 32 R/W 0000_0000h 38.3.1/668 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 667 FGPIO memory map and register definition FGPIO memory map (continued) Absolute address (hex) Width Access (in bits) Register name Section/ page Reset value F80F_F044 Port Set Output Register (FGPIOB_PSOR) 32 W (always 0000_0000h reads 0) 38.3.2/668 F80F_F048 Port Clear Output Register (FGPIOB_PCOR) 32 W (always 0000_0000h reads 0) 38.3.3/669 F80F_F04C Port Toggle Output Register (FGPIOB_PTOR) 32 W (always 0000_0000h reads 0) 38.3.4/669 F80F_F050 Port Data Input Register (FGPIOB_PDIR) 32 R 0000_0000h 38.3.5/670 F80F_F054 Port Data Direction Register (FGPIOB_PDDR) 32 R/W 0000_0000h 38.3.6/670 38.3.1 Port Data Output Register (FGPIOx_PDOR) This register configures the logic levels that are driven on each general-purpose output pins. Address: Base address + 0h offset Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FGPIOx_PDOR field descriptions Field Description 31-0 PDO Port Data Output Unimplemented pins for a particular device read as zero. 0 1 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 38.3.2 Port Set Output Register (FGPIOx_PSOR) This register configures whether to set the fields of the PDOR. Address: Base address + 4h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R 0 W PTSO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 668 Freescale Semiconductor, Inc. Chapter 38 General-Purpose Input/Output (GPIO) FGPIOx_PSOR field descriptions Field Description 31-0 PTSO Port Set Output Writing to this register will update the contents of the corresponding bit in the PDOR as follows: 0 1 Corresponding bit in PDORn does not change. Corresponding bit in PDORn is set to logic 1. 38.3.3 Port Clear Output Register (FGPIOx_PCOR) This register configures whether to clear the fields of PDOR. Address: Base address + 8h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R 0 W PTCO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FGPIOx_PCOR field descriptions Field Description 31-0 PTCO Port Clear Output Writing to this register will update the contents of the corresponding bit in the Port Data Output Register (PDOR) as follows: 0 1 Corresponding bit in PDORn does not change. Corresponding bit in PDORn is cleared to logic 0. 38.3.4 Port Toggle Output Register (FGPIOx_PTOR) Address: Base address + Ch offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R 0 W PTTO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FGPIOx_PTOR field descriptions Field 31-0 PTTO Description Port Toggle Output Writing to this register will update the contents of the corresponding bit in the PDOR as follows: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 669 FGPIO memory map and register definition FGPIOx_PTOR field descriptions (continued) Field Description 0 1 Corresponding bit in PDORn does not change. Corresponding bit in PDORn is set to the inverse of its existing logic state. 38.3.5 Port Data Input Register (FGPIOx_PDIR) Address: Base address + 10h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDI R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FGPIOx_PDIR field descriptions Field Description 31-0 PDI Port Data Input Reads 0 at the unimplemented pins for a particular device. Pins that are not configured for a digital function read 0. If the Port Control and Interrupt module is disabled, then the corresponding bit in PDIR does not update. 0 1 Pin logic level is logic 0, or is not configured for use by digital function. Pin logic level is logic 1. 38.3.6 Port Data Direction Register (FGPIOx_PDDR) The PDDR configures the individual port pins for input or output. Address: Base address + 14h offset Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FGPIOx_PDDR field descriptions Field 31-0 PDD Description Port Data Direction Configures individual port pins for input or output. 0 1 Pin is configured as general-purpose input, for the GPIO function. Pin is configured as general-purpose output, for the GPIO function. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 670 Freescale Semiconductor, Inc. Chapter 38 General-Purpose Input/Output (GPIO) 38.4 Functional description 38.4.1 General-purpose input The logic state of each pin is available via the Port Data Input registers, provided the pin is configured for a digital function and the corresponding Port Control and Interrupt module is enabled. 38.4.2 General-purpose output The logic state of each pin can be controlled via the port data output registers and port data direction registers, provided the pin is configured for the GPIO function. The following table depicts the conditions for a pin to be configured as input/output. If Then A pin is configured for the GPIO function and the corresponding port data direction register bit is clear. The pin is configured as an input. A pin is configured for the GPIO function and the corresponding port data direction register bit is set. The pin is configured as an output and and the logic state of the pin is equal to the corresponding port data output register. To facilitate efficient bit manipulation on the general-purpose outputs, pin data set, pin data clear, and pin data toggle registers exist to allow one or more outputs within one port to be set, cleared, or toggled from a single register write. The corresponding Port Control and Interrupt module does not need to be enabled to update the state of the port data direction registers and port data output registers including the set/clear/toggle registers. 38.4.3 IOPORT The GPIO registers are also aliased to the IOPORT interface on the Cortex-M0+ from address $F800_0000. Accesses via the IOPORT interface occur in parallel with any instruction fetches and will therefore complete in a single cycle. If the DMA attempts to access the GPIO registers on the same cycle as an IOPORT access, then the DMA access will stall until any IOPORT accesses have completed. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 671 Functional description During Compute Operation, the GPIO registers remain accessible via the IOPORT interface only. Since the clocks to the Port Control and Interrupt modules are disabled during Compute Operation, the Pin Data Input Registers do not update with the current state of the pins. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 672 Freescale Semiconductor, Inc. Chapter 39 Touch Sensing Input (TSI) 39.1 Introduction The touch sensing input (TSI) module provides capacitive touch sensing detection with high sensitivity and enhanced robustness. Each TSI pin implements the capacitive measurement by a current source scan, charging and discharging the electrode, once or several times. A reference oscillator ticks the scan time and stores the result in a 16-bit register when the scan completes. Meanwhile, an interrupt request is submitted to CPU for post-processing if TSI interrupt is enabled and DMA function is not selected.The TSI module can be periodically triggered to work in low power mode with ultra-low current adder and wake CPU at the end of scan or the conversion result is out of the range specified by TSI threshold. It provides a solid capacitive measurement module to the implementation of touch keyboard, rotaries and sliders. 39.1.1 Features TSI features includes: * Support up to 16 external electrodes * Automatic detection of electrode capacitance across all operational power modes * Internal reference oscillator for high-accuracy measurement * Configurable software or hardware scan trigger * Fully support Freescale touch sensing software (TSS) library, see www.freescale.com/touchsensing. * Capability to wake MCU from low power modes * Compensate for temperature and supply voltage variations * High sensitivity change with 16-bit resolution register * Configurable up to 4096 scan times. * Support DMA data transfer KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 673 Introduction 39.1.2 Modes of operation This module supports the following operation modes. Table 39-1. Operating modes Mode Description Stop and low power stop TSI module is fully functional in all of the stop modes as long as TSI_GENCS[STPE] is set. The channel specified by TSI_DATA[TSICH] will be scanned upon the trigger. After scan finishes, either end-of-scan or out-of-range interrupt can be selected to bring MCU out of low power modes. Wait TSI module is fully functional in this mode. When a scan completes, TSI submits an interrupt request to CPU if the interrupt is enabled. Run TSI module is fully functional in this mode. When a scan completes, TSI submits an interrupt request to CPU if the interrupt is enabled. 39.1.3 Block diagram The following figure is a block diagram of the TSI module. TSIEN TSIIEN STPE Int. 1.8V DVOLT Voltage Divider TSI2 TSI3 ANALOG MUX TSI0 TSI1 TSI_CNTH + - TSI14 Write SWTS "1" Electrode Oscillator 16-bit Counter TSI_CNTL Reference Clock Interrupt TSICH Control Logic MUX Hardware Trigger NSCN Reference Oscillator TSI15 TSI_PENx 2 PS STM EXTCHRG REFCHRG CURSW EOSF SCNIP TSIIEN Figure 39-1. TSI module block diagram KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 674 Freescale Semiconductor, Inc. Chapter 39 Touch Sensing Input (TSI) 39.2 External signal description The TSI module contains up to 16 external pins for touch sensing. The following table describes each of the TSI external pins. Table 39-2. TSI signal description Name TSI[15:0] Port TSI Direction I/O Function Reset state TSI capacitive pins. I/O Switches driver that connects directly to the electrode pins TSI[15:0] can operate as GPIO pins. 39.2.1 TSI[15:0] When TSI functionality is enabled , the TSI analog portion uses the corresponding channel to connect external on-board touch capacitors. The PCB connection between the pin and the touch pad must be kept as short as possible to reduce distribution capacity on board. 39.3 Register definition This section describes the memory map and control/status registers for the TSI module. TSI memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_5000 TSI General Control and Status Register (TSI0_GENCS) 32 R/W 0000_0000h 39.3.1/675 4004_5004 TSI DATA Register (TSI0_DATA) 32 R/W 0000_0000h 39.3.2/680 4004_5008 TSI Threshold Register (TSI0_TSHD) 32 R/W 0000_0000h 39.3.3/681 39.3.1 TSI General Control and Status Register (TSIx_GENCS) This control register provides various control and configuration information for the TSI module. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 675 Register definition NOTE When TSI is working, the configuration bits (GENCS[TSIEN], GENCS[TSIIEN], and GENCS[STM]) must not be changed. The EOSF flag is kept until the software acknowledge it. Bit 31 R OUTRGF Address: 4004_5000h base + 0h offset = 4004_5000h 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 ESO R MODE REFCHRG DVOLT EXTCHRG Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EOSF w1c SCNIP W 30 STPE STM w1c W Reset 0 CURSW NSCN TSIIEN PS TSIEN R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSIx_GENCS field descriptions Field Description 31 OUTRGF Out of Range Flag. 30-29 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 28 ESOR This flag is set if the result register of the enabled electrode is out of the range defined by the TSI_THRESHOLD register. This flag is set only when TSI is configured in non-noise detection mode. It can be read once the CPU wakes. Write "1" , when this flag is set, to clear it. End-of-scan or Out-of-Range Interrupt Selection This bit is used to select out-of-range or end-of-scan event to generate an interrupt. 0 1 Out-of-range interrupt is allowed. End-of-scan interrupt is allowed. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 676 Freescale Semiconductor, Inc. Chapter 39 Touch Sensing Input (TSI) TSIx_GENCS field descriptions (continued) Field 27-24 MODE Description TSI analog modes setup and status bits. Set up TSI analog modes, especially, setting MODE[3:2] to not 2'b00 will configure TSI to noise detection modes. MODE[1:0] take no effect on TSI operation mode and should always write to 2'b00 for setting up. When reading this field will return the analog status. Refer to chapter "Noise detection mode" for details. 0000 0100 Set TSI in capacitive sensing(non-noise detection) mode. Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is disabled. Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is enabled to work in higher frequencies operations. Set TSI analog to work in automatic noise detection mode. 1000 1100 23-21 REFCHRG REFCHRG These bits indicate the reference oscillator charge and discharge current value. 000 001 010 011 100 101 110 111 20-19 DVOLT DVOLT These bits indicate the oscillator's voltage rails as below. 00 01 10 11 18-16 EXTCHRG DV = 1.03 V; VP = 1.33 V; Vm = 0.30 V. DV = 0.73 V; VP = 1.18 V; Vm = 0.45 V. DV = 0.43 V; VP = 1.03 V; Vm = 0.60 V. DV = 0.29 V; VP = 0.95 V; Vm = 0.67 V. EXTCHRG These bits indicate the electrode oscillator charge and discharge current value. 000 001 010 011 100 101 110 111 15-13 PS 500 nA. 1 A. 2 A. 4 A. 8 A. 16 A. 32 A. 64 A. 500 nA. 1 A. 2 A. 4 A. 8 A. 16 A. 32 A. 64 A. PS These bits indicate the prescaler of the output of electrode oscillator. 000 001 Electrode Oscillator Frequency divided by 1 Electrode Oscillator Frequency divided by 2 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 677 Register definition TSIx_GENCS field descriptions (continued) Field Description 010 011 100 101 110 111 12-8 NSCN NSCN These bits indicate the scan number for each electrode. The scan number is equal to NSCN + 1, which allows the scan time ranges from 1 to 32. By default, NSCN is configured as 0, which asserts the TSI scans once on the selected eletrode channel. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 7 TSIEN Electrode Oscillator Frequency divided by 4 Electrode Oscillator Frequency divided by 8 Electrode Oscillator Frequency divided by 16 Electrode Oscillator Frequency divided by 32 Electrode Oscillator Frequency divided by 64 Electrode Oscillator Frequency divided by 128 Once per electrode Twice per electrode 3 times per electrode 4 times per electrode 5 times per electrode 6 times per electrode 7 times per electrode 8 times per electrode 9 times per electrode 10 times per electrode 11 times per electrode 12 times per electrode 13 times per electrode 14 times per electrode 15 times per electrode 16 times per electrode 17 times per electrode 18 times per electrode 19 times per electrode 20 times per electrode 21 times per electrode 22 times per electrode 23 times per electrode 24 times per electrode 25 times per electrode 26 times per electrode 27 times per electrode 28 times per electrode 29 times per electrode 30 times per electrode 31 times per electrode 32 times per electrode Touch Sensing Input Module Enable This bit enables TSI module. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 678 Freescale Semiconductor, Inc. Chapter 39 Touch Sensing Input (TSI) TSIx_GENCS field descriptions (continued) Field Description 0 1 6 TSIIEN Touch Sensing Input Interrupt Enable This bit enables TSI module interrupt request to CPU when the scan completes. The interrupt will wake MCU from low power mode if this interrupt is enabled. 0 1 5 STPE This bit enables TSI module function in low power modes (stop, VLPS, LLS and VLLS{3,2,1}). This bit specifies the trigger mode. User is allowed to change this bit when TSI is not working in progress. This read-only bit indicates if scan is in progress. This bit will get asserted after the analog bias circuit is stable after a trigger and it changes automatically by the TSI. This flag is set when all active electrodes are finished scanning after a scan trigger. Write "1" , when this flag is set, to clear it. Scan not complete. Scan complete. CURSW This bit specifies if the current sources of electrode oscillator and reference oscillator are swapped. 0 1 0 Reserved No scan in progress. Scan in progress. End of Scan Flag 0 1 1 CURSW Software trigger scan. Hardware trigger scan. Scan In Progress Status 0 1 2 EOSF TSI is disabled when MCU goes into low power mode. Allows TSI to continue running in all low power modes. Scan Trigger Mode 0 1 3 SCNIP TSI interrupt is disabled. TSI interrupt is enabled. TSI STOP Enable 0 1 4 STM TSI module disabled. TSI module enabled. The current source pair are not swapped. The current source pair are swapped. This field is reserved. This read-only field is reserved and always has the value 0. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 679 Register definition 39.3.2 TSI DATA Register (TSIx_DATA ) Address: 4004_5000h base + 4h offset = 4004_5004h 31 30 29 28 27 26 25 24 23 0 21 20 19 0 DMAEN R 22 TSICH W 18 17 16 0 SWTS Bit Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TSICNT R W Reset 0 0 0 0 0 0 0 0 0 TSIx_DATA field descriptions Field 31-28 TSICH Description TSICH These bits specify current channel to be measured. In hardware trigger mode (TSI_GENCS[STM] = 1), the scan will not start until the hardware trigger occurs. In software trigger mode (TSI_GENCS[STM] = 0), the scan starts immediately when TSI_DATA[SWTS] bit is written by 1. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Channel 0. Channel 1. Channel 2. Channel 3. Channel 4. Channel 5. Channel 6. Channel 7. Channel 8. Channel 9. Channel 10. Channel 11. Channel 12. Channel 13. Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 680 Freescale Semiconductor, Inc. Chapter 39 Touch Sensing Input (TSI) TSIx_DATA field descriptions (continued) Field Description 1110 1111 27-24 Reserved Channel 14. Channel 15. This field is reserved. This read-only field is reserved and always has the value 0. 23 DMAEN DMA Transfer Enabled This bit is used together with the TSI interrupt enable bits(TSIIE, ESOR) to generate a DMA transfer request instead of an interrupt. 0 1 22 SWTS Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert. DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert. Software Trigger Start This write-only bit is a software start trigger. When STM bit is clear, write "1" to this bit will start a scan. The electrode channel to be scanned is determinated by TSI_DATA[TSICH] bits. 0 1 21-16 Reserved No effect. Start a scan to determine which channel is specified by TSI_DATA[TSICH]. This field is reserved. This read-only field is reserved and always has the value 0. 15-0 TSICNT TSI Conversion Counter Value These read-only bits record the accumulated scan counter value ticked by the reference oscillator. 39.3.3 TSI Threshold Register (TSIx_TSHD) Address: 4004_5000h base + 8h offset = 4004_5008h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 THRESH 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 THRESL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSIx_TSHD field descriptions Field Description 31-16 THRESH TSI Wakeup Channel High-threshold 15-0 THRESL TSI Wakeup Channel Low-threshold This half-word specifies the high threshold of the wakeup channel. This half-word specifies the low threshold of the wakeup channel. 39.4 Functional description KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 681 Functional description 39.4.1 Capacitance measurement The electrode pin capacitance measurement uses a dual oscillator approach. The frequency of the TSI electrode oscillator depends on the external electrode capacitance and the TSI module configuration. After going to a configurable prescaler, the TSI electrode oscillator signal goes to the input of the module counter. The time for the module counter to reach its module value is measured using the TSI reference oscillator. The measured electrode capacitance is directly proportional to the time. 39.4.1.1 TSI electrode oscillator The TSI electrode oscillator circuit is illustrated in the following figure. A configurable constant current source is used to charge and discharge the external electrode capacitance. A buffer hysteresis defines the oscillator delta voltage. The delta voltage defines the margin of high and low voltage which are the reference input of the comparator in different time. Figure 39-8. TSI electrode oscillator circuit The current source applied to the pad capacitance is controlled by the SCANC[EXTCHRG]. The hysteresis delta voltage is defined in the module electrical specifications present in the device Data Sheet. The figure below shows the voltage amplitude waveform of the electrode capacitance charging and discharging with a programmable current. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 682 Freescale Semiconductor, Inc. Chapter 39 Touch Sensing Input (TSI) Electrode Capacitor Charging and Discharging with constant current Electrode Voltage Hysteresis Voltage Delta Time Figure 39-9. TSI electrode oscillator chart The oscillator frequency is give by the following equation Felec I 2 * Celec * V Figure 39-10. Equation 1: TSI electrode oscillator frequency Where: I: constant current Celec: electrode capacitance V: Hysteresis delta voltage So by this equation, for example, an electrode with Celec= 20 pF, with a current source of I = 16 A and V = 600 mV have the following oscillation frequency: Felec 16 A 2 * 20pF * 600mV 0.67MHz Figure 39-11. Equation 2: TSI electrode oscillator frequency The current source is used to accommodate the TSI electrode oscillator frequency with different electrode capacitance sizes. 39.4.1.2 Electrode oscillator and counter module control The TSI oscillator frequency signal goes through a prescaler defined by the GENCS[PS] and then enters in a modulus counter. The bit field GENCS[NSCN] defines the maximum count value of the modulus counter. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 683 Functional description The pin capacitance sampling time is given by the time the module counter takes to go from zero to its maximum value, defined by NSCN. The electrode sample time is expressed by the following equation: Tcap_samp PS * NSCN F elec Using Equation 1. Tcap_samp 2 * PS * NSCN * Celec * V I Figure 39-12. Equation 3: Electrode sampling time Where: PS: prescaler value NSCN: module counter maximum value I: constant current Celec: electrode capacitance V: Hysteresis delta voltage By this equation we have that an electrode with C = 20 pF, with a current source of I = 16 A and V = 600 mV, PS = 2 and NSCN = 16 have the following sampling time: Tcap_samp 2*2*16*20pF*600mV 48s 16A 39.4.1.3 TSI reference oscillator The TSI reference oscillator has the same topology of the TSI electrode oscillator. The TSI reference oscillator instead of using an external capacitor for the electrode oscillator has an internal reference capacitor. The TSI reference oscillator has an independent programmable current source controlled by the SCANC[REFCHRG]. The reference oscillator frequency is given by the following equation: Fref_osc Iref 2 *Cref * V Figure 39-13. Equation 4: TSI reference oscillator frequency Where: KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 684 Freescale Semiconductor, Inc. Chapter 39 Touch Sensing Input (TSI) Cref: Internal reference capacitor Iref: Reference oscillator current source V : Hysteresis delta voltage Considering Cref = 1.0 pF, Iref = 12 A and V = 600 mV, follows Fref_osc 12A 2 *1.0pF * 600mV 10.0MHz 39.4.2 TSI measurement result The capacitance measurement result is defined by the number of TSI reference oscillator periods during the sample time and is stored in the TSICHnCNT register. TSICHnCNT = Tcap_samp * Fref_osc Using Equation 2 and Equation 1 follows: TSICHnCNT Iref * PS *NSCN * Celec Cref * Ielec Figure 39-14. Equation 5: Capacitance result value In the example where Fref_osc = 10.0MHz and Tcap_samp = 48 s, TSICHnCNT = 480 39.4.3 Enable TSI module The TSI module can be fully functional in run, wait and low power modes. The TSI_GENCS[TSIEN] bit must be set to enable the TSI module in run and wait mode. When TSI_GENCS[STPE] bit is set, it allows the TSI module to work in low power mode. 39.4.4 Software and hardware trigger The TSI module allows a software or hardware trigger to start a scan. When a software trigger is applied ( TSI_GENCS[STM] bit clear), the TSI_GENCS[SWTS] bit must be written "1" to start the scan electrode channel that is identified by TSI_DATA[TSICH]. When a hardware trigger is applied ( TSI_GENCS[STM] bit set), the TSI will not start scanning until the hardware trigger arrives. The hardware trigger is different depending on the MCU configuration. Generally, it could be an event that RTC overflows. See chip configuration section for details. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 685 Functional description 39.4.5 Scan times The TSI provides multi-scan function. The number of scans is indicated by the TSI_GENCS[NSCN] bits that allow the scan number from 1 to 32. When TSI_GENCS[NSCN] is set to 0 (only once), the single scan is engaged. The 16-bit counter accumulates all scan results until the NSCN time scan completes, and users can read TSI_DATA[TSICNT] to get this accumulation. When DMA transfer is enabled, the counter values can also be read out by DMA engine. 39.4.6 Clock setting TSI is built with dual oscillator architecture. In normal sensing application, the reference oscillator clock is the only clock source for operations. The reference clock is used to measure the electrode oscillator by ticking a 16-bit counter. The reference oscillator frequency depends on the current source setting. Please refer to the Current source for more details. The output of electrode oscillator has several prescalers up to 128 indicated by TSI_GENCS[PS]bits. This allows a flexible counter configuration for different electrode oscillator frequency. 39.4.7 Reference voltage The TSI module offers a internal reference voltage for both electrode oscillator and reference oscillator. The internal reference voltage can work in low power modes even when the MCU regulator is partially powered down, which is ideally for low-power touch detection. The charge and discharge difference voltage is configurable upon the setting of TSI_GENCS[DVOLT] bits. The following table shows the all the delta voltage configurations.Note this table doesn't apply to noise mode, where the details should be consult form noise modes chapters. Table 39-11. Delta voltage configuration DVOLT Vp (V) Vm (V) V (V) 00 1.328 0.302 1.026 01 1.111 0.519 0.592 10 0.986 0.644 0.342 11 0.914 0.716 0.198 KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 686 Freescale Semiconductor, Inc. Chapter 39 Touch Sensing Input (TSI) 39.4.8 Current source The TSI module supports eight different current source power to increment from 500 nA to 64uA. The TSI_GENCS[EXTCHRG] bits determine the current of electrode oscillator that charges and discharges external electrodes. The TSI_GENCS[REFCHRG] bits determine the current of reference oscillator on which the internal reference clock depends. The lower current source takes more time for charge and discharge, which is useful to detect high-accuracy change. The higher current source takes less time, which can be used to charge a big electrode by less power consumption. The TSI_GENCS[CURSW] bit allows the current source to swap, so that the reference oscillator and electrode oscillator use the opposite current sources. When TSI_GENCS[CURSW] is set and the current sources are swapped, the TSI_GENCS[EXTCHRG] bits and TSI_GENCS[REFCHRG] bits still control the corresponding current sources, that is, TSI_GENCS[EXTCHRG] controls the reference oscillator current and TSI_GENCS[REFCHRG] controls the electrode oscillator current. 39.4.9 End of scan As a scan starts, [SCNIP] bit is set to indicate scan is in progress. When the scan completes, the [EOSF] bit is set. Before clearing the [EOSF] bit, the value in TSI_DATA[TSICNT] must be read. If the TSI_GENCS[TSIIEN] bit is set andTSI_GENCS[DMAEN]is not set, an interrupt is submitted to CPU for postprocessing immediately. The interrupt is also optional to wake MCU to execute ISR if it is in low power mode. When DMA function is enabled by setting TSI_GENCS[TSIIEN] and TSI_GENCS[ESOR], as soon as scan completes, a DMA transfer request is asserted to DMA controller for data movement, generally, DMA engine will fetch TSI conversion result from TSI_DATA register,store it to other memory space and then refresh the TSI scan channel index(TSI_DATA[TSICH]) for next loop. When DMA transfer is done, TSI_GENCS[EOSF] is cleared automatically. 39.4.10 Out-of-range interrupt If enabled, TSI will scan the electrode specified by TSI_DATA[TSICH] as soon as the trigger arrives. The TSI_GENCS[OUTRGF] flag generates a TSI interrupt request if the TSI_GENCS[TSIIE] bit is set and GENCS[ESOR] bit is cleared. With this configuration, after the end-of-electrode scan, the electrode capacitance will be converted and stored to the result register TSI_DATA[TSICNT], the out-of-range interrupt is only requested if KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 687 Functional description there is a considerable capacitance change defined by the TSI_TSHD. For instance, if in low power mode the electrode capacitance does not vary, the out-of-range interrupt does not interrupt the CPU. This interrupt will not happen in noise detection mode. It is worthy to note that when the counter value reaches 0xFFFF is treated as an extreme case the outof-range will not happen. Also in noise detection mode, the out-of-range will not assert either. 39.4.11 Wake up MCU from low power modes In low power modes, once enabled by TSI_GENCS[STPE] and TSI_GENCS[TSIIE], TSI can bring MCU out of its low power modes(STOP, VLPS, VLLS,etc) by either end of scan or out of range interrupt, that is, if TSI_GENCS[ESOR] is set, end of scan interrupt is selected and otherwise, out of range is selected. 39.4.12 DMA function support Transmit by DMA is supported only when TSI_DATA[DMAEN] is set. A DMA transfer request is asserted when all of TSI_GENCS[EOSF], TSI_GENCS[ESOR] and TSI_GENCS[TSIIE] are set. Then the on-chip DMA controller detects this request and transfers data between memory space and TSI register space. After the data tranfer, DMA DONE is asserted to clear TSI_GENCS[EOSF] automatically. This function is normally used by DMA controller to get the conversion result from TSI_DATA[TSICNT] upon a end-of-scan event and then refresh the channel index(TSI_DATA[TSICH]) for next trigger. DMA function is not available when MCU is in stop modes. 39.4.13 Noise detection mode The noise detection mode change the circuit configuration as shown in the following figure. With this configuration, it is possible to detect touch with high levels of EMC noise present. To enter the test mode, see TSIx_GENCS[MODE] register field. In noise detection mode the reference oscillator has the same configuration except the output goes to Counter2 and this counter will have the it's maximum count set by NSCN. 2^(PS). This means this oscillator will setup the noise detection mode sense duration. The blocks of external oscillator is changed and instead of an oscillator the circuit implements an RF amplitude detection. The thrshold for this amplitude detection is set by DVOLT register bits. Also the external voltage is biased by vmid voltage with a Rs series resistance. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 688 Freescale Semiconductor, Inc. Chapter 39 Touch Sensing Input (TSI) The vmid voltage is defined as V(vmid) = (V(vp) + V(vm))/2. The Rs value is defined by i_ext_3v<2:0> register bits. Figure 39-15. TSI circuit in noise detection mode To determine the noise level the below algorithm can be used: 1. Initialize Rs = maxrs; Dvolt = minDv (set other configurations also) 2. Perform a noise cycle. 3. If TSIcounter < 3, go to step 8 4. If Rs = minrs, go to step 6. 5. Reduce value of Rs. go to step 2 6. If Dvolt = maxDv, go to END 7. Increase value of Dvolt. Set Rs = maxrs. go to step 2 8. If Rs > minrs, (Reduce value of Rs, go to END) 9. Rs = maxrs, reduce value of Dvolt. 10. END Get value of Rs and Dvolt. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 689 Functional description One example of noise detection mode is shown in the following figure. in this figure the TSI is working in capacitive mode until 30uS when it is changed to noise detection mode. In noise detection mode the selected pad is biased with 0.815V and all AC waveform in this pad is caused by a noise source external to IC. It is possible to observe in the following figure that, in noise detection mode, the clkref output has the peak detection and the number of detected peaks can be counted or used by digital block. The clkext output has the internal oscillator output and can be used to set the maximum noise detection time window. The waveform of the following figure shows two operations during noise detection mode: * The V(vp) and V(vm) thresholds are changed in 34.4 s. * The Rs series resistance value is changed between 184 k (iext<2:0>=011) and 32 k (iext<2:0>=101). Because of this Rs change the amplitude of noise waveform change also. Figure 39-16. TSI noise detection mode waveform KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 690 Freescale Semiconductor, Inc. Chapter 39 Touch Sensing Input (TSI) 39.4.13.1 Automatic noise mode This mode is set by MODE[3:2] = 11 (noise mode 3). In this mode, the thresholds are incremented internally by the module until the point that there is no noise voltage trepassing the threshold. The following diagram shows how it is done. The threshold comparator output goes to a counter and as the DVOLT control bits are increased the DVOLT thresholds are increased as well. The four bits are counted until 1111 (=15) and the counter is stop with this maximum value. Figure 39-17. Block diagram automatic noise threshold operation The signals that have different behavior in this noise mode (wrt capacitive mode) are shown in the following table. Table 39-12. Signal properties in automatic noise operation mode Name Function MODE[3:2] 11 - Noise mode operation with frequency limitation and automatic threshold counter. I/O type I Power Up/Reset state 00 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 691 Functional description Table 39-12. Signal properties in automatic noise operation mode (continued) Name EXTCHRG[2:1] Function I/O type In this operation mode these I bits select the number of filter bits. Power Up/Reset state 00 00 - 3 filter bits 01 - 2 filter bits 10 - 1 filter bit 11 - no filter bit EXTCHRG[0] In this operation mode this bits selects the series resistance. I 0 0 - uses Rs=32 k 1 - uses Rs=187 k Independent of this bit selection the threshold 15 is done with Rs = 5.5 k DVOLT[1:0] Select voltage rails of the internal oscillator I 00 MODE[3:0] DVOLT counter bits output. O 0000 This register content is reset always the MODE[3:2] is not 11, and after beginning of automatic noise mode operation. 39.4.13.2 Single threshold noise modes These modes reset by MODE[3:2]=01 and 10. The difference between these two modes is that in mode 2 (MODE[3:2]=10) there is a frequency limitation circuit that enables the circuit to operate in higher frequencies. In mode 1 (MODE[3:2]=01) this frequency limitation circuit is not enabled. In this mode the thresholds are set by user via register bits as described in the following table. During these modes the internal oscillator rails are set to the maximum (equivalent to DVOLT[1:0]=00). Table 39-13. Signal properties in single noise modes (1,2) Name MODE[3:2] Function 01 or 10- Single thrshold noise mode operation. I/O type Power up / reset I 00 Table continues on the next page... KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 692 Freescale Semiconductor, Inc. Chapter 39 Touch Sensing Input (TSI) Table 39-13. Signal properties in single noise modes (1,2) (continued) Name DVOLT[1:0], EXTCHRG[2:1] Function In this operation mode these 4 bits are used select the noise threshold. I/O type Power up / reset I XXXX I XX 0000 - DVpm = 0.038 V, Vp = 0.834 V, Vm = 0.796 V 0001 - DVpm = 0.050 V, Vp = 0.830 V, Vm = 0.790 V 0010 - DVpm = 0.066 V, Vp = 0.848 V, Vm = 0.782 V 0011 - DVpm = 0.087 V, Vp = 0.858 V, Vm = 0.772 V 0100 - DVpm = 0.114 V, Vp = 0.872 V, Vm = 0.758 V 0101 - DVpm = 0.150 V, Vp = 0.890 V, Vm = 0.740 V 0110 - DVpm = 0.197 V, Vp = 0.914 V, Vm = 0.716 V 0111 - DVpm = 0.260 V, Vp = 0.945 V, Vm = 0.685 V 1000 - DVpm = 0.342 V, Vp = 0.986 V, Vm = 0.644 V 1001 - DVpm = 0.450 V, Vp = 1.040 V, Vm = 0.590 V 1010 - DVpm = 0.592 V, Vp = 1.111 V, Vm = 0.519 V 1011 - DVpm = 0.780 V, Vp = 1.205 V, Vm = 0.425 V 1100 - DVpm = 1.026 V, Vp = 1.328 V, Vm = 0.302 V 1101 - DVpm = 1.350 V, Vp = 1.490 V, Vm = 0.140 V 1110 - DVpm = 1.630 V, Vp = 1.630 V, Vm = 0 V 1111 - DVpm = 1.630 V, Vp = 1.630 V, Vm = 0 V EXTCHRG[0] In this operation mode this bits selects the series resistance. 0 - uses Rs = 32 k. 1- uses Rs = 187 k. Independent of this bit selection the threshold 15 is done with Rs = 5.5 k. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc. 693 Functional description KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 694 Freescale Semiconductor, Inc. Appendix A Revision History of this Document This appendix describes corrections to the this reference manual for convenience. Grammatical and formatting changes are not listed here unless the meaning of something changed. A.1 Changes between revisions 3.1 and 3 Table A-1. Changes between revisions 3.1 and 3 Chapter A.2 Description Chip Configuration * Added a section of Alternate Clock for ADC. Micro Trace Buffer (MTB) * Updated MTB_POSITION, MTB_MASTER and MTB_FLOW registers and fields descriptions. Changes between revisions 3 and 2 Table A-2. Changes between revisions 3 and 2 Chapter Description Flash Memory Module (FTFA) * Updated register absolute address. 12-bit Digital-to-Analog Converter (DAC) * Updated register absolute address. KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor A-1 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. 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