KL05 Sub-Family Reference Manual
Supports: MKL05Z8VFK4, MKL05Z16VFK4, MKL05Z32VFK4,
MKL05Z8VLC4, MKL05Z16VLC4, MKL05Z32VLC4, MKL05Z8VFM4,
MKL05Z16VFM4, MKL05Z32VFM4, MKL05Z16VLF4, and
MKL05Z32VLF4
Document Number: KL05P48M48SF1RM
Rev. 3.1, November 2012
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................31
1.1.1 Purpose.........................................................................................................................................................31
1.1.2 Audience......................................................................................................................................................31
1.2 Conventions..................................................................................................................................................................31
1.2.1 Numbering systems......................................................................................................................................31
1.2.2 Typographic notation...................................................................................................................................32
1.2.3 Special terms................................................................................................................................................32
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................33
2.2 Kinetis L Series.............................................................................................................................................................33
2.3 KL05 Sub-Family Introduction.....................................................................................................................................36
2.4 Module functional categories........................................................................................................................................37
2.4.1 ARM® Cortex™-M0+ Core Modules.........................................................................................................37
2.4.2 System Modules...........................................................................................................................................38
2.4.3 Memories and Memory Interfaces...............................................................................................................39
2.4.4 Clocks...........................................................................................................................................................39
2.4.5 Security and Integrity modules....................................................................................................................39
2.4.6 Analog modules...........................................................................................................................................40
2.4.7 Timer modules.............................................................................................................................................40
2.4.8 Communication interfaces...........................................................................................................................41
2.4.9 Human-machine interfaces..........................................................................................................................41
2.5 Orderable part numbers.................................................................................................................................................42
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................43
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3.2 Module to Module Interconnects..................................................................................................................................43
3.2.1 Module to Module Interconnects.................................................................................................................43
3.2.2 Analog reference options.............................................................................................................................45
3.3 Core Modules................................................................................................................................................................46
3.3.1 ARM Cortex-M0+ Core Configuration.......................................................................................................46
3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................48
3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................52
3.4 System Modules............................................................................................................................................................53
3.4.1 SIM Configuration.......................................................................................................................................53
3.4.2 System Mode Controller (SMC) Configuration...........................................................................................54
3.4.3 PMC Configuration......................................................................................................................................54
3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................55
3.4.5 MCM Configuration....................................................................................................................................57
3.4.6 Crossbar-Light Switch Configuration..........................................................................................................58
3.4.7 Peripheral Bridge Configuration..................................................................................................................59
3.4.8 DMA request multiplexer configuration......................................................................................................60
3.4.9 DMA Controller Configuration...................................................................................................................63
3.4.10 Computer Operating Properly (COP) Watchdog Configuration..................................................................63
3.5 Clock Modules..............................................................................................................................................................66
3.5.1 MCG Configuration.....................................................................................................................................66
3.5.2 OSC Configuration......................................................................................................................................67
3.6 Memories and Memory Interfaces................................................................................................................................68
3.6.1 Flash Memory Configuration.......................................................................................................................68
3.6.2 Flash Memory Controller Configuration.....................................................................................................70
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3.6.3 SRAM Configuration...................................................................................................................................71
3.7 Analog...........................................................................................................................................................................73
3.7.1 12-bit SAR ADC Configuration..................................................................................................................73
3.7.2 CMP Configuration......................................................................................................................................77
3.7.3 12-bit DAC Configuration...........................................................................................................................79
3.8 Timers...........................................................................................................................................................................80
3.8.1 Timer/PWM Module Configuration............................................................................................................80
3.8.2 PIT Configuration........................................................................................................................................83
3.8.3 Low-power timer configuration...................................................................................................................84
3.8.4 RTC configuration.......................................................................................................................................86
3.9 Communication interfaces............................................................................................................................................87
3.9.1 SPI configuration.........................................................................................................................................87
3.9.2 I2C Configuration........................................................................................................................................88
3.9.3 UART Configuration...................................................................................................................................89
3.10 Human-machine interfaces (HMI)................................................................................................................................91
3.10.1 GPIO Configuration.....................................................................................................................................91
3.10.2 TSI Configuration........................................................................................................................................93
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................95
4.2 System memory map.....................................................................................................................................................95
4.3 Flash Memory Map.......................................................................................................................................................96
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................96
4.4 SRAM memory map.....................................................................................................................................................97
4.5 Bit Manipulation Engine...............................................................................................................................................97
4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................98
4.6.1 Read-after-write sequence and required serialization of memory operations..............................................98
4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map..............................................................................................99
4.6.3 Modules Restricted Access in User Mode...................................................................................................102
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4.7 Private Peripheral Bus (PPB) memory map..................................................................................................................102
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................105
5.2 Programming model......................................................................................................................................................105
5.3 High-Level device clocking diagram............................................................................................................................105
5.4 Clock definitions...........................................................................................................................................................106
5.4.1 Device clock summary.................................................................................................................................107
5.5 Internal clocking requirements.....................................................................................................................................109
5.5.1 Clock divider values after reset....................................................................................................................109
5.5.2 VLPR mode clocking...................................................................................................................................110
5.6 Clock Gating.................................................................................................................................................................110
5.7 Module clocks...............................................................................................................................................................110
5.7.1 PMC 1-kHz LPO clock................................................................................................................................112
5.7.2 COP clocking...............................................................................................................................................112
5.7.3 RTC clocking...............................................................................................................................................112
5.7.4 LPTMR clocking..........................................................................................................................................113
5.7.5 TPM clocking...............................................................................................................................................113
5.7.6 UART clocking............................................................................................................................................114
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................115
6.2 Reset..............................................................................................................................................................................115
6.2.1 Power-on reset (POR)..................................................................................................................................116
6.2.2 System reset sources....................................................................................................................................116
6.2.3 MCU Resets.................................................................................................................................................119
6.2.4 Reset Pin .....................................................................................................................................................120
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6.2.5 Debug resets.................................................................................................................................................121
6.3 Boot...............................................................................................................................................................................122
6.3.1 Boot sources.................................................................................................................................................122
6.3.2 FOPT boot options.......................................................................................................................................122
6.3.3 Boot sequence..............................................................................................................................................123
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................125
7.2 Clocking Modes............................................................................................................................................................125
7.2.1 Partial Stop...................................................................................................................................................125
7.2.2 DMA Wakeup..............................................................................................................................................126
7.2.3 Compute Operation......................................................................................................................................127
7.2.4 Peripheral Doze............................................................................................................................................128
7.2.5 Clock Gating................................................................................................................................................129
7.3 Power modes.................................................................................................................................................................129
7.4 Entering and exiting power modes...............................................................................................................................131
7.5 Module Operation in Low Power Modes......................................................................................................................131
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................135
8.2 Flash Security...............................................................................................................................................................135
8.3 Security Interactions with other Modules.....................................................................................................................135
8.3.1 Security Interactions with Debug.................................................................................................................136
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................137
9.2 Debug Port Pin Descriptions.........................................................................................................................................137
9.3 SWD status and control registers..................................................................................................................................138
9.3.1 MDM-AP Control Register..........................................................................................................................139
9.3.2 MDM-AP Status Register............................................................................................................................140
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9.4 Debug Resets................................................................................................................................................................142
9.5 Micro Trace Buffer (MTB)...........................................................................................................................................143
9.6 Debug in Low Power Modes........................................................................................................................................143
9.7 Debug & Security.........................................................................................................................................................143
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................145
10.2 Signal Multiplexing Integration....................................................................................................................................145
10.2.1 Port control and interrupt module features..................................................................................................146
10.2.2 Clock gating.................................................................................................................................................147
10.2.3 Signal multiplexing constraints....................................................................................................................147
10.3 Pinout............................................................................................................................................................................147
10.3.1 KL05 signal multiplexing and pin assignments...........................................................................................147
10.3.2 KL05 Pinouts...............................................................................................................................................149
10.4 Module Signal Description Tables................................................................................................................................153
10.4.1 Core Modules...............................................................................................................................................153
10.4.2 System Modules...........................................................................................................................................154
10.4.3 Clock Modules.............................................................................................................................................154
10.4.4 Memories and Memory Interfaces...............................................................................................................154
10.4.5 Analog..........................................................................................................................................................154
10.4.6 Timer Modules.............................................................................................................................................155
10.4.7 Communication Interfaces...........................................................................................................................156
10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................156
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................159
11.2 Overview.......................................................................................................................................................................159
11.2.1 Features........................................................................................................................................................159
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11.2.2 Modes of operation......................................................................................................................................160
11.3 External signal description............................................................................................................................................160
11.4 Detailed signal description............................................................................................................................................161
11.5 Memory map and register definition.............................................................................................................................161
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................164
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................166
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................167
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................167
11.6 Functional description...................................................................................................................................................168
11.6.1 Pin control....................................................................................................................................................168
11.6.2 Global pin control........................................................................................................................................169
11.6.3 External interrupts........................................................................................................................................169
Chapter 12
System integration module (SIM)
12.1 Introduction...................................................................................................................................................................171
12.1.1 Features........................................................................................................................................................171
12.2 Memory map and register definition.............................................................................................................................171
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................173
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................173
12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................174
12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................176
12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................177
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................178
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................180
12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................182
12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................183
12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................185
12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................186
12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................187
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12.2.13 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................189
12.2.14 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................190
12.2.15 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................191
12.2.16 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................191
12.2.17 Unique Identification Register Low (SIM_UIDL)......................................................................................192
12.2.18 COP Control Register (SIM_COPC)...........................................................................................................192
12.2.19 Service COP Register (SIM_SRVCOP)......................................................................................................193
12.3 Functional description...................................................................................................................................................194
Chapter 13
System Mode Controller (SMC)
13.1 Introduction...................................................................................................................................................................195
13.2 Modes of operation.......................................................................................................................................................195
13.3 Memory map and register descriptions.........................................................................................................................197
13.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................197
13.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................199
13.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................200
13.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................201
13.4 Functional description...................................................................................................................................................202
13.4.1 Power mode transitions................................................................................................................................202
13.4.2 Power mode entry/exit sequencing..............................................................................................................205
13.4.3 Run modes....................................................................................................................................................207
13.4.4 Wait modes..................................................................................................................................................209
13.4.5 Stop modes...................................................................................................................................................210
13.4.6 Debug in low power modes.........................................................................................................................213
Chapter 14
Power Management Controller (PMC)
14.1 Introduction...................................................................................................................................................................215
14.2 Features.........................................................................................................................................................................215
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14.3 Low-voltage detect (LVD) system................................................................................................................................215
14.3.1 LVD reset operation.....................................................................................................................................216
14.3.2 LVD interrupt operation...............................................................................................................................216
14.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................216
14.4 I/O retention..................................................................................................................................................................217
14.5 Memory map and register descriptions.........................................................................................................................217
14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................218
14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................219
14.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................220
Chapter 15
Low-Leakage Wakeup Unit (LLWU)
15.1 Introduction...................................................................................................................................................................223
15.1.1 Features........................................................................................................................................................223
15.1.2 Modes of operation......................................................................................................................................224
15.1.3 Block diagram..............................................................................................................................................225
15.2 LLWU signal descriptions............................................................................................................................................226
15.3 Memory map/register definition...................................................................................................................................226
15.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................227
15.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................228
15.3.3 LLWU Module Enable register (LLWU_ME)............................................................................................229
15.3.4 LLWU Flag 1 register (LLWU_F1).............................................................................................................231
15.3.5 LLWU Flag 3 register (LLWU_F3).............................................................................................................232
15.3.6 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................234
15.3.7 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................235
15.4 Functional description...................................................................................................................................................236
15.4.1 LLS mode.....................................................................................................................................................237
15.4.2 VLLS modes................................................................................................................................................237
15.4.3 Initialization.................................................................................................................................................237
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Chapter 16
Reset Control Module (RCM)
16.1 Introduction...................................................................................................................................................................239
16.2 Reset memory map and register descriptions...............................................................................................................239
16.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................239
16.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................241
16.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................242
16.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................243
Chapter 17
Bit Manipulation Engine (BME)
17.1 Introduction...................................................................................................................................................................245
17.1.1 Overview......................................................................................................................................................246
17.1.2 Features........................................................................................................................................................246
17.1.3 Modes of Operation.....................................................................................................................................247
17.2 External Signal Description..........................................................................................................................................247
17.3 Memory Map and Register Definition..........................................................................................................................248
17.4 Functional Description..................................................................................................................................................248
17.4.1 BME Decorated Stores.................................................................................................................................248
17.4.2 BME Decorated Loads.................................................................................................................................254
17.4.3 Additional Details on Decorated Addresses and GPIO Accesses................................................................261
17.5 Application Information................................................................................................................................................262
Chapter 18
Miscellaneous Control Module (MCM)
18.1 Introduction...................................................................................................................................................................265
18.1.1 Features........................................................................................................................................................265
18.2 Memory map/register descriptions...............................................................................................................................265
18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................266
18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................267
18.2.3 Platform Control Register (MCM_PLACR)................................................................................................267
18.2.4 Compute Operation Control Register (MCM_CPO)...................................................................................270
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Chapter 19
Micro Trace Buffer (MTB)
19.1 Introduction...................................................................................................................................................................273
19.1.1 Overview......................................................................................................................................................273
19.1.2 Features........................................................................................................................................................276
19.1.3 Modes of Operation.....................................................................................................................................277
19.2 External Signal Description..........................................................................................................................................277
19.3 Memory Map and Register Definition..........................................................................................................................278
19.3.1 MTB_RAM Memory Map...........................................................................................................................278
19.3.2 MTB_DWT Memory Map...........................................................................................................................291
19.3.3 System ROM Memory Map.........................................................................................................................301
Chapter 20
Crossbar Switch Lite (AXBS-Lite)
20.1 Introduction...................................................................................................................................................................307
20.1.1 Features........................................................................................................................................................307
20.2 Memory Map / Register Definition...............................................................................................................................307
20.3 Functional Description..................................................................................................................................................308
20.3.1 General operation.........................................................................................................................................308
20.3.2 Arbitration....................................................................................................................................................309
20.4 Initialization/application information...........................................................................................................................310
Chapter 21
Peripheral Bridge (AIPS-Lite)
21.1 Introduction...................................................................................................................................................................311
21.1.1 Features........................................................................................................................................................311
21.1.2 General operation.........................................................................................................................................311
21.2 Functional description...................................................................................................................................................312
21.2.1 Access support.............................................................................................................................................312
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Chapter 22
Direct Memory Access Multiplexer (DMAMUX)
22.1 Introduction...................................................................................................................................................................313
22.1.1 Overview......................................................................................................................................................313
22.1.2 Features........................................................................................................................................................314
22.1.3 Modes of operation......................................................................................................................................314
22.2 External signal description............................................................................................................................................315
22.3 Memory map/register definition...................................................................................................................................315
22.3.1 Channel Configuration register (DMAMUXx_CHCFGn)..........................................................................315
22.4 Functional description...................................................................................................................................................316
22.4.1 DMA channels with periodic triggering capability......................................................................................317
22.4.2 DMA channels with no triggering capability...............................................................................................319
22.4.3 Always-enabled DMA sources....................................................................................................................319
22.5 Initialization/application information...........................................................................................................................320
22.5.1 Reset.............................................................................................................................................................320
22.5.2 Enabling and configuring sources................................................................................................................320
Chapter 23
DMA Controller Module
23.1 Introduction...................................................................................................................................................................325
23.1.1 Overview......................................................................................................................................................325
23.1.2 Features........................................................................................................................................................326
23.2 DMA Transfer Overview..............................................................................................................................................327
23.3 Memory Map and Registers..........................................................................................................................................328
23.3.1 Source Address Register (DMA_SARn).....................................................................................................329
23.3.2 Destination Address Register (DMA_DARn).............................................................................................330
23.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn).............................................................331
23.3.4 DMA Control Register (DMA_DCRn)........................................................................................................333
23.4 Functional Description..................................................................................................................................................337
23.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)............................................................................337
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23.4.2 Channel Initialization and Startup................................................................................................................337
23.4.3 Dual-Address Data Transfer Mode..............................................................................................................339
23.4.4 Advanced Data Transfer Controls: Auto-Alignment...................................................................................340
23.4.5 Termination..................................................................................................................................................341
Chapter 24
Multipurpose Clock Generator (MCG)
24.1 Introduction...................................................................................................................................................................343
24.1.1 Features........................................................................................................................................................343
24.1.2 Modes of Operation.....................................................................................................................................345
24.2 External Signal Description..........................................................................................................................................346
24.3 Memory Map/Register Definition.................................................................................................................................346
24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................346
24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................348
24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................349
24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................349
24.3.5 MCG Control 6 Register (MCG_C6)...........................................................................................................351
24.3.6 MCG Status Register (MCG_S)..................................................................................................................351
24.3.7 MCG Status and Control Register (MCG_SC)............................................................................................352
24.3.8 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................354
24.3.9 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................354
24.4 Functional Description..................................................................................................................................................354
24.4.1 MCG mode state diagram............................................................................................................................354
24.4.2 Low Power Bit Usage..................................................................................................................................358
24.4.3 MCG Internal Reference Clocks..................................................................................................................358
24.4.4 External Reference Clock............................................................................................................................359
24.4.5 MCG Fixed frequency clock .......................................................................................................................359
24.4.6 MCG Auto TRIM (ATM)............................................................................................................................359
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24.5 Initialization / Application information........................................................................................................................361
24.5.1 MCG module initialization sequence...........................................................................................................361
24.5.2 Using a 32.768 kHz reference......................................................................................................................363
24.5.3 MCG mode switching..................................................................................................................................364
Chapter 25
Oscillator (OSC)
25.1 Introduction...................................................................................................................................................................371
25.2 Features and Modes......................................................................................................................................................371
25.3 Block Diagram..............................................................................................................................................................372
25.4 OSC Signal Descriptions..............................................................................................................................................372
25.5 External Crystal / Resonator Connections....................................................................................................................373
25.6 External Clock Connections.........................................................................................................................................374
25.7 Memory Map/Register Definitions...............................................................................................................................375
25.7.1 OSC Memory Map/Register Definition.......................................................................................................375
25.8 Functional Description..................................................................................................................................................376
25.8.1 OSC Module States......................................................................................................................................376
25.8.2 OSC Module Modes.....................................................................................................................................378
25.8.3 Counter.........................................................................................................................................................379
25.8.4 Reference Clock Pin Requirements.............................................................................................................379
25.9 Reset..............................................................................................................................................................................380
25.10 Low Power Modes Operation.......................................................................................................................................380
25.11 Interrupts.......................................................................................................................................................................380
Chapter 26
Flash Memory Controller (FMC)
26.1 Introduction...................................................................................................................................................................381
26.1.1 Overview......................................................................................................................................................381
26.1.2 Features........................................................................................................................................................381
26.2 Modes of operation.......................................................................................................................................................382
26.3 External signal description............................................................................................................................................382
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26.4 Memory map and register descriptions.........................................................................................................................382
26.5 Functional description...................................................................................................................................................382
Chapter 27
Flash Memory Module (FTFA)
27.1 Introduction...................................................................................................................................................................385
27.1.1 Features........................................................................................................................................................386
27.1.2 Block Diagram.............................................................................................................................................386
27.1.3 Glossary.......................................................................................................................................................387
27.2 External Signal Description..........................................................................................................................................388
27.3 Memory Map and Registers..........................................................................................................................................388
27.3.1 Flash Configuration Field Description.........................................................................................................388
27.3.2 Program Flash IFR Map...............................................................................................................................389
27.3.3 Register Descriptions...................................................................................................................................390
27.4 Functional Description..................................................................................................................................................398
27.4.1 Flash Protection............................................................................................................................................399
27.4.2 Interrupts......................................................................................................................................................399
27.4.3 Flash Operation in Low-Power Modes........................................................................................................400
27.4.4 Functional Modes of Operation...................................................................................................................400
27.4.5 Flash Reads and Ignored Writes..................................................................................................................400
27.4.6 Read While Write (RWW)...........................................................................................................................401
27.4.7 Flash Program and Erase..............................................................................................................................401
27.4.8 Flash Command Operations.........................................................................................................................401
27.4.9 Margin Read Commands.............................................................................................................................406
27.4.10 Flash Command Description........................................................................................................................407
27.4.11 Security........................................................................................................................................................420
27.4.12 Reset Sequence............................................................................................................................................422
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Chapter 28
Analog-to-Digital Converter (ADC)
28.1 Introduction...................................................................................................................................................................423
28.1.1 Features........................................................................................................................................................423
28.1.2 Block diagram..............................................................................................................................................424
28.2 ADC Signal Descriptions..............................................................................................................................................425
28.2.1 Analog Power (VDDA)...............................................................................................................................426
28.2.2 Analog Ground (VSSA)...............................................................................................................................426
28.2.3 Voltage Reference Select.............................................................................................................................426
28.2.4 Analog Channel Inputs (ADx).....................................................................................................................427
28.3 Register definition.........................................................................................................................................................427
28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................428
28.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................431
28.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................433
28.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................434
28.3.5 Compare Value Registers (ADCx_CVn).....................................................................................................435
28.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................436
28.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................438
28.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................439
28.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................440
28.3.10 ADC Plus-Side General Calibration Value Register (ADCx_CLPD).........................................................440
28.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................441
28.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)..........................................................441
28.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)..........................................................442
28.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)..........................................................442
28.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)..........................................................443
28.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)..........................................................443
28.4 Functional description...................................................................................................................................................444
28.4.1 Clock select and divide control....................................................................................................................444
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28.4.2 Voltage reference selection..........................................................................................................................445
28.4.3 Hardware trigger and channel selects..........................................................................................................445
28.4.4 Conversion control.......................................................................................................................................446
28.4.5 Automatic compare function........................................................................................................................453
28.4.6 Calibration function.....................................................................................................................................455
28.4.7 User-defined offset function........................................................................................................................456
28.4.8 Temperature sensor......................................................................................................................................457
28.4.9 MCU wait mode operation...........................................................................................................................458
28.4.10 MCU Normal Stop mode operation.............................................................................................................458
28.4.11 MCU Low-Power Stop mode operation......................................................................................................459
28.5 Initialization information..............................................................................................................................................460
28.5.1 ADC module initialization example............................................................................................................460
28.6 Application information................................................................................................................................................462
28.6.1 External pins and routing.............................................................................................................................462
28.6.2 Sources of error............................................................................................................................................464
Chapter 29
Comparator (CMP)
29.1 Introduction...................................................................................................................................................................469
29.2 CMP features................................................................................................................................................................469
29.3 6-bit DAC key features.................................................................................................................................................470
29.4 ANMUX key features...................................................................................................................................................471
29.5 CMP, DAC and ANMUX diagram...............................................................................................................................471
29.6 CMP block diagram......................................................................................................................................................472
29.7 Memory map/register definitions..................................................................................................................................474
29.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................474
29.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................475
29.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................477
29.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................477
29.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................478
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29.7.6 MUX Control Register (CMPx_MUXCR)..................................................................................................479
29.8 Functional description...................................................................................................................................................480
29.8.1 CMP functional modes.................................................................................................................................480
29.8.2 Power modes................................................................................................................................................489
29.8.3 Startup and operation...................................................................................................................................490
29.8.4 Low-pass filter.............................................................................................................................................490
29.9 CMP interrupts..............................................................................................................................................................493
29.10 DMA support................................................................................................................................................................493
29.11 CMP Asyncrhonous DMA support...............................................................................................................................493
29.12 Digital-to-analog converter...........................................................................................................................................494
29.13 DAC functional description..........................................................................................................................................494
29.13.1 Voltage reference source select....................................................................................................................494
29.14 DAC resets....................................................................................................................................................................495
29.15 DAC clocks...................................................................................................................................................................495
29.16 DAC interrupts..............................................................................................................................................................495
29.17 CMP Trigger Mode.......................................................................................................................................................495
Chapter 30
12-bit Digital-to-Analog Converter (DAC)
30.1 Introduction...................................................................................................................................................................497
30.2 Features.........................................................................................................................................................................497
30.3 Block diagram...............................................................................................................................................................497
30.4 Memory map/register definition...................................................................................................................................498
30.4.1 DAC Data Low Register (DACx_DATnL).................................................................................................499
30.4.2 DAC Data High Register (DACx_DATnH)................................................................................................499
30.4.3 DAC Status Register (DACx_SR)...............................................................................................................500
30.4.4 DAC Control Register (DACx_C0).............................................................................................................500
30.4.5 DAC Control Register 1 (DACx_C1)..........................................................................................................502
30.4.6 DAC Control Register 2 (DACx_C2)..........................................................................................................502
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30.5 Functional description...................................................................................................................................................503
30.5.1 DAC data buffer operation...........................................................................................................................503
30.5.2 DMA operation............................................................................................................................................504
30.5.3 Resets...........................................................................................................................................................504
30.5.4 Low-Power mode operation.........................................................................................................................504
Chapter 31
Timer/PWM Module (TPM)
31.1 Introduction...................................................................................................................................................................507
31.1.1 TPM Philosophy..........................................................................................................................................507
31.1.2 Features........................................................................................................................................................507
31.1.3 Modes of Operation.....................................................................................................................................508
31.1.4 Block Diagram.............................................................................................................................................508
31.2 TPM Signal Descriptions..............................................................................................................................................509
31.2.1 TPM_EXTCLK — TPM External Clock....................................................................................................509
31.2.2 TPM_CHn — TPM Channel (n) I/O Pin.....................................................................................................510
31.3 Memory Map and Register Definition..........................................................................................................................510
31.3.1 Status and Control (TPMx_SC)...................................................................................................................512
31.3.2 Counter (TPMx_CNT).................................................................................................................................513
31.3.3 Modulo (TPMx_MOD)................................................................................................................................514
31.3.4 Channel (n) Status and Control (TPMx_CnSC)...........................................................................................515
31.3.5 Channel (n) Value (TPMx_CnV).................................................................................................................517
31.3.6 Capture and Compare Status (TPMx_STATUS).........................................................................................517
31.3.7 Configuration (TPMx_CONF).....................................................................................................................519
31.4 Functional Description..................................................................................................................................................521
31.4.1 Clock Domains.............................................................................................................................................521
31.4.2 Prescaler.......................................................................................................................................................522
31.4.3 Counter.........................................................................................................................................................522
31.4.4 Input Capture Mode.....................................................................................................................................524
31.4.5 Output Compare Mode.................................................................................................................................525
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31.4.6 Edge-Aligned PWM (EPWM) Mode...........................................................................................................526
31.4.7 Center-Aligned PWM (CPWM) Mode........................................................................................................528
31.4.8 Registers Updated from Write Buffers........................................................................................................530
31.4.9 DMA............................................................................................................................................................530
31.4.10 Reset Overview............................................................................................................................................531
31.4.11 TPM Interrupts.............................................................................................................................................531
Chapter 32
Periodic Interrupt Timer (PIT-RTI)
32.1 Introduction...................................................................................................................................................................533
32.1.1 Block diagram..............................................................................................................................................533
32.1.2 Features........................................................................................................................................................534
32.2 Signal description..........................................................................................................................................................534
32.3 Memory map/register description.................................................................................................................................535
32.3.1 PIT Module Control Register (PIT_MCR)..................................................................................................535
32.3.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)...............................................................................537
32.3.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)...............................................................................537
32.3.4 Timer Load Value Register (PIT_LDVALn)...............................................................................................538
32.3.5 Current Timer Value Register (PIT_CVALn).............................................................................................538
32.3.6 Timer Control Register (PIT_TCTRLn)......................................................................................................539
32.3.7 Timer Flag Register (PIT_TFLGn)..............................................................................................................540
32.4 Functional description...................................................................................................................................................540
32.4.1 General operation.........................................................................................................................................540
32.4.2 Interrupts......................................................................................................................................................542
32.4.3 Chained timers.............................................................................................................................................542
32.5 Initialization and application information.....................................................................................................................542
32.6 Example configuration for chained timers....................................................................................................................543
32.7 Example configuration for the lifetime timer...............................................................................................................544
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Chapter 33
Low-Power Timer (LPTMR)
33.1 Introduction...................................................................................................................................................................547
33.1.1 Features........................................................................................................................................................547
33.1.2 Modes of operation......................................................................................................................................547
33.2 LPTMR signal descriptions..........................................................................................................................................548
33.2.1 Detailed signal descriptions.........................................................................................................................548
33.3 Memory map and register definition.............................................................................................................................548
33.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)......................................................................549
33.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)................................................................................550
33.3.3 Low Power Timer Compare Register (LPTMRx_CMR).............................................................................552
33.3.4 Low Power Timer Counter Register (LPTMRx_CNR)...............................................................................552
33.4 Functional description...................................................................................................................................................553
33.4.1 LPTMR power and reset..............................................................................................................................553
33.4.2 LPTMR clocking..........................................................................................................................................553
33.4.3 LPTMR prescaler/glitch filter......................................................................................................................553
33.4.4 LPTMR compare..........................................................................................................................................555
33.4.5 LPTMR counter...........................................................................................................................................555
33.4.6 LPTMR hardware trigger.............................................................................................................................556
33.4.7 LPTMR interrupt..........................................................................................................................................556
Chapter 34
Real Time Clock (RTC)
34.1 Introduction...................................................................................................................................................................557
34.1.1 Features........................................................................................................................................................557
34.1.2 Modes of operation......................................................................................................................................557
34.1.3 RTC Signal Descriptions.............................................................................................................................557
34.2 Register definition.........................................................................................................................................................558
34.2.1 RTC Time Seconds Register (RTC_TSR)...................................................................................................559
34.2.2 RTC Time Prescaler Register (RTC_TPR)..................................................................................................559
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34.2.3 RTC Time Alarm Register (RTC_TAR).....................................................................................................560
34.2.4 RTC Time Compensation Register (RTC_TCR).........................................................................................560
34.2.5 RTC Control Register (RTC_CR)................................................................................................................561
34.2.6 RTC Status Register (RTC_SR)..................................................................................................................563
34.2.7 RTC Lock Register (RTC_LR)....................................................................................................................564
34.2.8 RTC Interrupt Enable Register (RTC_IER).................................................................................................565
34.3 Functional description...................................................................................................................................................566
34.3.1 Power, clocking, and reset...........................................................................................................................566
34.3.2 Time counter................................................................................................................................................567
34.3.3 Compensation...............................................................................................................................................567
34.3.4 Time alarm...................................................................................................................................................568
34.3.5 Update mode................................................................................................................................................568
34.3.6 Register lock................................................................................................................................................569
34.3.7 Interrupt........................................................................................................................................................569
Chapter 35
Serial Peripheral Interface (SPI)
35.1 Introduction...................................................................................................................................................................571
35.1.1 Features........................................................................................................................................................571
35.1.2 Modes of Operation.....................................................................................................................................572
35.1.3 Block Diagrams............................................................................................................................................573
35.2 External Signal Description..........................................................................................................................................575
35.2.1 SPSCK — SPI Serial Clock.........................................................................................................................575
35.2.2 MOSI — Master Data Out, Slave Data In...................................................................................................576
35.2.3 MISO — Master Data In, Slave Data Out...................................................................................................576
35.2.4 SS — Slave Select........................................................................................................................................576
35.3 Memory Map and Register Descriptions......................................................................................................................577
35.3.1 SPI control register 1 (SPIx_C1)..................................................................................................................577
35.3.2 SPI control register 2 (SPIx_C2)..................................................................................................................579
35.3.3 SPI baud rate register (SPIx_BR).................................................................................................................580
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35.3.4 SPI status register (SPIx_S).........................................................................................................................581
35.3.5 SPI data register (SPIx_D)...........................................................................................................................582
35.3.6 SPI match register (SPIx_M).......................................................................................................................583
35.4 Functional Description..................................................................................................................................................584
35.4.1 General.........................................................................................................................................................584
35.4.2 Master Mode................................................................................................................................................584
35.4.3 Slave Mode..................................................................................................................................................586
35.4.4 SPI Transmission by DMA..........................................................................................................................587
35.4.5 SPI Clock Formats.......................................................................................................................................589
35.4.6 SPI Baud Rate Generation...........................................................................................................................592
35.4.7 Special Features...........................................................................................................................................592
35.4.8 Error Conditions...........................................................................................................................................594
35.4.9 Low Power Mode Options...........................................................................................................................595
35.4.10 Reset.............................................................................................................................................................596
35.4.11 Interrupts......................................................................................................................................................597
35.5 Initialization/Application Information..........................................................................................................................598
35.5.1 Initialization Sequence.................................................................................................................................598
35.5.2 Pseudo-Code Example.................................................................................................................................599
Chapter 36
Inter-Integrated Circuit (I2C)
36.1 Introduction...................................................................................................................................................................603
36.1.1 Features........................................................................................................................................................603
36.1.2 Modes of operation......................................................................................................................................604
36.1.3 Block diagram..............................................................................................................................................604
36.2 I2C signal descriptions..................................................................................................................................................605
36.3 Memory map and register descriptions.........................................................................................................................605
36.3.1 I2C Address Register 1 (I2Cx_A1)..............................................................................................................606
36.3.2 I2C Frequency Divider register (I2Cx_F)....................................................................................................607
36.3.3 I2C Control Register 1 (I2Cx_C1)...............................................................................................................608
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36.3.4 I2C Status register (I2Cx_S)........................................................................................................................609
36.3.5 I2C Data I/O register (I2Cx_D)...................................................................................................................611
36.3.6 I2C Control Register 2 (I2Cx_C2)...............................................................................................................612
36.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT).......................................................................613
36.3.8 I2C Range Address register (I2Cx_RA)......................................................................................................614
36.3.9 I2C SMBus Control and Status register (I2Cx_SMB).................................................................................615
36.3.10 I2C Address Register 2 (I2Cx_A2)..............................................................................................................616
36.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................617
36.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................617
36.4 Functional description...................................................................................................................................................617
36.4.1 I2C protocol.................................................................................................................................................617
36.4.2 10-bit address...............................................................................................................................................623
36.4.3 Address matching.........................................................................................................................................624
36.4.4 System management bus specification........................................................................................................625
36.4.5 Resets...........................................................................................................................................................628
36.4.6 Interrupts......................................................................................................................................................628
36.4.7 Programmable input glitch filter..................................................................................................................630
36.4.8 Address matching wakeup...........................................................................................................................631
36.4.9 DMA support...............................................................................................................................................631
36.5 Initialization/application information...........................................................................................................................632
Chapter 37
Universal Asynchronous Receiver/Transmitter (UART0)
37.1 Introduction...................................................................................................................................................................635
37.1.1 Features........................................................................................................................................................635
37.1.2 Modes of operation......................................................................................................................................636
37.1.3 Block diagram..............................................................................................................................................636
37.2 Register definition.........................................................................................................................................................638
37.2.1 UART Baud Rate Register High (UARTx_BDH).......................................................................................639
37.2.2 UART Baud Rate Register Low (UARTx_BDL)........................................................................................640
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37.2.3 UART Control Register 1 (UARTx_C1).....................................................................................................640
37.2.4 UART Control Register 2 (UARTx_C2).....................................................................................................642
37.2.5 UART Status Register 1 (UARTx_S1)........................................................................................................643
37.2.6 UART Status Register 2 (UARTx_S2)........................................................................................................645
37.2.7 UART Control Register 3 (UARTx_C3).....................................................................................................647
37.2.8 UART Data Register (UARTx_D)...............................................................................................................648
37.2.9 UART Match Address Registers 1 (UARTx_MA1)....................................................................................649
37.2.10 UART Match Address Registers 2 (UARTx_MA2)....................................................................................650
37.2.11 UART Control Register 4 (UARTx_C4).....................................................................................................650
37.2.12 UART Control Register 5 (UARTx_C5).....................................................................................................651
37.3 Functional description...................................................................................................................................................652
37.3.1 Baud rate generation....................................................................................................................................652
37.3.2 Transmitter functional description...............................................................................................................652
37.3.3 Receiver functional description...................................................................................................................654
37.3.4 Additional UART functions.........................................................................................................................657
37.3.5 Interrupts and status flags............................................................................................................................659
Chapter 38
General-Purpose Input/Output (GPIO)
38.1 Introduction...................................................................................................................................................................661
38.1.1 Features........................................................................................................................................................661
38.1.2 Modes of operation......................................................................................................................................661
38.1.3 GPIO signal descriptions.............................................................................................................................662
38.2 Memory map and register definition.............................................................................................................................663
38.2.1 Port Data Output Register (GPIOx_PDOR).................................................................................................664
38.2.2 Port Set Output Register (GPIOx_PSOR)....................................................................................................665
38.2.3 Port Clear Output Register (GPIOx_PCOR)................................................................................................665
38.2.4 Port Toggle Output Register (GPIOx_PTOR).............................................................................................666
38.2.5 Port Data Input Register (GPIOx_PDIR).....................................................................................................666
38.2.6 Port Data Direction Register (GPIOx_PDDR).............................................................................................667
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