LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
ICS853011C
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 1
ICS853011CM REV. A JUNE 12, 2007
General Description
The ICS853011C is a low skew, high performance
1-to-2 Differential-to-2.5V, 3.3V LVPECL/ECL
Fanout Buffer and a member of the HiPerClockS ™
family of High Performance Clock Solutions from
IDT. The ICS853011C is characterized to operate
from either a 2.5V or a 3.3V power supply. Guaranteed output and
part-to-part skew characteristics make the ICS853011C ideal for
those clock distribution applications demanding well defined
performance and repeatability.
Features
•Two differential 2.5V or 3.3V LVPECL/ECL outputs
•One differential PCLK, nPCLK input pair
•PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, LVDS, CML, SSTL
•Output frequency: >2.5GHz
•Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
•Additive phase jitter, RMS: 0.16ps (typical)
•Output skew: 15ps (maximum)
•Part-to-part skew: 130ps (maximum)
•Propagation delay: 330ps (maximum)
•LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
•ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
•-40°C to 85°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
HiPerClockS™
ICS
Q0
nQ0
PCLK
nPCLK
Q1
nQ1
Pullup/Pulldown
Pulldown
ICS853011C
8 Lead SOIC
3.90mm x 4.90mm x 1.37mm
package body
M Package
Top View
ICS853011C
8 Lead TSSOP, 118mil
3.0mm x 3.0mm x 0.97
package body
G Package
Top View
1
2
3
4
8
7
6
5
Q0
nQ0
Q1
nQ1
VCC
PCLK
nPCLK
VEE
Pin Assignment
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 2
ICS853011CM REV. A JUNE 12, 2007
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2 Q0, nQ0 Output Differential output pair. LVPECL/ECL interface levels.
3, 4 Q1, nQ1 Output Differential output pair. LVPECL/ECL interface levels.
5V
EE Power Negative supply pin.
6nPCLKInput
Pullup/
Pulldown Inverting differential LVPECL clock input. VCC/2 default when left floating.
7 PCLK Input Pulldown Non-inverting differential LVPECL clock input.
8V
CC Power Positive supply pin.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
RPULLUP Input Pullup Resistor 37 kΩ
RPULLDOWN Input Pulldown Resistor 75 kΩ
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 3
ICS853011CM REV. A JUNE 12, 2007
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Item Rating
Supply Voltage, VCC 4.6V (LVPECL mode, VEE = 0V)
Negative Supply Voltage, VEE -4.6V (ECL mode, VCC = 0V)
Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V
Inputs, VI (ECL mode) 0.5V to VEE – 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Operating Temperature Range, TA-40°C to 85°C
Storage Temperature, TSTG -65°C to 150°C
Package Thermal Impedance, θJA
(Junction-to-Ambient) for 8 Lead SOIC
112.7°C/W (0 lfpm)
Package Thermal Impedance, θJA
(Junction-to-Ambient) for 8 Lead TSSOP
101.7°C/W (0 mps)
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Positive Supply Voltage 2.375 3.3 3.8 V
IEE Power Supply Current 24 mA
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 4
ICS853011CM REV. A JUNE 12, 2007
Table 3B. LVPECL DC Characteristics, VCC = 3.3V; VEE = 0V, TA = -40°C to 85°C
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
Table 3C. LVPECL DC Characteristics, VCC = 2.5V; VEE = 0V, TA = -40°C to 85°C
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
Symbol Parameter
-40°C 25°C 80°C
UnitsMin Typ Max Min Typ Max Min Typ Max
VOH Output High Current; NOTE 1 2.175 2.275 2.38 2.225 2.295 2.37 2.22 2.295 2.365 V
VOL Output Low Current; NOTE 1 1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63 V
VPP Peak-to-Peak Input Voltage 150 800 1200 150 800 1200 150 800 1200 V
VCMR
Input High Voltage Common
Mode Range; NOTE 2, 3 1.2 3.3 1.2 3.3 1.2 3.3 V
IIH
Input
High Current PCLK/nPCLK 150 150 150 µA
IIL
Input
Low Current
PCLK -10 -10 -10 µA
nPCLK -150 -150 -150 µA
Symbol Parameter
-40°C 25°C 80°C
UnitsMin Typ Max Min Typ Max Min Typ Max
VOH Output High Current; NOTE 1 1.375 1.475 1.58 1.425 1.495 1.57 1.42 1.495 1.565 V
VOL Output Low Current; NOTE 1 0.605 0.745 0.88 0.625 0.72 0.815 0.64 0.735 0.83 V
VPP Peak-toPeak Input Voltage 150 800 1200 150 800 1200 150 800 1200 V
VCMR
Input High Voltage Common
Mode Range; NOTE 2, 3 1.2 2.5 1.2 2.5 1.2 2.5 V
IIH
Input
High Current PCLK/nPCLK 150 150 150 µA
IIL
Input
Low Current
PCLK -10 -10 -10 µA
nPCLK -150 -150 -150 µA
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 5
ICS853011CM REV. A JUNE 12, 2007
Table 3D. ECL DC Characteristics, VCC = 0V; VEE = -3.8V to -2.375V, TA = -40°C to 85°C
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
AC Electrical Characteristics
Table 4. AC Characteristics, VCC = 0V; VEE = -3.8V to -2.375V or, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
All parameters are measured at f ≤ 1.4GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter
-40°C 25°C 80°C
UnitsMin Typ Max Min Typ Max Min Typ Max
VOH Output High Current; NOTE 1 -1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.08 -1.005 -0.935 V
VOL Output Low Current; NOTE 1 -1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67 V
VPP Peak-toPeak Input Voltage 150 800 1200 150 800 1200 150 800 1200 V
VCMR
Input High Voltage Common
Mode Range; NOTE 2, 3 VEE+1.2 0 VEE+1.2 0 VEE+1.2 0 V
IIH
Input
High Current
PCLK/
nPCLK 150 150 150 µA
IIL
Input
Low Current
PCLK -10 -10 -10 µA
nPCLK -150 -150 -150 µA
Symbol Parameter
-40°C 25°C 80°C
UnitsMin Typ Max Min Typ Max Min Typ Max
fMAX Output Frequency >2.5 >2.5 >2.5 GHz
tPD Propagation Delay; NOTE 1 170 320 180 330 190 345 ps
tjit Additive Phase Jitter, RMS; refer
to Additive Phase Jitter section 0.16 0.16 0.16 ps
tsk(o) Output Skew; NOTE 2, 4 15 15 15 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 150 150 150 ps
tR / tF
Output
Rise/Fall Time 20% to 80% 100 250 100 250 100 250 ps
odc Output Duty Cycle 48 52 48 52 48 52 %
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 6
ICS853011CM REV. A JUNE 12, 2007
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.16ps (typical)
100 1k 10k 100k 1M 10M 100M
SSB Phase Noise dBc/Hz
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 7
ICS853011CM REV. A JUNE 12, 2007
Parameter Measurement Information
LVPECL Output Load AC Test Circuit
Part-to-Part Skew
Output Rise/Fall Time
Differential Input Level
Output Skew
Propagation Delay
SCOPE
Qx
nQx
LVPECL
VEE
VCC
2V
-1.8V to -0.375V
nQx
Qx
tsk(pp)
Part 1
Part 1
nQx
Qx
Clock
Outputs 20%
80% 80%
20%
tRtF
VSWING
-
VCMR
Cross Points
VPP
VCC
VEE
nPCLK
PCLK
tsk(o)
nQx
Qx
nQx
Qx
tPD
nQ0, nQ1
Q0, Q1
nPCLK
PCLK
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 8
ICS853011CM REV. A JUNE 12, 2007
Parameter Measurement Information, continued
Output Duty Cycle/Pulse Width/Period
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Figure 1. Single-Ended Signal Driving Differential Input
tPW
tPERIOD
tPW
tPERIOD
odc = x 100%
nQ0, nQ1
Q0, Q1
Single Ended Clock Input
VCC
PCLK
nPCLK
R1
C1
0.1u R2
1K
1K
V_REF
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 9
ICS853011CM REV. A JUNE 12, 2007
LVPECL Clock Input Interface
The PCLK/nPCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 2A to 2E show interface
examples for the HiPerClockS PCLK/nPCLK input driven by the
most common driver types. The input interfaces suggested here
are examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
Figure 2A. HiPerClockS PCLK/nPCLK Input
Driven by an Open Collector CML Driver
Figure 2C. HiPerClockS PCLK/nPCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2E. HiPerClockS PCLK/nPCLK Input
Driven by an SSTL Driver
Figure 2B. HiPerClockS PCLK/nPCLK Input
Driven by a Built-In Pullup CML Driver
Figure 2D. HiPerClockS PCLK/nPCLK Input Driven by
a 3.3V LVPECL Driver with AC Couple
Figure 2F. HiPerClockS PCLK/nPCLK Input
Driven by a 3.3V LVDS Driver
R1
50
R2
50
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
HiPerClockS
Input
R3
125
R4
125
R1
84
R2
84
3.3V
Zo = 50Ω
Zo = 50Ω
PCLK
nPCLK
3.3V
3.3V
LVPECL HiPerClockS
Input
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
SSTL
2.5V
Zo = 60Ω
Zo = 60Ω
2.5V
3.3V
R1
120
R2
120
R3
120
R4
120
3.3V
R1
100
CML Built-In Pullup
PCLK
nPCLK
3.3V
HiPerClockS
PCLK/nPCLK
Zo = 50Ω
Zo = 50Ω
R3
84
R4
84
R1
125
R2
125
R5
100 - 200
R6
100 - 200
PCLK
nPCLK
3.3V LVPECL
3.3V
Zo = 50Ω
Zo = 50Ω
3.3V
3.3V
HiPerClockS
PCLK/nPCLK
C1
C2
PCLK
nPCLK
3.3V
HiPerClockS
PCLK/nPCLK
R3
1k
R4
1k
R1
1k
R2
1k
3.3V
Zo = 50Ω
Zo = 50Ω
3.3V
C1
C2
R5
100
LVDS
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 10
ICS853011CM REV. A JUNE 12, 2007
Recommendations for Unused Output Pins
Outputs:
LVPECL Outputs:
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination
VCC - 2V
50Ω50Ω
RTT
Zo = 50Ω
Zo = 50Ω
FOUT FIN
RTT = Zo
1
((VOH + VOL) / (VCC – 2)) – 2
3.3V
125Ω125Ω
84Ω84Ω
Zo = 50Ω
Zo = 50Ω
FOUT FIN
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 11
ICS853011CM REV. A JUNE 12, 2007
Termination for 2.5V LVPECL Outputs
Figure 4A and Figure 4B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to
ground level. The R3 in Figure 4B can be eliminated and the
termination is shown in Figure 4C.
Figure 4A. 2.5V LVPECL Driver Termination Example
Figure 4C. 2.5V LVPECL Driver Termination Example
Figure 4B. 2.5V LVPECL Driver Termination Example
2.5V LVPECL Driver
VCC = 2.5V
2.5V
2.5V
50Ω
50Ω
R1
250
R3
250
R2
62.5
R4
62.5
+
–
2.5V LVPECL Driver
VCC = 2.5V
2.5V
50Ω
50Ω
R1
50
R2
50
+
–
2.5V LVPECL Driver
VCC = 2.5V
2.5V
50Ω
50Ω
R1
50
R2
50
R3
18
+
–
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 12
ICS853011CM REV. A JUNE 12, 2007
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS53011C.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS53011C is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 24mA = 91.2mW
• Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW
Total Power_MAX (3.8V, with all outputs switching) = 91.2mW + 61.88mW = 153.08mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate
air flow or 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.153W * 103.3°C/W = 100.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 5A. Thermal Resitance θJA for 8 Lead SOIC, Forced Convection
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 5B. Thermal Resitance θJA for 8 Lead TSSOP, Forced Convection
θJA by Velocity
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
θJA by Velocity
Meters Per Second 012
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 13
ICS853011CM REV. A JUNE 12, 2007
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
Figure 5. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
of VCC – 2V.
• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.935V
(VCC_MAX – VOH_MAX) = 0.935V
• For logic low, VOUT = VOL_MAX = VCC_MAX – 1.67V
(VCC_MAX – VOL_MAX) = 1.67V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
VOUT
VCC
VCC
- 2V
Q1
RL
50Ω
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 14
ICS853011CM REV. A JUNE 12, 2007
Reliability Information
Table 6A. θJA vs. Air Flow Table for an 8 Lead SOIC
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 6B. θJA vs. Air Flow Table for an 8 Lead TSSOP
Transistor Count
The transistor count for ICS853011C is: 96
Pin compatible with MC100LVEP11 and SY100EP11U
Package Outline and Package Dimension
Package Outline - G Suffix for 8 Lead TSSOP Table 7A. Package Dimensions
Reference Document: JEDEC Publication 95, MO-187
θJA by Velocity
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
θJA by Velocity
Meters Per Second 012
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
A2
All Dimensions in Millimeters
Symbol Minimum Maximum
N8
A1.10
A1 00.15
A2 0.79 0.97
b0.22 0.38
c0.08 0.23
D3.00 Basic
E4.90 Basic
E1 3.00 Basic
e0.65 Basic
e1 1.95 Basic
L0.40 0.80
α0° 8°
aaa 0.10
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 15
ICS853011CM REV. A JUNE 12, 2007
Package Outline - M Suffix for 8 Lead SOIC Table 7A. Package Dimensions
Reference Document: JEDEC Publication 95, MO-187
All Dimensions in Millimeters
Symbol Minimum Maximum
N8
A1.10
A1 00.15
A2 0.79 0.97
b0.22 0.38
c0.08 0.23
D3.00 Basic
E4.90 Basic
E1 3.00 Basic
e0.65 Basic
e1 1.95 Basic
L0.40 0.80
α0° 8°
aaa 0.10
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 16
ICS853011CM REV. A JUNE 12, 2007
Ordering Information
Table 8. Ordering Information
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Part/Order Number Marking Package Shipping Packaging Temperature
ICS853011CM 853011C 8 Lead SOIC Tube -40°C to 85°C
ICS853011CMT 853011C 8 Lead SOIC 2500 Tape & Reel -40°C to 85°C
ICS853011CMLF 3011CLF “Lead-Free” 8 Lead SOIC Tube -40°C to 85°C
ICS853011CMLFT 3011CLF “Lead-Free” 8 Lead SOIC 2500 Tape & Reel -40°C to 85°C
ICS853011CG 011C 8 Lead TSSOP Tube -40°C to 85°C
ICS853011CGT 011C 8 Lead TSSOP 2500 Tape & Reel -40°C to 85°C
ICS853011CGLF 11CL “Lead-Free” 8 Lead TSSOP Tube -40°C to 85°C
ICS853011CGLFT 11CL “Lead-Free” 8 Lead TSSOP 2500 Tape & Reel -40°C to 85°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™
2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 17
ICS853011CM REV. A JUNE 12, 2007
Revision History Sheet
Rev Table Page Description of Change Date
A T8 16 Ordering Information table - added lead-free marking for TSSOP package. 6/12/07
www.IDT.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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ICS853011C
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
