NCP1587DR2G - ON SEMICONDUCTOR - Datasheet.Directory

May, 2012 − Rev. 5

1Publication Order Number:

NCP1587/D

NCP1587, NCP1587A

Low Voltage Synchronous

Buck Controller

The NCP1587 and NCP1587A are low cost PWM controllers

designed to operate from a 5 V or 12 V supply. These devices are

capable of producing an output voltage as low as 0.8 V. These 8−pin

devices provide an optimal level of integration to reduce size and cost

of the power supply. The NCP1587/A provide a 1 A gate driver design

and an internally set 275 kHz (NCP1587) and 200 kHz (NCP1587A)

oscillator. In addition to the 1 A gate drive capability, other efficiency

enhancing features of the gate driver include adaptive non−overlap

circuitry. The devices also incorporate an externally compensated

error amplifier and a capacitor programmable soft−start function.

Protection features include programmable short circuit protection and

under voltage lockout (UVLO). The NCP1587/A comes in an 8−pin

SOIC package.

Features

•Input Voltage Range from 4.5 to 13.2 V

•275 kHz (NCP1587) and 200 kHz (NCP1587A) Internal Oscillator

•Boost Pin Operates to 30 V

•Voltage Mode PWM Control

•0.8 V ±1.0 % Internal Reference Voltage

•Adjustable Output Voltage

•Capacitor Programmable Soft−Start

•Internal 1 A Gate Drivers

•80% Max Duty Cycle

•Input Under Voltage Lockout

•Programmable Current Limit

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Applications

•Graphics Cards

•Desktop Computers

•Servers / Networking

•DSP & FPGA Power Supply

•DC−DC Regulator Modules

SOIC−8

D SUFFIX

CASE 7511

MARKING DIAGRAM

PIN CONNECTIONS

1587x = Specific Device Code

(x = A for NCP1587A,

blank for NCP1587)

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Device

BST 8PHASE

GND

7COMP/DIS

6FB

5VCC

(Top View)

1587x

ALYW

Device Package Shipping†

ORDERING INFORMATION

NCP1587DR2G SOIC−8

(Pb−Free)

2500/Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

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NCP1587ADR2G SOIC−8

(Pb−Free)

2500/Tape & Reel

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Figure 1. Typical Application Diagram

BST

GND BG

COMP/DIS

VCC

VOUT

PHASE

12 V 3.3 V

Figure 2. Detailed Block Diagram

LATCH

COMP/DIS

0.8 V

(VREF)

VCC

Clock

Ramp

OSC

PWM

OUT

FAULT

2 V

FAULT

BST

PHASE

VCC

GND

FAULT +

SCP

POR

UVLO 5

VOCTH

Rset

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PIN FUNCTION DESCRIPTION

Pin No. Symbol Description

1 BST Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the

desired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (CBST) between this pin

and the PHASE pin. Typical values for CBST range from 0.1 mF to 1 mF. Ensure that CBST is placed near the IC.

2 TG Top gate MOSFET driver pin. Connect this pin to the gate of the top N−Channel MOSFET.

3 GND IC ground reference. All control circuits are referenced to this pin.

4 BG Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−Channel MOSFET.

5 VCC Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 mF

capacitor to GND. Ensure that this decoupling capacitor is placed near the IC.

6 FB This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to

compensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) or dir-

ectly to Vout.

7 COMP/DIS Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM com-

parator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop. The com-

pensation capacitor also acts as a soft−start capacitor. Pull this pin low for disable.

8 PHASE Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top

MOSFET.

ABSOLUTE MAXIMUM RATINGS

Pin Name Symbol VMAX VMIN

Main Supply Voltage Input VCC 15 V −0.3 V

Bootstrap Supply Voltage Input BST 35 V wrt/PGND

40 V < 50 ns wrt/PGND

15 V wrt/SW

−0.3 V

Switching Node (Bootstrap Supply Return) PHASE 35 V

40 V < 50 ns

−5.0 V

−10 V for < 200 ns

High−Side Driver Output (Top Gate) TG 30 V wrt/GND

15 V wrt/PHASE

−0.3 V wrt/PHASE

−2 V < 200 ns wrt/PHASE

Low−Side Driver Output (Bottom Gate) BG 15 V −0.3 V

−5.0 V for < 200 ns

Feedback FB 5.5 V −0.3 V

COMP/DISABLE COMP/DIS 5.5 V −0.3 V

MAXIMUM RATINGS

Rating Symbol Value Unit

Thermal Resistance, Junction−to−Ambient RqJA 165 °C/W

Thermal Resistance, Junction−to−Case RqJC 45 °C/W

NCP1587A Operating Junction Temperature Range TJ0 to 125 °C

NCP1587A Operating Ambient Temperature Range TA0 to 70 °C

Storage Temperature Range Tstg −55 to +150 °C

Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free 260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

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ELECTRICAL CHARACTERISTICS (0_C < TA < 70_C; 4.5 V < VCC < 13.2 V, 4.5 V < [BST−PHASE] < 13.2 V, 4.5 V < BST < 30 V,

0 V < PHASE < 21 V, CTG = CBG = 1.0 nF, for min/max values unless otherwise noted.)

Characteristic Conditions Min Typ Max Unit

Input Voltage Range −4.5 −13.2 V

Boost Voltage Range −4.5 −26.5 V

Supply Current

Quiescent Supply Current VFB = 1.0 V, No Switching, VCC = 13.2 V 1.0 −8.0 mA

Boost Quiescent Current VFB = 1.0 V, No Switching, VCC = 13.2 V 0.1 −1.0 mA

Under Voltage Lockout

UVLO Threshold VCC Rising Edge 3.8 −4.2 V

UVLO Hysteresis − − 350 −mV

Switching Regulator

VFB Feedback Voltage,

Control Loop in Regulation

TA = 0 to 70°C 792 800 808 mV

Oscillator Frequency NCP1587

NCP1587A

TA = 0 to 70°C 250

180

275

200

300

220

kHz

Ramp−Amplitude Voltage 0.8 1.1 1.4 V

Minimum Duty Cycle 0− − %

Maximum Duty Cycle 70 75 80 %

Error Amplifier (GM)

Transconductance 3.0 −4.4 mmho

Open Loop DC Gain 55 70 −DB

Output Source Current

Output Sink Current

VFB < 0.8 V

VFB > 0.8 V

120

−

Input Bias Current −0.1 1.0 mA

Soft−Start

SS Source Current VFB < 0.8 V 8.49 11 13.3 mA

Switch Over Threshold VFB = 0.8 V −100 −% of Vref

Gate Drivers

Upper Gate Source

VCC = 12 V, VTG = VBG = 2.0 V

−1.0 −A

Upper Gate Sink −1.0 −A

Lower Gate Source −1.0 −A

Lower Gate Sink −2.0 −A

TG Falling to BG Rising Delay VCC = 12 V, TG < 2.0 V, BG > 2.0 V −40 90 ns

BG Falling to TG Rising Delay VCC = 12 V, BG < 2.0 V, TG > 2.0 V −35 90 ns

Enable Threshold 0.3 0.4 0.5 V

Over−Current Protection

OCSET Current Source Sourced from BG pin, before SS 9.89 10 11.1 mA

OC Switch−Over Threshold −700 −mV

Fixed OC Threshold − −375 −mV

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TYPICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

Figure 3. ICC vs. Temperature Figure 4. Oscillator Frequency (FSW) vs.

Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

706050403020100

3.5

3.8

4.1

4.4

4.7

5.0

706050403020100

198

199

200

201

202

203

Figure 5. Soft Start Sourcing Current vs.

Temperature

Figure 6. SCP Threshold vs. Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

706050403020100

325

335

345

355

365

375

Figure 7. Reference Voltage (Vref) vs.

Temperature

TJ, JUNCTION TEMPERATURE (°C)

706050403020100

792

794

796

800

802

804

806

808

ICC (mA)

FSW, FREQUENCY (Khz)

SOFT START SOURCING CURRENT (mA)

SCP THRESHOLD (mV)

Vref, REFERENCE (mV)

VCC = 5 V

VCC = 12 V

798

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DETAILED OPERATING DESCRIPTION

General

The NCP1587 and NCP1587A are PWM controllers

intended for DC−DC conversion from 5.0 V & 12 V buses.

The devices have a 1 A internal gate driver circuit designed

to drive N−channel MOSFETs in a synchronous−rectifier

buck topology. The output voltage of the converter can be

precisely regulated down to 800 mV ±1.0% when the VFB

pin is tied to VOUT. The switching frequency, is internally set

to 275 kHz (NCP1587) and 200 kHz (NCP1587A). A high

gain operational transconductance error amplifier (OTA) is

used.

Duty Cycle and Maximum Pulse Width Limits

In steady state DC operation, the duty cycle will stabilize

at an operating point defined by the ratio of the input to the

output voltage. The devices can achieve an 80% duty cycle.

There is a built in off−time which ensures that the bootstrap

supply is charged every cycle. Both parts can allow a 12 V

to 0.8 V conversion at 275 kHz (NCP1587) and 200 kHz

(NCP1587A).

Input Voltage Range (VCC and BST)

The input voltage range for both VCC and BST is 4.5 V to

13.2 V with respect to GND and PHASE, respectively.

Although BST is rated at 13.2 V with respect to PHASE, it

can also tolerate 26.4 V with respect to GND.

External Enable/Disable

When the Comp pin voltage falls or is pulled externally

below the 400 mV threshold, it disables the PWM Logic and

the gate drive outputs. In this disabled mode, the operational

transconductance amplifier (EOTA) output source current is

reduced and limited to the Soft−Start mode of 10 mA.

Normal Shutdown Behavior

Normal shutdown occurs when the IC stops switching

because the input supply reaches UVLO threshold. In this

case, switching stops, the internal SS is discharged, and all

GATE pins go low. The switch node enters a high impedance

state and the output capacitors discharge through the load

with no ringing on the output voltage.

External Soft−Start

The NCP1587/A features an external soft−start function,

which reduces inrush current and overshoot of the output

voltage. Soft−start is achieved by using the internal current

source of 10 mA (typ), which charges the external integrator

capacitor of the transconductance amplifier. Figure 8 is a

typical soft−start sequence. This sequence begins once VCC

surpasses its UVLO threshold and OCP programming is

complete. During soft−start, as the Comp Pin rises through

400 mV, the PWM Logic and gate drives are enabled. When

the feedback voltage crosses 800 mV, the EOTA will be

given control to switch to its higher regulation mode output

current of 120 mA.

Figure 8. Soft−Start Implementation

4.2 V

0.9 V

0.8 V

Comp

VCC

Vfb

Vout

NORMALSSPOR

UVLO

550 mV

50 mV

OCP

Program

ming

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UVLO

Undervoltage Lockout (UVLO) is provided to ensure that

unexpected behavior does not occur when VCC is too low to

support the internal rails and power the converter. For the

NCP1587/A, the UVLO is set to permit operation when

converting from a 5.0 input voltage.

Overcurrent Threshold Setting

NCP1587/A can easily program an Overcurrent

Threshold ranging from 50 mV to 550 mV, simply by adding

a resistor (RSET) between BG and GND. During a short

period of time following VCC rising over UVLO threshold,

an internal 10 mA current (IOCSET) is sourced from BG pin,

determining a voltage drop across ROCSET. This voltage

drop will be sampled and internally held by the device as

Overcurrent Threshold. The OC setting procedure overall

time length is about 6 ms. Connecting a ROCSET resistor

between BG and GND, the programmed threshold will be:

IOCth +IOCSET @ROCSET

RDS(on)

(eq. 1)

RSET values range from 5 kW to 55 kW. In case ROCSET

is not connected, the device switches the OCP threshold to

a fixed 375 mV value: an internal safety clamp on BG is

triggered as soon as BG voltage reaches 700 mV, enabling

the 375 mV fixed threshold and ending OC setting phase.

The current trip threshold tolerance is ±25 mV. The accuracy

of the set point is best at the highest set point (550 mV). The

accuracy will decrease as the set point decreases.

Current Limit Protection

In case of a short circuit or overload, the low−side (LS)

FET will conduct large currents. The controller will shut

down the regulator in this situation for protection against

overcurrent. The low−side RDS(on) sense is implemented at

the end of each of the LS−FET turn−on duration to sense the

over current trip point. While the LS driver is on, the Phase

voltage is compared to the internally generated OCP trip

voltage. If the phase voltage is lower than OCP trip voltage,

an overcurrent condition occurs and a counter is initiated.

When the counter completes, the PWM logic and both

HS−FET and LS−FET are turned off. The controller has to

go through a Power On Reset (POR) cycle to reset the OCP

fault.

Drivers

The NCP1587 and NCP1587A include gate drivers to

switch external N−channel MOSFETs. This allows the

devices to address high−power as well as low−power

conversion requirements. The gate drivers also include

adaptive non−overlap circuitry. The non−overlap circuitry

increase efficiency, which minimizes power dissipation, by

minimizing the body diode conduction time.

A detailed block diagram of the non−overlap and gate

drive circuitry used in the chip is shown in Figure 9.

Figure 9. Block Diagram

BST

PHASE

GND

Rset

FAULT

VCC

2 V

Careful selection and layout of external components is

required, to realize the full benefit of the onboard drivers.

The capacitors between VCC and GND and between BST

and SWN must be placed as close as possible to the IC. The

current paths for the TG and BG connections must be

optimized. A ground plane should be placed on the closest

layer for return currents to GND in order to reduce loop area

and inductance in the gate drive circuit.

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APPLICATION SECTION

Input Capacitor Selection

The input capacitor has to sustain the ripple current

produced during the on time of the upper MOSFET, so it

must have a low ESR to minimize the losses. The RMS value

of this ripple is:

IinRMS +IOUT D (1 *D)

Ǹ,

where D is the duty cycle, IinRMS is the input RMS current,

& IOUT is the load current. The equation reaches its

maximum value with D = 0.5. Loss in the input capacitors

can be calculated with the following equation:

PCIN +ESRCIN IinRMS

where PCIN is the power loss in the input capacitors &

ESRCIN is the effective series resistance of the input

capacitance. Due to large dI/dt through the input capacitors,

electrolytic or ceramics should be used. If a tantalum must

be used, it must by surge protected. Otherwise, capacitor

failure could occur.

Calculating Input Start-up Current

To calculate the input start up current, the following

equation can be used.

Iinrush +COUT VOUT

tSS

where Iinrush is the input current during start-up, COUT is the

total output capacitance, VOUT is the desired output voltage,

and tSS is the soft start interval.

If the inrush current is higher than the steady state input

current during max load, then the input fuse should be rated

accordingly, if one is used.

Calculating Soft Start Time

To calculate the soft start time, the following equation can

be used.

tss +(Cp)Cc)*DV

Iss

Where Cc is the compensation as well as the soft start

capacitor,

Cp is the additional capacitor that forms the second pole.

Iss is the soft start current

DV is the comp voltage from zero to until it reaches

regulation: ((d * ramp) + 0.9)

Vcomp

900 mV

Vout

The above calculation includes the delay from comp

rising to when output voltage starts becomes valid.

To calculate the time of output voltage rising to when it

reaches regulation; DV is the difference between the comp

voltage reaching regulation and 0.9 V.

Output Capacitor Selection

The output capacitor is a basic component for the fast

response of the power supply. In fact, during load transient,

for the first few microseconds it supplies the current to the

load. The controller immediately recognizes the load

transient and sets the duty cycle to maximum, but the current

slope is limited by the inductor value.

During a load step transient the output voltage initial

drops due to the current variation inside the capacitor and the

ESR. ((neglecting the effect of the effective series

inductance (ESL)):

DVOUT−ESR +DIOUT ESRCOUT

where VOUT-ESR is the voltage deviation of VOUT due to the

effects of ESR and the ESRCOUT is the total effective series

resistance of the output capacitors.

A minimum capacitor value is required to sustain the

current during the load transient without discharging it. The

voltage drop due to output capacitor discharge is given by

the following equation:

DVOUT−DISCHARGE +DIOUT 2 LOUT

2 COUT (VIN D*VOUT),

where VOUT-DISCHARGE is the voltage deviation of VOUT

due to the effects of discharge, LOUT is the output inductor

value & VIN is the input voltage.

It should be noted that ΔVOUT-DISCHARGE and

ΔVOUT-ESR are out of phase with each other, and the larger

of these two voltages will determine the maximum deviation

of the output voltage (neglecting the effect of the ESL).

Inductor Selection

Both mechanical and electrical considerations influence

the selection of an output inductor. From a mechanical

perspective, smaller inductor values generally correspond to

smaller physical size. Since the inductor is often one of the

largest components in the regulation system, a minimum

inductor value is particularly important in space-constrained

applications. From an electrical perspective, the maximum

current slew rate through the output inductor for a buck

regulator is given by:

SlewRateLOUT +VIN *VOUT

LOUT

This equation implies that larger inductor values limit the

regulator’s ability to slew current through the output

inductor in response to output load transients. Consequently,

output capacitors must supply the load current until the

inductor current reaches the output load current level. This

results in larger values of output capacitance to maintain

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tight output voltage regulation. In contrast, smaller values of

inductance increase the regulator’s maximum achievable

slew rate and decrease the necessary capacitance, at the

expense of higher ripple current. The peak-to-peak ripple

current for NCP1587 is given by the following equation:

Ipk *pkLOUT +VOUT(1 *D)

LOUT 275 kHz ,

where Ipk-pkLOUT is the peak to peak current of the output.

From this equation it is clear that the ripple current increases

as LOUT decreases, emphasizing the trade-off between

dynamic response and ripple current.

Feedback and Compensation

The NCP1587 allows the output of the DC-DC converter

to be adjusted from 0.8 V to 5.0 V via an external resistor

divider network. The controller will try to maintain 0.8 V at

the feedback pin. Thus, if a resistor divider circuit was

placed across the feedback pin to VOUT, the controller will

regulate the output voltage proportional to the resistor

divider network in order to maintain 0.8 V at the FB pin.

VOUT

The relationship between the resistor divider network above

and the output voltage is shown in the following equation:

R2+R1 ǒVREF

VOUT *VREFǓ

Resistor R1 is selected based on a design tradeoff between

efficiency and output voltage accuracy. For high values of

R1 there is less current consumption in the feedback

network, However the trade off is output voltage accuracy

due to the bias current in the error amplifier. The output

voltage error of this bias current can be estimated using the

following equation (neglecting resistor tolerance):

Error% +0.1 mA R1

VREF 100%

Once R1 has been determined, R2 can be calculated.

Figure 10. Type II Transconductance Error

Amplifier

Vref

−

Figure 10 shows a typical Type II transconductance error

amplifier (EOTA). The compensation network consists of

the internal error amplifier and the impedance networks ZIN

(R1, R2) and external ZFB (Rc, Cc and Cp). The

compensation network has to provide a closed loop transfer

function with the highest 0 dB crossing frequency to have

fast response (but always lower than FSW/8) and the highest

gain in DC conditions to minimize the load regulation. A

stable control loop has a gain crossing with -20 dB/decade

slope and a phase margin greater than 45°. Include

worst-case component variations when determining phase

margin. Loop stability is defined by the compensation

network around the EOTA, the output capacitor, output

inductor and the output divider. Figure 11 shows the open

loop and closed loop gain plots.

Compensation Network Frequency:

The inductor and capacitor form a double pole at the

frequency

FLC +1

2p Lo Co

The ESR of the output capacitor creates a “zero” at the

frequency,

FESR +1

2p ESR Co

The zero of the compensation network is formed as,

FZ+1

2p RcCc

The pole of the compensation network is calculated as,

Fp+1

2p Rc Cp

Figure 11. Gain Plot of the Error Amplifier

Thermal Considerations

The power dissipation of the NCP1587 varies with the

MOSFETs used, VCC, and the boost voltage (VBST). The

average MOSFET gate current typically dominates the

control IC power dissipation. The IC power dissipation is

determined by the formula:

PIC +(ICC VCC))PTG )PBG

Where:

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PIC = control IC power dissipation,

ICC = IC measured supply current,

VCC = IC supply voltage,

PTG = top gate driver losses,

PBG = bottom gate driver losses.

The upper (switching) MOSFET gate driver losses are:

PTG +QTG fSW VBST

Where:

QTG = total upper MOSFET gate charge at VBST,

fSW = the switching frequency,

VBST = the BST pin voltage.

The lower (synchronous) MOSFET gate driver losses are:

PBG +QBG fSW VCC

Where:

QBG = total lower MOSFET gate charge at VCC.

The junction temperature of the control IC can then be

calculated as:

TJ+TA)PIC qJA

Where:

TJ = the junction temperature of the IC,

TA = the ambient temperature,

θJA = the junction−to−ambient thermal resistance of the

IC package.

The package thermal resistance can be obtained from the

specifications section of this data sheet and a calculation can

be made to determine the IC junction temperature. However,

it should be noted that the physical layout of the board, the

proximity of other heat sources such as MOSFETs and

inductors, and the amount of metal connected to the IC,

impact the temperature of the device. Use these calculations

as a guide, but measurements should be taken in the actual

application.

Layout Considerations

As in any high frequency switching converter, layout is

very important. Switching current from one power device to

another can generate voltage transients across the

impedances of the interconnecting bond wires and circuit

traces. These interconnecting impedances should be

minimized by using wide, short printed circuit traces. The

critical components should be located as close together as

possible using ground plane construction or single point

grounding. The figure below shows the critical power

components of the converter. To minimize the voltage

overshoot the interconnecting wires indicated by heavy lines

should be part of ground or power plane in a printed circuit

board. The components shown in the figure below should be

located as close together as possible. Please note that the

capacitors CIN and COUT each represent numerous physical

capacitors. It is desirable to locate the NCP1587 within 1

inch of the MOSFETs, Q1 and Q2. The circuit traces for the

MOSFETs’ gate and source connections from the NCP1587

must be sized to handle up to 2 A peak current.

Figure 12. Components to be Considered for

Layout Specifications

DESIGN EXAMPLE I: Type II Compensation

(Electrolytic Cap. with large ESR)

Switching Frequency FSW = 275 KHz

Output Capacitance RESR = 45 mW/Each

Output Capacitance Cout = 2×1800 mF

Output Inductance Lout = 1 mH

Input Voltage Vin = 12 V

Output Voltage Vout = 1.6 V

Choose the loop gain crossover frequency;

Fco +1

5 Fsw +55 KHz

The corner frequency of the output filter is calculated below;

FLC +1

2 p 1mH 3600 mF

Ǹ+2.65 KHz

Check that the ESR zero frequency is not too high;

FESR +1

2 p RESR COtFco

FESR +1

2 p 45 mW

2 (1800 mF 2) +2KHz

If ESR zero is larger than Fco/10, Type III compensation

is necessary.

Choose CC for the crossover frequency and the soft start

CC+100 nF

The compensation capacitor (CC) is related to the loop

gain magnitude, zero position and the soft start. By adjusting

the value of this compensation capacitor, the crossover

frequency and the soft start time can be adjusted.

Zero of the compensation network is calculated as follows;

FZ+FLC +2.65 KHz

RC+1

2 p Fz CC

2 p 2.65 kHz 100 nF +600.6 W

Pole of the compensation network is calculated as follows;

Fp+Fsw +275 KHz

Cp+1

2 p Fp RC

2 p 275 kHz 600.6 +963.6 pF

The recommended compensation values are; RC = 604,

CC= 100 nF, CP = 1000 pF

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Blue curve: Gain-Frequency

Red curve: Gain-Frequency

(Phase margin = 61.417 degree, Gain margin = 9.347 dB)

Figure 13. Closed-loop Voltage Loop-gain of the NCP1587

DESIGN EXAMPLE II: Type III Compensation

(Oscon Cap. with small ESR; Do not place RC, CC, CP)

Switching Frequency Fsw = 275 KHz

Output Capacitance RESR = 7 mW/Each

Output Capacitance Cout = 2×560 mF

Output Inductance Lout = 1 mH

Input Voltage Vin = 12 V

Output Voltage Vout = 1.6 V

Choose the loop gain crossover frequency;

Fco +1

5 Fsw +55 KHz

The corner frequency of the output filter is calculated below;

FLC +1

2 p 1mH 1120 mF

Ǹ+4.7 KHz

Check the ESR zero frequency;

FESR +1

2 p RESR CO

FESR +1

2 p 7mW 560 mF+40.6 KHz

Choose CC1 for the soft start

CC1 +33 nF

The compensation capacitor (CC1) is related to the loop

gain magnitude, one zero position and the soft start. By

adjusting the value of this compensation capacitor, the

crossover frequency and the soft start time can be adjusted.

Zeros of the compensation network are calculated as follows;

1st zero;

FZ1 +FLC

10 +470 Hz

RC1 +1

2 p Fz1 CC1

2 p 470 Hz 30 nF +11.3 kW

RC1 should be much larger than 2/gm in order to get the

stable system with transconductance amplifier. Ù choose

RC1 = 12.1 kW

2nd zero;

Choose R3 for the crossover frequency. R3 should be

much larger than 2/gm for the stable system.

R3 +10 kW

Fz2 +FLC +4.7 KHz

C20 +1

2 p Fz2 R3

2 p 4.7 KHz 10 kW+3.4 nF

Choose C20 = 3.3 nF

Poles of the compensation network are calculated as follows;

1st pole;

Choose R4 to cancel the output capacitor ESR zero.

FP1 +FESR +40.6 KHz

R4 +1

2 p FP1 C20

2 p 40.6 kHz 3.3 n +1.2 kW

NCP1587, NCP1587A

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After choose R4 value, adjust R4 to get enough phase

margin Ù R4 = 665 W

2nd pole;

Choose CP1 to eliminate the noise;

FP2 +Fsw +275 KHz

CP1 +1

2 p FP2 RC1

2 p 275 kHz 12 kW+48.23 pF

Choose CP1 = 47 pF

The recommended compensation values are;

R2 = 10 kW, R3 = 10 kW, R4 = 665 W,

RC1 = 12.1 kW, CC1 = 33 nF, CP1= 47 pF,

C20 = 3.3 nF

Blue curve: Gain-Frequency

Red curve: Gain-Frequency

(Phase margin = 80.285 degree, Gain margin = 19.362 dB)

Figure 14. Closed-loop Voltage Loop-gain of the NCP1587

NCP1587, NCP1587A

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Figure 15. Demo Board PCB Layout

Vin

bst

GND

OUTP

SWITCH_NODE

VCC

GND

Note : gating

length s

Note : gating

length sho

GND

COMP

GND

SO8−FLIPAKDPAK IPAK SO8−FLDPAK

IPAK SO8−FLDPAK IPAK SO8−FLDPAK

DUAL PLACEMENT SITE DUAL PLACEMENT SITE DUAL PLACEMENT SITE

SWITCH_NODE

VOUT

BST

Vin

COMP

Vbst

VCC

GND

VOUT

Q12

DNP

1uF

C22

10uF

TP111

C20

DNP

+C4

1500uF

C19

10uF

TP112

TP97

Rc1

DNP

5.11

DNP

604

TP7

C23

10uF

DNP

NTD4815

1uF

NCP1587

6 4

BSTCOMP

FBBG

PHASE

GND

VCC

TP98

+C12

1800uF

Cp1

DNP

TP109

R639

Q11

DNP

TP9

+C24

DNP

C11

0.1uF

100pF

NTD4806

MH1

TP110

TP105

+C13

1800uF

NTD4815

C25

10uF

TP95

NTD4815

+C5

DNP

TP106

TP100

NTD4806 C16

10uF

DNP

TP94

C21

DNP

TP104

Cc1

DNP

0.1uF

NTD4806

TP107

TP1

R90

MH4

TP102

TP93

TP113

NTD4806

NTD4815

TP96

TP108

TP103

TP20

L11uH

MH3

C17

10uF

TP2

+C15

DNP

1.02K

TP99

C18

10uF

CR1

BAS1

16LT1

MH2

Q10

DNP

1.02K

L2DNP

TP101

NCP1587, NCP1587A

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Bill of Materials

Item Number Part Reference Value Quantity MFG

1 C4 1500 mF1 PANASONIC

2 C5 DNP 1 -

3 C8,C9 1 mF2TAIYO YUDEN

4 C11 0.1 mF1AVX

5 C12,C13 1800 mF2 PANASONIC

6 C15,C24 DNP 2 -

7 C16,C17,C18,C19,C22,C23,C25 10 mF7 PANASONIC

8 C20,CC1,CP1 DNP 3 -

9 C21 DNP 1 -

10 CC 0.1 mF1 TDK

11 CR1 BAS116LT1 1 ON SEMICONDUCTOR

12 CP 100 pF 1 PANASONIC

13 J9 20PIN 2ROW 1 MOLEX

14 J23 5PIN 1 PASTERNACK

ENTERPRISES

15 L1 1 mH1 PANASONIC

16 L2 DNP 1 -

17 Q1,Q2 NTD4815 2 ON SEMICONDUCTOR

18 Q3,Q4 NTD4815 2 ON SEMICONDUCTOR

19 Q5,Q6 NTD4806 2 ON SEMICONDUCTOR

20 Q7,Q8 NTD4806 2 ON SEMICONDUCTOR

21 Q9,Q10,Q11,Q12 DNP 4 -

22 Q17,Q18,Q19,Q20,Q21,Q22,Q23,Q24,Q25,Q26,

Q27,Q28,Q29,Q30,Q31,Q32,Q33,Q34,Q35,Q36,

Q37,Q38,Q39,Q40

NTHS5404T1 24 ON SEMICONDUCTOR

23 R1 10 1 PANASONIC

24 R2,R3 1.02 K 2 DALE

25 R4,RC1 DNP 2 -

26 R5 5.11 1 DALE

27 R6,R7,R639 0 3 PANASONIC

28 R8 DNP 1 -

29 R9 0 1 DALE

30 R551,R552,R553,R569,R570,R571,R584,R585,

R586,R599,R600,R601,R608,R609,R610,R617,

R618,R619,R626,R627,R628,R635,R636,R637

100 K 24 DALE

31 R602,R603,R604,R605,R606,R607,R611,R612,

R613,R614,R615,R616,R620,R621,R622,R623,

R624,R625,R629,R630,R631,R632,R633,R634

0.56 24 PANASONIC

32 R638 49.9 1 DALE

33 RC 604 1 DALE

34 TP97,TP98,TP99,TP100,TP101,TP102,TP103,

TP104,TP105,TP106,TP107,TP108,TP109,

TP110,TP111,TP112

TP 16 KEYSTONE

35 U1 NCP1587 1 ON SEMICONDUCTOR

NCP1587, NCP1587A

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Figure 16. Gate Waveforms 20 A Load Sustaining Figure 17. Over Current Protection (12.4 A DC Trip)

Figure 18. Start-up Sequence Figure 19. Transient Response 0-10 A Load Step

NCP1587 Efficiency

0246810121416

Load Current (A)

Efficiency (%)

Figure 20. Efficiency vs. Load Current

NCP1587, NCP1587A

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PACKAGE DIMENSIONS

SOIC−8

D SUFFIX

CASE 751−07

ISSUE AK

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

NCP1587/D

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