Linear Voltage Regulator with Bias Rail, 1.5 A, Very Low Dropout and Programmable SoftStart NCV59748 The NCV59748 is dual-rail very low dropout voltage regulator, capable of providing an output current in excess of 1.5 A with a dropout voltage of 60 mV typ. at full load current. The devices are stable with ceramic and any other type of output capacitor 2.2 mF. This series contains adjustable output voltage version with output voltage down to 0.8 V and 0.75 V Fixed Voltage version. Internal protection features consist of built-in thermal shutdown and output current limiting protection. User-programmable Soft-Start and Power-Good pins are available. The NCV59748 is offered in DFN10 3x3 package, wettable flank options available for Enhanced Optical Inspection. Features * * * * * * * * * * * * Output Current in Excess of 1.5 A VIN Range: 0.8 V to 5.5 V VBIAS Range: 2.7 V to 5.5 V Output Voltage Range: 0.8 V to 3.6 V (Adj), 0.75 V (FixVolt) Dropout Voltage: 60 mV at 1.5 A Programmable Soft-Start Open Drain Power Good Output Fast Transient Response Stable with Any Type of Output Capacitor 2.2 mF Current Limit and Thermal Shutdown Protection NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable These are Pb-Free Devices www.onsemi.com DFN10 CASE 485C 1 DFNW10 CASE 507AE MARKING DIAGRAM 1 xxxxx xxxxx ALYWG G 1 xxxxx xxxxx ALYWG G xxxxx = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) PIN CONNECTIONS IN 1 10 OUT IN 2 9 OUT PG BIAS EN 3 8 FB/SNS SS GND 4 5 Thermal Pad 7 6 DFN10/DFNW10 3y3 Applications * Automotive, Consumer and Industrial Equipment Point of Load * * Regulation FPGA, DSP and Logic Power Supplies Switching Power Supply Post Regulation (c) Semiconductor Components Industries, LLC, 2017 December, 2019 - Rev. 3 ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 11 of this data sheet. 1 Publication Order Number: NCV59748/D NCV59748 NCV59748 VIN PG IN RPG EN CIN VBIAS R1 SS CBIAS FB COUT R2 GND CSS VOUT OUT BIAS Figure 1. Typical Application Schematic, Adjustable Voltage Version NCV59748 VIN PG IN VBIAS CBIAS RPG EN CIN CSS BIAS OUT SS SNS GND Figure 2. Typical Application Schematic, Fixed Voltage Version www.onsemi.com 2 VOUT COUT NCV59748 IN Current Limit BIAS UVLO OUT Thermal Limit 0.44 A SS CSS Soft-Start Discharge + - VOUT R1 + + - 0.8 V Reference FB PG EN - Hysteresis and Deglitch R2 + + 0.9 x VREF - GND Figure 3. Simplified Schematic Block Diagram - Adjustable Voltage Version IN Current Limit BIAS UVLO OUT Thermal Limit 0.44 A SS CSS Soft-Start Discharge + - + + - 0.75 V Reference SNS PG EN - Hysteresis and Deglitch + + 0.9 x VREF - GND Figure 4. Simplified Schematic Block Diagram - Fixed Voltage Version www.onsemi.com 3 VOUT NCV59748 Table 1. PIN FUNCTION DESCRIPTION Name DFN10/DFNW10 IN 1, 2 EN 5 Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left floating. SS 7 Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left floating, the regulator output soft-start ramp time is typically 200 ms. BIAS 4 Bias input voltage for error amplifier, reference, and internal control circuits. PG 3 Power-Good (PG) is an open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold the pin is driven to a low-impedance state. A pull-up resistor from 10 kW to 1 MW should be connected from this pin to a supply up to 5.5 V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left floating if output monitoring is not necessary. FB 8 (Adjustable Voltage device) This pin is the feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating. SNS 8 (Fixed Voltage device) Output voltage Sensing Input. Connect to Output voltage node on the PCB. This pin must not be left floating. OUT 9, 10 GND 6 PAD/TAB Description Unregulated input to the device. Regulated output voltage. A small capacitor (total typical capacitance 2.2 mF, ceramic) is needed from this pin to ground to assure stability. Ground Should be soldered to the ground plane for increased thermal performance. www.onsemi.com 4 NCV59748 Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Input Voltage Range VIN -0.3 to +6 V Input Voltage Range VBIAS -0.3 to +6 V Enable Voltage Range VEN -0.3 to +6 V Power-Good Voltage Range VPG -0.3 to +6 V PG Sink Current IPG 0 to +1.5 mA SS Pin Voltage Range VSS -0.3 to +6 V VFB/SNS -0.3 to +6 V Output Voltage Range VOUT -0.3 to (VIN + 0.3) 6 V Maximum Output Current IOUT Internally Limited PD See Thermal Characteristics Table and Formula Maximum Junction Temperature TJMAX +150 C Storage Junction Temperature Range TSTG -55 to +150 C ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V ESD Capability, Machine Model (Note 2) ESDMM 200 V Feedback / Sense Pin Voltage Range Output Short Circuit Duration Indefinite Continuous Total Power Dissipation Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC-Q100-002 ESD Machine Model tested per AEC-Q100-003 Latch-up Current Maximum Rating 100 mA per AEC-Q100-004 Table 3. THERMAL CHARACTERISTICS Rating Symbol Value Unit Thermal Resistance, Junction-to-Ambient (Note 5) RqJA 41.5 C/W Thermal Resistance, Junction-to-Case (bottom) (Note 6) RqJC 6.6 C/W Thermal Characteristics, DFN10/DFNW10 3x3 Packages 3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 4. Thermal data are derived by thermal simulations based on methodology specified in the JEDEC JESD51 series standards. The following assumptions are used in the simulations: This data was generated with only a single device at the center of a high-K (2s2p) board with 3 in x 3 in copper area which follows the JEDEC51.7 guidelines. - DFN10: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array. Vias are 0.3 mm diameter, plated. - DFN10: Each of top and bottom copper layers are assumed to have thermal conductivity representing 20% copper coverage. 5. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a high-K board, following the JEDEC51.7 guidelines with assumptions as above, in an environment described in JESD51-2a. 6. The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the IC exposed pad. Test description can be found in the ANSI SEMI standard G30-88. Table 4. RECOMMENDED OPERATING CONDITIONS (Note 7) Rating Symbol Min Max Unit Input Voltage VIN VOUT + VDO 5.5 V Bias Voltage VBIAS 2.7 5.5 V TJ -40 125 C Junction Temperature Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 7. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. www.onsemi.com 5 NCV59748 Table 5. ELECTRICAL CHARACTERISTICS (At VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 mF, CSS = 1 nF, CIN = COUT = 10 mF, IOUT = 50 mA, VBIAS = 5.0 V, TJ = -40C to +125C, unless otherwise noted. Typical values are at TJ = +25C.) Symbol VIN Parameter Test Conditions Input Voltage Range Min Typ Max Unit VOUT + VDO - 5.5 V 2.7 - 5.5 V - - 1.6 0.4 - - V VBIAS Bias Pin Voltage Range UVLO Undervoltage Lock-out VBIAS Rising Hysteresis VREF Internal Reference (Adj.) TJ = +25C 0.796 0.8 0.804 V VOUT Output Voltage Range (Adj.) VIN = 5 V, IOUT = 1.5 A VREF - 3.6 V Accuracy (Note 8) 2.97 V < VBIAS < 5.5 V, 50 mA < IOUT < 1.5 A -2 0.5 +2 % VOUT/VIN Line Regulation VOUT (NOM) + 0.3 < VIN < 5.5 V - 0.03 - %/V VOUT/IOUT Load Regulation 50 mA < IOUT < 1.5 A - 0.09 - %/A VIN Dropout Voltage (Note 9) IOUT = 1.5 A, VBIAS - VOUT (NOM) 3.25 V (Note 10) - 60 165 mV VBIAS Dropout Voltage (Notes 9, 11) IOUT = 1.5 A, VIN = VBIAS - 1.31 1.6 V Current Limit VOUT = 80% x VOUT (NOM) 2.0 - 5.5 A - 1 2 mA - 1 50 mA VDO ICL IBIAS Bias Pin Current ISHDN Shutdown Supply Current (IGND) IFB, ISNS PSRR VEN 0.4 V FB / SNS Pin Current Power-Supply Rejection (VIN to VOUT) Power-Supply Rejection (VBIAS to VOUT) -1 0.15 1 mA 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V - 75 - dB 300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V - 30 - 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V - 75 - 300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V - 30 - dB Noise Output Noise Voltage 100 Hz to 100 kHz, IOUT = 1.5 A - 25 x VOUT - mVrms tSTRT Minimum Startup Time RLOAD for IOUT = 1.0 A, CSS = open - 200 - ms Soft-Start Charging Current VSS = 0.4 V - 0.44 - mA ISS VEN, HI Enable Input High Level 1.1 - 5.5 V VEN, LO Enable Input Low Level 0 - 0.4 V VEN, HYS Enable Pin Hysteresis - 50 - mV VEN, DG Enable Pin Deglitch Time - 20 - ms IEN Enable Pin Current VEN = 5 V - 0.1 1 mA VIT PG Trip Threshold VOUT Decreasing 85 90 94 %VOUT VHYS PG Trip Hysteresis - 3 - %VOUT - 0.3 V VPG, LO PG Output Low Voltage IPG = 1 mA (Sinking), VOUT < VIT - IPG, LKG PG Leakage Current VPG = 5.25 V, VOUT > VIT - 0.1 1 mA Thermal Shutdown Temperature Shutdown, Temperature Increasing Reset, Temperature Decreasing - - +165 +140 - - C TSD Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 8. Adjustable devices tested at VREF; external resistor tolerance is not taken into account. 9. Dropout is defined as the voltage from the input to VOUT when VOUT is 3% below nominal. 10. 3.25 V is a test condition of this device and can be adjusted by referring to Figure 8. 11. Due to a minimum Bias Pin operating voltage of 2.7 V, VBIAS dropout voltage is not applicable for VOUT 1.4 V. Adjustable devices tested at VOUT = 1.5 V. www.onsemi.com 6 NCV59748 TYPICAL CHARACTERISTICS 0.20 0.5 0.15 0.4 0.10 -40C +125C 0.05 0 CHANGE IN VOUT (%) CHANGE IN VOUT (%) At TJ = +25C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 mF, CBIAS = 4.7 mF, and COUT = 10 mF, unless otherwise noted. +25C -0.05 -0.10 -0.15 -0.20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 -0.1 -0.3 0.5 1.0 1.5 2.0 2.5 3.0 VBIAS - VOUT (V) Figure 5. VIN Line Regulation Figure 6. VBIAS Line Regulation 3.5 4.0 0.5 0.3 0.2 CHANGE IN VOUT (%) 0.4 0.3 +125C 0.1 +25C 0 -0.1 -0.2 -0.3 -40C 0 10 20 30 40 50 0.1 +25C 0 -0.1 -0.2 -0.3 -40C 0 0.5 1.0 1.5 IOUT, OUTPUT CURRENT (mA) IOUT, OUTPUT CURRENT (A) Figure 7. Load Regulation Figure 8. Load Regulation 50 +125C 40 +25C 30 -40C 20 10 0 +125C 0.2 -0.4 -0.5 60 0 +25C -0.2 0.4 -0.4 -0.5 +125C -40C 0.1 VIN - VOUT (V) VDO (VIN - VOUT) DROPOUT VOLTAGE (mV) CHANGE IN VOUT (%) 0.2 -0.4 -0.5 0.5 VDO (VIN - VOUT) DROPOUT VOLTAGE (mV) 0.3 0.5 1.0 1.5 200 180 IOUT = 1.5 A 160 140 120 100 80 +125C 60 +25C 40 -40C 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 IOUT, OUTPUT CURRENT (A) VBIAS - VOUT (V) Figure 9. VIN Dropout Voltage vs. IOUT and Temperature TJ Figure 10. VIN Dropout Voltage vs. (VBIAS - VOUT) and Temperature TJ www.onsemi.com 7 4.5 NCV59748 TYPICAL CHARACTERISTICS VDO (VBIAS - VOUT) DROPOUT VOLTAGE (mV) VDO (VIN - VOUT) DROPOUT VOLTAGE (mV) At TJ = +25C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 mF, CBIAS = 4.7 mF, and COUT = 10 mF, unless otherwise noted. 200 1200 180 IOUT = 0.5 A 160 140 -40C 120 +25C 100 +125C 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VBIAS - VOUT (V) 1100 -40C 1000 +25C 900 +125C 800 700 600 0 2000 2000 1800 -40C 1000 800 -40C 1000 800 600 400 400 200 200 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 IOUT, OUTPUT CURRENT (A) VBIAS (V) Figure 13. BIAS Pin Current vs. IOUT and Temperature TJ Figure 14. BIAS Pin Current vs. VBIAS and Temperature TJ 0.500 5.5 VPG,LO, L-LEVEL PG VOLTAGE (V) 1.0 0.475 0.450 ISS (mA) +125C 1200 600 0 +25C 1400 IBIAS (mA) 1200 IBIAS (mA) 1600 +25C +125C 1.5 Figure 12. VBIAS Dropout Voltage vs. IOUT and Temperature TJ 1800 1400 1.0 IOUT, OUTPUT CURRENT (A) Figure 11. VIN Dropout Voltage vs. (VBIAS - VOUT) and Temperature TJ 1600 0.5 0.425 0.400 0.375 0.350 0.325 0.300 -50 -25 0 25 50 75 100 125 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 TJ, JUNCTION TEMPERATURE (C) IPG, PG PIN CURRENT (mA) Figure 15. Soft Start Charging Current ISS vs. Temperature TJ Figure 16. L-level PG Voltage vs. Current www.onsemi.com 8 12 NCV59748 TYPICAL CHARACTERISTICS At TJ = +25C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 mF, CBIAS = 4.7 mF, and COUT = 10 mF, unless otherwise noted. 4.5 -40C ICL, CURRENT LIMIT (A) 4.0 3.5 +25C +125C 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VBIAS - VOUT (V) Figure 17. Current Limit vs. (VBIAS - VOUT) www.onsemi.com 9 5.0 NCV59748 APPLICATIONS INFORMATION example), the recommended CIN and CBIAS value is 1 mF or greater. Ceramic or other low ESR capacitors are recommended. For the best performance all the capacitors should be connected to the NCV59748 respective pins directly in the device PCB copper layer, not through vias having not negligible impedance. The NCV59748 dual-rail very low dropout voltage regulator is using NMOS pass transistor for output voltage regulation from VIN voltage. All the low current internal controll circuitry is powered from the VBIAS voltage. The use of an NMOS pass transistor offers several advantages in applications. Unlike a PMOS topology devices, the output capacitor has reduced impact on loop stability. Vin to Vout operating voltage difference can be very low compared with standard PMOS regulators in very low Vin applications. The NCV59748 offers programmable smooth monotonic start-up. The controlled voltage rising limits the inrush current what is advantageous in applications with large capacitive loads. The Voltage Controlled Soft Start timing is programmable by external Css capacitor value. The Enable (EN) input is equipped with internal hysteresis and deglitch filter. Open Drain type Power Good (PG) output is available for Vout monitoring and sequencing of other devices. NCV59748 Adjustable and Fixed Voltage version is available. Typical application schematic for Adjustable version is shown in Figure 18. Enable Operation The enable pin will turn the regulator on or off. The threshold limits are covered in the electrical characteristics table in this data sheet. If the enable function is not to be used then the pin should be connected to VIN or VBIAS. Output Noise When the NCV59748 device reaches the end of the Soft-Start cycle, the Soft Start capacitor is switched to serve as a Noise filtering capacitor. Output Voltage Adjust The output voltage of Adjustable device can be adjusted from 0.8 V to 3.6 V using resistors divider between the output and the FB input. Recommended resistor values for frequently used voltages can be found in the Table 6. NCV59748 V IN IN EN C IN C BIAS R PG OUT SS C SS The Soft-Start ramp time depends on the Soft Start charging current ISS, Soft-Start capacitor value CSS and internal reference voltage VREF. The Soft -Start time can be calculated using following equations: tss = CSS x (VREF / ISS) [s, F,V,A] or in more practical units tSS = CSS x 0.8 V / 0.44 = CSS x 1.82 (Adj. device) and tSS = CSS x 0.75 V / 0.44 = CSS x 1.7 (FixVolt device) where tss = Soft-Start time in miliseconds CSS = Soft-Start capacitor value in nano Farads Please note VREF = 0.8 V for Adj device and VREF = 0.75 V for the Fixed voltage device. Capacitor values for Adjustable device and frequently used Soft-Start times can be found in the Table 7. The maximal recommended value of CSS capacitor is 15 nF. For higher CSS values the capacitor full discharging before new Soft-Start cycle is not guaranteed. PG BIAS V BIAS Programmable Soft-Start GND V OUT + 0.8 FB R1 VOUT C OUT R2 1 ) R 1R 2 Figure 18. Typical Application Schematics - Adjustable Version Dropout Voltage Because of two power supply inputs VIN and VBIAS and one VOUT regulator output, there are two Dropout voltages specified. The first, the VIN Dropout voltage is the voltage difference (VIN - VOUT) when VOUT starts to decrease by percents specified in the Electrical Characteristics table. VBIAS is high enough, specific value is published in the Electrical Characteristics table. The second, VBIAS dropout voltage is the voltage difference (VBIAS - VOUT) when VIN and VBIAS pins are joined together and VOUT starts to decrease. Current Limitation The internal Current Limitation circuitry allows the device to supply the full nominal current and surges but protects the device against Current Overload or Short. Input and Output Capacitors The device is designed to be stable for all available types and values of output capacitors 2.2 mF. The device is also stable with multiple capacitors in parallel, which can be of any type or value. In applications where no low input supplies impedance available (PCB inductance in VIN and/or VBIAS inputs as Thermal Protection Internal thermal shutdown (TSD) circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When TSD activated , the www.onsemi.com 10 NCV59748 regulator output turns off. When cooling down under the low temperature threshold, device output is activated again. This TSD feature is provided to prevent failures from accidental overheating. Table 7. CAPACITOR VALUES FOR PROGRAMMING THE SOFT-START TIME (Adjustable Device) Power Dissipation The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. For reliable operation junction temperature should be limited to +125C. Soft-Start Time CSS 0.2 ms Open 0.5 ms 270 pF 1 ms 560 pF 5 ms 2.7 nF 10 ms 5.6 nF 18 ms 10 nF Table 6. RESISTOR VALUES FOR PROGRAMMING THE OUTPUT VOLTAGE VOUT (V) R1 (kW) R2 (kW) 0.8 Short Open 0.9 0.619 4.99 1.0 1.13 4.53 1.05 1.37 4.33 1.1 1.87 4.99 1.2 2.49 4.99 1.5 4.12 4.75 1.8 3.57 2.87 2.5 3.57 1.69 3.3 3.57 1.15 NOTE: VOUT = 0.8 x (1 + R1/R2) Resistors in the table are standard 1% types Table 8. ORDERING INFORMATION Output Current Output Voltage Marking Package Package Shipping NCV59748MNADJTBG 1.5 A ADJ NCV 59748 DFN10 Case 485C (Pb-Free) Non-Wettable Flank 3000 / Tape & Reel NCV59748MWADJTBG 1.5 A ADJ NCVW 59748 DFN10 Case 485C (Pb-Free) Wettable Flank, SFS Process 3000 / Tape & Reel NCV59748MLADJTBG 1.5 A ADJ NCVL 59748 DFNW10 Case 507AE (Pb-Free) Wettable Flank, SLP Process 3000 / Tape & Reel NCV59748ML075TBG 1.5 A 0.75 V 59748 L075 DFNW10 Case 507AE (Pb-Free) Wettable Flank, SLP Process 3000 / Tape & Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN10, 3x3, 0.5P CASE 485C ISSUE E DATE 11 FEB 2016 SCALE 2:1 D PIN ONE REFERENCE 2X 2X 0.15 C A B ALTERNATE A-1 ALTERNATE A-2 DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS TOP VIEW A1 (A3) DETAIL B 0.10 C L L1 CCC CCC CCC CCC 0.15 C L EE EE CC A1 ALTERNATE CONSTRUCTIONS D2 DETAIL A 1 C 10X 5 SEATING PLANE L A3 A1 DETAIL B WETTABLE FLANK OPTION CONSTRUCTION E2 K 10 6 e 10X 0.10 C A B BOTTOM VIEW NOTE 3 SOLDERING FOOTPRINT* 2.64 PACKAGE OUTLINE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 2.40 2.60 3.00 BSC 1.70 1.90 0.50 BSC 0.19 TYP 0.35 0.45 0.00 0.03 GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. 10X 0.55 1.90 DIM A A1 A3 b D D2 E E2 e K L L1 XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) b 0.05 C MOLD CMPD ALTERNATE B-2 DETAIL B 0.08 C SIDE VIEW EE EE CC EXPOSED Cu ALTERNATE B-1 A 10X A3 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS ONTO BOTTOM SURFACE OF TERMINAL b. 6. FOR DEVICE OPN CONTAINING W OPTION, DETAIL A AND B ALTERNATE CONSTRUCTION ARE NOT APPLICABLE. WETTABLE FLANK CONSTRUCTION IS DETAIL B AS SHOWN ON SIDE VIEW OF PACKAGE. 3.30 10X 0.50 PITCH 0.30 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON03161D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. DFN10, 3X3 MM, 0.5 MM PITCH PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. (c) Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFNW10, 3x3, 0.5P CASE 507AE ISSUE A 1 SCALE 2:1 DATE 15 JUN 2018 A B D PIN ONE REFERENCE L3 L EEEE EEEE EEEE EEEE L ALTERNATE CONSTRUCTION DETAIL A E EXPOSED COPPER A4 A1 PLATING A1 A4 TOP VIEW DETAIL B 0.05 C L3 ALTERNATE CONSTRUCTION A DETAIL B A4 A3 C C 0.05 C NOTE 4 PLATED SURFACES SEATING PLANE C SIDE VIEW SECTION C-C D2 DETAIL A 5 1 L3 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. THIS DEVICE CONTAINS WETTABLE FLANK DESIGN FEATURE TO AID IN FILLET FORMATION ON THE LEADS DURING MOUNTING. MILLIMETERS MIN NOM MAX 0.80 0.90 1.00 --- --- 0.05 0.20 REF 0.10 --- --- 0.20 0.25 0.30 0.25 REF 2.90 3.00 3.10 2.30 2.40 2.50 2.90 3.00 3.10 1.55 1.65 1.75 0.50 BSC 0.28 REF 0.30 0.40 0.50 0.05 REF DIM A A1 A3 A4 b b2 D D2 E E2 e K L L3 GENERIC MARKING DIAGRAM* 10X L 1 E2 e 4X XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) b2 10 6 10X b e 0.10 C A B BOTTOM VIEW 0.05 C NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 3.30 2.50 XXXXX XXXXX ALYWG G *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. Some products may not follow the Generic Marking. 10X 0.58 PACKAGE OUTLINE 0.50 PITCH 1.75 3.30 4X 0.28 1 0.50 PITCH 10X 0.30 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON17793G DFNW10 3x3, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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