CHIP
CAPACITORS
www.vishay.com For technical questions, contact: efi@vishay.com Document Number: 61042
106 Revision: 14-Mar-08
CBB, CBC
Vishay Electro-Films
Thin Film Binary MOS Capacitors
The CBB and CBC MOS capacitor chips each contain five
different capacitors in binary increments allowing the user
many choices in value selection.
These chips are manufactured using Vishay Electro-Films
(EFI) sophisticated Thin Film equipment and manufacturing
technology. The CBB and CBCs are 100 % electrically tested
and visually inspected to MIL-STD-883.
FEATURES
•Wire bondable
•User value selection
•Five capacitors on a 0.019 x 0.048 inches (CBB) or
0.044 inches square (CBC) chip
•Capacitance range: 1.0 pF to 93 pF in binary increments
•Dielectric: Silicon dioxide
•Low dielectric loss
•Substrate: Silicon with gold backing
APPLICATIONS
Vishay EFI CBB and CBC binary MOS multi-value capacitor chips are designed to be a useful device for trimming hybrid circuits
by adding or subtracting capacitance, using normal wire-bonding techniques.
Product may not
be to scale
WV (DC) VALUES AND TOLERANCES
CAPACITOR MODEL CBB CBC
Total Capacitance 31 pF 93 pF
Individual Capacitance 1 pF, 2 pF, 4 pF, 8 pF, 16 pF 3 pF, 6 pF, 12 pF, 24 pF, 48 pF
Tolerance ± 10 % ± 10 %
DC Working Voltage 75 V 75 V
STANDARD ELECTRICAL SPECIFICATIONS
PARAMETER
Peak Voltage at + 25 °C 1.5 x working voltage
Dissipation Factor, 1 kHz, 1 VRMS, + 25 °C 0.1 %
Q at 1 mHz, 50 mVRMS, + 25 °C 1000 min.
TCC, - 55 °C to + 150 °C + 15 ± 25 ppm/°C
Insulation Resistance at Working Voltage, + 25 °C 109 min.
Operating Temperature Range - 55 °C to + 150 °C
Thermal Shock ± 0.25 % + 0.25 pF max. ΔC/C
Moisture Resistance, MIL-STD-202, Method 106 ± 1.0 % + 0.25 pF max. ΔC/C
Short Time Overload, + 25 °C, 5 s; 1.5 x Working Voltage ± 0.25 % + 0.25 pF max. ΔC/C
High Temperature Exposure: 100 h at + 150 °C Ambient ± 0.25 % + 0.25 pF max.
Life, MIL-STD-202, Method 108,
Condition D, + 125 °C Ambient, 1000 h at Working Voltage ± 2.0 % + 0.25 pF max. ΔC/C
CHIP
CAPACITORS
Document Number: 61042 For technical questions, contact: efi@vishay.com www.vishay.com
Revision: 14-Mar-08 107
CBB, CBC
Thin Film Binary MOS Capacitors Vishay Electro-Films
CONFIGURATIONS in inches
SCHEMATIC
Options: Gold bonding pads 15 kÅ minimum
Consult Applications Engineer
0.008
0.048
0.004
0.0075
0.00375
0.004 0.004
0.015 0.019
0.016
1 pF 2 pF 4 pF 8 pF 16 pF
CBB
0.009
0.040
0.020
0.018
0.0124
0.044
12 pF
24 pF
49 pF
CBC
0.003
0.009
0.029
0.018
3 pF 6 pF
TOP BONDING PADS
1 pF 2 pF 4 pF 8 pF
Back of chip
16 pF
TOP BONDING PADS
3 pF 6 pF 12 pF 24 pF
Back of chip
48 pF
MECHANICAL SPECIFICATIONS in inches
PARAMETER
Chip Size, CBB
CBC
0.019 x 0.048 ± 0.002 (0.48 x 1.2 ± 0.05 mm)
0.044 x 0.044 ± 0.002 (1.1 x 1.1 ± 0.05 mm)
Chip Thickness 0.010 ± 0.002 (0.254 ± 0.05 mm)
Chip Substrate Material Semiconductor silicon
Dielectric Silicon dioxide (MOS)
Bonding Pads 10 kÅ minimum aluminum
Backing 3 kÅ minimum gold
ORDERING INFORMATION
Example: 100 % visualled, 93 pF, 10 %, CBC capacitor, aluminum pads, class H visual inspection
W
INSPECTION/
PACKAGING
W = 100 % visually inspected
parts per MIL-STD-883
X = Sample, visually inspected
parts loaded in matrix
trays (4 % AQL)
CBC
PRODUCT
FAMILY
CBB
CBC
012
PROCESS
CODE
008 = CBB
012 = CBC
9300
CAPACITANCE
VALUE (pF)
Use first 4
significant digits of the
capacitance (CT)
B
MULTIPLIER
CODE
C = 0.001
B = 0.01
A = 0.1
0 = 1
K
TOLERANCE
CODE
J = 5.0 %
K = 10 %
M = 20 %
L = 25 %
N = 50 %
Document Number: 91000 www.vishay.com
Revision: 11-Mar-11 1
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