Precision Mixed Signal Copyright © 2004 by Silicon Laboratories 6.15.2004
Port 0
Latch
Port 1
Latch
JTAG
Logic
TCK
TMS
TDI
TDO
UART
SMBus
SPI Bus
5-Chnl
PCA
32 kB
FLASH
2048 Byte
XRAM
VDD
Monitor
SFR Bus
Port 2
Latch
Port 3
Latch
8
0
5
1
C
o
r
e
Timers
0,1,2
Timer 3
P
1
D
r
v
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P
0
D
r
v
P
3
D
r
v
P
2
D
r
v
C
R
O
S
S
B
A
R
S
W
I
T
C
H
AV+
AV+
VDD
VDD
DGND
DGND
AGND
AGND
Reset
RST
XTAL1
XTAL2
External
Oscillator
Circuit System Clock
Internal
Oscillator
Digital Power
Analog Power
Debug HW
Boundary Scan
256 Byte
RAM
WDT
DAC1 DAC1
(12-Bit)
DAC0
(12-Bit)
ADC
100 ksps
(12-Bit)
A
M
U
X
AIN0.0
AIN0.1
AIN0.2
AIN0.3
DAC0
CP0+
CP0-
TEMP
SENSOR
VREF
Prog
Gain
CP0
CP1
VREF
C8051F007
25 MIPS, 32 kB Flash, 12-Bit ADC, 32-Pin Mixed-Signal MCU
Analog Peripherals
12-Bit ADC
-±1 LSB INL; no missing codes
-Programmable throughput up to 100 ksps
-4 external inputs; programmable as single-ended or differential
-Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
-Data-dependent windowed interrupt generator
-Built-in temperature sensor (±3 °C)
Two 12-Bit DACs
-Voltage output
-10 µsec settling time
Comparator
-16 programmable hysteresis values
-Configurable to generate interrupts or reset
Internal Voltage Reference
VDD Monitor/Brown-out Detector
On-Chip JTAG Debug
-On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit
emulation
-Supports breakpoints, single stepping, watchpoints, inspect/modify
memory, and registers
-Superior performance to emulation systems using ICE-chips, target
pods, and sockets
-Fully compliant with IEEE 1149.1 specification
High-Speed 8051 µC Core
-Pipelined instruction architecture; executes 70% of Instructions in 1 or 2
system clocks
-Up to 25 MIPS throughput with 25 MHz clock
-Expanded interrupt handler; up to 21 interrupt sources
Memory
-2304 bytes data RAM
-32 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
Digital Peripherals
-8 port I/O; all are 5 V tolerant
-Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports
available concurrently
-Programmable 16-bit counter/timer array with five capture/compare
modules
-4 general-purpose 16-bit counter/timers
-Dedicated watchdog timer; bidirectional reset
Clock Sources
-Internal programmable oscillator: 2–16 MHz
-External oscillator: Crystal, RC, C, or Clock
-Can switch between clock sources on-the-fly
Supply Voltage: 2.7 to 3.6 V
-Typical operating current: 12.5 mA at 25 MHz
-Multiple power saving sleep and shutdown modes
32-Pin LQFP
Temperature Range: –40 to +85 °C
Precision Mixed Signal Copyright © 2004 by Silicon Laboratories 6.15.2004
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
C8051F007
25 MIPS, 32 kB Flash, 12-Bit ADC, 32-Pin Mixed-Signal MCU
Selected Electrical Specifications
(TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified)
PARAMETER CONDITIONS MIN TYP MAX UNITS
GLOBAL CHARACTERISTICS
Analog Supply Voltage 2.7 3.6 V
Analog Supply Current Internal REF, ADC, DAC, Comparators all
active
0.8 mA
Analog Supply Current with
analog sub-systems inactive
Internal REF, ADC, DAC, Comparators all
disabled
5 µA
Digital Supply Voltage 2.7 3.6 V
Digital Supply Current with
CPU active
Clock = 25 MHz
Clock = 1 MHz
Clock = 32 kHz
12
0.5
20
mA
mA
µA
Digital Supply Current
(shutdown mode)
Oscillator not running 2 µA
VDD Data Retention Voltage RAM remains valid 1.5 V
CPU & DIGITAL I/O
Clock Frequency Range DC 25 MHz
Port Output High Voltage IOH = –3 mA, Port I/O push-pull VDD – 0.7 V
Port Output Low Voltage IOL = 8.5 mA 0.6 V
Input High Voltage 0.8 x VDD V
Input Low Voltage 0.2 x VDD V
SMBus SCL Frequency SYSCLK = MCU system clock SYSCLK/8 MHz
SPI Bus Clock Frequency SYSCLK = MCU system clock SYSCLK/2 MHz
A/D CONVERTER
Resolution 12 bits
Integral Nonlinearity ±1 LSB
Differential Nonlinearity Guaranteed Monotonic ±1 LSB
Throughput Rate 100 ksps
Input Voltage Range 0 VREF V
D/A CONVERTERS
Resolution 12 bits
Integral Nonlinearity Specified from Data Word 014h to FEBh ±4 LSB
Differential Nonlinearity Guaranteed Monotonic ±1 LSB
Offset Error Data Word = 014h ±3 LSB
Output Settling Time To ½ LSB of full-scale 10 µs
Output Voltage Swing 0 VREF –1 LSB V
COMPARATOR
Supply Current 1.5 µA
Response Time | (CP+) – (CP-) | = 100 mV 4 µs
Input Voltage Range –0.25 (AV+) +0.25 V
Input Bias Current –5 0.001 +5 nA
Input Offset Voltage –10 +10 mV
Package Information
A
A1
A2
b
D
D1
e
E
E1
-
0.05
1.35
0.30
-
-
-
-
-
-
-
1.40
0.37
9.00
7.00
0.80
9.00
7.00
1.60
0.15
1.45
0.45
-
-
-
-
-
MIN
(mm)
NOM
(mm)
MAX
(mm)
PIN 1
IDENTIFIER
A1
eb
1
32
E1
D1
D
E
A2
A
C8051F005DK Development Kit
