REV. PrC 24/05/02
Preliminary Technical Data
PRELIMINARY TECHNICAL DA T A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD7451/AD7441
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
Pseudo Differential, 1MSPS,
12- & 10-Bit ADCs in 8-lead SOT-23
FEATURES
Fast Throughput Rate: 1MSPS
Specified for VDD of 2.7 V to 5.25 V
Low Power at max Throughput Rate:
3.75 mW typ at 1MSPS with VDD = 3 V
9 mW typ at 1MSPS with VDD = 5 V
Pseudo Differential Analog Input
Wide Input Bandwidth:
70dB SINAD at 300kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface - SPITM/QSPITM/
MICROWIRETM/ DSP Compatible
Power-Down Mode: 1µA max
8 Pin SOT-23 and µSOIC Packages
APPLICATIONS
Transducer Interface
Battery Powered Systems
Data Acquisition Systems
Portable Instrumentation
Motor Control
Communications
GENERAL DESCRIPTION
The AD7451/AD7441 are respectively 12- and 10-bit,
high speed, low power, successive-approximation (SAR)
analog-to-digital converters that feature a pseudo differen-
tial analog input. These parts operate from a single 2.7 V
to 5.25 V power supply and feature throughput rates up to
1MSPS.
The parts contains a low-noise, wide bandwidth, differen-
tial track and hold amplifier (T/H) which can handle
input frequencies in excess of 1MHz with the -3dB point
being 20MHz typically. The reference voltage is 2.5 V
and is applied externally to the V
REF
pin.
The conversion process and data acquisition are controlled
using CS and the serial clock allowing the device to inter-
face with Microprocessors or DSPs. The input signals are
sampled on the falling edge of CS and the conversion is
also initiated at this point.
The SAR architecture of these parts ensures that there are
no pipeline delays.
FUNCTIONAL BLOCK DIAGRAM
The AD7451/41 use advanced design techniques to achieve
very low power dissipation at high throughput rates.
PRODUCT HIGHLIGHTS
1.Operation with 2.7 V to 5.25 V power supplies.
2.High Throughput with Low Power Consumption.
With a 3V supply, the AD7451/41 offer 3.75mW typ
power consumption for 1MSPS throughput.
3.Pseudo Differential Analog Input.
The V
IN-
input can be used as an offset from ground
4.Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. These
parts also feature a shutdown mode to maximize power
efficiency at lower throughput rates.
5.No Pipeline Delay.
6.Accurate control of the sampling instant via a CS input
and once off conversion control.
MICROWIRE is a trademark of National Semiconductor Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
12-BIT SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
AD7451/
AD7441
VIN+
VIN-
VREF
GND
SCLK
SDATA
+5
VDD
T/H
REV. PrC
PRELIMINARY TECHNICAL DA T A
–2–
Parameter Test Conditions/Comments B Version
1
Unit
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion)
(SINAD)
2
70 dB min
Total Harmonic Distortion (THD)
2
-80dB typ -75 dB max
Peak Harmonic or Spurious Noise
2
-82dB typ -75 dB max
Intermodulation Distortion (IMD)
2
Second Order Terms -85 dB typ
Third Order Terms -85 dB typ
Aperture Delay
2
10 ns typ
Aperture Jitter
2
50 ps typ
Full Power Bandwidth
2
@ -3 dB 20 MHz typ
@ -0.1 dB 2.5 MHz typ
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity (INL)
2
±1 LSB max
Differential Nonlinearity (DNL)
2
Guaranteed No Missed Codes
to 12 Bits. ± 1 LSB max
Offset Error
2
±3 LSB max
Gain Error
2
±3 LSB max
ANALOG INPUT
Full Scale Input Span V
IN+
- V
IN-
V
REF
V
Absolute Input Voltage
V
IN+
V
REF
V
V
IN-3
0.1 to 1 V
DC Leakage Current ±1 µA max
Input Capacitance When in Track 20 pF typ
When in Hold 6 pF typ
REFERENCE INPUT
V
REF
Input Voltage ±1% tolerance for
specified performance 2.5 V
DC Leakage Current ±1 µA max
V
REF
Input Capacitance 15 pF typ
LOGIC INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Current, I
IN
Typically 10nA, V
IN
= 0VorV
DD
±1 µA max
Input Capacitance, C
IN4
10 pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DD
= 5V; I
SOURCE
= 200µA 2.8 V min
V
DD
= 3V; I
SOURCE
= 200µA 2.4 V min
Output Low Voltage, V
OL
I
SINK
=200µA 0.4 V max
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance
4
10 pF max
Output Coding Straight
(Natural)
Binary
AD7451 - SPECIFICATIONS
1
( VDD = 2.7V to 5.25V, fSCLK = 18MHz, fS = 1MHz, VREF = 2.5 V; FIN = 300kHz;
TA = TMIN to TMAX, unless otherwise noted.)
REV. PrC
PRELIMINARY TECHNICAL DA T A
–3–
AD7451/AD7441
Parameter Test Conditions/Comments
B Version
1
Units
CONVERSION RATE
Conversion Time 888ns with an 18MHz SCLK 16 SCLK cycles
Track/Hold Acquisition Time
2
Sine Wave Input 200 ns max
Step Input TB D TB D ns max
Throughput Rate
6
1 MSPS max
POWER REQUIREMENTS
V
DD
2.7/5.25 Vmin/max
I
DD5,7
Normal Mode(Static) SCLK On or Off 0.5 mA typ
Normal Mode (Operational) V
DD
= 5 V. 1.8 mA max
V
DD
= 3 V. 1.25 mA max
Full Power-Down Mode SCLK On or Off 1 µA max
Power Dissipation
Normal Mode (Operational) V
DD
=5 V. 9 mW max
V
DD
=3 V. 3.75 mW max
Full Power-Down V
DD
=5 V. SCLK On or Off 5 µW max
V
DD
=3 V. SCLK On or Off 3 µW max
NOTES
1
Temperature ranges as follows: B Versions: –40°C to +85°C.
2
See ‘Terminology’ section.
3
A small DC input is applied to V
IN-
to provide a pseudo ground for V
IN+
4
Sample tested @ +25°C to ensure compliance.
5
See POWER VERSUS THROUGHPUT RATE section.
6
See ‘Serial Interface Section’.
7
Measured with a midscale DC input.
Specifications subject to change without notice.
AD7451 - SPECIFICATIONS
1
REV. PrC
PRELIMINARY TECHNICAL DA T A
–4–
Parameter Test Conditions/Comments B Version
1
Unit
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion)
(SINAD)
2
61 dB min
Total Harmonic Distortion (THD)
2
-80dB typ -73 dB max
Peak Harmonic or Spurious Noise
2
-82dB typ -73 dB max
Intermodulation Distortion (IMD)
2
Second Order Terms -78 dB typ
Third Order Terms -78 dB typ
Aperture Delay
2
10 ns typ
Aperture Jitter
2
50 ps typ
Full Power Bandwidth
2
@ -3 dB 20 MHz typ
@ -0.1 dB 2.5 MHz typ
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity (INL)
2
±0.5 LSB max
Differential Nonlinearity (DNL)
2
Guaranteed No Missed Codes
to 10 Bits. ±0.5 LSB max
Offset Error
2
±3 LSB max
Gain Error
2
±3 LSB max
ANALOG INPUT
Full Scale Input Span V
IN+
- V
IN-
V
REF
V
Absolute Input Voltage
V
IN+
V
REF
V
V
IN-3
0.1 to 1 V
DC Leakage Current ±1 µA max
Input Capacitance When in Track 20 pF typ
When in Hold 6 pF typ
REFERENCE INPUT
V
REF
Input Voltage ±1% tolerance
for specified performance 2.5 V
DC Leakage Current ±1 µA max
V
REF
Input Capacitance 15 pF typ
LOGIC INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Current, I
IN
Typically 10nA, V
IN
= 0VorV
DD
±1 µA max
Input Capacitance, C
IN4
10 pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DD
= 5V; I
SOURCE
= 200µA 2.8 V min
V
DD
= 3V; I
SOURCE
= 200µA 2.4 V min
Output Low Voltage, V
OL
I
SINK
=200µA 0.4 V max
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance
4
10 pF max
Output Coding Straight
(Natural)
Binary
AD7441 - SPECIFICATIONS
1
( VDD = 2.7V to 5.25V, fSCLK = 18MHz, fS = 1MHz, VREF = 2.5 V; FIN = 300kHz;
TA = TMIN to TMAX, unless otherwise noted.)
REV. PrC
PRELIMINARY TECHNICAL DA T A
–5–
AD7451/AD7441
Parameter Test Conditions/Comments
B Version
1
Units
CONVERSION RATE
Conversion Time 888ns with an 18MHz SCLK 16 SCLK cycles
Track/Hold Acquisition Time
2
Sine Wave Input 200 ns max
Step Input TB D ns max
Throughput Rate
6
1 MSPS max
POWER REQUIREMENTS
V
DD
2.7/5.25 Vmin/max
I
DD6,7
Normal Mode(Static) SCLK On or Off 0.5 mA typ
Normal Mode (Operational) V
DD
= 5 V. 1.8 mA max
V
DD
= 3 V. 1.25 mA max
Full Power-Down Mode SCLK On or Off 1 µA max
Power Dissipation
Normal Mode (Operational) V
DD
=5 V. 9 mW max
V
DD
=3 V. 3.75 mW max
Full Power-Down V
DD
=5 V. SCLK On or Off 5 µW max
V
DD
=3 V. SCLK On or Off 3 µW max
NOTES
1
Temperature ranges as follows: B Versions: –40°C to +85°C.
2
See ‘Terminology’ section.
3
A small DC input is applied to V
IN-
to provide a pseudo ground for V
IN+
4
Sample tested @ +25°C to ensure compliance.
5
See POWER VERSUS THROUGHPUT RATE section.
6
See ‘Serial Interface Section’.
7
Measured with a midscale DC input.
Specifications subject to change without notice.
AD7441 - SPECIFICATIONS
1
REV. PrC
PRELIMINARY TECHNICAL DA T A
–6–
Limit at
Parameter T
MIN
, T
MAX
Units Description
f
SCLK 4
10 kHz min
18 MHz max
t
CONVERT
16 x t
SCLK
t
SCLK
= 1/f
SCLK
888 ns max
t
QUIET
25 ns min Minimum Quiet Time between the End of a Serial Read and the
Next Falling Edge of CS
t
1
10 ns min Minimum CS Pulsewidth
t
2
10 ns min CS falling Edge to SCLK Falling Edge Setup Time
t
35
20 ns max Delay from CS Falling Edge Until SDATA 3-State Disabled
t
45
40 ns max Data Access Time After SCLK Falling Edge
t
5
0.4 t
SCLK
ns min SCLK High Pulse Width
t
6
0.4 t
SCLK
ns min SCLK Low Pulse Width
t
7
10 ns min SCLK Edge to Data Valid Hold Time
t
86
10 ns min SCLK Falling Edge to SDATA 3-State Enabled
35 ns max SCLK Falling Edge to SDATA 3-State Enabled
t
POWER-UP7
1 µs max Power-Up Time from Full Power-Down
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 Volts.
2
See Figure 1, Figure 2 and the ‘Serial Interface’ section.
3
Common Mode Voltage.
4
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
5
Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
DD
= 5 V and time for
an output to cross 0.4 V or 2.0 V for V
DD
= 3 V.
6
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured num-
ber is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the
timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
7
See ‘Power-up Time’ Section.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1,2
( VDD = 2.7V to 5.25V, fSCLK = 18MHz, fS = 1MHz, VREF = 2.5 V; FIN = 300kHz;
TA = TMIN to TMAX, unless otherwise noted.)
Figure 1. AD7451 Serial Interface Timing Diagram
Figure 2. AD7441 Serial Interface Timing Diagram
AD7451/AD7441
12345 13 161514
t3
00 0 0DB11 DB10 DB2 DB1 DB0
t2
4 LEADING ZERO’S 3-STATE
t4
t6
t5
t7t8tQUIET
CONVERT
t
B
+5
SCLK
SDATA
t1
12345 13 161514
t3
00 0 0DB9 DB8 DB0 00
t2
4 LEADING ZERO’S 3-STATE
t4
t6
t5
t7
t8tQUIET
CONVERT
t
B
+5
SCLK
SDATA
t1
2 TRAILING ZEROS
REV. PrC
PRELIMINARY TECHNICAL DA T A
–7–
AD7451/AD7441
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the AD7451/AD7441 features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V
V
IN+
to GND . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
IN-
to GND . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to GND . . . . . . . . -0.3 V to +7 V
Digital Output Voltage to GND . -0.3 V to V
DD
+ 0.3 V
V
REF
to GND . . . . . . . . . . . . . . . . . -0.3 V to V
DD
+0.3 V
Input Current to Any Pin Except Supplies
2
. . . . ±10mA
Operating Temperature Range
Commercial (A, B Version) . . . . . . . . . -40
o
C to +85
o
C
Storage Temperature Range . . . . . . . . . -65
o
C to +150
o
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +150
o
C
JA
Thermal Impedance . . . . . . . . . . 205.9°C/W (µSOIC)
211.5°C/W (SOT-23)
JC
Thermal Impedance . . . . . . . . . 43.74°C/W (µSOIC)
91.99°C/W (SOT-23)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . +215
o
C
Infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . +220
o
C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.5kV
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch up.
Linearity Package
Model Range Error (LSB)
1
Option
4
Branding Information
AD7451BRT -40°C to +85°C ±1 LSB RT-8 TBD
AD7451BRM -40°C to +85°C ±1 LSB RM-8 TBD
AD7441BRT -40°C to +85°C ±0.5 LSB RT-8 TBD
AD7441BRM -40°C to +85°C ±0.5 LSB RM-8 TBD
TBD Evaluation Board
EVAL-CONTROL BRD2
3
Controller Board
ORDERING GUIDE
NOTES
1
Linearity error here refers to Integral Non-linearity Error.
2
This can be used as a stand-alone evaluation board or in conjunction with the EVALUATION BOARD CONTROLLER for evaluation/demonstration purposes.
3
EVALUATION BOARD CONTROLLER. This board is a complete unit allowing a PC to control and communicate with all Analog Devices
evaluation boards ending in the CB designators. To order a complete Evaluation Kit, you will need to order the ADC evaluation board i.e.
TBD, the EVAL-CONTROL BRD2 and a 12V AC transformer. See the TBD technote for more information.
4
RT = SOT-23; RM = µSOIC
Figure 3. Load Circuit for Digital Output Timing
Specifications
I
OL
1.6mA
I
OH
200µA
+1.6V
C
L
50pF
TO
OUT P UT
PIN
REV. PrC
PRELIMINARY TECHNICAL DA T A
–8–
AD7451/AD7441
PIN CONFIGURATION µSOIC
PIN FUNCTION DESCRIPTION
Pin Mnemonic Function
V
REF
Reference Input for the AD7451/41. An external 2.5 V reference must be applied to this input.This pin
should be decoupled to GND with a capacitor of at least 0.1µF.
V
IN+
Non-Inverting Input.
V
IN-
Inverting Input. This pin sets the ground reference point for the V
IN+
input. Connect to Ground or to
a small DC offset to provide a pseudo ground.
G N D Analog Ground. Ground reference point for all circuitry on the AD7451/41. All analog input
signals and any external reference signal should be referred to this GND voltage.
CS Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on
the AD7451/41 and framing the serial data transfer.
SDATA Serial Data. Logic Output. The conversion result from the AD7451/41 is provided on this out
put as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data
stream of the AD7451 consists of four leading zeros followed by the 12 bits of conversion data which
are provided MSB first; the data stream of the AD7441 consists of four leading zeros, followed by the
10-bits of conversion data, followed by two trailing zeros. In both cases, the output coding is Straight
(Natural) Binary.
SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock
input is also used as the clock source for the conversion process.
V
DD
Power Supply Input. V
DD
is 2.7 V to 5.25 V. This supply should be decoupled to GND with a 0.1µF
Capacitor and a 10µF Tantalum Capacitor.
PIN CONFIGURATION 8-LEAD SOT-23
AD7451/AD7441
SOT-23
(Not to Scale)
TOP VIEW
1
2
3
45
6
7
8VREF
VIN +
VIN -
GND
+5
SDATA
SCLK
VDD
AD7451/AD7441
µSOIC
(Not to Scale)
TOP VIEW
1
2
3
45
6
7
8
VREF
VIN +
VIN -
GND +5
SDATA
SCLK
VDD
REV. PrC
PRELIMINARY TECHNICAL DA T A
–9–
AD7451/AD7441
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion)
at the output of the ADC. The signal is the rms amplitude
of the fundamental. Noise is the sum of all
nonfundamental signals up to half the sampling frequency
(f
S
/2), excluding dc. The ratio is dependent on the number
of quantization levels in the digitization process; the more
levels, the smaller the quantization noise. The theoretical
signal to (noise + distortion) ratio for an ideal N-bit con-
verter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB and for a 10-bit
converter this is 62dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms
sum of harmonics to the fundamental. For the AD7450, it
is defined as:
THD (dB ) =20 log V2
2+V3
2+V4
2+V5
2+V6
2
V1
where V
1
is the rms amplitude of the fundamental and V
2
,
V
3
, V
4
, V
5
and V
6
are the rms amplitudes of the second to
the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of
the rms value of the next largest component in the ADC
output spectrum (up to f
S
/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried
in the noise floor, it will be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities will create
distortion products at sum and difference frequencies of
mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation
distortion terms are those for which neither m nor n are
equal to zero. For example, the second order terms in-
clude (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7451/41 is tested using the CCIF standard where
two input frequencies near the top end of the input band-
width are used. In this case, the second order terms are
usually distanced in frequency from the original sine waves
while the third order terms are usually at a frequency close
to the input frequencies. As a result, the second and third
order terms are specified separately. The calculation of the
intermodulation distortion is as per the THD specification
where it is the ratio of the rms sum of the individual dis-
tortion products to the rms amplitude of the sum of the
fundamentals expressed in dBs.
Aperture Delay
This is the amount of time from the leading edge of the
sampling clock until the ADC actually takes the sample.
Aperture Jitter
This is the sample to sample variation in the effective
point in time at which the actual sample is taken.
Full Power Bandwidth
The full power bandwidth of an ADC is that input fre-
quency at which the amplitude of the reconstructed
fundamental is reduced by 0.1dB or 3dB for a full scale
input.
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line pass-
ing through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1
LSB change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (000...000 to
000...001) from the ideal (i.e. AGND + 1LSB)
Gain Error
This is the deviation of the last code transition (111...110 to
111...111) from the ideal (i.e., V
REF
- 1LSB), after the Offset
Error has been adjusted out.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode on the
13th SCLK rising edge (see the “Serial Interface Sec-
tion”). The track/hold acquisition time is the minimum
time required for the track and hold amplifier to remain in
track mode for its output to reach and settle to within 0.5
LSB of the applied input signal.
Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio is defined as the ratio of
the power in the ADC output at full-scale frequency, f, to
the power of a 200mV p-p sine wave applied to the ADC
V
DD
supply of frequency fs. The frequency of this input
varies from 1kHz to 1MHz.
PSRR (dB) = 10 log (Pf/Pfs)
Pf is the power at frequency f in the ADC output; Pfs is
the power at frequency fs in the ADC output.
REV. PrC
PRELIMINARY TECHNICAL DA T A
–10–
AD7451/AD7441
TITLE
0
0
0000
TITLE
0000
6*,
TPC 1. SINAD vs Analog Input Frequency for Various
Supply Voltages
TPC 2 and TPC 3 shows the Power Supply Rejection
Ratio (see Terminology) versus V
DD
supply ripple fre-
quency for the AD7451/41 with and without power supply
decoupling respectively.
TITLE
0
0
0000
TITLE
0000
6*,
TPC 2. PSRR vs. Supply Ripple Frequency without Supply
Decoupling
TITLE
0
0
0000
TITLE
0000
6*,
TPC 3. PSRR vs. Supply Ripple Frequency with Supply
Decoupling of TBD
TITLE
0
0
0000
TITLE
0000
6*,
TPC 4. THD vs. Analog Input Frequency for Various
Source Impedances
TITLE
0
0
0000
TITLE
0000
6*,
TPC 5. THD vs. Analog Input Frequency for Various
Supply Voltages
PERFORMANCE CURVES
(Default Conditions: TA = 25°C, Fs = 1MSPS, FSCLK = 18MHz, V
DD
= 2.7 V to 5.25 V, V
REF
= 2.5 V)
REV. PrC
PRELIMINARY TECHNICAL DA T A
–11–
AD7451/AD7441
AD7451 PERFORMANCE CURVES
(Default Conditions: TA = 25°C, Fs = 1MSPS, FSCLK
= 18MHz, V
DD
= 2.7 V to 5.25 V, V
REF
= 2.5 V)
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TPC 6. AD7451 Dynamic Performance
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TPC 7. Typical DNL For the AD7451
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TPC 8. Typical INL For the AD7451
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TPC 9. Histogram of 10000 conversions of a DC Input for
the AD7451
REV. PrC
PRELIMINARY TECHNICAL DA T A
–12–
AD7451/AD7441
AD7441 PERFORMANCE CURVES
(Default Conditions: TA = 25°C, Fs = 1MSPS, FSCLK
= 18MHz, V
DD
= 2.7 V to 5.25 V, V
REF
= 2.5 V)
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TPC 10. AD7441 Dynamic Performance
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TPC 11. Typical DNL For the AD7441
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TPC 12. Typical INL For the AD7441
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0
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TPC 13. Histogram of 10000 conversions of a DC Input for
the AD7441
REV. PrC
PRELIMINARY TECHNICAL DA T A
–13–
AD7451/AD7441
SERIAL INTERFACE
Figures 1 and 2 show detailed timing diagrams for the
serial interface of the AD7451 and the AD7441 respec-
tively. The serial clock provides the conversion clock and
also controls the transfer of data from the device during
conversion. CS initiates the conversion process and frames
the data transfer. The falling edge of CS puts the track
and hold into hold mode and takes the bus out of three-
state. The analog input is sampled and the conversion
initiated at this point. The conversion will require 16
SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track and
hold will go back into track on the next SCLK rising edge
as shown at point B in Figures 1 and 2. On the 16th
SCLK falling edge the SDATA line will go back into
three-state.
If the rising edge of CS occurs before 16 SCLKs have
elapsed, the conversion will be terminated and the SDATA
line will go back into three-state on the 16th SCLK falling
edge.
The conversion result from the AD7451/41 is provided on
the SDATA output as a serial data streatm. The bits are
clocked out on the falling edge of the SCLK input. The data
streatm of the AD7451 consists of four leading zeros,
followed by 12 bits of conversion data which is provided MSB
first; the data stream of the AD7441 consists of four leading
zeros, followed by the 10 bits of conversion data, followed by
two trailing zeros, which is also provided MSB first. In both
cases, the output coding is straight (natural) binary.
16 serial clock cycles are required to perform a conversion
and to access data from the AD7451/41. CS going low
provides the first leading zero to be read in by the micro-
controller or DSP. The remaining data is then clocked out
on the subsequent SCLK falling edges beginning with the
second leading zero. Thus the first falling clock edge on the
serial clock provides the second leading zero. The final bit
in the data transfer is valid on the 16th falling edge, having
been clocked out on the previous (15th) falling edge. Once
the conversion is complete and the data has been accessed
after the 16 clock cycles, it is important to ensure that, before
the next conversion is initiated, enough time is left to meet
the acquisition and quiet time specifications - see the Timing
Examples. To achieve 1MSPS with an 18MHz clock for
V
DD
= 3 V and 5 V, an 18 clock burst will perform the
conversion and leave enough time before the next conversion
for the acquisition and quiet time.
In applications with a slower SCLK, it may be possible to
read in data on each SCLK rising edge i.e. the first rising
edge of SCLK after the CS falling edge would have the
leading zero provided and the 15th SCLK edge would have
DB0 provided.
Timing Example 1
Having F
SCLK
= 18MHz and a throughput rate of
1MSPS gives a cycle time of:
1/Throughput = 1/1000000 = 1µs
A cycle consists of:
t
2
+ 12.5 (1/F
SCLK
) + t
ACQ
= 1µs.
Therefore if t
2
= 10ns then:
10ns + 12.5(1/18MHz) + t
ACQ
= 1µs
t
ACQ
= 296ns
This 296ns satisfies the requirement of 200ns for t
ACQ
.
From Figure 4, t
ACQ
comprises of:
2.5(1/F
SCLK
) + t
8
+ t
QUIET
where t
8
= 35ns. This allows a value of 122ns for t
QUIET
satisfying the minimum requirement of 25ns.
Timing Example 2
Having FSCLK = 5MHz and a throughput rate of
315kSPS gives a cycle time of :
1/Throughput = 1/315000 = 3.174µs
A cycle consists of:
t2 + 12.5 (1/FSCLK) + tACQ = 3.174µs.
Therefore if t2 is 10ns then:
10ns + 12.5(1/5MHz) + t
ACQ
= 3.174µs
t
ACQ
= 664ns
This 664ns satisfies the requirement of 200ns for tACQ.
From Figure 4, tACQ comprises of:
2.5(1/FSCLK) + t8 + tQUIET
where t8 = 35ns. This allows a value of 129ns for tQUIET
satisfying the minimum requirement of 25ns.
As in this example and with other slower clock values, the
signal may already be acquired before the conversion is
complete but it is still necessary to leave 25ns minimum
tQUIET between conversions. In example 2 the signal should
be fully acquired at approximately point C in Figure 4.
Figure 4. Serial Interface Timing Example
12345 13 161514
t2
t6
t5
t8
t
QUIET
CONVERT
t
B
+5
tACQUISITION
12.5(1/fSCLK)
1/Throughput
10ns
SCLK
C
REV. PrC
PRELIMINARY TECHNICAL DA T A
–14–
AD7451/AD7441
MODES OF OPERATION
The mode of operation of the AD7451 and the AD7441 is
selected by controlling the logic state of the CS signal during
a conversion. There are two possible modes of operation,
Normal Mode and Power-Down Mode. The point at which
CS is pulled high after the conversion has been initiated will
determine whether or not the AD7451/41 will enter the
power-down mode. Similarly, if already in power-down, CS
controls whether the devices will return to normal operation
or remain in power-down. These modes of operation are
designed to provide flexible power management options.
These options can be chosen to optimize the power dissipa-
tion/throughput rate ratio for differing application
requirements.
Normal Mode
This mode is intended for fastest throughput rate perfor-
mance. The user does not have to worry about any
power-up times with the AD7451/41 remaining fully
powered up all the time. Figure 5 shows the general dia-
gram of the operation of the AD7451/41 in this mode.
The conversion is initiated on the falling edge of CS as
described in the ‘Serial Interface Section’. To ensure the
part remains fully powered up, CS must remain low until
at least 10 SCLK falling edges have elapsed after the fall-
ing edge of CS.
If CS is brought high any time after the 10th SCLK fall-
ing edge, but before the 16th SCLK falling edge, the part
will remain powered up but the conversion will be termi-
nated and SDATA will go back into three-state. Sixteen
serial clock cycles are required to complete the conversion
and access the complete conversion result. CS may idle
high until the next conversion or may idle low until some-
time prior to the next conversion. Once a data transfer is
complete, i.e. when SDATA has returned to three-state,
another conversion can be initiated after the quiet time,
t
QUIET
has elapsed by again bringing CS low.
4 LEADING ZEROS + CONVERSION RESULT
SDATA
10 16
+5
SCLK 1
Figure 5. Normal Mode Operation
Power Down Mode
This mode is intended for use in applications where
slower throughput rates are required; either the ADC is
powered down between each conversion, or a series of
conversions may be performed at a high throughput rate
and the ADC is then powered down for a relatively long
duration between these bursts of several conversions.
When the AD7451/AD7441 is in the power down mode,
all analog circuitry is powered down. To enter power
down mode, the conversion process must be interrupted
by bringing CS high anywhere after the second falling
edge of SCLK and before the tenth falling edge of SCLK
as shown in Figure 6.
Once CS has been brought high in this window of
SCLKs, the part will enter power down and the conver-
sion that was initiated by the falling edge of CS will be
terminated and SDATA will go back into three-state.
The time from the rising edge of CS to SDATA three-
state enabled will never be greater than t
8
(see the
‘Timing Specifications’). If CS is brought high before
the second SCLK falling edge, the part will remain in
normal mode and will not power-down. This will avoid
accidental power-down due to glitches on the CS line.
In order to exit this mode of operation and power the
AD7451/41 up again, a dummy conversion is performed.
On the falling edge of CS the device will begin to power
up, and will continue to power up as long as CS is held
low until after the falling edge of the 10th SCLK. The
device will be fully powered up after 1µsec has elapsed
and, as shown in Figure 7, valid data will result from the
next conversion.
If CS is brought high before the 10th falling edge of
SCLK, the AD7451/41 will again go back into power-
down. This avoids accidental power-up due to glitches on
the CS line or an inadvertent burst of eight SCLK cycles
while CS is low. So although the device may begin to
power up on the falling edge of CS, it will again power-
down on the rising edge of CS as long as it occurs before
the 10th SCLK falling edge.
+5
THREE STATE
SCLK
SDATA
12 10
Figure 6. Entering Power Down Mode
Power up Time
The power up time of the AD7451/41 is typically 1µsec,
which means that with any frequency of SCLK up to
18MHz, one dummy cycle will always be sufficient to
allow the device to power-up. Once the dummy cycle is
complete, the ADC will be fully powered up and the input
signal will be acquired properly. The quiet time t
QUIET
must still be allowed from the point at which the bus goes
back into three-state after the dummy conversion, to the
next falling edge of CS.
When running at the maximum throughput rate of
1MSPS, the AD7451/41 will power up and acquire a sig-
nal within ±0.5LSB in one dummy cycle, i.e. 1µs. When
powering up from the power-down mode with a dummy
cycle, as in Figure 7, the track and hold, which was in
hold mode while the part was powered down, returns to
track mode after the first SCLK edge the part receives
after the falling edge of CS. This is shown as point A in
Figure 7.
REV. PrC
PRELIMINARY TECHNICAL DA T A
–15–
AD7451/AD7441
Although at any SCLK frequency one dummy cycle is
sufficient to power the device up and acquire V
IN
, it does
not necessarily mean that a full dummy cycle of 16
SCLKs must always elapse to power up the device and
acquire V
IN
fully; 1µs will be sufficient to power the de-
vice up and acquire the input signal.
For example, if a 5MHz SCLK frequency was applied to
the ADC, the cycle time would be 3.2µs (i.e. 1/(5MHz) x
16). In one dummy cycle, 3.2µs, the part would be pow-
ered up and V
IN
acquired fully. However after 1µs with a
5MHz SCLK only 5 SCLK cycles would have elapsed. At
this stage, the ADC would be fully powered up and the
signal acquired. So, in this case the CS can be brought
high after the 10th SCLK falling edge and brought low
again after a time t
QUIET
to initiate the conversion.
When power supplies are first applied to the AD7451/41,
the ADC may either power up in the power-down mode or
normal mode. Because of this, it is best to allow a dummy
cycle to elapse to ensure the part is fully powered up be-
fore attempting a valid conversion. Likewise, if the user
wishes the part to power up in power-down mode, then the
dummy cycle may be used to ensure the device is in
power-down by executing a cycle such as that shown in
Figure 6.
Once supplies are applied to the AD7451/41, the power
up time is the same as that when powering up from the
power-down mode. It takes approximately 1µs to power
up fully if the part powers up in normal mode. It is not
necessary to wait 1µs before executing a dummy cycle to
ensure the desired mode of operation. Instead, the dummy
cycle can occur directly after power is supplied to the
ADC. If the first valid conversion is then performed di-
rectly after the dummy conversion, care must be taken to
ensure that adequate acquisition time has been allowed.
As mentioned earlier, when powering up from the power-
down mode, the part will return to track upon the first
SCLK edge applied after the falling edge of CS. How-
ever, when the ADC powers up initially after supplies are
applied, the track and hold will already be in track. This
means if (assuming one has the facility to monitor the
ADC supply current) the ADC powers up in the desired
mode of operation and thus a dummy cycle is not required
to change mode, then neither is a dummy cycle required
to place the track and hold into track.
POWER VERSUS THROUGHPUT RATE
By using the power-down mode on the AD7451/41 when
not converting, the average power consumption of the
ADC decreases at lower throughput rates. Figure 8 shows
how, as the throughput rate is reduced, the device remains
in its power-down state longer and the average power con-
sumption reduces accordingly. It shows this for both 5V
and 3V power supplies.
For example, if the AD7451/41 is operated in continous
sampling mode with a throughput rate of 100kSPS and an
SCLK of 18MHz and the device is placed in the power
down mode between conversions, then the power con-
sumption is calculated as follows:
Power dissipation during normal operation = 9mW max
(for V
DD
= 5V).
If the power up time is 1 dummy cycle i.e. 1µsec, and the
remaining conversion time is another cycle i.e. 1µsec, then
the AD7451/41 can be said to dissipate 9mW for 2µsec
during each conversion cycle.
If the throughput rate = 100kSPS then the cycle time =
10µsec and the average power dissipated during each cycle
is:
(2/10) x 9mW = 1.8mW
For the same scenario, if V
DD
= 3V, the power dissipation
during normal operation is 3.75mW max.
The AD7450 can now be said to dissipate 3.75mW for
2µsec* during each conversion cycle.
The average power dissipated during each cycle with a
throughput rate of 100kSPS is therefore:
(2/10) x 3.75mW = 0.75mW
This is how the power numbers in Figure 8 are calculated.
TBD
Figure 8. Power vs. Throughput rate for the
Power Down Mode
For throughput rates above 320kSPS, it is recommended
that for optimum power performance, the serial clock
frequency is reduced.
Figure 7. Exiting Power Down Mode
SDATA
+5
INVALID DATA
SCLK
116
VALID DATA
1
A
THE PART BEGINS
TO POWER UP THE PART IS FULLY POWERED
UP WITH VIN FULLY ACQUIRED
10 1016
tPOWERUP
