CY7C1357C-100BZC - Cypress Semiconductor

9-Mbit (256K x 36/512K x 18)

Flow-Through SRAM with NoBL™ Architecture

CY7C1355C

CY7C1357C

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05539 Rev . *E Revised September 14, 2006

Features

• No Bus Latency™ (NoBL™) architecture eliminates

dead cycles between write and read cycles

• Can support up to 133-MHz bus operations with zero

wait states

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

• 3.3V/2.5V I/O power supply (VDDQ)

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

• Clock Enable (CEN) pin to enable clock and suspend

operation

• Synchronous self-timed writes

• Asynchr onous Output Enable

• Available in JEDEC-standard and lead-free 100-Pin

TQFP, lead-free and non lead-free 119-Ball BGA

package and 165-Ball FBGA package

• Three chip enables for simple dep th expansion.

• Automatic Po wer-down feature available using ZZ

mode or CE deselect

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst Capability—linear or interle aved burst order

• Low standby power

Functional Description[1]

The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18

Synchronous Flow-through Burst SRAM designed specifically

to support unlimited true back-to-ba ck Read/Write operations

without the insertion of wait states. The

CY7C1355C/CY7C1357C i s equipped with the advanced No

Bus Latency (NoBL) logic required to enable consecutive

Read/Write operations with data being transferred on every

clock cycle. This feature dramatically improves the throughput

of data through the SRAM, especially in systems that req uire

frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of th e clock. The clo ck input is qual ified b y

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay fr om the clock rise is 6.5 ns (133-M Hz

device).

Write operations are controlled by the two or fo ur Byte Wri te

Select (BWX) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Selection Guide 133 MHz 100 MHz Unit

Maximum Access Time 6.5 7.5 ns

Maximum Operating Current 250 180 mA

Maximum CMOS Standby Current 40 40 mA

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

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Document #: 38-05539 Rev. *E Page 2 of 28

MODE

CE1

CE2

CE3

OE READ LOGIC

DQs

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

D0 Q1

ADV/LD

CE ADV/LD

WRITE

DRIVERS

WRITE ADDRESS

A0, A1, A

ZZ SLEEP

CONTROL

Logic Block Diagram – CY7C1355C (256K x 36)

MODE

CE1

CE2

CE3

OE READ LOGIC

DQs

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

D0 Q1

ADV/LD

CE ADV/LD

WRITE

DRIVERS

WRITE ADDRESS

A0, A1, A

SLEEP

CONTROL

Logic Block Diagram – CY7C1357C (512K x 18)

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Document #: 38-05539 Rev. *E Page 3 of 28

Pin Configurations 100-Pin TQFP Pinout

NC/288M

NC/144M

VSS

VDD

NC/36M

DQPB

DQB

VDDQ

VSS

DQB

VSS

VDDQ

DQB

VSS

VDD

DQA

VDDQ

VSS

DQA

VSS

VDDQ

DQA

DQPA

DQPC

DQC

VDDQ

VSS

DQC

VSS

VDDQ

DQC

Vss/DNU

VDD

VSS

DQD

VDDQ

VSS

DQD

VSS

VDDQ

DQD

DQPD

CE1

CE2

BWD

BWC

BWB

BWA

CE3

VDD

VSS

CLK

CEN

NC/18M

100

ADV/LD

MODE

NC/72M

CY7C1355C

BYTE A

BYTE B

BYTE D

BYTE C

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CY7C1357C

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Pin Configurations (continued)

100-Pin TQFP Pinout

NC/288M

NC/144M

VSS

VDD

NC/36M

VDDQ

VSS

DQPA

DQA

VSS

VDDQ

DQA

VSS

VDD

DQA

VDDQ

VSS

DQA

VSS

VDDQ

VSS

DQB

VSS

VDDQ

DQB

Vss/DNU

VDD

VSS

DQB

VDDQ

VSS

DQB

DQPB

VSS

VDDQ

CE1

CE2

BWB

BWA

CE3

VDD

VSS

CLK

CEN

NC/18M

100

ADV/LD

MODE

NC/72M

CY7C1357C BYTE A

BYTE B

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CY7C1357C

Document #: 38-05539 Rev. *E Page 5 of 28

Pin Configurations (continued)

2345671

VDDQ

NC/576M

NC/1G DQPC

DQC

DQD

DQC

DQD

AA AANC/18M VDDQ

CE2A

DQC

VDDQ

DQC

VDDQ

DQD

NC/144M

NC VDDQ

VDD

CLK

VDD

VSS

TDOTCKTDITMS NC/36MNC/72M

NC/288M

VDDQ

AAA

CE3

AA0

DQA

DQC

DQA

DQB

DQA

DQB

VDD

DQC

VDD

DQD

ADV/LD

CE1

VSS

VSS DQPA

MODE

DQPD

DQPB

BWB

BWC

NC VDD NC

BWA

CEN

BWD

2345671

VDDQ

NC/576M

NC/1G NCDQB

DQB

AA AANC/18M VDDQ

CE2A

VDDQ

NC/144M

NC/72M VDDQ

VDD

CLK

VDD

VSS

TDOTCKTDITMS AA NC/288M

VDDQ

A NC/36M A A

CE3

DQA

DQB

DQA

VDD

DQB

VDD

DQB

ADV/LD

CE1

VSS

VSS NC

MODE

DQPB

DQPA

VSS

BWB

NC VDD NC

BWA

CEN

VSS

CY7C1357 C (5 12 K x 18 )

CY7C135 5C (256K x 36)

119-Ball BGA Pinout (3 Chip Enables with JTAG)

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CY7C1357C

Document #: 38-05539 Rev. *E Page 6 of 28

Pin Configurations (continued)

165-Ball FBGA Pinout (3 Chip enable with JTAG)

CY7C1355C (256K x 36)

2345671

TDO

NC/576M

NC/1G

DQP

CE3

CEN

ACE2

MODE

NC/36M

NC/72M

DDQ

CLK WE

DDQ

TCK

TDI

NC V

NC/144M NC

DDQ

TMS

891011

NC/288M

ADV/LD

NC/18M ANC

DDQ

NC DQP

DDQ

DQP

DDQ

CY7C1357C (512K x 18)

2345671

TDO

NC/576M

NC/1G

DQP

CE3

CEN

ACE2

MODE

NC/36M

NC/72M

DDQ

NC BW

CLK WE

DDQ

TCK

TDI

NC V

NC NC V

NC/144M NC

DDQ

TMS

891011

NC/288M

ADV/LD

NC/18M ANC

DDQ

NC DQP

DDQ

NC DQ

DDQ

NCV

DDQ

NC ZZ

DDQ

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CY7C1357C

Document #: 38-05539 Rev. *E Page 7 of 28

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous Address Inputs used to select one of the address locations. Sampled at the rising edge

of the CLK. A[1:0] are fed to the two-bit burst counter.

BWA, BWB

BWC, BWDInput-

Synchronous Byte Write Inputs, active LOW. Qualified with WE to conduct Writes to the SRAM. Sampled

on the rising edge of CLK.

WE Input-

Synchronous Write Enable Input, active LOW . Sampled on the rising edge of CLK if CEN is active LOW .

This signal must be asserted LOW to initiate a write sequence.

ADV/LD Input-

Synchronous Advance/Load Input. Used to advance the on-chip address counter or load a new address.

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW,

a new address can be loaded into the device for an access. After being deselected, ADV/LD

should be driven LOW in order to load a new address.

CLK Input-

Clock Clock Input. Used to capture all synchronous inpu ts to the device. CLK is qualifie d with

CEN. CLK is only recognized if CEN is active LOW .

CE1Input-

Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE2, and CE 3 to select/deselect the device.

CE2Input-

Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

with CE1 and CE3 to select/deselect the device.

CE3Input-

Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE1 and CE2 to select/deselect the device.

OE Input-

Asynchronous Output Enable, asynchronous input, active LOW . Combined with the synchronous logic

block inside the device to control the direction of the I/O pins. When LOW , the I/O pins are

allowed to behave as outpu ts. When deasserted HIGH , I/O pins are tri -stated, and act as

input data pins. OE is masked during the data portion of a write sequence, during the first

clock when emerging from a deselected state, when the device has been deselected.

CEN Input-

Synchronous Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by

the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN

does not deselect the device, CEN can be used to extend the previous cycle when required.

ZZ Input-

Asynchronous ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”

condition wi th data integri ty preserved. For norm al operation, this pin has to be LOW or left

floating. ZZ pin has an internal pull-down.

DQsI/O-

Synchronous Bidirectio nal Data I/O lines. As inputs, they feed into an on-chip data register that is

triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

memory location specified by the addresses presented during the previous clock rise of the

Read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the

pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The

outputs are automatically tri-stated during the data portion of a Write sequence, during the

first clock when emerging from a deselected state, and when the device is deselected,

regardless of the state of OE.

DQPXI/O-

Synchronous Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During

Write sequences, DQPX is controlled by BWX correspondingly.

MODE Input Strap Pin Mode Input. Se lects th e burst order of the device. When tied to Gnd selects linear burst

sequence. When tied to VDD or left floating selects interleaved burst sequence.

VDD Power Supply Power supply inputs to the core of the device.

VDDQ I/O Power

Supply Power supply for the I/O circuitry.

VSS Ground Ground for the device.

TDO JT AG serial output

Synchronous Serial data-out to the JT AG circuit. Delivers data on the negative edge of TCK. If the JT AG

feature is not being utilized, this pin should be left unconnected. This pin is not available on

TQFP packages.

TDI JT AG serial input

Synchronous Serial dat a-In to the JT AG circuit. Sampled on the rising edge of TCK. If the JT AG feature

is not being utilized, this pin can be left floating or connected to VDD through a pull up resistor.

This pin is not available on TQFP packages.

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CY7C1357C

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Functional Overview

The CY7C1355C/CY7C1357C is a synchronous flow-through

burst SRAM designed specifically to eliminate wait states

during Write-Read transitions. All synchronous inputs pass

through input registers controlled by the rising edge of the

clock. The clock signal is qualified with the Clock Enable input

signal (CEN). If CEN is HIGH, the clock signal is not recog-

nized and all internal states are maintained. All synchronou s

operations are qualified with CEN. Maximum access delay

from the clock rise (tCDV) is 6.5 ns (133-MHz device).

Accesses can be initiated by asserting all three Chip Enables

(CE1, CE2, CE3) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a Read or Write operation, depending on

the status of the Write Enable (WE). BWX can be used to

conduct Byte Write operations.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed Write

circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enab le (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW , (2) CE1, CE2,

and CE3 are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and 4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the address register a nd presented to the memory arra y

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the output buffers. The data is available within 7.5

ns (133-MHz device) provided OE is active LOW. After the first

clock of the read access, the ou tput buffers are controlled b y

OE and the internal con trol logic. OE must be driven LOW in

order for the device to drive out the requested data. On the

subsequent clock, another operation (Read/Write/Deselect)

can be initiated. When the SRAM is deselected at clock rise

by one of the chip enable signals, its output will be tri-stated

immediately.

Burst Read Accesses

The CY7C1355C/CY7C1357C has an on-chip burst counter

that allows the user the ability to supply a single address and

conduct up to four Reads without reasserting the address

inputs. ADV/LD must be driven LOW in order to load a new

address into the SRAM, as described in the Single Read

Access section above. The sequence of the burst counter is

determined by the MODE input signal. A LOW input on MODE

selects a linear burst mode, a HIGH selects an interleaved

burst sequence. Both burst counters use A0 and A1 in the

burst sequence, and will wrap around when incremented suffi-

ciently. A HIGH input on ADV/LD will increment the internal

burst counter regardless of the state of chip enable inputs or

WE. WE is latched at the beginning of a burst cycle. Therefore,

the type of access (Read or Write) is maintained throughout

the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW , (2) CE1, CE2,

and CE3 are ALL asserted active, and (3) the Write signal WE

is asserted LOW. The address presented to the addre ss bus

is loaded into the address register. The write signals are

latched into the Control Logic block. The data lines are

automatically tri-stated regardless of the state of the OE input

signal. This allows the external logic to present the data on

DQs and DQPX.

On the next clock rise the data presented to DQs and DQPX

(or a subset for byte write operations, see Truth Table for

details) inputs is latched into the device and the write is

complete. Additional accesses (Read/Write/Deselect) can be

initiated on this cycle.

The data written during the Write operation is controlled by

BWX signals. The CY7C1355C/CY7C1357C provides byte

write capability that is describ ed in the Truth Table. Asserting

the Write Enable input (WE) with the selected Byte Write

Select input will selectively write to only the desired bytes.

Bytes not selected during a byte write operation will remain

unaltered. A synchronous self-timed Write mechanism has

been provided to simplify the Write operations. Byte Write

capability has been included in order to greatly simplify

Read/Modify/Write sequences, which can be reduced to

simple Byte Write operations.

Because the CY7C1355C/CY7C1357C is a common I/O

device, data should not be driven into the device while the

outputs are active. The Output Enable (OE) can be deasserted

HIGH before presenting data to the DQs and DQPX inputs.

Doing so will tri-state the output drivers. As a safety

TMS JT AG serial input

Synchronous Serial dat a-In to the JT AG circuit. Sampled on the rising edge of TCK. If the JT AG feature

is not being utilized, this pi n can be disconnected or connected to VDD. This pin is not

available on TQFP packages.

TCK JTAG

Clock Clock input to the JTAG circui try. If the JTAG feature is not being utilized, this pin must

be connected to VSS. This pin is not available on TQFP packages.

NC – No Connects. Not internally connected to the die. 18 Mbit, 36 Mbit, 72 Mbit, 144 Mbit, 288

Mbit, 576 Mbit and 1G are address expansion pins and are not internally connected to the

die.

VSS/DNU Ground/DNU This pin can be connected to Ground or should be left floating.

Pin Definitions (continued)

Name I/O Description

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CY7C1357C

Document #: 38-05539 Rev. *E Page 9 of 28

precautio n, DQ s and DQPX ar e automat ically tri -stat ed during

the data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1355C/CY7C1357C has an on-chip burst counter

that allows the user the ability to supply a single address and

conduct up to four Write operations without reasserting the

address inputs. ADV/LD must be driven LOW in order to load

the initial address, as described in the Single Write Access

section above. When ADV/LD is driven HIGH on the subse-

quent clock rise, the Chip Enables (CE1, CE2, and CE3) and

WE inputs are ignored and the burst counter is incremented.

The correct BWX inputs must be driven in each cycle of the

burst write, in order to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The d evice must be deselecte d prior to entering

the “sleep” mode. CE1, CE2, and CE3, must remain inactive

for the duration of tZZREC after the ZZ input returns LOW.

. .

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

IDDZZ Sleep mode standby current ZZ > VDD – 0.2V 50 mA

tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ active to sleep current This parameter is sampled 2tCYC ns

tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns

Truth Table[2, 3, 4, 5, 6, 7, 8]

Operation Address

Used CE1CE2CE3ZZ ADV/LD WE BWXOE CEN CLK DQ

Deselect Cycle None H X X L L X X X L L->H Tri-State

Deselect Cycle None X X H L L X X X L L->H Tri-State

Deselect Cycle None X L X L L X X X L L->H Tri-State

Continue Deselect Cycle None X X X L H X X X L L->H Tri-State

READ Cycle (Begin Burst) External L H L L L H X L L L->H Data Out (Q)

READ Cycle (Continue Burst) Next X X X L H X X L L L->H Data Out (Q)

NOP/DUMMY READ (Begin Burst) External L H L L L H X H L L->H Tri-State

DUMMY READ (Continue Burst) Next X X X L H X X H L L->H Tri-State

WRITE Cycle (Begin Burst) External L H L L L L L X L L->H Data In (D)

WRITE Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D)

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write

Selects are asserted, see Truth Table for details.

3. Write is defined by BWX, and WE. See Truth Table for Read/Write.

4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.

5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6. CEN = H, inserts wait states.

7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

8. OE is asynchronous and is not sa mpled with the clock rise. It is ma sked internally during W rite cycles. During a Read cycle DQs a nd DQPX = T ri-stat e when OE

is inactive or when the device is deselected, and DQs and DQPX = dat a when OE is active.

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CY7C1357C

Document #: 38-05539 Rev. *E Page 10 of 28

NOP/WRITE ABORT (Begin Burst) None L H L L L L H X L L->H Tri-State

WRITE ABORT (Continue Burst) Next X X X L H X H X L L->H Tri-State

IGNORE CLOCK EDGE (Stall) Current X X X L X X X X H L->H –

SLEEP MODE None X X X H X X X X X X Tri-State

Partial Truth Table for Read/Write[2, 3, 9]

Function (CY7C1355C) WE BWABWBBWCBWD

Read H X X X X

Write No bytes written L H H H H

Write Byte A – (DQA and DQPA)LLHHH

Write Byte B – (DQB and DQP B)LHLHH

Write Byte C – (DQC and DQPC)LHHLH

Write Byte D – (DQD and DQPD)LHHHL

Write All Bytes L L L L L

Truth Table for Read/Write[2, 3,9]

Function (CY7C1357C) WE BWABWB

Read H X X

Write - No bytes written L H H

Write Byte A – (DQA and DQPA)LHH

Write Byte B – (DQB and DQPB)LHH

Write All Bytes L L L

Note:

9. Table only lists a p artial listing of the byte write combinations. Any combination of BWX is valid. Appropria te write will be done based o n which byte write is active.

Truth Table[2, 3, 4, 5, 6, 7, 8]

Operation Address

Used CE1CE2CE3ZZ ADV/LD WE BWXOE CEN CLK DQ

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CY7C1357C

Document #: 38-05539 Rev. *E Page 11 of 28

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1355C/CY7C1357C incorporates a serial boundary

scan test access port (TAP) in the BGA package only. The

TQFP package does not offer this functionality. This part

operates in accordance with IEEE S tandard 1149.1-1900, but

doesn’t have the set of functions required for full 1149.1

compliance. These functions from the IEEE specification are

excluded because their inclusion places an added delay in the

critical speed path of the SRAM. Note the TAP controller

functions in a manner that does not conflict with the operation

of other devices using 1149.1 fully compliant TAPs. The TAP

operates using JEDEC-standard 3.3V or 2.5V I/O logic le vels.

The CY7C1355C/CY7C1357C contains a TAP controller,

instruction register, boundary scan register, bypass register,

and ID register.

Disabling the JTAG Fea t ure

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied

LOW(VSS) to prevent clocking of the device. TDI and TMS are

internally pulled up and may be unconnected. They may alter-

nately be connected to VDD through a pull-up resistor. TDO

should be left unconnected. Upon power-up, the device will

come up in a reset state which will not interfere with the

operation of the device.

TAP Controller State Diagram

The 0/1 next to each state represents the value of TMS at the

rising edge of the TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the T AP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this ball unconnected if the TAP is not used. The ball is

pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. TDI

is internally pulled up and can be unconnected if the TAP is

unused in an application. TDI is connected to the most signif-

icant bit (MSB) of any register. (See Tap Controller Block

Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine. The output changes on the

falling edge of TCK. TDO is connected to the least signi fi cant

bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five

rising edges of TCK. This RESET does not affect the operation

of the SRAM and may be performed while the SRAM is

operating.

At power-up, the TAP is reset internally to ensure that TDO

comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can b e selected at a time through

the instruction register . Data is serially loaded into the TDI ball

on the rising edge o f TCK. Data is output on th e TDO bal l on

the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

TDI and TDO balls as shown in the Tap Controller Block

TEST-LOGIC

RESET

RUN-TEST/

IDLE SELECT

DR-SCAN SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

1 1

0 0

1 1

0 0

1 0

Bypass Register

Instruction Register

012

Identification Register

012293031 ...

Boundary Scan Register

012..x ...

election

Circuitr

Selection

Circuitry

TCK

MS TAP CONTROLLER

TDI TD

[+] Feedback [+] Feedback

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Document #: 38-05539 Rev. *E Page 12 of 28

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in th e pre v i o us section.

When the TAP controller is in the Capture-IR state, the two

least significant bits are loaded with a binary “01” pattern to

allow for fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

TDI and TDO balls. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(VSS) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and

bidirectional balls on the SRAM.

The boundary scan regi ster is loaded with the contents of the

RAM I/O ring when the TAP controller is in the Capture-DR

state and is then placed between the TDI and TDO balls when

the controller is moved to the Shift-DR state. The EXTEST,

SAMPLE/PRELOAD and SAMPLE Z instructions can be used

to capture the contents of the I/O ring.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

Identifi cati on (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the T AP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

TAP Instruction Set

Overview

Eight different instructions are possible with the three bit

instruction register. All combinations are listed in the

Instruction Codes table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO balls.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Upda te-IR state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO balls and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state.The IDCODE instruction is

loaded into the instruction register upon power-up or

whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO pins when the T AP

controller is in a Shift-DR state. The SAMPLE Z command puts

the output bus in to a High-Z state until the next command is

given during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the in-

struction register and the TAP controlle r is in the Capture-DR

state, a snapshot of dat a on the inputs and output pins is cap-

tured in the boundary scan register.

The user must be aware that the T AP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM cl ock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is possi-

ble that during the Capture-DR state, an input or output will

undergo a transition. The T AP may then try to capture a signal

while in transition (metastable state). This will not harm the

device, but there i s no guarantee as to the value that will be

captured. Repeatable results may not be possible.

To guaran tee that the boundary scan registe r will capture the

correct value of a signal, the SRAM signa l must be stabilized

long enough to meet the TAP controller's capture set-up plus

hold times (tCS and tCH). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK# captured in the

boundary scan register.

Once the data is captured, it is possible to shift out the data by

putting the T AP into the Shift-DR state. This places the bound-

ary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells pri-

or to the selection of another boundary scan test ope ration.

The shifting of data for the SAMPLE and PRELOAD phases

can occur concurrently when required—that is, while data

captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be

driven out through the system output pins. This instruction also

selects the boundary scan register to be connected for serial

access between the TDI and TDO in the shift-DR controller

state.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

[+] Feedback [+] Feedback

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Document #: 38-05539 Rev. *E Page 13 of 28

TAP Timing

TAP AC Switching Characteristics Over the Operating Range[10, 11]

Parameter Description Min. Max. Unit

Clock

tTCYC TCK Clock Cycle Time 50 ns

tTF TCK Clock Frequency 20 MHz

tTH TCK Clock HIGH Time 20 ns

tTL TCK Clock LOW Time 20 ns

Output Times

tTDOV TCK Clock LOW to TDO Valid 10 ns

tTDOX TCK Clock LOW to TDO Invalid 0 ns

Set-up Times

tTMSS TMS Set-Up to TCK Clock Rise 5 ns

tTDIS TDI Set-Up to TCK Clock Rise 5 ns

tCS Capture Set-Up to TCK Rise 5 ns

Hold Times

tTMSH TMS Hold after TCK Clock Rise 5 ns

tTDIH TDI Hold after Clock Rise 5 ns

tCH Capture Hold after Clock Rise 5 ns

Notes:

10.tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

11.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

tTL

Test Clock

(TCK)

123456

est Mode Select

(TMS)

tTH

Test Data-Out

(TDO)

tCYC

Test Data-In

(TDI)

tTMSH

tTMSS

tTDIH

tTDIS

tTDOX

tTDOV

DON’T CARE UNDEFINED

[+] Feedback [+] Feedback

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Document #: 38-05539 Rev. *E Page 14 of 28

3.3V TAP AC Test Conditions

Input pulse levels................................................ VSS to 3.3V

Input rise and fall times............................................. ... ...1 ns

Input timing reference levels...........................................1.5V

Output reference levels...................................................1.5V

Test load termination supply voltage...............................1.5V

3.3V TAP AC Output Load Equivalent

2.5V TAP AC Test Conditions

Input pulse levels.............. ... ... .............................VSS to 2.5V

Input rise and fall time ......... ... .........................................1 ns

Input timing reference levels.........................................1.25V

Output reference levels ................................................1.25V

Test load termination supply voltage ............................1.25V

2.5V TAP AC Output Load Equivalent

1.5V

20p

Z = 50Ω

50Ω

1.25V

20p

Z = 50Ω

50Ω

TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.3V ± 0.165V unless

otherwise noted)[12]

Parameter Description Conditions Min. Max. Unit

VOH1 Output HIGH Voltage IOH = –4.0 mA, VDDQ = 3.3V

IOH = –1.0 mA, VDDQ = 2.5V 2.4 V

2.0 V

VOH2 Output HIGH Voltage IOH = –100 µA VDDQ = 3.3V 2.9 V

VDDQ = 2.5V 2.1 V

VOL1 Output LOW Voltage IOL = 8.0 mA VDDQ = 3.3V 0.4 V

IOL = 8.0 mA VDDQ = 2.5V 0.4 V

VOL2 Output LOW Voltage IOL = 100 µA VDDQ = 3.3V 0.2 V

VDDQ = 2.5V 0.2 V

VIH Input HIGH Vo ltage VDDQ = 3.3V 2.0 VDD + 0.3 V

VDDQ = 2.5V 1.7 VDD + 0.3 V

VIL Input LOW Voltage VDDQ = 3.3V –0.5 0.7 V

VDDQ = 2.5V –0.3 0.7 V

IXInput Load Current GND < VIN < VDDQ –5 5 µA

Identification Register Definitions

Instruction Field CY7C1355C

(256Kx36) CY7C1357C

(512Kx18) Description

Revision Number (31:29) 010 010 Describes the version numb er

Device Depth (28:24) 01010 01010 Reserved for Internal Use

Device Width (23:18) 001001 001001 Defines memory type and ar chitecture

Cypress Device ID (17:12) 100110 010110 Defines width and density

Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor

ID Register Presence Indicator (0) 1 1 Indicates the presence of an ID register

Note:

12.All voltages re ferenced to VSS (GND).

[+] Feedback [+] Feedback

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Document #: 38-05539 Rev. *E Page 15 of 28

Scan Register Sizes

Instruction 3 3

Bypass 1 1

ID 32 32

Boundary Scan Order (119-ball BGA package) 69 69

Boundary Scan Order (165-ball FBGA package) 69 69

Identification Codes

Instruction Code Description

EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.

IDCODE 001 Loads the ID register with the vend or ID code and places the register between TDI and

TDO. This operation does not affect SRAM operations.

SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation. This instruction does not implement 1149.1 preload

function and is therefore not 1149.1 compliant.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

[+] Feedback [+] Feedback

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Document #: 38-05539 Rev. *E Page 16 of 28

119-ball BGA Boundary Scan Order

CY7C1355C (256K x 36) CY7C1357C (512K x 18)

Bit# ball ID Signal

Name Bit# ball ID Signal

Name Bit# ball Id Signal

Name

1K4 CLK 37 R6 A 1 K4 CLK 37 R6 A

2H4 WE38 T5 A 2 H4 WE 38 T5 A

3M4CEN39 T3 A 3 M4 CEN 39 T3 A

4F4 OE40 R2 A 4 F4 OE 40 R2 A

5B4ADV/LD

41 R3 MODE 5 B4 ADV/LD 41 R3 MODE

6G4 A 42 P2 DQP

D6 G4 A 42 Internal Internal

7C3 A 43 P1 DQ

D7 C3 A 43 Internal Internal

8 B3 A 44 L2 DQD8 B3 A 44 Internal Internal

9D6DQP

B45 K1 DQD9 T2 A 45 Internal Internal

10 H7 DQB46 N2 DQD10 Internal Internal 46 P2 DQPB

11 G6 DQB47 N1 DQD11 Internal Internal 47 N1 DQB

12 E6 DQB48 M2 DQD12 Internal Internal 48 M2 DQB

13 D7 DQB49 L1 DQD13 D6 DQPA49 L1 DQB

14 E7 DQB50 K2 DQD14 E7 DQA50 K2 DQB

15 F6 DQB51 Internal Internal 15 F6 DQA51 Internal Internal

16 G7 DQB52 H1 DQC16 G7 DQA52 H1 DQB

17 H6 DQB53 G2 DQC17 H6 DQA53 G2 DQB

18 T7 ZZ 54 E2 DQC18 T7 ZZ 54 E2 DQB

19 K7 DQA55 D1 DQC19 K7 DQA55 D1 DQB

20 L6 DQA56 H2 DQC20 L6 DQA56 Internal Internal

21 N6 DQA57 G1 DQC21 N6 DQA57 Internal Internal

22 P7 DQA58 F2 DQC22 P7 DQA58 Internal Internal

23 N7 DQA59 E1 DQC23 Internal Internal 59 Internal Internal

24 M6 DQA60 D2 DQPC24 Internal Internal 60 Internal Internal

25 L7 DQA61 C2 A 25 Internal Internal 61 C2 A

26 K6 DQA62 A2 A 26 Internal Internal 62 A2 A

27 P6 DQPA63 E4 CE127 Internal Internal 63 E4 CE1

28 T4 A 64 B2 CE228 T6 A 64 B2 CE2

29 A3 A 65 L3 BWD29 A3 A 65 Internal Internal

30 C5 A 66 G3 BWC30 C5 A 66 G3 BWB

31 B5 A 67 G5 BWB 31 B5 A 67 Internal Internal

32 A5 A 68 L5 BWA32 A5 A 68 L5 BWA

33 C6 A 69 B6 CE333 C6 A 69 B6 CE3

34 A6 A 34 A6 A

35 P4 A0 35 P4 A0

36 N4 A1 36 N4 A1

[+] Feedback [+] Feedback

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Document #: 38-05539 Rev. *E Page 17 of 28

165-ball FBGA Boundary Scan Order

CY7C1355C (256K x 36) CY7C1357C (512K x 18)

Bit# ball ID Signal

Name Bit# ball ID Signal

Name

1 B6 CLK 37 R4 A 1 B6 CLK 37 R4 A

2B7 WE 38 P4 A 2 B7 WE 38 P4 A

3A7CEN39 R3 A 3 A7 CEN 39 R3 A

4B8 OE 40 P3 A 4 B8 OE 40 P3 A

5A8ADV/LD

41 R1 MODE 5 A8 ADV/LD 41 R1 MODE

6 A9 A 42 N1 DQPD6 A9 A 42 Internal Internal

7B10 A 43 L2 DQ

D7 B10 A 43 Internal Internal

8A10 A 44 K2 DQ

D8 A10 A 44 Internal Internal

9C11DQP

B45 J2 DQD9 A11 A 45 Internal Internal

10 E10 DQB46 M2 DQD10 Internal Internal 46 N1 DQPB

11 F10 DQB47 M1 DQD11 Internal Internal 47 M1 DQB

12 G10 DQB48 L1 DQD12 Internal Internal 48 L1 DQB

13 D10 DQB49 K1 DQD13 C11 DQPA49 K1 DQB

14 D11 DQB50 J1 DQD14 D11 DQA50 J1 DQB

15 E11 DQB51 Internal Internal 15 E11 DQA51 Internal Internal

16 F11 DQB52 G2 DQC16 F11 DQA52 G2 DQB

17 G11 DQB53 F2 DQC17 G11 DQA53 F2 DQB

18 H11 ZZ 54 E2 DQC18 H11 ZZ 54 E2 DQB

19 J10 DQA55 D2 DQC19 J10 DQA55 D2 DQB

20 K10 DQA56 G1 DQC20 K10 DQA56 Internal Internal

21 L10 DQA57 F1 DQC21 L10 DQA57 Internal Internal

22 M10 DQA58 E1 DQC22 M10 DQA58 Internal Internal

23 J11 DQA59 D1 DQC23 Internal Internal 59 Internal Internal

24 K11 DQA60 C1 DQPC24 Internal Internal 60 Internal Internal

25 L11 DQA61 B2 A 25 Internal Internal 61 B2 A

26 M11 DQA62 A2 A 26 Internal Internal 62 A2 A

27 N11 DQPA63 A3 CE127 Internal Internal 63 A3 CE1

28 R11 A 64 B3 CE228 R11 A 64 B3 CE2

29 R10 A 65 B4 BWD29 R10 A 65 Internal Internal

30 P10 A 66 A4 BWC30 P10 A 66 Internal Internal

31 R9 A 67 A5 BWB31 R9 A 67 A4 BWB

32 P9 A 68 B5 BWA32 P9 A 68 B5 BWA

33 R8 A 69 A6 CE333 R8 A 69 A6 CE3

34 P8 A 34 P8 A

35 R6 A0 35 R6 A0

36 P6 A1 36 P6 A1

[+] Feedback [+] Feedback

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Document #: 38-05539 Rev. *E Page 18 of 28

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VDD Relative to GND........–0.5V to +4.6V

Supply Voltage on VDDQ Relative to GND......–0.5V to +VDD

DC Voltage Applied to Outputs

in Tri-State.................... ... ... .............. ...–0.5V to VDDQ + 0.5V

DC Input Voltage ......... ... .. .....................–0.5V to VDD + 0.5V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage...........................................> 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current....................................................> 200 mA.

Operating Range

Range Ambient

Temperature VDD VDDQ

Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%

to VDD

Industrial –40°C to +85°C

Electrical Characteristics Over the Operating Range[13, 14]

Parameter Description Test Conditions Min. Max. Unit

VDD Power Supply Voltage 3.135 3.6 V

VDDQ I/O Supply Voltage for 3.3V I/O 3.135 VDD V

for 2.5V I/O 2.375 2.625

VOH Output HIGH Vo ltage for 3.3V I/O, IOH = −4.0 mA 2.4 V

for 2.5V I/O, IOH = −1.0 mA 2.0 V

VOL Output LOW Voltage for 3.3V I/O, IOL= 8.0 mA 0.4 V

for 2.5V I/O, IOL= 1.0 mA 0.4 V

VIH Input HIGH Voltage[13] for 3.3V I/O 2.0 VDD + 0.3V V

for 2.5V I/O 1.7 VDD + 0.3V V

VIL Input LOW Voltage[13] for 3.3V I/O –0.3 0.8 V

for 2.5V I/O –0.3 0.7 V

IXInput Leakage Current

except ZZ and MODE GND ≤ VI ≤ VDDQ –5 5 µA

Input Current of MODE Input = VSS –30 µA

Input = VDD 5µA

Input Current of ZZ Input = VSS –5 µA

Input = VDD 30 µA

IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled –5 5 µA

IDD VDD Operating Supply

Current VDD = Max., IOUT = 0 mA,

f = fMAX = 1/tCYC 7.5-ns cycle, 133 MHz 250 mA

10-ns cycle, 100 MHz 180 mA

ISB1 Automatic CE

Power-down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL

f = fMAX, inputs switching

All speeds 110 mA

ISB2 Automatic CE

Power-down

Current—CMOS Inputs

VDD = Max, Device Deselected,

VIN ≤ 0.3V or VIN > VDD – 0.3V,

f = 0, inputs static

All speeds 40 mA

ISB3 Automatic CE

Power-down

Current—CMOS Inputs

VDD = Max, Device Deselected, or

VIN ≤ 0.3V or VIN > VDDQ – 0.3V

f = fMAX, inputs switching

All speeds 100 mA

ISB4 Automatic CE

Power-down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL, f = 0, inputs

static

All Speeds 40 mA

Notes:

13.Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).

14.TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During th is time VIH < VDD and VDDQ < VDD.

[+] Feedback [+] Feedback

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Document #: 38-05539 Rev. *E Page 19 of 28

Capacitance[15]

Parameter Description Test Conditions 100 TQFP

Max. 119 BGA

Max. 165 FBGA

Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = 3.3V.

VDDQ = 2.5V

555pF

CCLK Clock Input Capacitance 5 5 5 pF

CI/O Input/Output Capacitance 5 7 7 pF

Thermal Resistance[15]

Parameter Description Test Conditions 100 TQFP

Package 119 BGA

Package 165 FBGA

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient) Test conditions follow standard

test methods and procedures

for measuring thermal

impedance, per EIA/JESD51.

29.41 34.1 16.8 °C/W

ΘJC Thermal Resistance

(Junction to Case) 6.31 14.0 3.0 °C/W

AC Test Loads and Waveforms

Note:

15.Tested initially and after any design or process change that may affect these paramet ers

OUTPUT

R = 317Ω

R = 351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

= 1.5V

3.3V ALL INPUT PULSES

VDDQ

GND

90%

10% 90%

10%

≤1 ns ≤1 ns

(c)

OUTPUT

R = 1667Ω

R = 1538Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

VT= 1.25V

2.5V ALL INPUT PULSES

VDDQ

GND

90%

10% 90%

10%

≤1 ns ≤1 ns

(c)

3.3V I/O Test Load

2.5V I/O Test Load

[+] Feedback [+] Feedback

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Document #: 38-05539 Rev. *E Page 20 of 28

Switching Characteristics Over the Operating Range [16, 17]

Parameter Description

–133 –100

UnitMin. Max. Min. Max.

tPOWER VDD(Typical) to the First Access[18] 11ms

Clock

tCYC Clock Cycle Time 7.5 10 ns

tCH Clock HIGH 3.0 4.0 ns

tCL Clock LOW 3.0 4.0 ns

Output Times

tCDV Data Output Valid after CLK Rise 6.5 7.5 ns

tDOH Data Output Hold after CLK Rise 2.0 2.0 ns

tCLZ Clock to Low-Z[19, 20, 21] 00ns

tCHZ Clock to High-Z[19, 20, 21] 3.5 3.5 ns

tOEV OE LOW to Output Valid 3.5 3.5 ns

tOELZ OE LOW to Output Low-Z[19, 20, 21] 00ns

tOEHZ OE HIGH to Output High-Z[19, 20, 21] 3.5 3.5 ns

Set-up Times

tAS Address Set-up before CLK Rise 1.5 1.5 ns

tALS ADV/LD Set-up before CLK Rise 1.5 1.5 ns

tWES WE, BWX Set-up before CLK Rise 1.5 1.5 ns

tCENS CEN Set-up before CLK Rise 1.5 1.5 ns

tDS Data Input Set-up before CLK Rise 1.5 1.5 ns

tCES Chip Enable Set-Up before CLK Rise 1.5 1.5 ns

Hold Times

tAH Address Hold after CLK Rise 0.5 0.5 ns

tALH ADV/LD Hold after CLK Rise 0.5 0.5 ns

tWEH WE, BWX Hold after CLK Rise 0.5 0.5 ns

tCENH CEN Hold after CLK Rise 0.5 0.5 ns

tDH Data Input Hold after CLK Rise 0.5 0.5 ns

tCEH Chip Enable Hold after CLK Rise 0.5 0.5 ns

Notes:

16.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

17.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

18.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a Read or Write operation

can be initiated.

19.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Tr ansition is measured ± 200 mV from steady-state voltage.

20.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention bet ween SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condi tion, but ref lect p aramete rs gu arantee d o ver wo rst case u ser con dit ions. Device is de si gned

to achieve High-Z prior to Low-Z under the same system conditions.

21.This parameter is sampled and not 100% tested.

[+] Feedback [+] Feedback

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Document #: 38-05539 Rev. *E Page 21 of 28

Switching Waveforms

Read/Write Waveforms[22, 23, 24]

Notes:

22.For this waveform ZZ is tied LOW.

23.When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

24.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

WRITE

D(A1)

123456789

CLK

tCYC

tCL

tCH

tCEH

tCES

CEN

tCENH

tCENS

BWX

ADV/LD

tAH

tAS

ADDRESS A1 A2 A3 A4 A5 A6 A7

tDH

tDS

OMMAND

tCLZ

D(A1) D(A2) Q(A4)Q(A3)

D(A2+1)

tDOH tCHZ

tCDV

WRITE

D(A2) BURST

WRITE

D(A2+1)

READ

Q(A3) READ

Q(A4) BURST

READ

Q(A4+1)

WRITE

D(A5) READ

Q(A6) WRITE

D(A7) DESELECT

tOEV

tOELZ

tOEHZ

DON’T CARE UNDEFINED

D(A5)

tDOH

Q(A4+1)

D(A7)Q(A6)

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CY7C1357C

Document #: 38-05539 Rev. *E Page 22 of 28

NOP, STALL and DESELECT Cycles[22, 23 , 25 ]

Note:

25.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed durin g this cycle.

Switching Waveforms (continued)

WRITE

D(A1)

123456789

CLK

tCYC

tCL

tCH

tCEH

tCES

CEN

tCENH

tCENS

BWX

ADV/LD

tAH

tAS

ADDRESS A1 A2 A3 A4 A5 A6 A7

tDH

tDS

OMMAND

tCLZ

D(A1) D(A2) Q(A4)Q(A3)

D(A2+1)

tDOH tCHZ

tCDV

WRITE

D(A2) BURST

WRITE

D(A2+1)

READ

Q(A3) READ

Q(A4) BURST

READ

Q(A4+1)

WRITE

D(A5) READ

Q(A6) WRITE

D(A7) DESELECT

tOEV

tOELZ

tOEHZ

DON’T CARE UNDEFINED

D(A5)

tDOH

Q(A4+1)

D(A7)Q(A6)

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Document #: 38-05539 Rev. *E Page 23 of 28

ZZ Mode Timing[26, 27]

Notes:

26.Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.

27.DQs are in high-Z when exiting ZZ sleep mode.

Switching Waveforms (continued)

tZZ

ISUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q) High-Z

DESELECT or READ Only

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Document #: 38-05539 Rev. *E Page 24 of 28

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Part and Package Type Operating

Range

133 CY7C1355C-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1357C-133AXC

CY7C1355C-133BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1357C-133BGC

CY7C1355C-133BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1357C-133BGXC

CY7C1355C-133BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1357C-133BZC

CY7C1355C-133BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1357C-133BZXC

CY7C1355C-133AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial

CY7C1357C-133AXI

CY7C1355C-133BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1357C-133BGI

CY7C1355C-133BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1357C-133BGXI

CY7C1355C-133BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1357C-133BZI

CY7C1355C-133BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1357C-133BZXI

100 CY7C1355C-100AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1357C-100AXC

CY7C1355C-100BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1357C-100BGC

CY7C1355C-100BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1357C-100BGXC

CY7C1355C-100BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1357C-100BZC

CY7C1355C-100BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1357C-100BZXC

CY7C1355C-100AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial

CY7C1357C-100AXI

CY7C1355C-100BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1357C-100BGI

CY7C1355C-100BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1357C-100BGXI

CY7C1355C -100BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1357C-100BZI

CY7C1355C-100BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1357C-100BZXI

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Document #: 38-05539 Rev. *E Page 25 of 28

Package Diagrams

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

3. DIMENSIONS IN MILLIMETERS

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

0.30±0.08

0.65

20.00±0.10

22.00±0.20

1.40±0.05

12°±1°

1.60 MAX.

0.05 MIN.

0.60±0.15

0° MIN.

0.25

0°-7°

(8X)

STAND-OFF

R 0.08 MIN.

TYP.

0.20 MAX.

0.15 MAX.

0.20 MAX.

R 0.08 MIN.

0.20 MAX.

14.00±0.10

16.00±0.20

0.10

SEE DETAIL A

DETAIL

100

31 50

GAUGE PLANE

1.00 REF.

0.20 MIN.

SEATING PLANE

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)

51-85050-*B

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Document #: 38-05539 Rev. *E Page 26 of 28

Package Diagrams (continued)

1.27

20.32

2165437

12.00

19.50

30° TYP.

2.40 MAX.

A1 CORNER

0.70 REF.

2143657

Ø1.00(3X) REF.

7.62

22.00±0.20

14.00±0.20

1.27

0.60±0.10

0.15 C

0.15(4X)

Ø0.05 M C

Ø0.75±0.15(119X)

Ø0.25MCAB

SEATING PLANE

0.90±0.05

3.81

10.16

0.25 C

0.56

51-85115-*B

119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)

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CY7C1355C

CY7C1357C

Document #: 38-05539 Rev. *E Page 27 of 28

© Cypress Semi con duct or Cor po rati on , 20 06 . The information contained he re i n is su bj ect to change withou t n oti ce. C ypr ess S em icon ductor Corporation assumes no responsib ility f or the u se

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furtherm ore, Cypress doe s not authorize i ts

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Package Diagrams (continued)

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device

Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders

PIN 1 CORNER

15.00±0.10

13.00±0.10

7.00

1.00

Ø0.50 (165X)

Ø0.25MCAB

Ø0.05 M C

0.15(4X)

0.35±0.06

SEATING PLANE

0.53±0.05

0.25 C

0.15 C

PIN1CORNER

TOP VIEW

BOTTOM VIEW

2345678910

10.00

14.00

1110986754321

15.00±0.10

13.00±0.10

1.00

5.00

0.36

-0.06

+0.14

1.40 MAX.

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

NOTES :

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

51-85180-*A

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

PIN 1 CORNER

15.00±0.10

13.00±0.10

7.00

1.00

Ø0.50 (165X)

Ø0.25 M C A B

Ø0.05 M C

0.15(4X)

0.35±0.06

SEATING PLANE

0.53±0.05

0.25 C

0.15 C

PIN 1 CORNER

TOP VIEW

BOTTOM VIEW

2345678910

10.00

14.00

1110986754321

15.00±0.10

13.00±0.10

1.00

5.00

0.36

-0.06

+0.14

1.40 MAX.

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

NOTES :

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

51-85180-*A

165-Ball FB G A (1 3 x 1 5 x 1.4 mm) (51-85180)

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Document #: 38-05539 Rev. *E Page 28 of 28

Document History Page

Document Title: CY7C1355C/CY7C1357C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture

Document Number: 38-05539

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 242032 See ECN RKF New data sheet

*A 332059 See ECN PCI Changed Boundary Scan Order to match the B rev of these devices

Removed description on Extest Output Bus Tri-state

Removed 117 MHz Speed Bin

Changed IDDZZ from 35 mA to 50 mA on Pg # 9

Changed ISB1 and ISB3 from 40 mA to 110 and 100 mA respectively

Address expansion pins/balls in the pinouts for all packages are modified as

per JEDEC standard

Modified VOL, VOH test conditions

Corrected ISB4 Test Condition from (VIN ≥ VDD – 0.3V or VIN ≤ 0.3V) to (VIN ≥ VIH

or VIN ≤ VIL) in the Electrical Characteristic Table on Pg #18

Changed ΘJA and ΘJc for TQFP Package from 25 and 9 °C/W to 29.41 and

6.13 °C/W

respectively

Changed ΘJA and ΘJc for BGA Package from 25 and 6 °C/W to 34.1 and 14.0

°C/W

respectively

Changed ΘJA and ΘJc for FBGA Package from 27 and 6 °C/W to 16.8 and 3.0

°C/W respectively

Added lead-free information for 100-pin TQF P, 119 BGA and 165 FBGA

Packages

Updated Ordering Information Table

Changed from Preliminary to Fina l

*B 351895 See ECN PCI Changed ISB2 from 30 to 40 mA

Updated Ordering Information Table

*C 377095 See ECN PCI Modified test condition in note# 14 from VIH < VDD to VIH < VDD

*D 408298 See ECN RXU Changed address of Cypress Semiconductor Corporatio n on Page# 1 from

“3901 North First Street” to “198 Champion Court”

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table

Changed three-state to tri-state

Replaced Package Name column with Package Diagram in the Ordering

Information table

Updated Ordering Information Table

*E 501793 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC

Switching Characteristics table.

Updated the Ordering Information table.

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