© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 0
1Publication Order Number:
KAI−08052/D
KAI-08052
3296 (H) x 2472 (V)
Interline CCD Image Sensor
Description
The KAI−08052 Image Sensor is an 8−megapixel, 4/3” optical
format CCD that provides increased Quantum Efficiency (particularly
for NIR wavelengths) compared to members of the standard 5.5 mm
family.
The sensor shares the same broad dynamic range, excellent imaging
performance, and flexible readout architecture as other members of
the 5.5 mm pixel family. But QE at 820 nm has been approximately
doubled compared to existing devices, enabling enhanced sensitivity
without a corresponding decrease in the Modulation Transfer Function
(MTF) of the device.
The KAI−08052 is available with the Sparse Color Filter Pattern,
which provides a 2x improvement in light sensitivity compared to a
standard color Bayer part.
The KAI−08052 is drop−in compatible with the KAI−08051 Image
Sensor, simplifying adoption by camera manufacturers currently
working with the KAI−08051.
Table 1. GENERAL SPECIFICATIONS
Parameter Typical Value
Architecture Interline CCD; Progressive Scan
Total Number of Pixels 3364 (H) x 2520 (V)
Number of Effective Pixels 3320 (H) x 2496 (V)
Number of Active Pixels 3296 (H) x 2472 (V)
Pixel Size 5.5 mm (H) x 5.5 mm (V)
Active Image Size 18.13 mm (H) x 13.60 mm (V)
22.66 mm (diag), 4/3” optical format
Aspect Ratio 4:3
Number of Outputs 1, 2, or 4
Charge Capacity 20,000 electrons
Output Sensitivity 35 mV/e−
Quantum Efficiency
Pan (−ABA, −QBA)
R, G, B (−FBA, −QBA)
48%, 12%, 5% (535, 850, 920 nm)
42%, 41%, 38% (615, 535, 460 nm)
Read Noise (f = 40 MHz) 10 e−
Dark Current
Photodiode / VCCD 1 / 70 electrons/s
Dark Current Doubling Temp.
Photodiode / VCCD 7°C / 9°C
Dynamic Range 66 dB
Charge Transfer Efficiency 0.999999
Blooming Suppression > 300 X
Smear −100 dB
Image Lag < 10 electrons
Maximum Pixel Clock Speed 40 MHz
Maximum Frame Rates
Quad / Dual / Single Output 16 / 8 / 4 fps
Package 68 pin PGA
Cover Glass AR coated, 2 Sides or Clear Glass
NOTE: All parameters are specified at T = 40°C unless otherwise noted.
www.onsemi.com
Figure 1. KAI−08052 CCD Image Sensor
Features
•Increased QE, with 2x Improvement
at 820 nm
•Bayer Color, Sparse Color,
and Monochrome Configurations
•Progressive Scan Readout
•Flexible Readout Architecture
•High Sensitivity, Low Noise Architecture
•Excellent Smear Performance
Applications
•Scientific and Medical Imaging
•Intelligent Transportation Systems
•Machine Vision
See detailed ordering and shipping information on page 2 of
this data sheet.
ORDERING INFORMATION
KAI−08052
www.onsemi.com
2
ORDERING INFORMATION
Table 2. ORDERING INFORMATION
Part Number Description Marking Code
KAI−08052−ABA−JD−BA Monochrome, Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides),
Standard Grade
KAI−08052−ABA
Serial Number
KAI−08052−ABA−JD−AE Monochrome, Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides),
Engineering Grade
KAI−08052−ABA−JP−BA Monochrome, Telecentric Microlens, PGA Package,
Taped Clear Cover Glass, no coatings, Standard Grade
KAI−08052−ABA−JP−AE Monochrome, Telecentric Microlens, PGA Package,
Taped Clear Cover Glass, no coatings, Engineering Grade
KAI−08052−FBA−JD−BA Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides),
Standard Grade
KAI−08052−FBA
Serial Number
KAI−08052−FBA−JD−AE Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides),
Engineering Grade
KAI−08052−QBA−JD−BA Gen2 Color (Sparse CFA), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides),
Standard Grade
KAI−08052−QBA
Serial Number
KAI−08052−QBA−JD−AE Gen2 Color (Sparse CFA), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides),
Engineering Grade
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
KAI−08052
www.onsemi.com
3
DEVICE DESCRIPTION
Architecture
Figure 2. Block Diagram (Monochrome − No Filter Pattern)
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
HLOD
12 Dark
12
V1B
12 Buffer
12
12
22
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
1 Dummy
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
1 Dummy
3296H x 2472V
5.5 mm x 5.5 mm Pixels
1648 1648
1648 1648
(Last VCCD Phase = V1 → H1S)
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sa
H1Ba
H2Sa
H2Ba
RDa
Ra
VDDa
VOUTa
GND
H1Sb
H1Bb
H2Sb
H2Bb
RDc
Rc
VDDc
VOUTc
GND
RDd
Rd
VDDd
VOUTd
GND
RDb
Rb
VDDb
VOUTb
GND
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sd
H1Bd
H2Sd
H2Bd
H1Sc
H1Bc
H2Sc
H2Bc
H2SLa
OGa
H2SLc
OGc
H2SLd
OGd
H2SLb
OGb
ESD ESD
SUBSUB
822 10 112822101 12
822101 12 8 2212
22 12
DevID
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
HLOD
10 1
Dark Reference Pixels
There are 12 dark reference rows at the top and 12 dark
rows at the bottom of the image sensor. The dark rows are not
entirely dark and so should not be used for a dark reference
level. Use the 22 dark columns on the left or right side of the
image sensor as a dark reference.
Under normal circumstances use only the center 20
columns of the 22 column dark reference due to potential
light leakage.
Dummy Pixels
Within each horizontal shift register there are 11 leading
additional shift phases. These pixels are designated as
dummy pixels and should not be used to determine a dark
reference level.
In addition, there is one dummy row of pixels at the top
and bottom of the image.
Active Buffer Pixels
12 unshielded pixels adjacent to any leading or trailing
dark reference regions are classified as active buffer pixels.
These pixels are light sensitive but are not tested for defects
and non−uniformities.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron−hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non−linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
KAI−08052
www.onsemi.com
4
ESD Protection
Adherence to the power−up and power−down sequence is
critical. Failure to follow the proper power−up and
power−down sequences may cause damage to the sensor.
See Power−Up and Power−Down Sequence section.
Bayer Color Filter Pattern
Figure 3. Bayer Color Filter Pattern
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
HLOD
12 Dark
12
V1B
12 Buffer
12
12
B G
GR
22
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
1 Dummy
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
1 Dummy
3296H x 2472V
5.5 mm x 5.5 mm Pixels
1648 1648
1648 1648
(Last VCCD Phase = V1 → H1S)
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sa
H1Ba
H2Sa
H2Ba
RDa
Ra
VDDa
VOUTa
GND
H1Sb
H1Bb
H2Sb
H2Bb
RDc
Rc
VDDc
VOUTc
GND
RDd
Rd
VDDd
VOUTd
GND
RDb
Rb
VDDb
VOUTb
GND
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sd
H1Bd
H2Sd
H2Bd
H1Sc
H1Bc
H2Sc
H2Bc
H2SLa
OGa
H2SLc
OGc
H2SLd
OGd
H2SLb
OGb
ESD ESD
SUBSUB
822 10 112822101 12
822101 12 8 22 10 112
22 12
DevID
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
HLOD
B G
GR
B G
GR
B G
GR
Sparse Color Filter Pattern
Figure 4. Sparse Color Filter Pattern
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
HLOD
12 Dark
12
V1B
12 Buffer
12
12
22
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
1 Dummy
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
1 Dummy
3296H x 2472V
5.5 mm x 5.5 mm Pixels
1648 1648
1648 1648
(Last VCCD Phase = V1 → H1S)
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sa
H1Ba
H2Sa
H2Ba
RDa
Ra
VDDa
VOUTa
GND
H1Sb
H1Bb
H2Sb
H2Bb
RDc
Rc
VDDc
VOUTc
GND
RDd
Rd
VDDd
VOUTd
GND
RDb
Rb
VDDb
VOUTb
GND
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sd
H1Bd
H2Sd
H2Bd
H1Sc
H1Bc
H2Sc
H2Bc
H2SLa
OGa
H2SLc
OGc
H2SLd
OGd
H2SLb
OGb
ESD ESD
SUBSUB
822 10 112
822101 12
822101 12 8 22 10 112
22 12
DevID
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
HLOD
P B G
R
P
B P
P
G
G
G
P
P
P R P
P B G
R
P
B P
P
G
G
G
P
P
P R P
P B G
R
P
B P
P
G
G
G
P
P
P R P
P B G
R
P
B P
P
G
G
G
P
P
P R P
KAI−08052
www.onsemi.com
5
PHYSICAL DESCRIPTION
Pin Description and Device Orientation
Figure 5. Package Pin Designations − Top View
Pixel
(1,1)
1 3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V3B V1B
V4B
VDDa
V2B
GND
VOUTa
Ra
RDa
H2SLa
OGa
H1Bb
H2Bb
H2Sb
H1Sb
N/C
SUB
H2Sa
H1Sa
H1Ba
H2Ba
23
24
H2SLb
OGb
25
26
27
28
29
30
31
32
V1B
V4B
VDDb
V2B
GND
VOUTb
Rb
RDb
33
34
V3B
ESD
68 66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
ESD V4T
V1T
V2T
VDDc
VOUTc
GND
RDc
Rc
OGc
H2SLc
H2Bd
H1Bd
H1Sd
H2Sd
SUB
N/C
H1Sc
H2Sc
H2Bc
H1Bc
46
45
OGd
H2SLd
44
43
42
41
40
39
38
37
V4T
V1T
V2T
VDDd
VOUTd
GND
RDd
Rd
36
35
DevID
V3T
67
V3T
KAI−08052
www.onsemi.com
6
Table 3. PIN DESCRIPTION
Pin Name Description
1 V3B Vertical CCD Clock, Phase 3, Bottom
3 V1B Vertical CCD Clock, Phase 1, Bottom
4 V4B Vertical CCD Clock, Phase 4, Bottom
5 VDDa Output Amplifier Supply, Quadrant a
6 V2B Vertical CCD Clock, Phase 2, Bottom
7 GND Ground
8 VOUTa Video Output, Quadrant a
9 Ra Reset Gate, Quadrant a
10 RDa Reset Drain, Quadrant a
11 H2SLa Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant a
12 OGa Output Gate, Quadrant a
13 H1Ba Horizontal CCD Clock, Phase 1, Barrier,
Quadrant a
14 H2Ba Horizontal CCD Clock, Phase 2, Barrier,
Quadrant a
15 H2Sa Horizontal CCD Clock, Phase 2,
Storage, Quadrant a
16 H1Sa Horizontal CCD Clock, Phase 1,
Storage, Quadrant a
17 N/C No Connect
18 SUB Substrate
19 H2Sb Horizontal CCD Clock, Phase 2,
Storage, Quadrant b
20 H1Sb Horizontal CCD Clock, Phase 1,
Storage, Quadrant b
21 H1Bb Horizontal CCD Clock, Phase 1, Barrier,
Quadrant b
22 H2Bb Horizontal CCD Clock, Phase 2, Barrier,
Quadrant b
23 H2SLb Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant b
24 OGb Output Gate, Quadrant b
25 Rb Reset Gate, Quadrant b
26 RDb Reset Drain, Quadrant b
27 GND Ground
28 VOUTb Video Output, Quadrant b
29 VDDb Output Amplifier Supply, Quadrant b
30 V2B Vertical CCD Clock, Phase 2, Bottom
31 V1B Vertical CCD Clock, Phase 1, Bottom
32 V4B Vertical CCD Clock, Phase 4, Bottom
33 V3B Vertical CCD Clock, Phase 3, Bottom
34 ESD ESD Protection Disable
Pin Name Description
68 ESD ESD Protection Disable
67 V3T Vertical CCD Clock, Phase 3, Top
66 V4T Vertical CCD Clock, Phase 4, Top
65 V1T Vertical CCD Clock, Phase 1, Top
64 V2T Vertical CCD Clock, Phase 2, Top
63 VDDc Output Amplifier Supply, Quadrant c
62 VOUTc Video Output, Quadrant c
61 GND Ground
60 RDc Reset Drain, Quadrant c
59 Rc Reset Gate, Quadrant c
58 OGc Output Gate, Quadrant c
57 H2SLc Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant c
56 H2Bc Horizontal CCD Clock, Phase 2, Barrier,
Quadrant c
55 H1Bc Horizontal CCD Clock, Phase 1, Barrier,
Quadrant c
54 H1Sc Horizontal CCD Clock, Phase 1,
Storage, Quadrant c
53 H2Sc Horizontal CCD Clock, Phase 2,
Storage, Quadrant c
52 SUB Substrate
51 N/C No Connect
50 H1Sd Horizontal CCD Clock, Phase 1,
Storage, Quadrant d
49 H2Sd Horizontal CCD Clock, Phase 2,
Storage, Quadrant d
48 H2Bd Horizontal CCD Clock, Phase 2, Barrier,
Quadrant d
47 H1Bd Horizontal CCD Clock, Phase 1, Barrier,
Quadrant d
46 OGd Output Gate, Quadrant d
45 H2SLd Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant d
44 RDd Reset Drain, Quadrant d
43 Rd Reset Gate, Quadrant d
42 VOUTd Video Output, Quadrant d
41 GND Ground
40 V2T Vertical CCD Clock, Phase 2, Top
39 VDDd Output Amplifier Supply, Quadrant d
38 V4T Vertical CCD Clock, Phase 4, Top
37 V1T Vertical CCD Clock, Phase 1, Top
36 DevID Device Identification
35 V3T Vertical CCD Clock, Phase 3, Top
1. Liked named pins are internally connected and should have a
common drive signal.
2. N/C pins (17, 51) should be left floating.
KAI−08052
www.onsemi.com
7
IMAGING PERFORMANCE
Table 4. TYPICAL OPERATION CONDITIONS
Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.
Description Condition Notes
Light Source Continuous red, green and blue LED illumination For monochrome sensor, only green LED used.
Operation Nominal operating voltages and timing
Table 5. SPECIFICATIONS
All Configurations
Description Symbol Min. Nom. Max. Units
Sampling
Plan
Temperature
Tested At
(5C) Notes
Dark Field Global Non−Uniformity DSNU − − 2.0 mVpp Die 27, 40
Bright Field Global Non−Uniformity −2.0 5.0 %rms Die 27, 40 1
Bright Field Global Peak to Peak
Non−Uniformity
PRNU −5.0 15.0 %pp Die 27, 40 1
Bright Field Center Non−Uniformity −1.0 2.0 %rms Die 27, 40 1
Maximum Photoresponse
Nonlinearity
NL −2−% Design 2
Maximum Gain Difference Between
Outputs
DG−10 −% Design 2
Maximum Signal Error due to
Nonlinearity Differences
DNL −1−% Design 2
Horizontal CCD Charge Capacity HNe −55 −ke−Design
Vertical CCD Charge Capacity VNe −40 −ke−Design
Photodiode Charge Capacity PNe −20 −ke−Die 27, 40 3
Horizontal CCD Charge Transfer
Efficiency
HCTE 0.999995 0.999999 −Die
Vertical CCD Charge Transfer
Efficiency
VCTE 0.999995 0.999999 −Die
Photodiode Dark Current Ipd −1 70 e/p/s Die 40
Vertical CCD Dark Current Ivd −70 300 e/p/s Die 40
Image Lag Lag − − 10 e−Design
Antiblooming Factor Xab 300 − − Design
Vertical Smear Smr − −100 −dB Design
Read Noise ne−T−10 −e−rms Design 4
Dynamic Range DR −66 −dB Design 4, 5
Output Amplifier DC Offset Vodc −9.1 −V Die 27, 40
Output Amplifier Bandwidth f−3db −250 −MHz Die 6
Output Amplifier Impedance ROUT −127 −WDie 27, 40
Output Amplifier Sensitivity DV/DN−35 −mV/e−Design
1. Per color
2. Value is over the range of 10% to 90% of photodiode saturation.
3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such
that the photodiode charge capacity is 800 mV.
4. At 40 MHz
5. Uses 20LOG (PNe/ ne−T)
6. Assumes 5 pF load.
KAI−08052
www.onsemi.com
8
Table 6. KAI−08052−ABA AND KAI−08052−QBA CONFIGURATIONS WITH MAR GLASS
Description Symbol Min. Nom. Max. Units
Sampling
Plan
Temperature
Tested At
(5C) Notes
Peak Quantum Efficiency QEmax −48 −% Design
Peak Quantum Efficiency
Wavelength
lQE −535 −nm Design
Quantum Efficiency (850 nm) QEmax −12 −% Design
Quantum Efficiency (920 nm) QEmax −5−% Design
Table 7. KAI−08052−ABA CONFIGURATIONS WITH TAPED CLEAR GLASS
Description Symbol Min. Nom. Max. Units
Sampling
Plan
Temperature
Tested At
(5C) Notes
Peak Quantum Efficiency
(No Glass)
QEmax −48 −% Design
Peak Quantum Efficiency
Wavelength (No Glass)
lQE −535 −nm Design
Table 8. KAI−08052−FBA AND KAI−08052−QBA CONFIGURATIONS WITH MAR GLASS
Description Symbol Min. Nom. Max. Units
Sampling
Plan
Temperature
Tested At
(5C) Notes
Peak Quantum Efficiency Blue
Green
Red
QEmax −38
41
42
−% Design
Peak Quantum Efficiency
Wavelength
Blue
Green
Red
lQE −460
535
615
−nm Design
KAI−08052
www.onsemi.com
11
Angular Quantum Efficiency
For the curves marked “Horizontal”, the incident light
angle is varied in a plane parallel to the HCCD.
For the curves marked “Vertical”, the incident light angle
is varied in a plane parallel to the VCCD.
Monochrome with Microlens
Figure 10. Monochrome with Microlens Angular Quantum Efficiency
Dark Current versus Temperature
Figure 11. Dark Current versus Temperature
KAI−08052
www.onsemi.com
13
DEFECT DEFINITIONS
Table 9. OPERATION CONDITIONS FOR DEFECT TESTING AT 405C
Description Condition Notes
Operational Mode Two outputs, using VOUTa and VOUTc, continuous readout
HCCD Clock Frequency 10 MHz
Pixels Per Line 3520 1
Lines Per Frame 1360 2
Line Time 354.9 ms
Frame Time 482.7 ms
Photodiode Integration Time Mode A: PD_Tint = Frame Time = 482.7 ms, no electronic shutter used
Mode B: PD_Tint = 33 ms, electronic shutter used
VCCD Integration Time 447.2 ms 3
Temperature 40°C
Light Source Continuous red, green and blue LED illumination 4
Operation Nominal operating voltages and timing
1. Horizontal overclocking used.
2. Vertical overclocking used.
3. VCCD Integration Time = 1260 lines x Line Time, which is the total time a pixel will spend in the VCCD registers.
4. For monochrome sensor, only the green LED is used.
Table 10. DEFECT DEFINITIONS FOR TESTING AT 405C
Description Definition Standard Grade Notes
Major dark field defective bright pixel PD_Tint = Mode A → Defect ≥ 191 mV
or
PD_Tint = Mode B → Defect ≥ 13.8 mV
80 1
Major bright field defective dark pixel Defect ≥ 12%
Minor dark field defective bright pixel PD_Tint = Mode A → Defect ≥ 99 mV
or
PD_Tint = Mode B → Defect ≥ 7 mV
800
Cluster defect A group of 2 to 10 contiguous major defective pixels, but no
more than 3 adjacent defects
horizontally.
15 2
Column defect A group of more than 10 contiguous major
defective pixels along a single column
0 2
1. For the Bayer color device (KAI−08052−FBA), a bright field defective pixel deviates by 12% with respect to pixels of the same color.
2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects).
KAI−08052
www.onsemi.com
14
Table 11. OPERATION CONDITIONS FOR DEFECT TESTING AT 275C
Description Condition Notes
Operational Mode Two outputs, using VOUTa and VOUTc, continuous readout
HCCD Clock Frequency 20 MHz
Pixels Per Line 3520 1
Lines Per Frame 1360 2
Line Time 177.8 ms
Frame Time 241.8 ms
Photodiode Integration Time
(PD_Tint)
Mode A: PD_Tint = Frame Time = 241.8 ms, no electronic shutter used
Mode B: PD_Tint = 33 ms, electronic shutter used
VCCD Integration Time 224.0 ms 3
Temperature 27°C
Light Source Continuous red, green and blue LED illumination 4
Operation Nominal operating voltages and timing
1. Horizontal overclocking used.
2. Vertical overclocking used.
3. VCCD Integration Time = 1260 lines x Line Time, which is the total time a pixel will spend in the VCCD registers.
4. For monochrome sensor, only the green LED is used.
Table 12. DEFECT DEFINITIONS FOR TESTING AT 275C
Description Definition Standard Grade Notes
Major dark field defective bright pixel PD_Tint = Mode A → Defect ≥ 30 mV
or
PD_Tint = Mode B → Defect ≥ 4.6 mV
80 1
Major bright field defective dark pixel Defect ≥ 12%
Cluster defect A group of 2 to 10 contiguous major defective pixels, but no
more than 3 adjacent defects
horizontally.
15 2
Column defect A group of more than 10 contiguous major
defective pixels along a single column
0 2
1. For the Bayer color device (KAI−08052−FBA), a bright field defective pixel deviates by 12% with respect to pixels of the same color.
2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects).
Defect Map
The defect map supplied with each sensor is based upon
testing at an ambient (27°C) temperature. Minor point
defects are not included in the defect map. All defective
pixels are reference to pixel 1, 1 in the defect maps. See
Figure 14: Regions of interest for the location of pixel 1,1.
KAI−08052
www.onsemi.com
15
TEST DEFINITIONS
Test Regions of Interest
Image Area ROI: Pixel (1, 1) to Pixel (3320, 2496)
Active Area ROI: Pixel (13, 13) to Pixel (3308, 2484)
Center ROI: Pixel (1611, 1199) to Pixel (1710, 1298)
Only the Active Area ROI pixels are used for performance and defect tests.
Overclocking
The test system timing is configured such that the sensor
is overclocked in both the vertical and horizontal directions.
See Figure 14 for a pictorial representation of the regions of
interest.
Figure 14. Regions of Interest
Horizontal Overclock
12 buffer rows
12 buffer rows
12 buffer columns
12 buffer columns
22 dark columns
22 dark columns
12 dark rows
VOUTa
12 dark rows
3296 x 2472
Active Pixels
1, 1
13,
13
Pixel
Pixel
VOUTc
Tests
Dark Field Global Non−Uniformity
This test is performed under dark field conditions. The
sensor is partitioned into 768 sub regions of interest, each of
which is 103 by 103 pixels in size. The average signal level
of each of the 768 sub regions of interest is calculated. The
signal level of each of the sub regions of interest is calculated
using the following formula:
Signal of ROI[i] = (ROI Average in counts − Horizontal
overclock average in counts) * mV per count
Where i = 1 to 768. During this calculation on the 768 sub
regions of interest, the maximum and minimum signal levels
are found. The dark field global uniformity is then calculated
as the maximum signal found minus the minimum signal
level found.
Units: mVpp (millivolts peak to peak)
KAI−08052
www.onsemi.com
16
Global Non−Uniformity
This test is performed with the imager illuminated to a
level such that the output is at 70% of saturation
(approximately 560 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 800 mV. Global non−uniformity is
defined as
GlobalNon−Uniformity +100 ǒActiveAreaStandardDeviation
ActiveAreaSignal Ǔ
Units: %rms.
Active Area Signal = Active Area Average − Dark Column
Average
Global Peak to Peak Non−Uniformity
This test is performed with the imager illuminated to a
level such that the output is at 70% of saturation
(approximately 560 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 800 mV. The sensor is partitioned
into 768 sub regions of interest, each of which is 103 by 103
pixels in size. The average signal level of each of the 768 sub
regions of interest (ROI) is calculated. The signal level of
each of the sub regions of interest is calculated using the
following formula:
Signal of ROI[i] = (ROI Average in counts − Horizontal
overclock average in counts) * mV per count
Where i = 1 to 768. During this calculation on the 768 sub
regions of interest, the maximum and minimum signal levels
are found. The global peak to peak uniformity is then
calculated as:
GlobalUniformity +100 MaximumSignal *MinimumSignal
ActiveAreaSignal
Units: %pp
Center Non−Uniformity
This test is performed with the imager illuminated to a
level such that the output is at 70% of saturation
(approximately 560 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 800 mV. Defects are excluded for
the calculation of this test. This test is performed on the
center 100 by 100 pixels of the sensor. Center uniformity is
defined as:
Center ROI Uniformity +100 ǒCenter ROI Standard Deviation
Center ROI Signal Ǔ
Units: %rms.
Center ROI Signal = Center ROI Average − Dark Column
Average
Dark Field Defect Test
This test is performed under dark field conditions. The
sensor is partitioned into 768 sub regions of interest, each of
which is 103 by 103 pixels in size. In each region of interest,
the median value of all pixels is found. For each region of
interest, a pixel is marked defective if it is greater than or
equal to the median value of that region of interest plus the
defect threshold specified in the “Defect Definitions”
section.
Bright Field Defect Test
This test is performed with the imager illuminated to a
level such that the output is at approximately 476 mV. Prior
to this test being performed the substrate voltage has been set
such that the charge capacity of the sensor is 680 mV. The
average signal level of all active pixels is found. The bright
and dark thresholds are set as:
Dark defect threshold = Active Area Signal * threshold
Bright defect threshold = Active Area Signal * threshold
The sensor is then partitioned into 768 sub regions of
interest, each of which is 103 by 103 pixels in size. In each
region of interest, the average value of all pixels is found.
For each region of interest, a pixel is marked defective if it
is greater than or equal to the median value of that region of
interest plus the bright threshold specified or if it is less than
or equal to the median value of that region of interest minus
the dark threshold specified.
Example for major bright field defective pixels:
•Average value of all active pixels is found to be
560 mV
•Dark defect threshold: 560 mV * 12 % = 67 mV
•Bright defect threshold: 560 mV * 12 % = 67 mV
•Region of interest #1 selected. This region of interest is
pixels 13, 13 to pixels 115, 115.
♦Median of this region of interest is found to be
560 mV.
♦Any pixel in this region of interest that
is ≥ (560 + 67 mV) 627 mV in intensity will be
marked defective.
♦Any pixel in this region of interest that
is ≤ (560 − 67 mV) 493 mV in intensity will be
marked defective.
•All remaining 768 sub regions of interest are analyzed
for defective pixels in the same manner.
KAI−08052
www.onsemi.com
17
OPERATION
Table 13. ABSOLUTE MAXIMUM RATINGS
Description Symbol Minimum Maximum Units Notes
Operating Temperature TOP −50 70 °C 1
Humidity RH 5 90 % 2
Output Bias Current Iout 60 mA 3
Off−chip Load CL10 pF
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Noise performance will degrade at higher temperatures.
2. T = 25°C. Excessive humidity will degrade MTTF.
3. Total for all outputs. Maximum current is −15 mA for each output. Avoid shorting output pins to ground or any low impedance source during
operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity).
Table 14. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND
Description Minimum Maximum Units Notes
VDDa, VOUTa−0.4 15.5 V 1
RDa−0.4 15.5 V 1
V1B, V1T ESD − 0.4 ESD + 24.0 V
V2B, V2T, V3B, V3T, V4B, V4T ESD − 0.4 ESD + 14.0 V
H1Sa, H1Ba, H2Sa, H2Ba, H2SLa, Ra, OGaESD − 0.4 ESD + 14.0 V 1
ESD −10.0 0.0 V
SUB −0.4 40.0 V 2
1. a denotes a, b, c or d
2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. (AND9183/D)
Power−Up and Power−Down Sequence
Adherence to the power−up and power−down sequence is critical. Failure to follow the proper power−up and power−down
sequences may cause damage to the sensor.
Figure 15. Power−Up and Power−Down Sequence
VDD
SUB
ESD VCCD
Low
HCCD
Low
time
V+
V−Activate all other biases when ESD is stable and SUB is above 3 V
Do not pulse the electronic shutter until ESD is stable
Notes:
1. Activate all other biases when ESD is stable and
SUB is above 3 V
2. Do not pulse the electronic shutter until ESD is
stable
3. VDD cannot be +15 V when SUB is 0 V
4. The image sensor can be protected from an
accidental improper ESD voltage by current
limiting the SUB current to less than 10 mA. SUB
and VDD must always be greater than GND. ESD
must always be less than GND. Placing diodes
between SUB, VDD, ESD and ground will protect
the sensor from accidental overshoots of SUB,
VDD and ESD during power on and power off.
See the figure below.
KAI−08052
www.onsemi.com
18
The VCCD clock waveform must not have a negative
overshoot more than 0.4 V below the ESD voltage.
Figure 16.
All VCCD Clocks absolute
maximum overshoot of 0.4 V
0.0 V
ESD
ESD − 0.4 V
Example of external diode protection for SUB, VDD and
ESD. a denotes a, b, c or d
Figure 17.
GND
SUB
VDDa
ESD
Table 15. DC BIAS OPERATING CONDITIONS
Description Pins Symbol Minimum Nominal Maximum Units
Maximum DC
Current Notes
Reset Drain RDaRD 11.8 12.0 12.2 V 10 mA1
Output Gate OGaOG −2.2 −2.0 −1.8 V10 mA1
Output Amplifier Supply VDDaVDD 14.5 15.0 15.5 V 11.0 mA 1, 2
Ground GND GND 0.0 0.0 0.0 V −1.0 mA
Substrate SUB VSUB 5.0 VAB VDD V 50 mA3, 8
ESD Protection Disable ESD ESD −9.2 −9.0 Vx_L V 50 mA6, 7, 9
Output Bias Current VOUTaIout −3.0 −7.0 −10.0 mA 1, 4, 5
1. a denotes a, b, c or d
2. The maximum DC current is for one output. Idd = Iout + Iss. See Figure 18.
3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such
that the photodiode charge capacity is the nominal PNe (see Specifications).
4. An output load sink must be applied to each VOUT pin to activate each output amplifier.
5. Nominal value required for 40 MHz operation per output. May be reduced for slower data rates and lower noise.
6. Adherence to the power−up and power−down sequence is critical. See Power−Up and Power−Down Sequence section.
7. ESD maximum value must be less than or equal to V1_L + 0.4 V and V2_L + 0.4 V
8. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions (AND9183/D)
9. Where Vx_L is the level set for V1_L, V2_L, V3_L, or V4_L in the application.
KAI−08052
www.onsemi.com
20
AC Operating Conditions
Table 16. CLOCK LEVELS
Description Pins (1) Symbol Level Minimum Nominal Maximum Units Capacitance (2)
Vertical CCD Clock,
Phase 1
V1B, V1T V1_L Low −8.2 −8.0 −7.8 V43 nF (6)
V1_M Mid −0.2 0.0 0.2
V1_H High 11.5 12.0 12.5
Vertical CCD Clock,
Phase 2
V2B, V2T V2_L Low −8.2 −8.0 −7.8 V43 nF (6)
V2_H High −0.2 0.0 0.2
Vertical CCD Clock,
Phase 3
V3B, V3T V3_L Low −8.2 −8.0 −7.8 V43 nF (6)
V3_H High −0.2 0.0 0.2
Vertical CCD Clock,
Phase 4
V4B, V4T V4_L Low −8.2 −8.0 −7.8 V43 nF (6)
V4_H High −0.2 0.0 0.2
Horizontal CCD Clock,
Phase 1 Storage
H1SaH1S_L Low −5.2 (7) −4.0 −3.8 V280 pF (6)
H1S_A Amplitude 3.8 4.0 5.2 (7)
Horizontal CCD Clock,
Phase 1 Barrier
H1BaH1B_L Low −5.2 (7) −4.0 −3.8 V190 pF (6)
H1B_A Amplitude 3.8 4.0 5.2 (7)
Horizontal CCD Clock,
Phase 2 Storage
H2SaH2S_L Low −5.2 (7) −4.0 −3.8 V280 pF (6)
H2S_A Amplitude 3.8 4.0 5.2 (7)
Horizontal CCD Clock,
Phase 2 Barrier
H2BaH2B_L Low −5.2 (7) −4.0 −3.8 V190 pF (6)
H2B_A Amplitude 3.8 4.0 5.2 (7)
Horizontal CCD Clock,
Last Phase (3) H2SLaH2SL_L Low −5.2 −5.0 −4.8 V20 pF (6)
H2SL_A Amplitude 4.8 5.0 5.2
Reset Gate RaR_L (4) Low −3.5 −2.0 −1.5 V16 pF (6)
R_H High 2.5 3.0 4.0
Electronic Shutter (5) SUB VES High 29.0 30.0 40.0 V 3 nF (6)
1. a denotes a, b, c or d
2. Capacitance is total for all like named pins
3. Use separate clock driver for improved speed performance.
4. Reset low should be set to –3 V for signal levels greater than 40,000 electrons.
5. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions (AND9183/D)
6. Capacitance values are estimated
7. If the minimum horizontal clock low level is used (–5.2 V), then the maximum horizontal clock amplitude should be used (5.2 V amplitude)
to create a –5.2 V to 0.0 V clock. If a 5 V clock driver is used, the horizontal low level should be set to –5.0 V and the high level should be
a set to 0.0 V.
The figure below shows the DC bias (VSUB) and AC
clock (VES) applied to the SUB pin. Both the DC bias and
AC clock are referenced to ground.
Figure 19.
VSUB
VES
GND GND
KAI−08052
www.onsemi.com
21
Device Identification
The device identification pin (DevID) may be used to determine which 5.5 micron pixel interline CCD sensor is being used.
Note that the KAI−08052 shares the same Device ID value as the KAI−08050 and KAI−08051.
Table 17. DEVICE IDENTIFICATION
Description Pins Symbol Minimum Nominal Maximum Units
Maximum DC
Current Notes
Device Identification DevID DevID 8,000 10,000 12,000 W50 mA1, 2
1. If the Device Identification is not used, it may be left disconnected.
2. Values specified are for 40°C.
Recommended Circuit
Note that V1 must be a different value than V2.
Figure 20. Device Identification Recommended Circuit
ADC
R_external
V1 V2
DevID
GND
KAI−08052
R_DeviceID
KAI−08052
www.onsemi.com
22
TIMING
Table 18. REQUIREMENTS AND CHARACTERISTICS
Description Symbol Minimum Nominal Maximum Units Notes
Photodiode Transfer tpd 1.0 − − ms
VCCD Leading Pedestal t3p 4.0 − − ms
VCCD Trailing Pedestal t3d 4.0 − − ms
VCCD Transfer Delay td1.0 − − ms
VCCD Transfer tv2.0 − − ms
VCCD Clock Cross−over VVCR 75 100 %
VCCD Rise, Fall Times tVR, tVF 5−10 % 2, 3
HCCD Delay ths 0.2 − − ms
HCCD Transfer te25.0 − − ns
Shutter Transfer tsub 1.0 − − ms
Shutter Delay thd 1.0 − − ms
Reset Pulse tr2.5 − − ns
Reset – Video Delay trv −2.2 −ns
H2SL – Video Delay thv −3.1 −ns
Line Time tline 45.5 − − msDual HCCD Readout
87.6 − − Single HCCD Readout
Frame Time tframe 57.4 − − ms Quad HCCD Readout
114.8 − − Dual HCCD Readout
220.7 − − Single HCCD Readout
1. Refer to timing diagrams as shown in Figures 21, 22, 23, 24 and 25.
2. Refer to Figure 25: VCCD Clock Edge Alignment
3. Relative to the pulse width
KAI−08052
www.onsemi.com
23
Timing Diagrams
The timing sequence for the clocked device pins may be
represented as one of seven patterns (P1−P7) as shown in the
table below. The patterns are defined in Figure 21 and
Figure 22. Contact ON Semiconductor Application
Engineering for other readout modes.
Table 19.
Device Pin Quad Readout
Dual Readout
VOUTa, VOUTb
Dual Readout
VOUTa, VOUTc
Single Readout
VOUTa
V1T P1T P1B P1T P1B
V2T P2T P4B P2T P4B
V3T P3T P3B P3T P3B
V4T P4T P2B P4T P2B
V1B P1B
V2B P2B
V3B P3B
V4B P4B
H1Sa P5
H1Ba
H2Sa2 P6
H2Ba
Ra P7
H1Sb P5 P5
H1Bb P6
H2Sb (2) P6 P6
H2Bb P5
Rb P7 P7 (1) or Off (3) P7 (1) or Off (3)
H1Sc P5 P5 (1) or Off (3) P5 P5 (1) or Off (3)
H1Bc
H2Sc (2) P6 P6 (1) or Off (3) P6 P6 (1) or Off (3)
H2Bc
Rc P7 P7 (1) or Off (3) P7 P7 (1) or Off (3)
H1Sd P5 P5 (1) or Off (3) P5 P5 (1) or Off (3)
H1Bd P6
H2Sd (2) P6 P6 (1) or Off (3) P6 P6 (1) or Off (3)
H2Bd P5
Rd P7 P7 (1) or Off (3) P7 (1) or Off (3) P7 (1) or Off (3)
# Lines/Frame (Minimum) 1260 2520 1260 2520
# Pixels/Line (Minimum) 1693 3386
1. For optimal performance of the sensor. May be clocked at a lower frequency. If clocked at a lower frequency, the frequency selected should
be a multiple of the frequency used on the a and b register.
2. H2SLx follows the same pattern as H2Sx For optimal speed performance, use a separate clock driver.
3. Off = +5 V. Note that there may be operating conditions (high temperature and/or very bright light sources) that will cause blooming from the
unused c/d register into the image area.
KAI−08052
www.onsemi.com
24
Photodiode Transfer Timing
A row of charge is transferred to the HCCD on the falling
edge of V1 as indicated in the P1 pattern below. Using this
timing sequence, the leading dummy row or line is
combined with the first dark row in the HCCD. The “Last
Line” is dependent on readout mode – either 632 or 1264
minimum counts required. It is important to note that, in
general, the rising edge of a vertical clock (patterns P1−P4)
should be coincident or slightly leading a falling edge at the
same time interval. This is particularly true at the point
where P1 returns from the high (3rd level) state to the
mid−state when P4 transitions from the low state to the high
state.
Figure 21. Photodiode Transfer Timing
Last Line L1 + Dummy Line
P1B
P2B
P3B
P4B
Pattern
L2
P1T
P2T
P3T
P4T
tv
tv/2
tpd
tv/2 tv/2
td
tdt3p t3d
tv
ths
tv
tv/2
tv
ths
tv/2 tv/2
P5
P6
P7
1 2 3 4 5 6
Line and Pixel Timing
Each row of charge is transferred to the output, as
illustrated below, on the falling edge of H2SL (indicated as
P6 pattern). The number of pixels in a row is dependent on
readout mode – either 853 or 1706 minimum counts
required.
Figure 22. Line and Pixel Timing
P1T
P5
P6
P7
Pixel
n
Pixel
1
Pixel
34
tline
tv
ths
te
tr
te/2
VOUT
Pattern
P1B
tv
KAI−08052
www.onsemi.com
25
Pixel Timing Detail
Figure 23. Pixel Timing Detail
P5
P6
P7
VOUT
thv trv
Frame/Electronic Shutter Timing
The SUB pin may be optionally clocked to provide
electronic shuttering capability as shown below.
The resulting photodiode integration time is defined from
the falling edge of SUB to the falling edge of V1 (P1
pattern).
Figure 24. Frame/Electronic Shutter Timing
P1T/B
P6
SUB tint
tframe
thd
thd
tsub
Pattern
VCCD Clock Edge Alignment
Figure 25. VCCD Clock Edge Alignment
VVCR
90%
10%
tV
tVR tVF
90%
10%
tVR
tV
tVF
KAI−08052
www.onsemi.com
27
MECHANICAL INFORMATION
Completed Assembly
Figure 27. Completed Assembly, Top and Side View
Notes:
1. See Ordering Information for
marking code.
2. No materials to interfere
with clearance through guide
holes.
3. The center of the active
image is nominally at the
center of the package.
4. Die rotation < 0.5 degrees
5. Internal traces may be
exposed on sides of package.
Do not allow metal to
contact sides of ceramic
package.
6. Recommended mounting
screws: 1.6 X 0.35 mm (ISO
Standard); 0 − 80 (Unified
Fine Thread Standard)
7. Units: millimeters
KAI−08052
www.onsemi.com
28
Figure 28. Completed Assembly, Bottom View
Notes:
1. See Ordering Information for marking code.
2. No materials to interfere with clearance through guide holes.
3. Recommended mounting screws: 1.6 X 0.35 mm (ISO Standard); 0 – 80 (Unified Fine Thread Standard)
4. Units: millimeters
KAI−08052
www.onsemi.com
29
Figure 29. Completed Assembly, Side View with Glass and Die Detail
Notes:
1. No materials to interfere with clearance through guide holes.
2. Internal traces may be exposed on sides of package. Do not allow metal to contact sides of ceramic package.
3. Recommended mounting screws: 1.6 X 0.35 mm (ISO Standard); 0 – 80 (Unified Fine Thread Standard)
4. Units: millimeters
KAI−08052
www.onsemi.com
33
STORAGE AND HANDLING
Table 20. STORAGE CONDITIONS
Description Symbol Minimum Maximum Units Notes
Storage Temperature TST −55 80 °C 1
Humidity RH 5 90 % 2
1. Long term storage toward the maximum temperature will accelerate color filter degradation.
2. T = 25°C. Excessive humidity will degrade MTTF.
REFERENCES
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference Manual (SOLDERRM/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
KAI−08052/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
