DS206 September 10, 2010 www.xilinx.com 1
Product Specification v3.167 & v4.13
© 2002-2010 Xi linx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated bra nds included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG.
Features
•Fully compliant 32-bit, 66/33 MHz Initiator/Target
core for PCI®
•Customizable, programmable, single-chip solution
•Pre-defined implementation for predictable timing
•Incorporates Xilinx Smart-IP™ technology
•3.3V operation at 0–66 MHz
•Fully verified design tested with Xilinx proprietary
test bench and hardware
•Delivered through the Xilinx CORE Generator™
software
•CardBus compliant
•Supported initiator functions:
♦Configuration read, configuration write
♦Memory read, memory write, MRM, MRL
♦Interrupt acknowledge, special cycles
♦I/O read, I/O write
•Supported target functions:
♦Type 0 configuration space header
♦Up to three base address registers (MEM or
I/O with adjustable block size from 16 bytes to
2 GB)
♦Medium decode speed
♦Parity generation, parity error detection
♦Configuration read, configuration write
♦Memory read, memory write, MRM, MRL
♦Interrupt acknowledge
♦I/O read, I/O write
♦Target abort, target retry, target disconnect
LogiCORE IP 32-Bit
Initiator/Target
v3 & v4 for PCI
DS206 September 10, 2010 Product Specification v3.1 67 & v4.13
LogiCORE IP Facts
Core Specifics
Supported Device
Family See Table 1.
Resources Used(1)
1. Depends on configuration of the interface and design. Unused re-
sources are trimmed by the Xilinx technology mapper. The utiliza-
tion figures reported represent a maximum configuration.
v4 Core v3 Core
LUTs 506 553
Slice Flip-Flops 333 566
IOB Flip-Flops 270 97
IOBs 55 50
GCLKs(2)
2. Virtex-4 and Virtex-5 implementations require additional BUFG for
200 MHz reference clock.
21
Provided with Core
Documentation
Getting Started Guide v4
Getting Started Guide v3
User Guide v4
User Guide v3
Design File Formats Verilog/VHDL Simulation Model
NGC Netlist (v4 core only)
NGO Netlist (v3 core only)
Constrai nts File .ucf (user constraints file)
Example Design Verilog/VHDL Example Design
Design Tool Requirements
Xilinx Implem entation
Tools ISE® 12.2
Verification(3) (4)
3. See the PCI Getting Start ed Guide or product release notes for cur-
rent supported version.
4. Requires a Verilog LRM-IEEE 1364-2005 encryption-compliant
simulator. For VHDL simulation, a mixed HDL license is required.
Synplicity™ Synplify
Xilinx XST((5))
Mentor Graphics® ModelSim® v6.4b
and above
Cadence® IUS v8.1 -s009 and above
5. XST is a command line option only.
Support
Provided by Xilinx, Inc .
LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI
2www.xilinx.com DS206 September 10, 2010
Product Specification v3.167 & v4.13
Note: Xilinx provides technical support f or this LogiCORE IP product when used only as described in the Getting
Started and User Gu ides. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices not listed, or if it is customized beyond the guidelines provided in the associated product documentation.
For Spartan-6 devices, only those devices listed in Table 1 have been tested with the latest software
speed files to meet PCI timing. If you require a part or package not listed in the data sheet, open a
WebCase with Xilinx for latest available status
Table 1: Core Implementation
Supported Devices(1), (2), (3) Core Version Signaling Environment
PCI32/66
Virtex-5 XC5VFX70T-FF1136-2C/I(4) (regional clock) v4 3.3V only
Virtex-5 XC5VLX50-FF1153-2C/I(4) (regional clock) v4 3.3V only
Virtex-5 XC5VLX50T-FF1136-2/C/I(4) (regional clock) v4 3.3V only
Virtex-5 XC5VLX110-FF1153-2C/I(4) (regional clock) v4 3.3V only
Virtex-5 XC5VLX110T-FF1136-2/C/I(4) (regional clock) v4 3.3V only
Virtex-5 XC5VSX50T-FF1136-2/C/I(4) (regional clock) v4 3.3V only
Virtex-5 XC5VSX95T-FF1136-2/C/I(4) (regional clock) v4 3.3V only
Virtex-4 XC4VFX20-FF672-11C/I(4) (regional clock) v3 3.3V only
Virtex-4 XC4VLX25-FF688-11C/I(4), (5) (regional clock) v3 3.3V only
Virtex-4 XC4VSX35-FF668-11C/I(4), (5) (regional clock) v3 3.3V only
Spartan-3A XC3S400A-FG400-5C v3 3.3V only
Spartan-3A XC3S700A-FG400-5C v3 3.3V only
Spartan-3A XC3S700A-FG484-5C v3 3.3V only
Spartan-3A XC3S1400A-FG484-5C v3 3.3V only
Spartan-3A XC3S1400A-FG676-5C v3 3.3V only
Spartan-3AN XC3S400AN-FGG400-5C v3 3.3V only
Spartan-3AN XC3S700AN-FGG484-5C v3 3.3V only
Spartan-3AN XC3S140 0AN-FGG676-5C v3 3.3V only
Spartan-3ADSP XC3SD1800A-FG676-5C v3 3.3V only
Spartan-3ADSP XC3SD3400A-FG676-5C v3 3.3V only
Spartan-3E XC3S500E-FT256-5C(5) v3 3.3V only
Spartan-3E XC3S1200E-FG400-5C(5) v3 3.3V only
PCI32/33
Virtex-5 XC5VFX70T-FF1136-1C/I(4) (global clock) v4 3.3V only
Virtex-5 XC5VFX70T-FF1136-1C/I(4) (regional clock) v4 3.3V only
Virtex-5 XC5VLX50-FF1153-1C/I(4) (global clock) v4 3.3V only
Virtex-5 XC5VLX50-FF1153-1C/I(4) (regional clock) v4 3.3V only
Virtex-5 XC5VLX50T-FF1136-1C/I(4) (global clock) v4 3.3V only
Virtex-5 XC5VLX110T-FF1136-1C/I(4) (global clock) v4 3.3V only
Virtex-5 XC5VLX110T-FF1136-1C/I(4) (regional clock) v4 3.3V only
Virtex-5 XC5VSX50T-FF1136-1C/I(4) (regiona l clock) v4 3.3V only
Virtex-5 XC5VSX95T-FF1136-1C/I(4) (global clock) v4 3.3V only
DS206 September 10, 2010 www.xilinx.com 3
Product Specification v3.167 & v4.13
LogiCORE IP 32-Bit Initiato r/Target v3 & v4 for PCI
Virtex-5 XC5VSX95T-FF1136-1C/I(4) (regiona l clock) v4 3.3V only
Virtex-5 XC5VLX110-FF1153-1C/I(4) (global clock) v4 3.3V only
Virtex-5 XC5VLX110-FF1153-1C/I(4) (regional clock) v4 3.3V only
Virtex-4 XC4VFX20-FF672-10C/I(4) (global clock) v3 3.3V only
Virtex-4 XC4VFX20-FF672-10C/I(4) (regional clock) v3 3.3V only
Virtex-4 XC4VLX25-FF668-10C/I(4), (5) (global clock) v3 3.3V only
Virtex-4 XC4VLX25-FF668-10C/I(4), (5) (regional clock) v3 3.3V only
Virtex-4 XC4VSX35-FF668-10C/I(4), (5) (global clock) v3 3.3V only
Virtex-4 XC4VSX35-FF668-10C/I(4), (5) (regional clock) v3 3.3V only
Spartan-6 XC6SLX4-TQG144-2C/I v4 3.3V only
Spartan-6 XC6SLX4-CPG196-2C/I v4 3.3V only
Spartan-6 XC6SLX4-CSG225-2C/I v4 3.3V only
Spartan-6 XC6SLX9-CPG196-2C/I v4 3.3V only
Spartan-6 XC6SLX9-TQG144-2C/I v4 3.3V only
Spartan-6 XC6SLX9-CSG225-2C/I v4 3.3V only
Spartan-6 XC6SLX9-FTG256-2C/I v4 3.3V only
Spartan-6 XC6SLX9-CSG324-2C/I v4 3.3V only
Spartan-6 XC6SLX16-CSG22 5-2C/ v4 3.3V only
Spartan-6 XC6SLX16-FTG256-2C/I v4 3.3V only
Spartan-6 XC6SLX16-CSG324-2C/I v4 3.3V only
Spartan-6 XC6SLX16-CPG196-2C/I v4 3.3V only
Spartan-6 XC6SLX25-FTG256-2C/I v4 3.3V only
Spartan-6 XC6SLX25-CSG324-2C/I v4 3.3V only
Spartan- 6 XC6SLX25T-CSG324-2 C/I v4 3.3V only
Spartan-6 XC6SLX25-FGG484-2C/I v4 3.3V only
Spartan- 6 XC6SLX25T-FGG484-2 C/I v4 3.3V only
Spartan-6 XC6SLX45-CSG324-2C/I v4 3.3V only
Spartan- 6 XC6SLX45T-CSG324-2 C/I v4 3.3V only
Spartan-6 XC6SLX45-FGG484-2C/I v4 3.3V only
Spartan-6 XC6SLX45T-FGG484-2C/I v4 3.3V only
Spartan-6 XC6SLX45-FGG676-2C/I v4 3.3V only
Spartan-6 XC6SLX45-CSG484-2C/I v4 3.3V only
Spartan-6 XC6SLX45T-CSG-484-2C/I v4 3.3V only
Spartan-6 XC6SLX75-CSG484-2C/I v4 3.3V only
Spartan-6 XC6SLX75T-CSG484-2C/I v4 3.3V only
Spartan-6 XC6SLX75-FGG484-2C/I v4 3.3V only
Spartan-6 XC6SLX75T-FGG484-2C/I v4 3.3V only
Spartan-6 XC6SLX75-FGG676-2C/I v4 3.3V only
Table 1: Core Implementation (Cont’d)
Supported Devices(1), (2), (3) Core Version Signaling Environment
LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI
4www.xilinx.com DS206 September 10, 2010
Product Specification v3.167 & v4.13
Spartan-6 XC6SLX75T-FGG676-2C/I v4 3.3V only
Spartan-6 XC6SLX100-CSG484-2C /I v4 3.3V only
Spartan-6 XC6SLX100T-CSG484-2C/I v4 3.3V only
Spartan-6 XC6SLX100-FGG484-2C /I v4 3.3V only
Spartan-6 XC6SLX100T-FGG484-2C/I v4 3.3V only
Spartan-6 XC6SLX100-FGG676-2C /I v4 3.3V only
Spartan-6 XC6SLX100T-FGG676-2C/I v4 3.3V only
Spartan-6 XC6SLX150-CSG484-2C /I v4 3.3V only
Spartan-6 XC6SLX150T-CSG484-2C/I v4 3.3V only
Spartan-6 XC6SLX150-FGG484-2C /I v4 3.3V only
Spartan-6 XC6SLX150T-FGG484-2C/I v4 3.3V only
Spartan-6 XC6SLX150-FGG676-2C /I v4 3.3V only
Spartan-6 XC6SLX150T-FGG676-2C/I v4 3.3V only
Spartan-3A XC3S400A-FG400-4C/I v3 3.3V only
Spartan-3A XC3S700A-FG400-4C/I v3 3.3V only
Spartan-3A XC3S700A-FG484-4C/I v3 3.3V only
Spartan-3A XC3S1400A-FG484-4C/I v3 3.3V only
Spartan-3A XC3S1400A-FG676-4C/I v3 3.3V only
Spartan-3AN XC3S400 AN-FGG400-4C/I v3 3.3V only
Spartan-3AN XC3S700 AN-FGG484-4C/I v3 3.3V only
Spartan-3AN XC3S1400AN-FGG676-4C/I v3 3.3V only
Spartan-3ADSP XC3SD1800A-FG676-4C/I v3 3.3V only
Spartan-3ADSP XC3SD3400A-FG676-4C/I v3 3.3V only
Spartan-3E XC3S500E-FT256-4C/I(5) v3 3.3V only
Spartan-3E XC3S1200E-FG400-4C/I(5) v3 3.3V onl y
Spartan-3 XC3S1000-FG456-4C/I v3 3.3V only
1. Virtex-5, Virt ex-4, Sp artan-6 , Spar tan-3A , Spar tan -3AN, S part an-3ADSP , Spar tan-3E and Spart an-3 devices are su ppor ted over co m-
mercial and industrial temperature ranges.
2. Packages listed are supported in both standard and lead-free variants, if available. For example, FF1136 denotes support for both
FF1136 and FFG1136 packages.
3. For additional part/ package combinations in Spartan-3 and older device families, see the UCF Generator at
www.xilinx.com/cgi-bin/UCFgen/UCF4PCI.cgi. For Spar tan-3E, Spartan-3A, Spartan-3AN, Sp artan-3A DSP, Virtex-4 and newer device
families, use the UCF Generator in the CORE Generator software.
4. Virtex-4 and Virtex-5 so lutions require a 200 MHz reference clock.
5. Virtex-4 (except FX) and Spart an-3E solutions require silicon stepping 1 or later.
Table 1: Core Implementation (Cont’d)
Supported Devices(1), (2), (3) Core Version Signaling Environment
DS206 September 10, 2010 www.xilinx.com 5
Product Specification v3.167 & v4.13
LogiCORE IP 32-Bit Initiato r/Target v3 & v4 for PCI
Applications
•Embedded applications in networking, industrial, and telecommunication systems
•Add-in boards for PCI such as frame buffers, network adapters, and data acquisition boards
•Hot swap CompactPCI boards
•CardBus compliant
•Any applications that require an interface for PCI
General Description
The Initiator/Target core for PCI is a pre-implemented and fully tested module for Xilinx FPGAs. The
pinout for each device and the relative placement of the internal logic are predefined. Critical paths are
controlled by constraints files to ensure predictable timing. This significantly reduces engineering time
required to implement the PCI portion of your design. Resources can instead be focused on your
unique user application logic in the FPGA and on the system-level design. As a result, Xilinx products
for PCI minimize your product development time.
The core meets the setup, hold, and clock-to-timing requirements as defined in the PCI specification.
The interface is verified through extensive simulation.
Other FPGA resources that can be used in conjunction with the core to enable efficient implementation
of a PCI system include:
•Block SelectRAM™ memory. Blocks of on-chip ultra-fast RAM with synchronous write and dual-
port RAM capabilities. Used in PCI designs to implement FIFOs.
•SelectRAM memory. Distributed on-chip ultra-fast RAM with synchronous write option and dual-
port RAM capabilities. Used in PCI designs to implement FIFOs.
•Internal three-state bus capability for data multiplexing.
The interface is carefully optimized for best possible performance and utilization in Xilinx FPGA
devices.
Smart-IP Technology
Drawing on the architectural advantages of Xilinx FPGAs, Xilinx Smart-IP technology ensures the
highest performance, predictability, repeatability, and flexibility in PCI designs. The Smart-IP technol-
ogy is incorporated in every Initiator/Target core for PCI.
Xilinx Smart-IP technology leverages the Xilinx architectural advantages, such as look-up tables and
segmented routing, as well as floorplanning information, such as logic mapping and location con-
straints. This technology provides the best physical layout, predictability, and performance. In addi-
tion, these features allow for significantly reduced compile times over competing architectures.
To guarantee the critical setup, hold, minimum clock-to-out, and maximum clock-to-out timing, the
core is delivered with Smart-IP constraint files that are unique for a device and package combination.
These constraint files guide the implementation tools so that the critical paths always are within speci-
fication.
Xilinx provides Smart-IP constraint files for many device and package combinations. Constraint files
for unsupported device and package combinations may be generated using the web-based constraint
file generator.
LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI
6www.xilinx.com DS206 September 10, 2010
Product Specification v3.167 & v4.13
Functional Description
Figure 1 illustrates a user application and the PCI Interface partitioned into five major blocks.
I/O Interface Block
The I/O interface block handles the physical connection to the PCI bus including all signaling, input
and output synchronization, output three-state controls, and all request-grant handshaking for bus
mastering.
User Application
The Initiator/Target core for PCI provides a simple, general-purpose interface for a wide range of
applications.
X-Ref Target - Figure 1
Figure 1: Initiator/Target core for PCI Block Diagram
Parity
Generator/
Checker
PCI Configuration Space
Initiator
State
Machine
Interrupt
Pin and
Line
Register
Latency
Timer
Register
Vendor ID,
Rev ID,
Other User
Data
Target
State
Machine
PCI I/O INTERFACE
USER APPLICATION
ADIO[63:0]
AD[63:0]
PAR
GNT-
PERR-
SERR-
FRAME-
IRDY-
REQ-
TRDY-
DEVSEL-
STOP-
Base
Address
Register
0
Base
Address
Register
1
Command/
Status
Register
Base
Address
Register
2
ADIO[63:0]
DS206 September 10, 2010 www.xilinx.com 7
Product Specification v3.167 & v4.13
LogiCORE IP 32-Bit Initiato r/Target v3 & v4 for PCI
Configuration Space
This block provides the first 64 bytes of Type 0, version 3.0 Configuration Space Header, as shown in
Table 2, to support software-driven Plug-and-Play initialization and configuration. This includes infor-
mation for Command and Status, and three Base Address Registers (BARs).
The capability for extending configuration space has been built into the user application interface. This
capability, including the ability to implement a capabilities pointer in configuration space, allows you
to implement functions such as power management and message signaled interrupts in your applica-
tion.
Table 2: Configuration Space Header for PCI
31 16 15 0
Device ID Vendor ID 00h
Status Command 04h
Class Code Rev ID 08h
BIST Header
Type Latency
Timer Cache Line
Size 0Ch
Base Address Register 0 (BAR0) 10h
Base Address Register 1 (BAR1) 14h
Base Address Register 2 (BAR2) 18h
Base Address Register 3 (BAR3) 1Ch
Base Address Register 4 (BAR4) 20h
Base Address Register 5 (BAR5) 24h
Cardbus CIS Pointer 28h
Subsystem ID Subsystem Vendor ID 2Ch
Expansion ROM Base Address 30h
Reserved CapPtr 34h
Reserved 38h
Max Lat Min Gnt Int Pin Int Line 3Ch
Reserved 40h-FFh
Note: Shaded areas are not implemented and return zero.
LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI
8www.xilinx.com DS206 September 10, 2010
Product Specification v3.167 & v4.13
Parity Generator/Checker
This block generates and checks even parity across the AD bus, the CBE# lines, and the parity signals.
It also reports data parity errors via PERR# and address parity errors via SERR#.
Initiator State Machine
This block controls the Initiator/Target core for PCI initiator functions. The states implemented are a
subset of those defined in "Appendix B" of the PCI Local Bus Specification. The initiator control logic uses
one-hot encoding for maximum performance.
Target State Machine
This block controls core target functions. The states implemented are a subset of those defined in
"Appendix B" of the PCI Local Bus Specification. The target control logic uses one-hot encoding for max-
imum performance.
Core Configuration
The core can be easily configured to fit unique system requirements using the Xilinx CORE Generator
GUI or by changing the HDL configuration file. The following customization options, among many
others, are supported by the core.
•Device and vendor ID
•Base Address Registers (number, size, and type)
See the Initiator/Target core for PCI user guides for more information.
Burst Tr ansfer
The PCI bus derives its performance from its ability to support burst transfers. Performance of any PCI
application depends largely on the size of the burst transfer. Buffers to support PCI burst transfer can
efficiently be implemented using on-chip RAM resources.
DS206 September 10, 2010 www.xilinx.com 9
Product Specification v3.167 & v4.13
LogiCORE IP 32-Bit Initiato r/Target v3 & v4 for PCI
Supported Commands for PCI
Table 3 illustrates the PCI bus commands supported by the core.
Bandwidth
The Initiator/Target core for PCI supports fully compliant zero wait-state burst operations for both
sourcing and receiving data. The core supports a sustained bandwidth of up to 264 MBps, and can be
configured to support very long bursts.
The flexible user application interface, combined with support for many different features for PCI, pro-
vides a solution that lends itself to use in many high-performance applications. You are not locked into
one DMA engine; therefore, you can create an optimized design that fits a specific application.
Recommended Design Experience
The Initiator/Target core for PCI is pre-implemented, allowing engineering focus on the unique user
application functions of a design. Regardless, PCI is a high-performance design that is challenging to
implement in any technology. Therefore, previous experience with building high-performance, pipe-
lined FPGA designs using Xilinx implementation software and constraint files is recommended. The
challenge to implement a complete PCI design including user application functions varies depending
on configuration and functionality of your application. Contact your local Xilinx representative for a
closer review and estimation for your specific requirements.
Table 3: Bus Commands for PCI
CBE [3:0] Command PCI
Initiator PCI
Target
0000 Interrupt Acknowledge Yes Yes
0001 Special Cycle Yes Ignore
0010 I/O Read Yes Yes
0011 I/O Write Yes Yes
0100 Reserved Ignore Ignore
0101 Reserved Ignore Ignore
0110 Memory Read Yes Yes
0111 Memory Wr ite Yes Yes
1000 Reserved Ignore Ignore
1001 Reserved Ignore Ignore
1010 Configuration Read Yes Yes
1011 Configuration Write Yes Yes
1100 Memory Read Multiple Yes Yes
1101 Dual Address Cycle No Ignore
1110 Memory Read Line Yes Yes
1111 Memory Wr ite Invalidate No Yes
LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI
10 www.xilinx.com DS206 September 10, 2010
Product Specification v3.167 & v4.13
Timing Specifications
The maximum speed at which your user design is capable of running can be affected by the size and
quality of the design. Table 4 lists the Timing Parameters in the 66 MHz implementations and Table 5
lists Timing Parameters in the 33 MHz implementations.
Table 4: Timing Parameters, 66 MHz Implementations
Symbol Parameter Min Max
Tcyc CLK Cycle Time 15(1)
1. Controlled by timespec constraints, included in product .
30
Thigh CLK High Time 6 -
Tlow CLK Low Time 6 -
Tval CLK to Signal Valid Delay
(bussed signals) 2(2)
2. Controlled by SelectIO configured for PCI66_3.
62
Tval CLK to Signal Valid Delay
(point to point signals) 2262
Ton Float to Active Delay 22-
Toff Active to Float Delay - 141
Tsu Input Setup Time to CLK
(bussed signals) 32,(3)
3. Controlled by directed-routing constra ints, included in product.
-
Tsu Input Setup Time to CLK
(point to point signals) 52,3 -
ThInput Hold Time from CLK 02,3 -
Trstoff Reset Active to Output Float - 40
Table 5: Timing Parameters, 33 MHz Implementations
Symbol Parameter Min Max
Tcyc CLK Cycle Time 30(1)
1. Controlled by timespec constraints, included in product .
-
Thigh CLK High Time 11 -
Tlow CLK Low Time 11 -
Tval CLK to Signal Valid Delay
(bussed signals) 2(2)
2. Controlled by SelectIO configured for PCI33_3 or PCI33_5.
112
Tval CLK to Signal Valid Delay
(point to point signals) 22112
Ton Float to Active Delay 22-
Toff Active to Float Delay - 281
Tsu Input Setup Time to CLK
(bussed signals) 72-
Tsu Input Setup Time to CLK
(point to point signals) 102-
ThInput Hold Time from CLK 02-
Trstoff Reset Active to Output Float - 40
DS206 September 10, 2010 www.xilinx.com 11
Product Specification v3.167 & v4.13
LogiCORE IP 32-Bit Initiato r/Target v3 & v4 for PCI
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
The Initiator/Target core for PCI is accessed through the Xilinx CORE Generator software. The Xilinx
CORE Generator software is bundled with the ISE Foundation software at no additional charge. To
purchase the core, please contact your local Xilinx sales representative.
Visit the Initiator/Target for PCI/PCI-X product offering page for more information.
Revision History
The following table shows the revision history for this document:
Date Version Description of Revisions
07/30/02 1.2 Style updates
12/18/02 1.3 Updated to build v3.0.103; v5.Ii, 1st feature: 32-bit was 64/32-bit
3/7/03 1.4 Updated to build v3.0.105; v5.2i
4/14/03 1.5 Updated to build v3.0.106; updated PC32/33 produ ct listings to include
Spartan-3 device support.
5/8/03 1.6 Updated Xilinx tools to 5.2i SP2; added Note 10.
9/17/03 1.7 Updated to build v3.0.113; Xilinx Tools v6.1i SP1 was v5.2i SP2; date w as May
8, 2003.
10/28/03 1.8 Updated to build v3.0.116, in Supported Devices table, added XC prefix to
device names.
1/30/04 1.9 Updated to build v3.0.122, updated copyright inform ation to 2004.
4/9/04 1.10 Updated to build v3.0.126; updated Xilinx tools to 6.2i SP1; in supported
devices tab le, added notes 11 and 12; added suffix /I to all Virtex-II Pro devices .
4/26/04 1.11 Updated to build v3.0.128, updated Xilinx tools to 6.2i SP2, changed date to
April 26, 2004.
7/15/04 1.12 Updated to build v3.0.129 and to support Xilinx tools v6.2i SP3. The data sheet
is updated to the new template.
11/11/04 1.13 Updated support for Xilinx tools v6.3i SP2; updated PCI spec to v3.0; added
Exemplar LeonardoSpectrum and Cadence NC-Verilog entry and verification
tools.
12/8/04 1.14 Updated to build 3.0.140 and Virt ex-4 support.
3/7/05 1.15 Updated to Xilinx tools 7.1i and build v3.0.145.
5/13/2005 2.0 Updated build to 3.0.150, added support for Spartan-3E, addition of SP2.
8/31/05 3.0 Updated build to 3.0.151, updated SP 2 to SP3 for 7.1i
LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI
12 www.xilinx.com DS206 September 10, 2010
Product Specification v3.167 & v4.13
Notice of Disc laimer
Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any
kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation
thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for
any implementation based on the Information. All specifications are subject to change without notice. XILINX
EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
INFORMATION OR ANY IMPLEMENTATION BASED THEREON, INCLUDING BUT NOT LIMITED TO ANY
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distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including,
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of Xilinx.
9/12/05 4.0 Updated build to 3.0.152, updated to SP4 for 7.1i, updated release date,
removed reference in Table 1 footnote to Spartan-3 as pending, moved
placemen t of Table 3 to immediat el y follow text reference.
1/18/06 5.0 Upda ted build to 3.0.155, ISE software to v8.1i, and release date
2/14/06 5.5 Updated build number to 158, added SP 2 support to ISE 8.1i, release date.
7/13/06 6.0 Added v4 core, Vir tex-5 support, ISE to 8.21, build number to 160, release
date.
2/15/07 6.5 Updated ISE to 9.1i, up dated various tool versions, added trademark and
registered TM symbols, added support for Spartan-3A,Spa rtan-3E 66 MHz,
and Virte x-5 LXT.
5/17/07 7.0 Corrected usage of PCI terminology to comply with PCI-SIG trademark
guidelines. Updated Cadence IUS to v5.7.
8/08/07 7.5 Updated to build 163, minor editorial updates for IP1 Jade Minor release, added
Spartan-3A DSP device support.
10/10/07 8.0 Updated trademark usage, release date, added Spar tan-3AN device support.
3/24/08 8.5 Update d to support ISE v10.1.
4/25/08 9.0 V4 build 7 PCI core update only for adding Virtex-5 FXT support.
9/19/08 9.5 Update d to support ISE v10.1 Service Pack 3.
4/24/09 10.1 Updated to support ISE v11.1 and Spartan-6 FPGAs. Remov ed support for
deprecated devices: Virtex-II, Virtex-II Pro, and Virtex-E.
6/24/09 10.5 Updated to support ISE v11.2.
9/16/09 11.0 Updated to v4.10 and ISE v11.3. Added additional Spartan-6 FPGA part and
package support.
12/02/09 11.5 Updated to v4.11 and to ISE v11.4. Added additional Spartan-6 FPGA part and
package support.
4/19/10 12.0 Updated to v4.12 and to ISE v12.1. Added additional Spartan-6 FPGA part and
package support.
4/19/10 12.1 Removed support for LX100 and LX110T devices.
7/23/10 13.0 Updated to v4.12 and to ISE v12.1. Added support for Spartan-6 LX100 and
LX110T devices.
9/10/10 13.1 Updated IP Facts Table to reflect correct “Resources Used.”
Date Version Description of Revisions
