VIPer20/SP/DIP
VIPer20A/ASP/ADIP
SMPS PRIMARY I.C.
November 1999
BLOCK DIAGRAM
TYPE VDSS InRDS(on)
VIPer20/SP/DIP 620V 0.5 A 16 Ω
VIPer20A/ASP/ADIP 700V 0.5 A 18 Ω
FEATURE
■ADJUSTABLESWITCHING FREQUENCY UP
TO200KHZ
■CURRENT MODE CONTROL
■SOFTSTART AND SHUT DOWN CONTROL
■AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
”BLUE ANGEL” NORM (<1W TOTAL POWER
CONSUMPTION)
■INTERNALLY TRIMMED ZENER
REFERENCE
■UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
■INTEGRATED START-UP SUPPLY
■AVALANCHERUGGED
■OVERTEMPERATURE PROTECTION
■LOW STAND-BYCURRENT
■ADJUSTABLECURRENT LIMITATION
DESCRIPTION
VIPer20/20A, made using VIPower M0
Technology, combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized high voltage avalanche rugged Vertical
Power MOSFET (620Vor 700V/ 0.5A).
Typical applications cover off line power supplies
with a secondary power capability of 10W in wide
range condition and 20W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the possibility to operate in stand-by
mode withoutextra components.
PowerSO-10
1
10
PENTAWATT HV PENTAWATT HV (022Y)
VDD
OSC
COMP
DRAIN
SOURCE
13 V
UVLO
LOGIC
SECURITY
LATCH PWM
LATCH
FFFF
R/S SQS
R1R2 R3 Q
OSCILLATOR
OVERTEMP.
DETECTOR
ERROR
AMPLIFIER
_
+
0.5V +
_
1.7
µs
delay
250ns
Blanking
CURRENT
AMPLIFIER
ON/OFF
0.5V
6 V/A
_
+
+
_
4.5V
FC00491
DIP-8
1/21
ABSOLUTE MAXIMUMRATING
Symbol Parameter Value Unit
VDS Continuous Drain-Source Voltage (Tj = 25 to 125oC)
for VIPer20/SP/DIP
for VIPer20A/ASP/ADIP -0.3 to 620
-0.3 to 700 V
V
IDMaximum Current Internally Limited A
VDD Supply Voltage 0 to 15 V
VOSC Voltage Range Input 0 to VDD V
VCOMP Voltage Range Input 0 to 5 V
ICOMP Maximum Continuous Current ±2mA
V
esd Electrostatic discharge (R = 1.5 KΩC = 100pF) 4000 V
ID(AR) Avalanche Drain-Source Current, Repetitive or Not-Repetitive
(TC = 100 oC, Pulse Width Limited by TJmax, δ <1%)
for VIPer20/SP
for VIPer20A/ASP/ADIP 0.5
0.4 A
A
Ptot Power Dissipation at Tc = 25oC57W
T
j
Junction Operating Temperature Internally Limited oC
Tstg Storage Temperature -65 to 150 oC
THERMAL DATA
PENTAWATT PowerSO-10 DIP-8
Rthj-pin 20 oC/W
Rthj-case Thermal Resistance Junction-case Max 2.0 2.0 oC/W
Rthj-amb. Thermal Resistance Ambient-case Max 70 60 35 # oC/W
(*) When mounted using the minimum recommended pad size on FR-4 board.
# On multylayer PCB
CURRENT AND VOLTAGE CONVENTIONS
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VCOMP
VOSC
VDD VDS
ICOMP
IOSC
IDD ID
FC00020
CONNECTION DIAGRAMS (Top View)
PENTAWATT HV PENTAWATT HV (022Y) PowerSO-10 DIP-8
1
4
8
5
OSC
Vdd
SOURC E
COMP
DRAIN
DRAIN
DRAIN
DRAIN
SC10540
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
2/21
PINSFUNCTIONAL DESCRIPTION
DRAINPIN:
Integrated power MOSFET drain pin. It provides
internal bias current during start-up via an
integrated high voltage current source which is
switched off during normal operation. The device
is able to handle an unclamped current during its
normal operation, assuring self protection against
voltage surges, PCB stray inductance, and
allowing a snubberless operation for low output
power.
SOURCE PIN:
Power MOSFET source pin. Primary side circuit
common ground connection.
VDD PIN :
This pin providestwo functions :
-It corresponds to the low voltage supply of the
control part of the circuit. If VDD goes below 8V,
the start-up current source is activated and the
output power MOSFET is switched off until the
VDD voltage reaches 11V. During this phase,
the internal current consumption is reduced,
the VDD pin is sourcing a current of about 2mA
and the COMP pin is shorted to ground. After
that, the current source is shut down, and the
device tries to start up by switchingagain.
-This pin is also connected to the error
amplifier, in order to allow primary as well as
secondary regulation configurations. In case of
primary regulation, an internal 13V trimmed
reference voltage is used to maintain VDD at
13V. For secondary regulation, a voltage
between 8.5V and 12.5V will be put on VDD pin
by transformer design, in order to stuck the
output of the transconductanceamplifier to the
high state. The COMP pin behaves as a
constant current source, and can easily be
connected to the output of an optocoupler.
Note that any overvoltage due to regulation
loop failure is still detected by the error
amplifier through the VDD voltage, which
cannot overpass 13V. The output voltage will
be somewhat higher than the nominal one, but
still undercontrol.
COMP PIN :
This pin provides two functions :
-It is the output of the error transconductance
amplifier, and allows for the connection of a
compensation network to provide the desired
transfer function of the regulation loop. Its
bandwidth can be easily adjusted to the
needed value with usual componentsvalue. As
stated above, secondary regulation
configurations are also implemented through
the COMPpin.
-When the COMP voltage is going below 0.5V,
the shut-downof the circuit occurs, with a zero
duty cycle for the power MOSFET. This feature
can be used to switch off the converter, and is
automatically activated by the regulation loop
(whatever is the configuration) to provide a
burst mode operation in case of negligible
output power or open load condition.
OSC PIN :
An RT-CTnetwork must be connected on that pin
to define the switching frequency. Note that
despite the connection of RTto VDD,no
significant frequency change occurs for VDD
varying from 8V to 15V. It provides also a
synchronisationcapability, when connected to an
external frequencysource.
ORDERING NUMBERS
PENTAWATT HV PENTAWATT HV (022Y) PowerSO-10 DIP-8
VIPer20
VIPer20A VIPer20 (022Y)
VIPer20A (022Y) VIPer20SP
VIPer20ASP VIPer20DIP
VIPer20ADIP
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
3/21
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
ID(ar) Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tjmax, δ <1%)
for VIPer20/SP/DIP
for VIPer20A/ASPA/DIP (see fig.12) 0.5
0.4 A
A
E(ar) Single Pulse Avalanche Energy
(starting Tj=25o
C, ID=I
D(ar)) (see fig.12) 10 mJ
ELECTRICAL CHARACTERISTICS (TJ=25o
C, VDD =13 V,unless otherwisespecified)
POWERSECTION
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BVDSS Drain-Source Voltage ID=1mA V
COMP =0V
for VIPer20/SP/DIP
for VIPer20A/ASP/DIP (see fig.5) 620
700 V
V
IDSS Off-State Drain Current VCOMP =0V T
J
=125o
C
V
DS = 620 V
for VIPer20/SP/DIP
VDS = 700 V
for VIPer20A/ASP/ADIP
1.0
1.0
mA
mA
RDS(on) Static Drain Source on
Resistance ID=0.4A
for VIPer20/SP/DIP
for VIPer20A/ASP/ADIP
ID=0.4A T
J=100o
C
for VIPer20/SP/DIP
for VIPer20A/ASP/ADIP
13.5
15.5 16
18
29
32
Ω
Ω
Ω
Ω
tfFall Time ID = 0.2 A Vin =300V(1)
(see fig.3) 100 ns
trRise Time ID=0.4A V
in = 300 V (1)
(see fig. 3) 50 ns
COSS Output Capacitance VDS =25V 90 pF
(1) On Inductive Load, Clamped.
SUPPLY SECTION
Symbol Parameter Test Conditions Min. Typ. Max. Unit
IDDch Start-up Charging
Current VDD =5V V
DS =70V
(see fig. 2 and fig. 15) -2 mA
IDD0 Operating Supply Current VDD =12V, F
SW =0KHz
(see fig. 2) 12 16 mA
IDD1 Operating Supply Current VDD =12V, F
SW =100KHz 13 mA
I
DD2 Operating Supply Current VDD =12V, F
SW =200KHz 14 mA
V
DDoff Undervoltage Shutdown (see fig. 2) 7.5 8 V
VDDon Undervoltage Reset (see fig. 2) 11 12 V
VDDhyst Hysteresis Start-up (see fig. 2) 2.4 3 V
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
4/21
ELECTRICAL CHARACTERISTICS (continued)
OSCILLATORSECTION
Symbol Parameter Test Conditions Min. Typ. Max. Unit
FSW Oscillator Frequency
Total Variation RT= 8.2 K
Ω
CT=2.4 nF
VDD = 9 to15 V
with RT± 1% CT ± 5%
(see fig. 6 and fig. 9)
90 100 110 KHz
VOSCih Oscillator Peak Voltage 7.1 V
VOSCil Oscillator Valley Voltage 3.7 V
ERROR AMPLIFIERSECTION
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDDreg VDD Regulation Point ICOMP = 0 mA (see fig.1) 12.6 13 13.4 V
∆VDDreg Total Variation TJ= 0 to 100 oC2%
G
BW Unity Gain Bandwidth From Input = VDD to Output = VCOMP
COMP pin is open (see fig. 10) 150 KHz
AVOL Open Loop Voltage
Gain COMP pin is open (see fig. 10) 45 52 dB
GmDC Transconductance VCOMP = 2.5 V (see fig. 1) 1.1 1.5 1.9 mA/V
VCOMPLO Output Low Level ICOMP =-400µAV
DD =14V 0.2 V
VCOMPHI Output High Level ICOMP = 400 µAV
DD =12V 4.5 V
ICOMPLO Output Low Current
Capability VCOMP =2.5V V
DD = 14 V -600 µA
ICOMPHI Output High Current
Capability VCOMP =2.5V V
DD = 12 V 600 µA
PWM COMPARATORSECTION
Symbol Parameter Test Conditions Min. Typ. Max. Unit
HID ∆VCOMP/∆IDpeak VCOMP = 1 to 3 V 4.2 6 7.8 V/A
VCOMPoff VCOMP offset IDpeak =10mA 0.5 V
I
Dpeak Peak Current Limitation VDD = 12 V COMP pin open 0.5 0.67 0.9 A
tdCurrent Sense Delay
to turn-off ID= 1 A 250 ns
tbBlanking Time 250 360 ns
ton(min) Minimum on Time 350 ns
SHUTDOWN AND OVERTEMPERATURE SECTION
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VCOMPth Restart threshold (see fig. 4) 0.5 V
tDISsu Disable Set Up Time (see fig. 4) 1.7 5 µs
Ttsd Thermal Shutdown
Temperature (see fig. 8) 140 170 190 oC
Thyst Thermal Shutdown
Hysteresis (see fig. 8) 40 oC
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
5/21
Figure1:V
DD RegulationPoint
ICOMP
ICOMPHI
ICOMPLO VDDreg
0VDD
Slope =
Gm in mA/V
FC00150
Figure3: TransitionTime
ID
VDS
t
t
tf tr
10%Ipeak
10%VD
90%VD
FC00160
Figure 2: UndervoltageLockout
VDDon
IDDch
IDD0
VDD
VDDoff
VDS =70V
Fsw = 0
IDD
VDDhyst
FC00170
Figure 4: ShutDown Action
VCOMP
VOSC
ID
t
tDISsu
t
t
ENABLE
DISABLE
ENABLE
VCOMPth
FC00060
Figure5: BreakdownVoltage vs Temperature Figure 6: Typical FrequencyVariation
Temperature (
C)
FC00180
0 20406080100120
0.95
1
1.05
1.1
1.15
BVDS S
(Normalize d)
Tem p erature ( C)
0 20 40 60 80 100 120 140
-5
-4
-3
-2
-1
0
1FC0019 0
(%)
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
6/21
Figure8: OvertemperatureProtection
t
t
t
t
Tj
Vdd
Id
Vco mp
Ttsd
Tts d-Thys t
Vddon
Vddoff
SC1 0191
Figure7: Start-upWaveforms
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
7/21
Figure9: Oscillator
1 2 3 5 10 20 30 50
30
50
100
200
300
500
1,000
Rt (kΩ)
Frequency (kHz)
Oscillatorfrequency vs Rt and Ct
Ct = 1.5 nF
Ct = 2.7 nF
Ct = 4.7 nF
Ct = 10 nF
FC00030FC00030
1 2 3 5 10 20 30 50
0.5
0.6
0.7
0.8
0.9
1
Rt (kΩ)
Dmax
Maximum duty cycle vs Rt FC00040
Rt
Ct
OSC
VDD
~360Ω
CLK
FC00050
For RT> 1.2 KΩ:
FSW =2.3
RTCTDMAX
DMAX =1−550
RT−150
RecommendedDMAX values:
100KHz: > 80%
200KHz: > 70%
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
8/21
Figure10: ErrorAmplifier Frequency Response
0.001 0.01 0.1 1 10 100 1,000
(20)
0
20
40
60
Frequency (kHz)
VoltageGain (dB)
RCOMP = +∞
RCOMP = 270k
RCOMP = 82k
RCOMP = 27k
RCOMP = 12k
FC00200
Figure11: ErrorAmplifier Phase Response
0.001 0.01 0.1 1 10 100 1,000
(50)
0
50
100
150
200
Frequency (kHz)
Phase (°)
RCOMP = +∞
RCOMP = 270k
RCOMP = 82k
RCOMP = 27k
RCOMP = 12k
FC00210
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
9/21
Figure12: AvalanceTest Circuit
FC00196
U1
VIPer20
13V
OSC
COMP SOURCE
DRAINVDD
-
+
23
54
1
R3
100
R2
1k
BT2
12V
C1
47uF
16V
Q1
2 x STHV102FIin parallel
R1
47
L1
1mH
GENERATORINPUT
500us PULSE
BT1
0 to 20V
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
10/21
Figure13: OffLine Power Supply With Auxliary Supply Feedback
AC IN +Vcc
GND
F1
BR1
D3
R9
C1
R7
C4
C2
TR2
R1
C3
D1
D2
C10
TR1
C9C7
L2
R3
C6
C5
R2
VIPer20
-
+
13V
OSC
COMP SOURCE
DRAINVDD
FC00401
C11
Figure14: OffLine Power Supply With OptocouplerFeedback
AC IN
F1
BR1
D3
R9
C1
R7
C4
C2
TR2
R1
C3
D1
D2
C10
TR1
C9C7
L2 +Vcc
GND
C8
C5
R2
VIPer20
U2
R4
R5
ISO1 R6
R3
C6
-
+
13V
OSC
COMP SOURCE
DRAINVDD
FC00411
C11
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
11/21
OPERATIONDESCRIPTION :
CURRENT MODE TOPOLOGY:
The current mode control method, like the one
integrated in the VIPer20/20A uses two control
loops - an inner current control loop and an outer
loop for voltage control. When the Power
MOSFET output transistor is on, the inductor
current (primary side of the transformer) is
monitored with a SenseFET technique and
converted into a voltage VSproportional to this
current. When VSreaches VCOMP (the amplified
output voltage error) the power switch is switched
off. Thus, the outer voltage control loop defines
the level at which the inner loop regulates peak
current through the power switch and the primary
windingof the transformer.
Excellent open loop D.C. and dynamic line
regulation is ensured due to the inherent input
voltage feedforward characteristic of the current
mode control. This results in an improved line
regulation, instantaneous correction to line
changes and better stability for the voltage
regulationloop.
Current mode topology also ensures good
limitation in the case of short circuit. During a first
phase the output current increases slowly
following the dynamic of the regulationloop. Then
it reaches the maximum limitation current
internally set and finally stops because the power
supply on VDD is no longer correct. For specific
applications the maximum peak current internally
set can be overridden by externally limiting the
voltage excursion on the COMP pin. An
integrated blanking filter inhibits the PWM
comparator output for a short time after the
integrated Power MOSFET is switched on. This
function prevents anomalous or premature
termination of the switching pulse in the case of
current spikes caused by primary side
capacitance or secondary side rectifier reverse
recovery time.
STAND-BY MODE
Stand-by operation in nearly open load condition
automatically leads to a burst mode operation
allowing voltage regulation on the secondary
side. The transition from normal operation to
burst mode operation happens for a power PSTBY
given by :
PSTBY =1
2LPISTBY
2FSW
Where:
LPisthe primary inductance of the transformer.
FSW is the normal switching frequency.
ISTBY is the minimum controllable current,
corresponding to the minimum on time that the
device is able to provide in normal operation.This
current can be computed as :
ISTBY =(tb+td)VIN
LP
tb+t
dis the sum of the blanking time and of the
propagation time of the internal current sense
and comparator, and represents roughly the
minimum on time of the device. Note that PSTBY
may be affectedby the efficiencyof the converter
at low load,and must includethe powerdrawn on
the primary auxiliary voltage.
As soon as the power goes below this limit, the
auxiliary secondary voltage starts to increase
above the 13V regulation level forcing the output
voltage of the transconductance amplifier to low
state (VCOMP <V
COMPth). This situation leads to
the shutdown mode where the power switch is
maintained in the off state, resulting in missing
cycles and zero duty cycle. As soon as VDD gets
back to the regulation level and the VCOMPth
threshold is reached, the device operates again.
The above cycle repeats indefinitely, providing a
burst mode of which the effective duty cycle is
much lower than the minimum one when in
normal operation. The equivalent switching
frequency is also lower than the normal one,
leading to a reduced consumption on the input
mains lines. This mode of operation allows the
VIPer20/20A to meet the new German ”Blue
Angel” Norm with less than 1W total power
consumption for the system when working in
stand-by. The output voltage remains regulated
around the normal level, with a low frequency
ripple corresponding to the burst mode. The
amplitude of this ripple is low, because of the
output capacitors and of the low output current
drawn in such conditions.The normal operation
resumes automatically when the power get back
to higherlevels than PSTBY.
HIGH VOLTAGE START-UP CURRENT
SOURCE
An integrated high voltage current source
provides a bias current from the DRAIN pin
during the start-up phase. This current is partially
absorbed by internal control circuits which are
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
12/21
placed into a standby mode with reduced
consumption and also provided to the external
capacitor connected to the VDD pin. As soon as
the voltage on this pin reaches the high voltage
threshold VDDon of the UVLO logic, the device
turns into active mode and starts switching. The
start up current generatoris switched off, and the
converter should normally provide the needed
current on the VDD pin through the auxiliary
winding of the transformer, as shown on figure
15.
In case of abnormal condition where the auxiliary
winding is unable to provide the low voltage
supply current to the VDD pin (i.e. short circuit on
the output of the converter), the external
capacitor discharges itself down to the low
threshold voltage VDDoff of the UVLO logic, and
the device get back to the inactive state where
the internal circuits are in standby mode and the
start up current source is activated. The converter
enters a endless start up cycle, with a start-up
duty cycle defined by the ratio of charging current
towards discharging when the VIPer20/20A tries
to start. This ratio is fixed by design to 2 to 15,
which gives a 12% start up duty cycle while the
power dissipation at start up is approximately 0.6
W, for a 230 Vrms input voltage. This low value of
start-up duty cycle prevents the stress of the
output rectifiers and of the transformer when in
short circuit.
The external capacitor CVDD on the VDD pin must
be sized according to the time needed by the
converter to start up, when the device starts
switching. This time tSS depends on many
parameters, among which transformer design,
output capacitors, soft start feature and
compensation network implemented on the
COMP pin. The following formula can be used for
definingthe minimum capacitorneeded:
CVDD >IDD tSS
VDDhyst
where:
IDD is the consumption current on the VDD pin
when switching. Refer to specified IDD1 and IDD2
values.
tSS is the start up time of the converter when the
device begins to switch. Worst case is generally
at fullload.
VDDhyst is the voltage hysteresis of the UVLO
logic. Refer to the minimumspecified value.
Soft start feature can be implemented on the
COMP pin through a simple capacitor which will
be also used as the compensation network. In
this case, the regulation loop bandwidth is rather
low, because of the large value of this capacitor.
In case a large regulation loop bandwidth is
mandatory, the schematics of figure 16 can be
Figure15: Behaviourof the high voltagecurrent source at start-up
Ref.
UNDERVOLTAGE
LOCK OUT LOGIC
15 mA1mA
3mA
2mA
15 mA
VDD DRAIN
SOURCE
VIPer20
Auxiliary primary
winding
VDD
t
VDDoff
VDDon
Startupdutycycle~12%
CVDD
FC00101A
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
13/21
used. It mixes a high performance compensation
network together with a separate high value soft
start capacitor. Both soft start time and regulation
loop bandwidthcan be adjustedseparately.
If the device is intentionally shut down by putting
the COMP pin to ground, the device is also
performing start-up cycles, and the VDD voltage is
oscillating between VDDon and VDDoff. This voltage
can be used for supplying external functions,
provided that their consumption doesn’t exceed
0.5mA. Figure 17 shows a typical application of
this function, with a latched shut down. Once the
”Shutdown” signal has been activated, the device
remains in the off state until the input voltage is
removed.
TRANSCONDUCTANCE ERROR AMPLIFIER
The VIPer20/20A includes a transconductance
error amplifier. Transconductance Gm is the
change in output current (ICOMP) versus change
in input voltage(VDD). Thus:
Gm=∂ICOMP
∂VDD
The output impedance ZCOMP at the output of this
amplifier (COMPpin) can be defined as:
ZCOMP =∂VCOMP
∂ICOMP =1
Gmx∂VCOMP
∂VDD
This last equation shows that the open loop gain
AVOL canbe relatedto GmandZCOMP:
AVOL =G
mxZ
COMP
where Gmvalue for VIPer20/20A is 1.5 mA/V
typically.
Gmis well defined by specification, but ZCOMP
and therefore AVOL are subject to large
tolerances. An impedance Z can be connected
between the COMP pin and ground in order to
define more accurately the transfer function F of
the error amplifier, according to the following
equation,very similar to the one above:
F(S) =Gm x Z(S)
The error amplifier frequency response is
reported in figure 10 for different values of a
simple resistance connected on the COMP pin.
The unloaded transconductance error amplifier
shows an internal ZCOMP of about 330 KΩ. More
complex impedance can be connected on the
COMP pin to achieve different compensation
laws. A capacitor will provide an integrator
function, thus eliminating the DC static error, and
a resistance in seriesleads to a flat gain at higher
frequency, insuring a correct phase margin. This
configurationis illustrated on figure18.
As shown in figure 18 an additional noise filtering
capacitor of 2.2 nF is generally needed to avoid
any highfrequencyinterference.
It can be also interesting to implement a slope
compensation when working in continuous mode
with duty cycle higher than 50%. Figure 19 shows
such a configuration. Note that R1 and C2 build
the classical compensation network, and Q1 is
injecting the slope compensation with the correct
polarity from the oscillatorsawtooth.
EXTERNAL CLOCK SYNCHRONIZATION:
The OSC pin provides a synchronisation
capability, when connected to an external
Figure 17: LatchedShut Down
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPer20
Shutdown Q1
Q2
R1
R2R3
R4 D1
FC00440
Figure16: Mixed Soft Startand Compensation
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPer20
R1
C1 +C2
D1
R2
R3
D2
D3
+C3
AUXILIARY
WINDING
FC00431
C4
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
14/21
frequency source. Figure 20 shows one possible
schematic to be adapted depending the specific
needs. If the proposed schematic is used, the
pulse duration must be kept at a low value (500ns
is sufficient) for minimizing consumption. The
optocoupler must be able to provide 20mA
through the optotransistor.
PRIMARY PEAKCURRENT LIMITATION
The primary IDPEAK current and, as resulting
effect, the output power can be limited using the
simple circuit shown in figure 21. The circuit
based on Q1, R1and R2clamps the voltage on
the COMP pin in order to limit the primary peak
current of the device to a value:
IDPEAK =VCOMP−0.5
HID
where:
VCOMP =0.6 xR1+R2
R2
The suggestedvalue for R1+R2is in the range of
220KΩ.
OVER-TEMPERATURE PROTECTION:
Over-temperature protection is based on chip
temperature sensing. The minimum junction
temperature at which over-temperature cut-out
occurs is 140oC while the typical value is 170oC.
The device is automatically restarted when the
junction temperature decreases to the restart
temperature threshold that is typically 40oC below
Figure 19: SlopeCompensation
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPer20
R1R2
Q1
C2
C1 R3
FC00461
C3
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPer20
R1
C1
FC00451
C2
Figure18: TypicalCompensation Network
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPer20
10 kΩ
FC00470
Figure20:ExternalClock Synchronization Figure 21:Current Limitation Circuit Example
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPer20
R1
R2
Q1
FC00480
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
15/21
T1
U1
VIPerXX0
13V
OSC
COMP SOURCE
DRAINVDD
-
+
1
5
23
4
C4
C2
C5
C1
D2
R1
R2
D1
C7
C6
C3
ISO1
From input
diodes bridge
Tosecondary
filtering and load
FC00500
Figure22: Recommendedlayout
LAYOUT CONSIDERATIONS
Some simple rules insure a correct running of
switching power supplies. They may be classified
into two categories:
-To minimise power loops: the way the switched
power current must be carefully analysed and
the corresponding paths must present the
smallest inner loop area as possible. This
avoids radiated EMC noises, conducted EMC
noises by magnetic coupling, and provides a
better efficiency by eliminating parasitic
inductances,especially onsecondaryside.
-To use different tracks for low level signals and
power ones. The interferencesdue to a mixing
of signal and power may result in instabilities
and/or anomalous behaviour of the device in
case of violent power surge (Input
overvoltages,output short circuits...).
In case of VIPer, these rules apply as shown on
figure 22. The loops C1-T1-U1, C5-D2-T1,
C7-D1-T1 must be minimised. C6 must be as
close as possible from T1. The signal
components C2, ISO1, C3 and C4 are using a
dedicated track to be connected directly to the
sourceof the device.
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
16/21
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.30 4.80 0.169 0.189
C 1.17 1.37 0.046 0.054
D 2.40 2.80 0.094 0.110
E 0.35 0.55 0.014 0.022
F 0.60 0.80 0.024 0.031
G1 4.90 5.28 0.193 0.208
G2 7.42 7.82 0.292 0.308
H1 9.30 9.70 0.366 0.382
H2 10.40 0.409
H3 10.05 10.40 0.396 0.409
L 16.60 17.30 0.653 0.681
L1 14.60 15.22 0.575 0.599
L2 21.20 21.85 0.835 0.860
L3 22.20 22.82 0.874 0.898
L5 2.60 3.00 0.102 0.118
L6 15.10 15.80 0.594 0.622
L7 6.00 6.60 0.236 0.260
M 2.50 3.10 0.098 0.122
M1 7.56 8.16 0.298 0.321
R 0.50 0.020
V4 90o90
Diam. 3.70 3.90 0.146 0.154
A
C
H2
H3
H1
L5
Diam
L2
L3
L6
L7
F
G1
G2
L
L1
D
R
M
M1
E
Resin
between
leads
V4
P023H3
PENTAWATT HV (VERTICAL) MECHANICAL DATA
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
17/21
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.30 4.80 0.169 0.189
C 1.17 1.37 0.046 0.054
D 2.40 2.80 0.094 0.110
E 0.35 0.55 0.014 0.022
F 0.60 0.80 0.024 0.031
G1 4.90 5.28 0.193 0.208
G2 7.42 7.82 0.292 0.308
H1 9.30 9.70 0.366 0.382
H2 10.40 0.409
H3 10.05 10.40 0.396 0.409
L 16.42 17.42 0.646 0.686
L1 14.60 15.22 0.575 0.599
L3 20.52 21.52 0.808 0.847
L5 2.60 3.00 0.102 0.118
L6 15.10 15.80 0.594 0.622
L7 6.00 6.60 0.236 0.260
M 2.50 3.10 0.098 0.122
M1 5.00 5.70 0.197 0.224
R 0.50 0.020
V4 90o90o
Diam. 3.70 3.90 0.146 0.154
A
C
H2
H3
H1
L5
Diam
L3
L6
L7
F
G1
G2
L
L1
D
R
M
M1
E
Resin
between
leads
V4
P023H2
PENTAWATT HV 022Y(VERTICAL HIGH PITCH) MECHANICAL DATA
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
18/21
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 3.35 3.65 0.132 0.144
A1 0.00 0.10 0.000 0.004
B 0.40 0.60 0.016 0.024
C 0.35 0.55 0.013 0.022
D 9.40 9.60 0.370 0.378
D1 7.40 7.60 0.291 0.300
e 1.27 0.050
E 9.30 9.50 0.366 0.374
E1 7.20 7.40 0.283 0.291
E2 7.20 7.60 0.283 0.300
E3 6.10 6.35 0.240 0.250
E4 5.90 6.10 0.232 0.240
F 1.25 1.35 0.049 0.053
h 0.50 0.002
H 13.80 14.40 0.543 0.567
L 1.20 1.80 0.047 0.071
q 1.70 0.067
α0o8o
DETAIL ”A”
PLANE
SEATING
α
L
A1
F
A1
h
A
D
D1
==
==
==
E4
0.10 A
E1E3
C
Q
A
==
B
B
DETAIL ”A”
SEATING
PLANE
==
==
E2
610
51
eB
HE
M
0.25
==
==
0068039-C
PowerSO-10 MECHANICAL DATA
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
19/21
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 3.3 0.130
a1 0.7 0.028
B 1.39 1.65 0.055 0.065
B1 0.91 1.04 0.036 0.041
b 0.5 0.020
b1 0.38 0.5 0.015 0.020
D 9.8 0.386
E 8.8 0.346
e 2.54 0.100
e3 7.62 0.300
e4 7.62 0.300
F 7.1 0.280
I 4.8 0.189
L 3.3 0.130
Z 0.44 1.6 0.017 0.063
P001F
Plastic DIP8 MECHANICAL DATA
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
20/21
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VIPer20/SP/DIP - VIPer20A/ASP/ADIP
21/21
