1
2001 Integrated Device Technology, Inc. DSC-2655/1
MAY 2001
CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
IDT72421, IDT72201
IDT72211, IDT72221
IDT72231, IDT72241
IDT72251
The IDT logo is a registered trademark and the SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEATURES:
••
••
•64 x 9-bit organization (IDT72421)
••
••
•256 x 9-bit organization (IDT72201)
••
••
•512 x 9-bit organization (IDT72211)
••
••
•1,024 x 9-bit organization (IDT72221)
••
••
•2,048 x 9-bit organization (IDT72231)
••
••
•4,096 x 9-bit organization (IDT72241)
••
••
•8,192 x 9-bit organization (IDT72251)
••
••
•10 ns read/write cycle time
••
••
•Read and Write Clocks can be independent
••
••
•Dual-Ported zero fall-through time architecture
••
••
•Empty and Full Flags signal FIFO status
••
••
•Programmable Almost-Empty and Almost-Full flags can be set
to any depth
••
••
•Programmable Almost-Empty and Almost-Full flags default to
Empty+7, and Full-7, respectively
••
••
•Output enable puts output data bus in high-impedance state
••
••
•Advanced submicron CMOS technology
••
••
•Available in the 32-pin plastic leaded chip carrier (PLCC) and
32-pin Thin Quad Flat Pack (TQFP)
••
••
•For through-hole product please see the IDT72420/72200/72210/
72220/72230/72240 data sheet
••
••
•Industrial temperature range (–40 °°
°°
°C to +85°°
°°
°C) is available
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN1
WEN2
D
0
- D
8
LD
OFFSET REGISTER
INPUT REGISTER
RAM ARRAY
64 x 9, 256 x 9,
512 x 9, 1,024 x 9,
2,048 x 9, 4,096 x 9,
8,192 x 9
WRITE CONTROL
LOGIC
WRITE POINTER
OUTPUT REGISTER
READ CONTROL
LOGIC
READ POINTER
FLAG
LOGIC
EF
PAE
PAF
FF
RESET LOGIC
OE
REN2
REN1
RS
RCLK
2655 drw01
Q
0
- Q
8
DESCRIPTION:
The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO™
are very high-speed, low-power First-In, First-Out (FIFO) memories with
clocked read and write controls. These devices have a 64, 256, 512, 1,024,
2,048, 4,096, and 8,192 x 9-bit memory array, respectively. These FIFOs are
applicable for a wide variety of data buffering needs such as graphics, local area
networks and interprocessor communication.
These FIFOs have 9-bit input and output ports. The input port is controlled
by a free-running clock (WCLK), and two write enable pins (WEN1, WEN2).
Data is written into the Synchronous FIFO on every rising clock edge when the
write enable pins are asserted. The output port is controlled by another clock
pin (RCLK) and two read enable pins (REN1, REN2). The Read Clock can
be tied to the Write Clock for single clock operation or the two clocks can run
asynchronous of one another for dual-clock operation. An output enable pin
(OE) is provided on the read port for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF).
Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are
provided for improved system control. The programmable flags default to
Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag
offset loading is controlled by a simple state machine and is initiated by asserting
the load pin (LD).
These FIFOs are fabricated using IDT’s high-speed submicron CMOS
technology.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SYNCFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9
2
PIN CONFIGURATION
TQFP (PR32-1, order code: PF)
TOP VIEW PLCC (J32-1, order code: J)
TOP VIEW
PIN DESCRIPTIONS
Symbol Name I/O Description
D0-D8Data Inputs I Data inputs for a 9-bit bus.
RS Reset I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,FF and
PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
WCLK Write Clock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted.
WEN1 Write Enable 1 I If the FIFO is configured to have programmable flags, WEN1 is the only write enable pin. When WEN1 is
LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have
two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be
written into the FIFO if the FF is LOW.
WEN2/ Write Enable 2/ I The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/LD is
LD Load HIGH at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset, this pin operates as a
control to load and read the programmable flag offsets. If the FIFO is configured to have two write enables,
WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the
FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write
or read the programmable flag offsets.
Q0-Q8Data Outputs O Data outputs for a 9-bit bus.
RCLK Read Clock I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted.
REN1 Read Enable 1 I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is LOW.
REN2 Read Enable 2 I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is LOW.
OE Output Enable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
EF Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH,
the FIFO is not empty. EF is synchronized to RCLK.
PAE Programmable O When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
Almost-Empty Flag offset at reset is Empty+7. PAE is synchronized to RCLK.
PAF Programmable O When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset
Almost-Full Flag at reset is Full-7. PAF is synchronized to WCLK.
FF Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO
is not full. FF is synchronized to WCLK.
VCC Power One +5 volt power supply pin.
GND Ground One 0 volt ground pin.
RS
WEN1
WCLK
WEN2/LD
5
6
7
8
16
V
CC
D
0
PAF
PAE
GND
REN1
RCLK
REN2
27 26 25
24
23
22
21
29 28
32 31 30
9 101112131415
2655 drw 02
EF
OE
FF
1
2
3
4
20
19
18
17
INDEX
D
1
Q
0
Q
1
Q
2
Q
3
Q
4
Q
8
Q
7
Q
6
Q
5
D
2
D
3
D
4
D
5
D
6
D
7
D
8
RS
WEN1
WCLK
WEN2/LD
V
CC
5
6
7
8
9
10
11
12
13
PAF
PAE
GND
REN1
RCLK
REN2
OE
27
26
25
24
23
22
21
29
28
432132 31 30
14 15 16 17 18 19 20
D
2
FF
EF
INDEX
2655 drw02a
D
3
D
4
D
5
D
6
D
7
D
8
Q
0
Q
1
Q
2
Q
3
Q
4
Q
8
Q
7
Q
6
Q
5
D
1
D
0
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SYNCFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9
IDT72421
IDT72201
IDT72211
IDT72221
IDT72231
IDT72241 IDT72251
Com'l and Ind'l(1) Com'l and Ind'l(1)
tCLK = 10, 15, 25 ns tCLK = 10, 15, 25 ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max.
ILI(2) Input Leakage Current (Any Input) –1 — 1 –1 — 1
ILO(3) Output Leakage Current –10 — 10 –10 — 10
VOH
Output Logic “1” Voltage, IOH = –2mA
2.4 — — 2.4 — —
VOL Output Logic “0” Voltage, IOL = 8mA — — 0.4 — — 0.4
ICC1(4,5,6) Active Power Supply Current — — 35 — — 50
ICC2(4,7) Standby Current — — 5 — — 5
NOTES:
1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.
2. Measurements with 0.4 ≤≤
≤≤
≤ VIN ≤≤
≤≤
≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 1.7 + 0.7*fS + 0.02*CL*fS (in mA).
These equations are valid under the following conditions:
VCC = 5V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V ± 10%, T
A
= 0
°
C to +70
°
C; Industrial: V
CC
= 5V ± 10%, T
A
= –40
°
C to +85
°
C)
Symbol Rating Com'l & Ind'l Unit
VTERM Terminal Voltage with –0.5 to +7.0 V
Respect to GND
TSTG Storage Temperature –55 to +125 °C
IOUT DC Output Current –50 to +50 m A
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
Commercial/Industrial
GND Supply Voltage 0 0 0 V
VIH Input High Voltage 2.0 — — V
Commercial/Industrial
VIL Input Low Voltage — — 0.8 V
Commercial/Industrial
TAOperating Temperature 0 — 70 °C
Commercial
TAOperating Temperature –40 — 85 °C
Industrial
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING
CONDITIONS
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SYNCFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9
4
Figure 1. Output Load
*includes jig and scope capacitances
or equivalent circuit
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, T A = –40°C to +85°C)
Commercial Com'l & Ind'l(1) Com'l & Ind'l(1)
IDT72421L10 IDT72421L15 IDT72421L25
IDT72201L10 IDT72201L15 IDT72201L25
IDT72211L10 IDT72211L15 IDT72211L25
IDT72221L10 IDT72221L15 IDT72221L25
IDT72231L10 IDT72231L15 IDT72231L25
IDT72241L10 IDT72241L15 IDT72241L25
IDT72251L10 IDT72251L15 IDT72251L25
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
fSClock Cycle Frequency — 100 — 66.7 — 40 MHz
tAData Access Time 2 6.5 2 10 2 15 ns
tCLK Clock Cycle Time 10 — 15 — 25 — ns
tCLKH Clock High Time 4.5 — 6 — 10 — ns
tCLKL Clock Low Time 4.5 — 6 — 10 — ns
tDS Data Setup Time 3 — 4 — 6 — ns
tDH Data Hold Time 0.5 — 1 — 1 — ns
tENS Enable Setup Time 3 — 4 — 6 — ns
tENH Enable Hold Time 0.5 — 1 — 1 — ns
tRS Reset Pulse Width(2) 10 — 15 — 15 — ns
tRSS Reset Setup Time 8 — 10 — 15 — ns
tRSR Reset Recovery Time 8 — 10 — 15 — ns
tRSF Reset to Flag and Output Time — 10 — 15 — 25 ns
tOLZ Output Enable to Output in Low-Z(3) 0— 0— 0 —ns
tOE Output Enable to Output Valid 3 6 3 8 3 13 ns
tOHZ Output Enable to Output in High-Z(3) 36 38 313ns
tWFF Write Clock to Full Flag — 6.5 — 10 — 15 ns
tREF Read Clock to Empty Flag — 6.5 — 10 — 15 ns
tPAF Write Clock to Programmable Almost-Full Flag — 6.5 — 10 — 15 ns
tPAE Read Clock to Programmable Almost-Empty Flag — 6.5 — 10 — 15 ns
tSKEW1 Skew time between Read Clock & Write Clock for 5 — 6 — 10 — ns
Empty Flag & Full Flag
tSKEW2 Skew time between Read Clock & Write Clock for 14 — 15 — 18 — ns
Almost-Empty Flag & Programmable Almost-Full Flag
NOTES:
1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
In Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
CAPACITANCE (T a = +25°C, f = 1.0MHz)
Symbol Parameter Conditions Max. Unit
CIN(2) Input Capacitance VIN = 0V 10 pF
COUT(1,2) Output Capacitance VOUT = 0V 10 pF
30pF*
1.1K
5V
680Ω
D.U.T.
2655 drw 03
NOTES:
1 . With output deselected (OE ≥ VIH).
2. Characterized values, not currently tested.
AC TEST CONDITIONS
5
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SYNCFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9
OUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receive data from the output register. When Output Enable (OE) is disabled
(HIGH), the Q output data bus is in a high-impedance state.
WRITE ENABLE 2/LOAD (WEN2/LD)
This is a dual-purpose pin. The FIFO is configured at Reset to have
programmable flags or to have two write enables, which allows depth expansion.
If Write Enable 2/Load (WEN2/LD) is set HIGH at Reset (RS = LOW), this pin
operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write Enable
(WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is HIGH, data can be
loaded into the input register and RAM array on the LOW-to-HIGH transition
of every Write Clock (WCLK). Data is stored in the RAM array sequentially and
independently of any ongoing read operation.
In this configuration, when Write Enable (WEN1) is HIGH and/or Write
Enable 2/Load (WEN2/LD) is LOW, the input register holds the previous data
and no new data is allowed to be loaded into the register.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)
will go HIGH after tWFF, allowing a valid write to begin. Write Enable 1 (WEN1)
and Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.
The FIFO is configured to have programmable flags when the Write Enable
2/Load (WEN2/LD) is set LOW at Reset (RS=LOW). The IDT72421/72201/
72211/72221/72231/72241/72251 devices contain four 8-bit offset registers
which can be loaded with data on the inputs, or read on the outputs. See Figure
3 for details of the size of the registers and the default values.
If the FIFO is configured to have programmable flags when the Write Enable
1 (WEN1) and Write Enable 2/Load (WEN2/LD) are set LOW, data on the inputs
D is written into the Empty (Least Significant Bit) Offset register on the first LOW-
to-HIGH transition of the Write Clock (WCLK). Data is written into the Empty (Most
Significant Bit) Offset register on the second LOW-to-HIGH transition of the Write
Clock (WCLK), into the Full (Least Significant Bit) Offset register on the third
transition, and into the Full (Most Significant Bit) Offset register on the fourth
transition. The fifth transition of the Write Clock (WCLK) again writes to the Empty
(Least Significant Bit) Offset register.
However, writing all offset registers does not have to occur at one time. One
or two offset registers can be written and then by bringing the Write Enable 2/
Load (WEN2/LD) pin HIGH, the FIFO is returned to normal read/write
operation. When the Write Enable 2/Load (WEN2/LD) pin is set LOW, the Write
Enable 1 (WEN1) is LOW, the next offset register in sequence is written.
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 - D8)
Data inputs for 9-bit wide data.
CONTROLS:
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken to a LOW
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power-up before a write operation can take
place. The Full Flag (FF) and Programmable Almost-Full flag (PAF) will be reset
to HIGH after tRSF. The Empty Flag (EF) and Programmable Almost-Empty
flag (PAE) will be reset to LOW after tRSF. During reset, the output register is
initialized to all zeros and the offset registers are initialized to their default values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
(WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH
transition of WCLK. The Full Flag (FF) and Programmable Almost-Full flag
(PAF) are synchronized with respect to the LOW-to-HIGH transition of WCLK.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE 1 (WEN1)
If the FIFO is configured for programmable flags, Write Enable 1 (WEN1)
is the only enable control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM array on the LOW-
to-HIGH transition of every Write Clock (WCLK). Data is stored in the RAM array
sequentially and independently of any ongoing read operation.
In this configuration, when Write Enable 1 (WEN1) is HIGH, the input register
holds the previous data and no new data is allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which allows for depth
expansion, there are two enable control pins. See Write Enable 2 paragraph
below for operation in this configuration.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)
will go HIGH after tWFF, allowing a valid write to begin. Write Enable 1 (WEN1)
is ignored when the FIFO is full.
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
Clock (RCLK). The Empty Flag (EF) and Programmable Almost-Empty flag
(PAE) are synchronized with respect to the LOW-to-HIGH transition of RCLK.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLES (REN1, REN2)
When both Read Enables (REN1, REN2) are LOW, data is read from the
RAM array to the output register on the LOW-to-HIGH transition of the Read
Clock (RCLK).
When either Read Enable (REN1, REN2) is HIGH, the output register holds
the previous data and no new data is allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty Flag (EF) will
go LOW, inhibiting further read operations. Once a valid write operation has
been accomplished, the Empty Flag (EF) will go HIGH after tREF and a valid
read can begin. The Read Enables (REN1, REN2) are ignored when the FIFO
is empty.
LD WEN1 WCLK Selection
0 0 Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0 1 No Operation
1 0 Write Into FIFO
1 1 No Operation
NOTE:
1. For the purposes of this table, WEN2 = VIH.
2. The same selection sequence applies to reading from the registers. REN1 and REN2
are enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Figure 2. Write Offset Register
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SYNCFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9
6
Figure 3. Offset Register Location and Default Values
86 0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
87 0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
IDT72421 - 64 x 9-BIT IDT72201 - 256 x 9-BIT
IDT72211 - 512 x 9-BIT
7
7
80
(MSB)
1
80
0
0
80
87 0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
87 0
Empty Offset (LSB) Reg.
Default Value 007H
80
Empty Offset (LSB)
Default Value 007H
IDT72221 - 1,024 x 9-BIT
IDT72231 - 2,048 x 9-BIT IDT72241 - 4,096 x 9-BIT
7
8080
(MSB)
0000
2(MSB)
000
3
80
(MSB)
00
1
80
(MSB)
00
1
5
65
80
8
0
8(MSB)
1
0
IDT72251 8,192 x 9-BIT
80
Empty Offset (LSB)
Default Value 007H
7
80
(MSB)
00000
4
87 0
Full Offset (LSB) Reg.
Default Value 007H
802(MSB)
000
80
Full Offset (LSB)
Default Value 007H
7
80
(MSB)
0000
3
80
Full Offset (LSB)
Default Value 007H
7
80
(MSB)
00000
4
2655 drw 05
The contents of the offset registers can be read on the output lines when the
Write Enable 2/Load (WEN2/LD) pin is set LOW and both Read Enables (REN1,
REN2) are set LOW. Data can be read on the LOW-to-HIGH transition of the
Read Clock (RCLK).
A read and write should not be performed simultaneously to the offset
registers.
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SYNCFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9
OUTPUTS:
FULL FLAG (FF)
The Full Flag (FF) will go LOW, inhibiting further write operation, when the
device is full. If no reads are performed after Reset (RS), the Full Flag (FF)
will go LOW after 64 writes for the IDT72421, 256 writes for the IDT72201, 512
writes for the IDT72211, 1,024 writes for the IDT72221, 2,048 writes for the
IDT72231, 4,096 writes for the IDT72241, and 8,192 writes for the IDT72251.
The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH
transition of the Write Clock (WCLK).
EMPTY FLAG (EF)
The Empty Flag (EF) will go LOW, inhibiting further read operations, when
the read pointer is equal to the write pointer, indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH
transition of the Read Clock (RCLK).
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. If no reads are performed after Reset (RS),
the Programmable Almost-Full flag (PAF) will go LOW after (64-m) writes for the
IDT72421, (256-m) writes for the IDT72201, (512-m) writes for the IDT72211,
TABLE 1 STATUS FLAGS
NUMBER OF WORDS IN FIFO
IDT72421 IDT72201 IDT72211 FF PAF PAE EF
000HHLL
1 to n 1 to n 1 to n H H L H
(n+1) to (64-(m+1)) (n+1) to (256-(m+1)) (n+1) to (512-(m+1)) H H H H
(64-m)(2) to 63 (256-m)(2) to 255 (512-m)(2) to 511 H L H H
64 256 512 L L H H
NUMBER OF WORDS IN FIFO
IDT72221 IDT72231 IDT72241 IDT72251 FF PAF PAE EF
00 0 0HHLL
1 to n(1) 1 to n(1) 1 to n(1) 1 to n(1) HHLH
(n+1) to (1,024-(m+1)) (n+1) to (2,048-(m+1)) (n+1) to (4,096-(m+1)) (n+1) to (8,192-(m+1)) H H H H
(1,024-m)(2) to 1,023 (2,048-m)(2) to 2,047 (4,096-m)(2) to 4,095 (8,192-m)(2) to 8,191 H L H H
1,024 2,048 4,096 8,192 L L H H
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
2655 tbl 09
(1,024-m) writes for the IDT72221, (2,048-m) writes for the IDT72231, (4,096-
m) writes for the IDT72241, and (8,192-m) writes for the IDT72251. The offset
“m” is defined in the Full offset registers.
If there is no Full offset specified, the Programmable Almost-Full flag (PAF)
will go LOW at Full-7 words.
The Programmable Almost-Full flag (PAF) is synchronized with respect to
the LOW-to-HIGH transition of the Write Clock (WCLK).
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The Programmable Almost-Empty flag (PAE) will go LOW when the read
pointer is "n+1" locations less than the write pointer. The offset "n" is defined
in the Empty Offset registers. If no reads are performed after Reset the
Programmable Almost-Empty flag (PAE) will go HIGH after "n+1" for the
IDT72421/72201/72211/72221/72231/72241/72251.
If there is no Empty offset specified, the Programmable Almost-Empty flag
(PAE) will go LOW at Empty+7 words.
The Programmable Almost-Empty flag (PAE) is synchronized with respect
to the LOW-to-HIGH transition of the Read Clock (RCLK).
DATA OUTPUTS (Q0 - Q8)
Data outputs for a 9-bit wide data.
(1) (1) (1)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SYNCFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9
8
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK
and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 5. Write Cycle Timing
NOTES:
1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/ LD LOW during reset will make the pin act as a load enable for the programmable
flag offset registers.
2. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
3. The clocks (RCLK, WCLK) can be free-running during reset. Figure 4. Reset Timing
tRS
tRSR
RS
REN1, REN2
tRSF
tRSF
OE = 1
OE = 0
(2)
EF, PAE
FF, PAF
Q0 - Q8
2655 drw 06
WEN1
(1)
WEN2/LD
tRSS
tRSF
tRSRtRSS
tRSRtRSS
t
DH
t
ENH
t
SKEW1(1)
t
CLK
t
CLKH
t
CLKL
t
DS
t
ENS
t
WFF
t
WFF
WCLK
D
0
- D
8
WEN1
WEN2/
(If Applicable)
FF
RCLK
REN1,
REN2
NO OPERATION
NO OPERATION
2655 drw 07
DATA IN VALID
t
ENH
t
ENS
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SYNCFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9
tDS
D0 (First Valid Write)
tSKEW1
D0D1
D3D2D1
tFRL(1)
tREF
tA
tOLZ tOE
tA
WCLK
D0 - D8
WEN2
(If Applicable)
RCLK
EF
REN1,
REN2
Q0 - Q8
OE
WEN1
2655 drw 09
tENS
tENS
tENS
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of RCLK
and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 6. Read Cycle Timing
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Figure 7. First Data Word Latency Timing
t
ENH
t
ENS
NO OPERATION
t
OLZ
VALID DATA
t
SKEW1(1)
t
CLK
t
CLKH
t
CLKL
t
REF
t
REF
t
A
t
OE
t
OHZ
RCLK
REN1,
REN2
EF
Q
0
- Q
8
OE
WCLK
WEN1
WEN2
2655 drw 08
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SYNCFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9
10
Figure 8. Full Flag Timing
Figure 9. Empty Flag Timing
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK+ tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
NOTE:
1. Only one of the two write enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
t
SKEW1
t
DS
t
SKEW1
t
ENH
t
ENH
NEXT DATA READDATA READ
WCLK
D
0
- D
8
FF
WEN1
WEN2
(If Applicable)
RCLK
REN1,
REN2
Q
0
- Q
8
t
WFF
t
WFF
t
WFF
t
ENS
t
ENS
DATA IN OUTPUT REGISTER
OE LOW
NO WRITE NO WRITE
2655 drw 10
t
A
t
A
t
ENS
t
ENS
t
ENS(1)
t
ENS(1)
t
ENH
t
ENH
NO WRITE
t
A
t
DS
t
DS
DATA WRITE 1
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
DATA WRITE 2
WCLK
D
0
- D
8
RCLK
EF
REN1,
REN2
OE
Q
0
- Q
8
DATA READ
t
SKEW1
(1)
t
FRL
t
FFL
DATA IN OUTPUT REGISTER
(1)
t
SKEW1
LOW
WEN2
(If Applicable)
t
REF
t
REF
t
REF
WEN1
2655 drw 11
11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SYNCFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9
Figure 11. Programmable Empty Flag Timing
NOTES:
1. n = PAE offset.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time between the rising edge of WCLK and
the rising edge of RCLK is less than tSKEW2, then PAE may not change state until the next RCLK rising edge.
3. If a read is performed on this rising edge of the Read Clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW.
NOTES:
1 . m = PAF offset .
2. 64-m words in FIFO for IDT72421, 256-m words for IDT72201, 512-m words for IDT72211, 1,024-m words for IDT72221, 2,048-m words for IDT72231, 4,096-m words for IDT72241,
and 8,192-m words for IDT72251.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and
the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK rising edge.
4. If a write is performed on this rising edge of the Write Clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW.
Figure 10. Programmable Full Flag Timing
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
WCLK
WEN1
WEN2
(If Applicable)
PAF
RCLK
REN1,
REN2
(4)
(1)
t
PAF
Full - (m+1) words in FIFO Full - m words in FIFO
(2)
t
CLKH
t
CLKL
t
SKEW2(3)
t
PAF
2655 drw 12
WCLK
WEN1
WEN2
PAE
RCLK
REN1,
REN2
t
ENS
t
ENH
t
ENS
t
ENH
t
SKEW2(2)
t
ENS
t
ENH
(If Applicable)
t
PAE
t
PAE
(3)
(1)
n words in FIFO n+1 words in FIFO
t
CLKH
t
CLKL
2655 drw 13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SYNCFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9
12
Figure 13. Read Offset Registers Timing
Figure 12. Write Offset Registers Timing
t
ENS
t
ENH
t
ENS
t
DS
t
DH
WCLK
LD
WEN1
D
0
- D
7
PAF OFFSET
(MSB)
PAF OFFSET
(LSB)
PAE OFFSET
(MSB)
PAE OFFSET
(LSB)
t
CLK
t
CLKL
t
CLKH
2655 drw 14
t
ENS
t
ENH
t
ENS
DATA IN OUTPUT REGISTER EMPTY OFFSET
(LSB) EMPTY OFFSET
(MSB) FULL OFFSET
(LSB)
FULL OFFSET
(MSB)
RCLK
LD
REN1,
REN2
Q
0
- Q
7
t
CLK
t
A
t
CLKL
t
CLKH
2655 drw15
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SYNCFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9
configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset so
that the pin operates as a control to load and read the programmable flag offsets.
DEPTH EXPANSION - The IDT72421/72201/72211/72221/72231/72241/
72251 can be adapted to applications when the requirements are for greater
than 64/256/512/1,024/2,048/4,096/8,192 words. The existence of two
enable pins on the read and write port allow depth expansion. The Write
Enable 2/Load pin is used as a second write enable in a depth expansion
configuration thus the Programmable flags are set to the default values. Depth
expansion is possible by using one enable input for system control while the
other enable input is controlled by expansion logic to direct the flow of data. A
typical application would have the expansion logic alternate data access from
one device to the next in a sequential manner. These devices operate in the
Depth Expansion configuration when the following conditions are met:
1. The WEN2/ LD pin is held HIGH during Reset so that this pin operates a
second Write Enable.
2. External logic is used to control the flow of data.
Please see the Application Note "DEPTH EXPANSION OF IDT'S SYN-
CHRONOUS FIFOs USING THE RING COUNTER APPROACH" for details
of this configuration.
Figure 15. Block Diagram of 64 x 18, 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18
Synchronous FIFO Used in a Width Expansion Configuration
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
A single IDT72421/72201/72211/72221/72231/72241/72251 may be used
when the application requirements are for 64/256/512/1,024/2,048/4,096/
8,192 words or less. When these FIFOs are in a Single Device Configuration,
the Read Enable 2 (REN2) control input can be grounded (see Figure 14). In
this configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset
so that the pin operates as a control to load and read the programmable flag
offsets.
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting the corresponding input
controls signals of multiple devices. A composite flag should be created for each
of the endpoint status flags (EF and FF). The partial status flags (AE and AF)
can be detected from any one device. Figure 15 demonstrates a 18-bit word
width by using two IDT72421/72201/72211/72221/72231/72241/72251s.
Any word width can be attained by adding additional IDT72421/72201/72211/
72221/72231/72241/72251s.
When these FIFOs are in a Width Expansion Configuration, the Read
Enable 2 (REN2) control input can be grounded (see Figure 15). In this
Figure 14. Block Diagram of Single 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 Synchronous FIFO
DATA OUT (Q
0
- Q
8
)DATA IN (D
0
- D
8
)
RESET (RS)
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
EMPTY FLAG (EF)
PROGRAMMABLE ALMOST-EMPTY (PAE)
READ ENABLE 2 (REN2)
WRITE CLOCK (WCLK)
WRITE ENABLE 1 (WEN1)
WRITE ENABLE 2/LOAD (WEN2/LD)
FULL FLAG (FF)
PROGRAMMABLE ALMOST-FULL (PAF)
IDT
72421
72201
72211
72221
72231
72241
72251
2655 drw 16
DATA IN (D)
WRITE CLOCK (WCLK)
18 9 9
RESET (RS)
READ CLOCK (RCLK)
DATA OUT (Q)
918
READ ENABLE 2 (REN2)READ ENABLE 2 (REN2)
WRITE ENABLE1 (WEN1)
FULL FLAG (FF) #1
PROGRAMMABLE (PAF)
PROGRAMMABLE (PAE)
EMPTY FLAG (EF) #2
OUTPUT ENABLE (OE)
READ ENABLE (REN)
9
WRITE ENABLE2/LOAD (WEN2/LD)
IDT
72421
72201
72211
72221
72231
72241
72251
FULL FLAG (FF) #2 EMPTY FLAG (EF) #1
RESET (RS)
IDT
72421
72201
72211
72221
72231
72241
72251
2655 drw 17
14
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 408-330-1753
Santa Clara, CA 95054 fax: 408-492-8674 FIFOhelp@idt.com
www.idt.com* J Pkg: www.idt.com/docs/PSC4013.pdf
PF Pkg: www.idt.com/docs/PSC4052.pdf
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The SyncFIFO and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
ORDERING INFORMATION
NOTES:
1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.
2655 drw18
Commercial (0°C to +70°C)
Industrial (›40° to +85°C)
XXXXXIDT Device Type XXX X X
Power Speed Package Process/
Temperature
Range
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
Plastic Leaded Chip Carrier (PLCC, J32-1)
Thin Quad Flat Pack (TQFP, PR32-1)
Commercial Only
Commercial & Industrial
Commercial & Industrial
64 x 9 SyncFIFO
256 x 9 SyncFIFO
512 x 9 SyncFIFO
1,024 x 9 SyncFIFO
2,048 x 9 SyncFIFO
4,096 x 9 SyncFIFO
8,192 x 9 SyncFIFO
BLANK
I
(1)
J
PF
10
15
25
L
72421
72201
72211
72221
72231
72241
72251
Low Power
DATASHEET DOCUMENT HISTORY
10/03/2000 pgs. 2, 3, 4 and 14.
05/01/2001 pgs. 1, 2, 3, 4 and 14.
