TL/F/9825
DM54LS273/DM74LS273 8-Bit Register with Clear
April 1992
DM54LS273/DM74LS273
8-Bit Register with Clear
General Description
The ’LS273 is a high speed 8-bit register, consisting of eight
D-type flip-flops with a common Clock and an asynchronous
active LOW Master Reset. This device is supplied in a 20-
pin package featuring 0.3 inch row spacing.
Features
YEdge-triggered
Y8-bit high speed register
YParallel in and out
YCommon clock and master reset
Connection Diagram
Dual-In-Line Package
TL/F/9825–1
Order Number DM54LS273E, DM54LS273J,
DM54LS273W, DM74LS273M or DM74LS273N
See NS Package Number E20A, J20A, M20B,
N20A or W20A
Pin Names Description
CP Clock Pulse Input (Active Rising Edge)
D0– D7 Data Inputs
MR Asynchronous Master Reset Input
(Active LOW)
Q0– Q7 Flip-Flop Outputs
C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range
DM54LS b55§Ctoa
125§C
DM74LS 0§Ctoa
70§C
Storage Temperature Range b65§Ctoa
150§C
Note:
The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol Parameter DM54LS273 DM74LS273 Units
Min Nom Max Min Nom Max
VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
VIL Low Level Input Voltage 0.7 0.8 V
IOH High Level Output Current b0.4 b0.4 mA
IOL Low Level Output Current 4 8 mA
TAFree Air Operating Temperature b55 125 0 70 §C
ts(H) Setup Time HIGH or LOW 15 15 ns
ts(L) Dnto CP 15 15
th(H) Hold Time HIGH or LOW 5 5 ns
th(L) Dnto CP 5 5
tw(H) CP Pulse Width HIGH or LOW 20 20 ns
tw(L) 20 20
tw(L) MR Pulse Width LOW 20 20 ns
trec Recovery Time 15 15 ns
MR to CP
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
(Note 1)
VIInput Clamp Voltage VCC eMin, IIeb
18 mA b1.5 V
VOH High Level Output VCC eMin, IOH eMax, DM54 2.5 V
Voltage VIL eMax DM74 2.7 3.4
VOL Low Level Output VCC eMin, IOL eMax, DM54 0.4
Voltage VIH eMin DM74 0.35 0.5 V
IOL e4 mA, VCC eMin DM74 0.25 0.4
IIInput Current @Max VCC eMax, VIe7V 0.1 mA
Input Voltage VIe10V (DM54)
IIH High Level Input Current VCC eMax, VIe2.7V 20 mA
IIL Low Level Input Current VCC eMax, VIe0.4V b0.4 mA
IOS Short Circuit VCC eMax DM54 b20 b100 mA
Output Current (Note 2) DM74 b20 b100
ICC Supply Current VCC eMax 27 mA
Note 1: All typicals are at VCC e5V, TAe25§C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2
Switching Characteristics VCC ea
5.0V, TAea25§C
CLe15 pF
Symbol Parameter DM54LS DM74LS Units
RLe2kX
Min Max Min Max
fmax Maximum Clock Frequency 30 30 MHz
tPLH Propagation Delay 24 24 ns
tPHL CP to Qn24 24
tPLH Propagation Delay 27 27 ns
MR to Qn
Functional Description
The ’LS273 is an 8-bit parallel register with a common Clock
and common Master Reset. When the MR input is LOW, the
Q outputs are LOW, independent of the other inputs. Infor-
mation meeting the setup and hold time requirements of the
D inputs is transferred to the Q outputs on the LOW-to-
HIGH transition of the clock input.
Truth Table
Inputs Outputs
MR CP DnQn
LXX L
HLHH
HLLL
H
e
HIGH Voltage Level
LeLOW Voltage Level
XeImmaterial
Logic Symbol
TL/F/9825–2
VCC ePin 20
GND ePin 10
Logic Diagram
TL/F/9825–3
3
Physical Dimensions inches (millimeters)
Ceramic Leadless Chip Carrier Package (E)
Order Number DM54LS273E
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54LS273J
NS Package Number J20A
4
Physical Dimensions inches (millimeters) (Continued)
20-Lead Wide Small Outline Molded Package (M)
Order Number DM74LS273M
NS Package Number M20B
20-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS273N
NS Package Number N20A
5
DM54LS273/DM74LS273 8-Bit Register with Clear
Physical Dimensions inches (millimeters) (Continued)
20-Lead Ceramic Flat Package (W)
Order Number DM54LS273W
NS Package Number W20A
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systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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