74HC132; 74HCT132 Quad 2-input NAND Schmitt trigger Rev. 3 -- 30 August 2012 Product data sheet 1. General description The 74HC132; 74HCT132 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt trigger inputs. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT is defined as the input hysteresis voltage VH. 2. Features and benefits ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Applications Wave and pulse shapers Astable multivibrators Monostable multivibrators 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 4. Ordering information Table 1. Ordering information Type number 74HC132N Package Temperature range Name Description Version 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74HCT132N 74HC132D 74HCT132D 74HC132DB 74HCT132DB 74HC132PW 74HCT132PW 5. Functional diagram 1 1A 1Y 2 4 2A 2Y 5 3 1B 1 6 2B 4 9 3A 3Y 10 & 3 & 6 & 8 & 11 2 5 8 3B 9 10 12 4A 4Y 13 12 11 Logic symbol 74HC_HCT132 Product data sheet Y 13 4B B mna407 Fig 1. A mna408 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 mna409 Fig 3. Logic diagram (one Schmitt trigger) (c) NXP B.V. 2012. All rights reserved. 2 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 6. Pinning information 6.1 Pinning 1A 1 14 VCC 1B 2 13 4B 1Y 3 2A 4 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y 12 4A 132 11 4Y mna406 Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 6.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 7. Functional description Table 3. Function table[1] Input Output nA nB nY L L H L H H H L H H H L [1] H = HIGH voltage level; L = LOW voltage level; X = don't care. 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 (c) NXP B.V. 2012. All rights reserved. 3 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V - 20 mA - 20 mA - 25 mA 50 mA IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current 0.5 V < VO < VCC + 0.5 V ICC supply current - IGND ground current 50 - mA Tstg storage temperature 65 +150 C DIP14 package - 750 mW SO14, and (T)SSOP14 packages - 500 mW total power dissipation Ptot [1] [2] [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C. For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC132 74HCT132 Unit Min Typ Max Min Typ Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 (c) NXP B.V. 2012. All rights reserved. 4 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min Typ IO = 20 A; VCC = 2.0 V 1.9 IO = 20 A; VCC = 4.5 V 4.4 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max 2.0 - 1.9 - 1.9 - V 4.5 - 4.4 - 4.4 - V 74HC132 VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VT IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V VI = VT+ or VT - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 2.0 - 20 - 40 A CI input capacitance - 3.5 - - - - - pF 74HCT132 VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VT; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V VI = VT+ or VT; VCC = 4.5 V IO = 20 A; - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; - 0.15 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 A ICC additional supply current per input pin; VI = VCC 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - 30 108 - 135 - 147 A CI input capacitance 74HC_HCT132 Product data sheet - 3.5 - - All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 - - - pF (c) NXP B.V. 2012. All rights reserved. 5 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 11. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 6. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 36 125 155 190 VCC = 4.5 V - 13 25 31 38 ns VCC = 5.0 V; CL = 15 pF - 11 - - - ns - 10 21 26 32 ns VCC = 2.0 V - 19 75 95 110 ns VCC = 4.5 V - 7 15 19 22 ns - 6 13 16 19 ns - 24 - - - pF - 20 33 41 50 ns 74HC132 propagation delay nA, nB to nY; see Figure 5 tpd [1] VCC = 2.0 V VCC = 6.0 V transition time tt [2] see Figure 5 VCC = 6.0 V power dissipation capacitance CPD ns per package; VI = GND to VCC [3] 74HCT132 propagation delay nA, nB to nY; see Figure 5 tpd [1] VCC = 4.5 V VCC = 5.0 V; CL = 15 pF transition time tt power dissipation capacitance CPD - 17 - - - ns VCC = 4.5 V; see Figure 5 [2] - 7 15 19 22 ns per package; VI = GND to VCC 1.5 V [3] - 20 - - - pF [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 (c) NXP B.V. 2012. All rights reserved. 6 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 12. Waveforms VI nA, nB input VM GND tPHL VOH tPLH VY VM VX nY output VOL tTHL tTLH 001aai814 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Input to output propagation delays Table 8. Measurement points Type Input Output VM VM VX VY 74HC132 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT132 1.3 V 1.3 V 0.1VCC 0.9VCC VI negative pulse tW 90 % VM GND tf tr tr tf VI 90 % positive pulse GND VM 10 % VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 6. Load circuitry for measuring switching times 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 (c) NXP B.V. 2012. All rights reserved. 7 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger Table 9. Test data Type Input Load Test VI tr, tf CL 74HC132 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL 74HCT132 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL 13. Transfer characteristics Table 10. Transfer characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); see Figure 7 and Figure 8. Symbol Parameter Tamb = 25 C Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 0.7 1.18 1.5 0.7 1.5 0.7 1.5 V VCC = 4.5 V 1.7 2.38 3.15 1.7 3.15 1.7 3.15 V 74HC132 VT+ VT VH positive-going threshold voltage VCC = 6.0 V 2.1 3.14 4.2 2.1 4.2 2.1 4.2 V negative-going VCC = 2.0 V threshold VCC = 4.5 V voltage VCC = 6.0 V 0.3 0.63 1.0 0.3 1.0 0.3 1.0 V 0.9 1.67 2.2 0.9 2.2 0.9 2.2 V 1.2 2.26 3.0 1.2 3.0 1.2 3.0 V hysteresis voltage VCC = 2.0 V 0.2 0.55 1.0 0.2 1.0 0.2 1.0 V VCC = 4.5 V 0.4 0.71 1.4 0.4 1.4 0.4 1.4 V VCC = 6.0 V 0.6 0.88 1.6 0.6 1.6 0.6 1.6 V VCC = 4.5 V 1.2 1.41 1.9 1.2 1.9 1.2 1.9 V VCC = 5.5 V 1.4 1.59 2.1 1.4 2.1 1.4 2.1 V negative-going VCC = 4.5 V threshold VCC = 5.5 V voltage 0.5 0.85 1.2 0.5 1.2 0.5 1.2 V 0.6 0.99 1.4 0.6 1.4 0.6 1.4 V hysteresis voltage VCC = 4.5 V 0.4 0.56 - 0.4 - 0.4 - V VCC = 5.5 V 0.4 0.60 - 0.4 - 0.4 - V 74HCT132 VT+ VT VH positive-going threshold voltage 14. Transfer characteristics waveforms VO VT+ VI VH VT- VI VH VT- Fig 7. VT+ Transfer characteristics 74HC_HCT132 Product data sheet VO mna207 mna208 Fig 8. Transfer characteristics definitions All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 (c) NXP B.V. 2012. All rights reserved. 8 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger DDD DDD ,&& $ ,&& $ 9,1 9 a. VCC = 2.0 V 9,1 9 b. VCC = 4.5 V DDD ,&& P$ 9,1 9 c. VCC = 6.0 V Fig 9. Typical 74HC132 transfer characteristics 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 (c) NXP B.V. 2012. All rights reserved. 9 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger DDD DDD ,&& P$ ,&& P$ 9,1 9 a. VCC = 4.5 V 9,1 9 b. VCC = 5.5 V Fig 10. Typical 74HCT132 transfer characteristics 15. Application information The slow input rise and fall times cause additional power dissipation, this can be calculated using the following formula: Padd = fi (tr ICC(AV) + tf ICC(AV)) VCC where: Padd = additional power dissipation (W); fi = input frequency (MHz); tr = rise time (ns); 10 % to 90 %; tf = fall time (ns); 90 % to 10 %; ICC(AV) = average additional supply current (A). Average ICC(AV) differs with positive or negative input transitions, as shown in Figure 11 and Figure 12. An example of a relaxation circuit using the 74HC132; 74HCT132 is shown in Figure 13. 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 (c) NXP B.V. 2012. All rights reserved. 10 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger DDD DYHUDJH ,&& $ SRVLWLYHJRLQJ HGJH QHJDWLYHJRLQJ HGJH 9&& 9 (1) Positive-going edge. (2) Negative-going edge. Fig 11. Average additional supply current as a function of VCC for 74HC132; linear change of VI between 0.1VCC to 0.9VCC. DDD DYHUDJH ,&& $ SRVLWLYHJRLQJ HGJH QHJDWLYHJRLQJ HGJH 9&& 9 (1) Positive-going edge. (2) Negative-going edge. Fig 12. Average additional supply current as a function of VCC for 74HCT132; linear change of VI between 0.1VCC to 0.9VCC. 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 (c) NXP B.V. 2012. All rights reserved. 11 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger VCC R VCC A Y B C 001aac440 For 74HC132 and 74HCT132: 1 1 f = --- -----------------T K RC For K-factor, see Figure 14 Fig 13. Relaxation oscillator DDD . DDD . 9&& 9 K-factor for 74HC132 9&& 9 K-factor for 74HCT132 Fig 14. Typical K-factor for relaxation oscillator 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 (c) NXP B.V. 2012. All rights reserved. 12 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 16. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 15. Package outline SOT27-1 (DIP14) 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 (c) NXP B.V. 2012. All rights reserved. 13 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 16. Package outline SOT108-1 (SO14) 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 (c) NXP B.V. 2012. All rights reserved. 14 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 17. Package outline SOT337-1 (SSOP14) 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 (c) NXP B.V. 2012. All rights reserved. 15 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 18. Package outline SOT402-1 (TSSOP14) 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 (c) NXP B.V. 2012. All rights reserved. 16 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 17. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 18. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT132 v.3 20120830 Product data sheet - 74HC_HCT132_CNV v.2 Modifications: * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. * * Legal texts have been adapted to the new company name where appropriate. Figure 14 added (typical K-factor for relaxation oscillator). 74HC_HCT132_CNV v.2 19970826 74HC_HCT132 Product data sheet Product specification - All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 - (c) NXP B.V. 2012. All rights reserved. 17 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT132 Product data sheet Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 (c) NXP B.V. 2012. All rights reserved. 18 of 20 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 30 August 2012 (c) NXP B.V. 2012. All rights reserved. 19 of 20 NXP Semiconductors 74HC132; 74HCT132 Quad 2-input NAND Schmitt trigger 21. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Transfer characteristics . . . . . . . . . . . . . . . . . . 8 Transfer characteristics waveforms. . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 30 August 2012 Document identifier: 74HC_HCT132