32K/64K x 16/18
Dual-Port Static RAM
CY7C027/028
CY7C037/038
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600
Document #: 38-06042 Rev. *A Revised December 27, 2002
25/0251
Features
True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
32K x 16 organization (CY7C027)
64K x 16 organization (CY7C028)
32K x 18 organization (CY7C037)
64K x 18 organization (CY7C038)
0.35-micron CMOS for optimum speed/power
High-spe ed acc ess : 12[1]/15/20 ns
Low operating power
Active: ICC = 180 mA (typical)
Standby: ISB3 = 0.05 mA (typical)
Fully asynchro nous opera tion
Automatic power-down
Expandable data bus to 32/36 bits or more using Mas-
ter/Slav e chip selec t when using more th an one devic e
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flags for port-to-port communication
Separate upper-byte and lower-byte control
Dual Chip Enables
Pin select for Master or Slave
Commercial and indus trial tem peratu re ranges
Available in 100-pin TQFP
Pin-compati ble and funct iona lly equiv ale nt to IDT7027
Notes:
1. See page 6 for Load Conditions.
2. I/O8I/O15 for x16 devices; I/O9I/O17 for x18 devices.
3. I/O0I/O7 for x16 devices; I/O0I/O8 for x18 devices.
4. A0A14 for 32K; A0A15 for 64K devices.
5. BUSY is an output in master mode and an input in slave mode.
R/WL
CE0L
CE1L
OEL
I/O8/9LI/O15/17L I/O
Control
Address
Decode
A0LA14/15L
CEL
OEL
R/WL
BUSYL
I/O
Control
CEL
Interrupt
Semaphore
Arbitration
SEML
INTL
M/S
UBL
LBL
I/O0LI/O7/8L
R/WR
CE0R
CE1R
OER
I/O8/9LI/O15/17R
CER
UBR
LBR
I/O0LI/O7/8R
UBL
LBL
Logic Block Diagram
A0LA14/15L True Dual-Ported
RAM Array
A0RA14/15R
CER
OER
R/WR
BUSYR
SEMR
INTR
UBR
LBR
Address
Decode A0RA14/15R
[2] [2]
[3] [3]
[4] [4]
[5] [5]
[4] [4]
15/16
8/9
8/9
15/16
8/9
8/9
15/16 15/16
For the most recent information, visit the Cypress web site at www.cypress.com
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 2 of 19
Functional Description
The CY7C027/028 and CY7C037/038 are low-power CMOS
32K, 64K x 16/18 dual-port static RAMs. Various arbitration
schemes are included on the devices to handle situations
when mu ltiple proces sors access the sam e piece of data . T wo
port s are provid ed, permittin g independe nt, asynch ronous ac-
cess f or re ads and write s to any l ocat ion in memo ry. The de -
vices can be utilized as standalone 16/18-bit dual-port static
RAMs or multiple devi ces can be combined in order to functio n
as a 32/36-bit or wider master/slave dual-port static RAM. An
M/S pin is provided for implementing 32/36-bit or wider mem-
ory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communica-
tions status buffering, and dual-port video/graphics memory.
Each port has independent control pins: dual chip enables
(CE0 and CE1), read or write enable (R/W), and o utp ut e nabl e
(OE). Two flags are provided on each port (B USY and INT). BUSY
signals that the port i s trying to access t he same locati on currently
being accessed by the other port. The interrupt flag (INT) permits
communication bet ween po rts or syste ms by mea ns of a mai l box.
The semaphores are used to pass a flag, or token, from one port to
the other to indicate that a shared resource is in use. The semaphore
logic is comprised of eight shared latches. Only one side can control
the latch (semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down feature is
controlled independently on each port by the chip enable pins.
The CY7 C027/028 an d CY7C037/038 are availabl e in 100-pin
Thin Quad Plastic Flatpack (TQFP) packages.
Pin Configurations
100-Pin TQFP (Top View)
Note:
6. This pin is NC for CY7C027.
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
A9R
A10R
A11R
A12R
A13R
A14R
UBR
NC
LBR
CE1R
SEMR
OER
GND
NC
A15R
GND
R/WR
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
CE0R
58
57
56
55
54
53
52
51
CY7C027 (32K x 16)
A9L
A10L
A11L
A12L
A13L
A14L
UBL
NC
LBL
CE1L
SEML
OEL
GND
NC
A15L
VCC
R/WL
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
CE0L
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
A8L
A7L
A6L
A5L
A4L
A3L
INTL
A1L
NC
GND
M/S
A0R
A1R
A0L
A2L
BUSYR
INTR
A2R
A3R
A4R
A5R
A6R
A7R
A8R
BUSYL
34 35 36 424139 403837 43 44 45 5048 494746
NC
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/01R
I/O4R
I/O2R
GND
I/O0L
I/O2L
I/O3L
I/O3R
I/O5R
I/O1L
GND
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
I/O0R
3332313029282726
CY7C028 (64K x 16)
[6] [6]
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 3 of 19
Pin Configurations (continued)
100-Pin TQFP (Top View)
Note:
7. This pin is NC for CY7C037.
Selection Guide
CY7C027/028
CY7C037/038
-12[1]
CY7C027/028
CY7C037/038
-15
CY7C027/028
CY7C037/038
-20
Maximum Access Time (ns) 12 15 20
Typical Operating Current (mA) 195 190 180
Typical Standby Current for ISB1 (mA) (Both ports TTL level) 55 50 45
Typical Standby Current for ISB3 (mA) (Both ports CMOS level) 0.05 0.05 0.05
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
A8R
A9R
A10R
A11R
A12R
A13R
CE0R
A15R
UBR
SEMR
R/WR
GND
I/O17R
LBR
A14R
GND
OER
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
CE1R
58
57
56
55
54
53
52
51
CY7C037 (32K x 18)
A9L
A10L
A11L
A12L
A13L
A14L
CE1L
LBL
CE0L
R/WL
OEL
I/O17L
I/O16L
UBL
A15L
VCC
GND
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
SEML
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
A8L
A7L
A6L
A5L
A4L
A3L
BUSYL
A1L
INTL
GND
VCC
INTR
A0R
A0L
A2L
M/S
BUSYR
A1R
A2R
A3R
A4R
A5R
A6R
A7R
GND
34 35 36 424139 403837 43 44 45 5048 494746
I/O10R
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/01R
I/O4R
I/O2R
GND
I/O0L
I/O2L
I/O3L
I/O3R
I/O5R
I/O1L
GND
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
I/O0R
3332313029282726
CY7C038 (64K x 18)
[7] [7]
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 4 of 19
Maximum Ratings[8]
(Above which the useful life may be impaired. For user guide-
lines, not tes ted .)
Storage Temperature .................................65°C to +150°C
Ambient Temperature with
Power Applied.............................................55°C to +125°C
Supply Vo ltage to Ground Potential...............0.3V to +7.0V
DC Voltage Applied to Outputs
in High Z State............................................ 0.5V to +7.0DC
Input Voltage[9] ...............................................0.5V to +7.0V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage........................................... >1100V
Latch-Up Current.................................................... >200 mA
Note:
8. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
9. Pulse width < 20 ns.
10. Industrial parts are available in CY7C028 and CY7C038 only.
Pin Definitions
Left Port Right Port Description
CE0L, CE1L CE0R, CE1R Chip Enable (CE is LOW when CE0 VIL and CE1 VIH)
R/WLR/WRRead/Write Enable
OELOEROutput Enable
A0LA15L A0RA15R Address (A0A14 for 32K; A0A15 for 64K de vices)
I/O0LI/O17L I/O0RI/O17R Data Bus Input/Output (I/O0I/O15 for x16 devices; I/O0I/O17 for x18)
SEML SEMRSemaphore Enable
UBLUBRUpper Byte Select (I/O8I/O15 for x 16 devices; I/O9I/O17 for x18 devices)
LBLLBRLower Byte Select (I/O0I/O7 for x16 devices; I/O0I/O8 for x18 devices)
INTLINTRInterrupt Flag
BUSYLBUSYRBusy Flag
M/S Master or Slave Select
VCC Power
GND Ground
NC No Connect
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial[10] 40°C to +85°C 5V ± 10%
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 5 of 19
Note:
11. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except outp ut enab le). f = 0 me ans no address or cont rol li nes chan ge. Thi s appli es only to inp uts at CMOS level st andby I SB3.
Electrical Characteristi cs Ov er the Operating Ran ge
Symbol Parameter
CY7C027/028
CY7C037/038
Unit
-12[1] -15 -20
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
VOH Output HIGH Voltage (VCC=Min.,
IOH= 4.0 mA) 2.4 2.4 2.4 V
VOL Output LOW Voltage (VCC=Min.,
IOH= +4.0 mA) 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.2 2.2 2.2 V
VIL Input LOW Voltage 0.8 0.8 0.8 V
IOZ Output Leakage Current 10 10 10 10 10 10 µA
ICC Operating Current
(VCC=Max, IOUT=0 mA)
Outputs Disabled
Coml. 195 325 190 280 180 265 mA
Ind.[10] 305 290 mA
ISB1 Standby Current (Both
Ports TTL Level) CEL & CER
VIH, f=fMAX
Coml. 55 75 50 70 45 65 mA
Ind.[10] 60 80 mA
ISB2 Standby Current (One Port
TTL Level) CEL | CER VIH,
f=fMAX
Coml. 125 205 120 180 110 160 mA
Ind.[10] 125 175 mA
ISB3 Standby Current (Both
Ports CMOS Level) CEL &
CER VCC 0.2V, f=0
Coml. 0.05 0.5 0.05 0.5 0.05 0.5 mA
Ind.[10] 0.05 0.5 mA
ISB4 Standby Current (One Port
CMOS Level) CEL | CER
VIH, f=fMAX[11]
Coml. 115 185 110 160 100 140 mA
Ind.[10] 115 155 mA
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 6 of 19
AC Test Loads (Applicable to -12 only)[13]
Notes:
12. Tested initially and after any design or process changes that may affect these parameters.
13. Test Conditions: C = 0 pF.
Capacitance[12]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 2 5°C, f = 1 MHz,
VCC = 5.0V 10 pF
COUT Output Capacitance 10 pF
AC Test Loads and Waveforms
3.0V
GND 90% 90%
10%
3ns 3ns
10%
ALL INPUTPULSES
(a) Normal Load (Load 1)
R1 = 893
5V
OUTPUT
R2 = 347
C= 30pF
VTH =1.4V
OUTPUT
C= 30 pF
(b) Thévenin Equivalent (Load 1) (c) Three-State Delay(Load 2)
R1 = 893
R2 = 347
5V
OUTPUT
C= 5pF
RTH = 250
(Used for tCKLZ, tOLZ, & t OHZ
including scope and jig)
V
TH
=1.4V
OUTPUT
C
(a) Load 1 (-12 only)
R = 50
(b) Load Derating Curve
Capacitance (pF)
(ns) for all -12 access ti mes
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
0 5 10 15 20 25 30
Z
0
= 50
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 7 of 19
Switching Characteristics Over the Operating Range[14]
Parameter Description
CY7C027/028
CY7C037/038
Unit
-12[1] -15 -20
Min. Max. Min. Max. Min. Max.
READ CYCL E
tRC Read Cycle Time 12 15 20 ns
tAA Address to Data Valid 12 15 20 ns
tOHA Output Hold From Address Change 3 3 3 ns
tACE[15] CE LOW to Data Valid 12 15 20 ns
tDOE OE LOW to Data Valid 810 12 ns
tLZOE[16, 1 7, 18] OE LOW to Low Z 3 3 3 ns
tHZOE[16, 17, 18] OE HIGH to High Z 10 10 12 ns
tLZCE[16 , 17, 18] CE LOW to Low Z 3 3 3 ns
tHZCE[16, 17, 18] CE HIGH to High Z 10 10 12 ns
tPU[18] CE LOW to Power-Up 0 0 0 ns
tPD[18] CE HIGH to Power-Down 12 15 20 ns
tABE[15] Byte Enable Access Time 12 15 20 ns
WRITE CYCLE
tWC Write Cycle Time 12 15 20 ns
tSCE[15] CE LOW to Write End 10 12 15 ns
tAW Address Valid to Write End 10 12 15 ns
tHA Address Hold From Write End 0 0 0 ns
tSA[15] Address Set-Up to Write Start 0 0 0 ns
tPWE Wr ite Pulse Width 10 12 15 ns
tSD Data Set-Up to Write End 10 10 15 ns
tHD Data Hold From Write End 0 0 0 ns
tHZWE[17, 18] R/W LOW to High Z 10 10 12 ns
tLZWE[17, 1 8] R/W HIGH to Low Z 3 3 3 ns
tWDD[19] Write Pulse to Data Delay 25 30 45 ns
tDDD[19] Write Data Valid to Read Data Valid 20 25 30 ns
Notes:
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V , and output loading of the specified
IOI/IOH and 30-pF l oad cap acit ance.
15. To access RAM, CE=L , UB=L, SEM=H. To access semaphore, CE=H and SEM= L. Either conditi on must be valid for th e entire tSCE time.
16. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
17. Test conditions used are Load 2.
18. This parameter is guaranteed by design, but it is not production tested.
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 8 of 19
Data Retention Mode
The CY7C027/028 and CY7C037/038 are designed with bat-
tery bac kup in mind. Dat a retention v oltage an d supply curre nt
are guaranteed over temperature. The following rules ensure
data retention:
1. Chip enable (CE ) must be held HIGH during data retention, with-
in VCC to VCC 0.2V.
2. CE must be kept between VCC 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5 volts).
BUSY TIMING[20]
tBLA BUSY LOW from Address Match 12 15 20 ns
tBHA BUSY HIGH from Address Mismatch 12 15 20 ns
tBLC BUSY LOW from CE LOW 12 15 20 ns
tBHC BUSY HIGH from CE HIGH 12 15 17 ns
tPS Port Set-Up for Priority 5 5 5 ns
tWB R/W HIGH after BUSY (Slav e) 0 0 0 ns
tWH R/W HIGH after BUSY HIGH (Slave) 11 13 15 ns
tBDD[21] BUSY HIGH to Data Valid 12 15 20 ns
INTERRUPT TIMING[20]
tINS INT Set Time 12 15 20 ns
tINR INT Reset Time 12 15 20 ns
SEMAPHORE TIMING
tSOP SEM Flag Update Pulse (OE or SEM)10 10 10 ns
tSWRD SEM Flag Write to Read Time 5 5 5 ns
tSPS SEM Flag Contention Window 5 5 5 ns
tSAA SEM Address Access Time 12 15 20 ns
Switching Characteristics Over the Operating Range[14] (continued)
Parameter Description
CY7C027/028
CY7C037/038
Unit
-12[1] -15 -20
Min. Max. Min. Max. Min. Max.
Timing
Parameter Test Conditions[22] Max. Unit
ICCDR1 @ VCCDR = 2V 1.5 mA
Data Retention Mode
4.5V 4.5V
VCC > 2.0V
VCC to VCC 0.2V
VCC
CE
tRC
VIH
Notes:
20. Test conditions used are Load 1.
21. tBDD is a calcul ated p aramet er and is the greate r of t WDDtPWE (actual) or tDDDtSD (actual).
22. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 9 of 19
Switching Waveforms
Notes:
23. R/W is H IGH f or read cycle s.
24. Device is continuously selected CE = V IL and UB or LB = VIL. This wavef orm ca nnot b e used for semap hore rea ds.
25. OE = VIL.
26. Address valid prior to or coincide nt with CE t ransiti on LOW.
27. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
tRC
tAA
tOHA
DATA VALIDPREVIO U S D ATA VALID
DATA OUT
ADDRESS
tOHA
Read Cycle No. 1 (Either Port Address Access)[23 , 24, 25]
tACE
tLZOE
tDOE
tHZOE
tHZCE
DATA VALID
tLZCE
tPU tPD
ISB
ICC
DATA OUT
OE
CE and
LB or UB
CURRENT
Read Cycle No. 2 (Either Port CE/OE Access)[23, 26, 27]
UB or LB
DATAOUT
tRC
ADDRESS
tAA tOHA
CE
tLZCEtABE
tHZCE
tHZCE
tACE
tLZCE
Read Cycle No. 3 (Either Port)[23, 25, 26, 27]
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 10 of 19
Notes:
28. R/W must be H IGH du ring al l address tran siti ons.
29. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM a nd a LOW UB or LB.
30. tHA is measur ed from the e arlier o f CE or R/W or (SEM or R/W) going HIGH at the end of write cycl e.
31. If OE is L OW during a R/W control led writ e cycle, the write pulse wid th must b e the l arger of tPWE or (tHZWE + tSD) to all ow the I/O drivers t o turn of f and data to b e placed on
the bus for the requi red tSD. If OE is HIGH duri ng an R/W contr olled write cycle, this requi rement does not apply and t he wr ite pul se ca n be as s hort a s the speci fied t PWE.
32. To access RAM, CE = VIL, SEM = VIH.
33. To access upper byte , CE = VIL, UB = VIL, SEM = VIH.
To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
34. Transition is measured ±500 mV fro m stea dy st ate with a 5-pF load (inc luding s cope and jig) . This p arame ter is s ampled an d not 100% tested.
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CE or SEM LOW trans ition occurs si multaneous ly with or after the R/W LOW transiti on, t he out puts r emain in th e high-i mpedance s tat e.
Switching Waveforms (continued)
tAW
tWC
tPWE
tHD
tSD
tHA
CE
R/W
OE
DATAOUT
DATA IN
ADDRESS
tHZOE
tSA
tHZWE tLZWE
Writ e Cycle No. 1: R/W Co ntrolled Timin g[28, 29, 30, 31]
[34]
[34]
[31]
[32,33]
NOTE 35 NOTE 35
tAW
tWC
tSCE
tHD
tSD
tHA
CE
R/W
DATA IN
ADDRESS
tSA
Write Cycle No. 2: CE Controlled Timing[28, 29, 30, 34, 35]
[32,33]
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 11 of 19
Notes:
37. CE = HIGH for the duration of the above timing (both write and read cycle).
38. I/O0R = I/O0L = LO W (reques t sema phore); CER = CEL = HIGH.
39. Semaphores are reset (available to both ports) at cycle start.
40. If tSPS is viol ated, t he sema phore w ill d efinite ly be ob tai ned by one si de or t he oth er , bu t whi ch sid e will get th e semap hore is unpr edictable.
Switching Waveforms (continued)
tSOP
tSAA
VA LID ADRESS VA LID ADRESS
tHD
DATAIN VALID DATAOUT VALID
tOHA
tAW tHA tACE
tSOP
tSCE
tSD
tSA tPWE
tSWRD tDOE
WRITE CYCLE READ CYCLE
OE
R/W
I/O0
SEM
A0A2
Semaphore Read After Write Timing, Either Side[37]
MATCH
tSPS
A0LA2L
MATCH
R/WL
SEML
A0RA2R
R/WR
SEMR
Timing Diagram of Semaphore Contention[38, 39, 40]
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 12 of 19
Note:
41. CEL = CER = LOW.
Switching Waveforms (continued)
VALID
tDDD
tWDD
MATCH
MATCH
R/WR
DATA INR
DATAOUTL
tWC
ADDRESSR
tPWE
VALID
tSD tHD
ADDRESSL
tPS
tBLA tBHA
tBDD
BUSYL
Timing Diagram of Read with BUSY (M/S=HIGH)[41]
tPWE
R/W
BUSY tWB tWH
Write Timing with Busy Input (M/S=LOW)
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 13 of 19
Note:
42. If tPS is violated, the busy signal will be ass erted on one side or the other , but there is no guaran tee to which side BUSY will be asserted.
Switching Waveforms (continued)
ADDRESS MATCH
tPS
tBLC tBHC
ADDRESS MATCH
tPS
tBLC tBHC
CERValidFirst:
ADDRESSL,R
BUSYR
CEL
CER
BUSYL
CER
CEL
ADDRESSL,R
Busy Timing Diagram No.1 (CE Arbitration)[42]
CELValid First:
ADDRESS MATCH
tPS
ADDRESSL
BUSYR
ADDR ES S MI SMATCH
tRC or tWC
tBLA tBHA
ADDRESSR
ADDRESS MATCH ADDR ES S MI SMATCH
tPS
ADDRESSL
BUSYL
tRC or tWC
tBLA tBHA
ADDRESSR
Right AddressValid First:
Busy Timing Diagram No. 2 (Address Arbitration)[42]
Left Address Valid First:
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 14 of 19
Notes:
43. tHA depen ds on which enable pin (CEL or R/WL) is deasserte d fir st.
44. tINS or tINR depends on w hich en able pin (CE L or R/WL) is asserted la st.
Switching Waveforms (continued)
Interrupt Timing Diagrams
WRITE 7FFF (FFFF for CY7C028/38)
tWC
Right SideClears INTR:
tHA
READ 7FFF
tRC
tINR
WRITE 7FFE (FFFE for CY7C028/38)
tWC
Right SideSets INTL:
Left Side Sets INTR:
Left SideClears INTL:
READ 7FFE
tINR
tRC
ADDRESSR
CE L
R/WL
INTL
OE L
ADDRESSR
R/WR
CER
INTL
ADDRESSR
CER
R/WR
INTR
OER
ADDRESSL
R/WL
CEL
INTR
tINS
tHA
tINS
(FFFF for CY7C028/38)
(FFFE for CY7C028/38)
[43]
[44]
[44]
[44]
[43]
[44]
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 15 of 19
Architecture
The CY7C027/028 and CY7C037/038 consist of an array of
32K and 64K words of 16 and 18 bits each of dual-port RAM
cells, I/O and a ddress lines , and co ntrol sign als (C E, OE, R/W).
These control pins permit independent access for reads or writes to
any location in memory. To handle simultaneous writes/reads to the
same location, a BUSY pin is pro vided on ea ch port. Two interrupt
(INT) pins can be utilized for port-to-port communication. T wo sema-
phore (S EM) cont ro l pi ns are us ed f or a llo cati ng share d r esour ces.
With the M/S pin, the devices can function as a master (BUSY pins
are outputs) or as a slave (BUSY pins are inputs). The devices also
have an automatic power-down feature controlled by CE. Each port
is provided with its own output enable control (OE), which allows data
to be read from the device.
Functional Description
Wr ite Ope ration
Data must be set up for a duration of tSD before the rising edge
of R/W in or der to guar antee a valid w rite. A write operat ion is con-
trolled by either the R/W pin (see Write Cycle No. 1 waveform) or the
CE pin (see Write Cycle No. 2 waveform). Required inputs for
non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay m ust occ ur be fore the data is read o n the ou tpu t; oth er-
wise the data read is not deterministic. Data will be val id on the
port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after OE is
asserted. If the user wishes t o access a semaphore flag, then th e
SEM pin must be asserted instead of the CE pin, and OE must also
be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (7FFF for the
CY7C027 /37, FFFF for the CY7C028/38) is the mailbox for the
right port and the second-highest memory location (7FFE for
the CY7C027/37, FFFE for the CY7C028/38) is the mailbox for
the left port. When one port writes to the other ports mailbox,
an interrupt is generated to the owner. The interrupt is reset
when the owner reads the contents of the mailbox. The mes-
sage is user defined.
Each port can read the other ports mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevent s t he port fro m se tting t he int errupt t o the winn ing po rt.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processors interrupt request
input pin.
The operation of the interrupts and their interaction with Busy
is summarized in Table 2.
Busy
The CY7 C027/028 an d CY7C037/038 p rovide on-ch ip arbitra-
tion to resolv e simultan eous memory loc ation access (conten-
tion). If bo th ports CEs are asserted and an address match occurs
within tPS of each other , the busy logic will determine which port has
access. If tPS is violated, one port will definitely gain permission to the
location, bu t it is not predictable whic h port w ill get that pe rmission.
BUSY will be a sse rted t BLA after an address match or tBLC after CE
is taken LOW .
Master/Slave
A M/S pin is provided in order to expand the word width by configur-
ing t he dev ice as either a mast er or a slave. T he BUSY output of the
master is connected to the BUSY input of the slave. This will allow the
device to interface to a master device with no external components.
Writing to slave devices must be delayed until after the BUSY input
has settled (tBLC or tBLA), otherwise, the slave chip may begin a write
cycle during a contention situation. When tied HIGH, the M/S pin al-
lows the device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration outcome
to a slave.
Semaphore Operation
The CY7C027/028 and CY7C037/038 provide eight sema-
phore lat ches, which are separate from the dual-port memory
locatio ns. Semaphores are used to res erve resource s that are
shared between the two ports.The state of the semaphore in-
dicates that a resource is in use. For example, if the left port
wants to request a given resource, it sets a latch by writing a
zero to a semaphore location. The left port then verifies its
success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for tSOP before at-
tempting to read the semaphore. The semaphore value will be avail-
able tSWRD + tDOE after the rising edge of the semaphore write. If the
left port was successful (reads a zero), it assumes control of the
shared re source, otherwise ( reads a one) it assumes t he righ t port
has control and continues to poll the semaphore. When the right side
has relinquished control of the semaphore (by writing a one), the left
side will succeed in gaining control of the semaphore. If the left side
no longer re quir es the semap hor e, a o ne i s w ritte n t o can cel its re-
quest.
Semaphores are accessed by asserting SEM LOW. The SEM
pin funct ions as a chip select f or the semaphor e latc hes (CE must
remain H IGH durin g SEM LOW). A02 represents the semaphore
addres s. OE and R/W are used in t he same manner as a norma l
memory access. When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will appear at
the same semaphore address on the right port. That semaphore can
now only be modi fied by the side showing zer o (the le ft port in th is
case). If the left port now relinquishes control by writing a one to the
semaphore, the semaphore will be set to one for both sides. Howev-
er, if the right port had requested the semaphore (written a zero) while
the left port had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows sam-
ple semaphore operations.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to p rev ent the s em aph ore f rom cha ngi ng st a te
during a write from the other port. If both ports attempt to ac-
cess t he sema phore wi thin tSPS of each other, the semaphore will
definitely be obtained by one side or the other, but there is no guaran-
tee which side will control the semaphore.
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 16 of 19
Table 1. Non-Contending Read/Write
Inputs Outputs
CE R/W OE UB LB SEM I/O9I/O17 I/O0I/O8Operation
H X X X X H High Z High Z Deselected: Power-Down
X X X H H H High Z High Z Deselected: Power-Down
L L X L H H Data In High Z Write to Upper Byte Only
L L X H L H High Z Data In Write to Lower Byte Only
L L X L L H Data In Data In Write to Both Bytes
L H L L H H Data Out High Z Read Upper Byte Only
L H L H L H High Z Data Out Read Lower Byte Only
L H L L L H Data Out Data Out Read Both Bytes
X X H X X X High Z High Z Output s Disable d
H H L X X L Data Out Data Out Read Data in Semaphore Flag
X H L H H L Da ta Out Data Out Read Data in Semaphore Flag
H X X X L Data In Data In Write DIN0 into Semaphore Flag
X X H H L Data In Data In Write DIN0 into Semaphore Flag
L X X L X L Not Allowed
L X X X L L Not Allowed
Table 2. Interrupt Op eration Example (assumes BUSYL=BUSYR=HIGH)[45]
Left Port Right Port
Function R/WLCELOELA0L14LINTLR/WRCEROERA0R14R INTR
Set Right INTR Flag L L X 7FFF X X X X X L[47]
Reset Right INTR Flag X X X X X X L L 7FFF H[46]
Set Left INTL Flag X X X X L[46] L L X 7FFE X
Reset Left INTL Flag X L L 7FFE H[47] X X X X X
Table 3. Semaphore Operation Example
Function I/O0I/O17 Left I/O0I/O17 Right Status
No action 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left Port has semaphore token
Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore
Left port writes 1 to semaphore 1 0 Right port obtains semaphore token
Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore
Right port writes 1 to semaphore 0 1 Left por t obtains semaphore token
Left port writes 1 to semaphore 1 1 Semaphore free
Right port writes 0 to semaphore 1 0 Right port has semaphore token
Right port writes 1 to semaphore 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left port has semaphore token
Left port writes 1 to semaphore 1 1 Semaphore free
Notes:
45. A0L15L and A 0R15R, FFFF/FFFE for the CY7C 028/038.
46. If BU SYR= L, the n no c hange.
47. If BU SYL=L , then no c hange.
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 17 of 19
Ordering Information
32K x16 Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
12[1] CY7C027-12AC A100 100-Pin Thin Quad Flat Pack Commercial
15 CY7C027-15AC A100 100-Pin Thin Quad Flat Pack Commercial
20 CY7C027-20AC A100 100-Pin Thin Quad Flat Pack Commercial
64K x16 Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
12[1] CY7C028-12AC A100 100-Pin Thin Quad Flat Pack Commercial
15 CY7C028-15AC A100 100-Pin Thin Quad Flat Pack Commercial
20 CY7C028-20AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C028-20AI A100 100-Pin Thin Quad Flat Pack Industrial
32K x18 Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
12[1] CY7C037-12AC A100 100-Pin Thin Quad Flat Pack Commercial
15 CY7C037-15AC A100 100-Pin Thin Quad Flat Pack Commercial
20 CY7C037-20AC A100 100-Pin Thin Quad Flat Pack Commercial
64K x18 Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
12[1] CY7C038-12AC A100 100-Pin Thin Quad Flat Pack Commercial
15 CY7C038-15AC A100 100-Pin Thin Quad Flat Pack Commercial
20 CY7C038-20AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C038-20AI A100 100-Pin Thin Quad Flat Pack Industrial
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 18 of 19
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-A
CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 19 of 19
Document Title: CY7C027/028, CY7C037/038 32K/64K x 16/18 Dual-Port Static RAM
Document Number: 38-06042
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 110190 09/29/01 SZV Change from Spec number: 38-00666 to 38-06042
*A 122292 12/27/02 RBI Power up requirements added to Maximum Ratings Information