IXA531 Preliminary Data Sheet 500mA 3-Phase Bridge Driver Features * Fully operational to +650V * * * * * * * * * * * * * * * * * * * * General Description The IXA531 is a monolithic, 3-phase, MOSFET/IGBT gate driver consisting of three independent, high and low side output channels. In addition to the six inputs, which are CMOS/TTL Compatible, for the three corresponding high side and three low side outputs, there are dedicated lines for FAULT, ENABLE and RESET. Overload/Short Circuit protection is implemented by sensing a voltage across a shunt or low value resistor which carries load current. Upon Overload/Short Circuit detection, all outputs are disabled. Likewise ENABLE (EN) pin, when LOW under abnormal operating conditions, affords soft shut down of outputs. FAULT(FLT) signal`s status indicates that shut down has occurred either due to Overload/Short Circuit in driven MOSFET/IGBT or Under Voltage on VCL. Clearing of FAULT (FLT) signal and restoration of normal operation ensue automatically after a programmed delay using an RC Network wired at RST (RESET) pin. Matched propagation delays ensure proper operation even at very high switching frequencies. Absence of cross conduction in output stages removes possibility of shoot through in driven power MOSFETs or IGBTs. Tolerant of negative transient voltages dV/dt immune (50V/ns) Latch-up protected over entire operating range Fault-current shutdown for all drive outputs User selectable delay or latching function for clearing of the FAULT signal, independent user controlled clearing of the FAULT signal is also available UVLO protection for all drive outputs Enable signal capable of disabling all driver outputs 3 half-bridge driver pairs (independent) 3.3V logic compatible Cross-conduction prevention logic, 220 ns - 360ns Phase leg deadtime Peak output current: 600mA Pull-up/Source, 600mA Pull-down/Sink Wide operating supply voltage range: 8.0V to 35V Capacitive load drive capability: 1250pF in < 100ns Matched, low propagation delay times Low supply current Monolithic construction ___ Fault monitoring is accompanied by a FLT signal indication, with programmable reset or user selectable latched protection Target package power dissipation capability is 2.0W. Full level of function available from -55C to + 125C Available in 48-Lead 7mm x 7mm MLP Quad package and 44-Lead PLCC package Applications * * * * * * Driving MOSFETs and IGBTs in half-bridge circuits High voltage, high side and low side drivers Motor Controls Switch Mode Power Supplies (SMPS) DC to DC Converters Class D Switching Amplifiers Ordering Information Part Package IXA531S10 48L - SSLGA IXA531L4 44L - PLCC Warning: The IXA531 is ESD sensitive. DS99187A(12/05) Copyright (c) IXYS CORPORATION 2005 1 First Release IXA531 Fig. 1. Single Phase Application up to + 650 V VCL VCL HIN1 HIN1 LIN1 LIN1 FLT FLT EN EN VCH1 HGO1 To HS1 Load IXA531 RST UVSEL ITRP LGO1 LS DG LGO3 LIN2 HG02 LGO2 LIN3 HS3 HG03 HIN2 VCH2 HS2 HIN3 VCH3 Pin Description And Configuration SYMBOL FUNCTION DESCRIPTION HS Input High side Input signal, TTL or CMOS compatible; HGO1,2,3 out of phase LS Input Low side Input signal, TTL or CMOS compatible; LGO1,2,3 out of phase EN Enable Chip enable. When driven high, both outputs go low. DG Ground Logic Reference Ground VCH1,2,3 Supply Voltage High Side Power Supply HGO1,2,3 Output High side driver output HS1,2,3 Return High side voltage return VCL Supply Voltage Low side and Logic fixed power supply. This power supply provides power for _______ HIN1,2,3 _______ LIN1,2,3 all outputs. Voltage range is from 8.0 to 35V. LGO1,2,3 Output Low side driver output LS ___ FLT Low side return Low side driver return Fault Indicates Low-Side under voltage or Over Current Trip ITRP Trip Input for over current shutdown RST Delay after trip Externally connected RC network decide FAULT CLEAR delay. 2 3 GND DG LS LGO1 HS1 ITRP FLT EN FLT EN HGO1 UVSEL LIN1 LIN1 VCH1 RST VCL HIN1 VCL HIN1 LIN2 HIN2 LGO2 HS2 HGO2 VCH2 Fig. 2. 3-Phase Application for the IXA531. To Load PH1 LIN2 HIN2 up to + 650 V PH2 To Load LIN3 HIN3 LIN3 HIN3 IXA531S10 LGO3 HS3 HGO3 VCH3 PH3 To Load IXA531 IXA531 Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to LS. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions Symbol Definition Min. Max. Units VCH High side floating supply voltage , (VCH1,2,3) -200 650 V VHS VHGO High side floating supply offset voltage , (VHS1,2,3) VCH1,2,3 - 35 VCH1,2,3 + 0.3 V High side floating output voltage , (VHGO1,2,3) VHS1,2,3- 0.3 VCH1,2,3 + 0.3 V VCL Low side and logic fixed supply voltage 8.0 35 V VDG Logic Supply offset voltage VLS - 0.7 VLS + 0.7 V VLGO VFLT FAULT output voltage VCL + 0.3 Lower of (VDG + 35) or (VCL + 0.3) VCL + 0.3 V VIN Low side output voltage _______ _______ Input voltage HIN1,2,3, LIN1,2,3, ITRP, RST , EN dV/dt Allowable offset voltage slew ratelew rate 50 V/ns PD Package power dissipation@ TA +25OC 2.0 W RthJA Thermal resistance, junction to ambient 63 K/W TJ Junction temperature 125 O TS Storage temperature 150 O 300 O TL - 0.3 VDG - 0.3 VDG - 0.3 -55 Lead temperature (soldering, 10 seconds) V V C C C Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute values referenced to LS. The VHS offset rating is tested with all supplies baised at 15V differential. Symbol Definition VCH1,2,3 High side floating supply voltage VHS1,2,3 VHGO1,2,3 High side floating supply offset voltage VLGO1,2,3 Min. VHS1,2,3 + 12 Max. VHS1,2,3 + 35 Units V - 200 650 V VHS1,2,3 VCH1,2,3 V Low side output voltage 0 VCL V VCL Low side and logic fixed supply voltage 12 35 V VDG Logic Supply offset voltage VLS - 0.3 VLS + 0.3 V VFLT FAULT output voltage VDG VCL V VRST RST input voltage VDG VCL V VITRP ITRP input voltage VDG VCL V VDG or VLS VCL VIN TA High side floating output voltage _______ _______ Logic input voltage HIN1,2,3, LIN1,2,3, EN Ambient temperature -40 4 125 V O C IXA531 Static Electrical Characteristics VBIAS (VCL, VCH1,2,3) = 15V unless otherwise specified. The VIN, VTH and IIN parameters are referenced to DG and are applicable to all six channels . The VO and IO parameters are referenced to LS and V and are applicable to the HS1,2,3 respective output leads: H and LGO1,2,3. GO1,2,3 Symbol Definition Min. Typ. Max. Units VINL Logic "0" input voltage HIN1,2,3; LIN1,2,3 VINH Logic "1" input voltage HIN1,2,3; LIN1,2,3 VEN,TH+ EN positve going threshold VEN,TH - EN negative going threshold 0.8 VITRP, TH+ ITRP positve going threshold 0.37 VITRP, HYS ITRP input hysteresis .07 V VRST,TH+ RST positive going threshold 8 V VRST, HYS RST input hysteresis 3 V VOH1,2,3 High level output voltage, VCH - VHGO or VCL- VLGO 0.9 1.4 V I0=20mA VOL1,2,3 Low level output voltage, VHGO or VLGO 0.4 0.6 V I0=20mA VCLUV+ VCL supply under-voltage positive going threshold 10.6 11.1 11.6 V VCHUV+ VCH supply under-voltage positive going threshold 10.6 11.1 11.6 V VCLUV- VCL supply under-voltage negaitive going threshold 10.4 10.9 11.4 V VCHUV- VCH supply under-voltage negaitive going threshold 10.4 10.9 11.4 V VCLUVH VCL supply under-voltage lockout hysteresis 0.2 V VCHUVH VCH supply under-voltage lockout hysteresis 0.2 V ILK Offset supply leakage current IQVCH IQVCL Quiescent VCH supply current 0.8 3.0 Test Conditions V V 3.0 V V 0.46 0.55 V 50 A VCH1,2,3= VHS1,2,3=600 V 70 120 A VIN=0V or 5V Quiescent VCL supply current 1.6 2.3 mA VIN=0V or 5V VIN Input clamp voltage (HIN,LIN,ITRP,EN) 4.9 V IIN = 100A ILIN+or IIN+ Logic "1" Input bias current for LIN1,2,3 200 300 A VLIN = 5V ILIN-or IIN- Logic "0" Input bias current for LIN1,2,3 100 220 A VLIN = 0V IHIN+or IIN+ Logic "1" Input bias current for HIN1,2,3 200 300 A VHIN = 5V IHIN-or IIN- Logic "0" Input bias current for HIN1,2,3 100 220 A VHIN = 0V IITRP+ "high" ITRP input bias current 30 100 A VITRP = 5V IITRP- "low" ITRP input bias current 0 1 A VITRP = 0V IEN+ "high" ENABLE input bias current 30 100 A VEN = 5V IEN- "low" ENABLE input bias current 0 1 A VEN = 0V IRST RST input bias current 0 1 A VRST = 0Vor 15V IGO+ Output high short circuit pulsed current 600 mA V0=0V,PW <10 s IGO- Output low short circuit pulsed current 600 mA V0=15V,PW<10s RON, RST RST low on resistance 50 100 RON, FLT FLT low on resistance 50 100 5 IXA531 Dynamic Electrical Characteristics VCL = VCH = VBIAS = 15V, VHS1,2,3 = VDG = VLS, TA = 25C and CL = 1000pF unless otherwise specified. Symbol Definition Min. Typ. Max. Units ton toff tr tf tEN 300 250 300 425 400 125 50 450 550 550 190 75 600 nS nS nS nS nS tITRP Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-on fall time ENABLE low to output shutdown propagation delay ITRP to output shutdown propagation delay 500 750 1000 nS tbl ITRP blanking time 100 150 tFLT ITRP to FAULT propagation delay 400 600 tFILIN Input filter time (HIN, LIN, EN) 100 200 tFLCLR FAULT clear time RST=2meg, C=1nF 1.3 1.65 2 mS DT MT MDT Dead time Matching delay ON and OFF Matching delay, max (ton , toff) - min (ton , toff) (ton,toff are applicable to all 3 channels) 220 290 40 360 75 nS nS 25 70 nS 40 75 nS PM Output pulse width matching, PWMIN-PWMOUT nS 800 nS nS Test Conds. VIN=0V & 5V VIN=0V & 5V ------VIN , VEN = 0 V or 5 V VITRP=5V VIN=0V or 5V VITRP = 5V V IN = 0V or 5V VITRP = 5V VIN = 0V & 5V VIN = 0V or 5V VITRP=0V VIN = 0V & 5V External Dead Time >400nsec VCL VCH ITRP ENABLE FAULT LGO1,2,3 HGO1,2,3 <UVCL X X X 0(note 1) 0 0 15V <UVCH 0V 15V high imp LIN1,2,3 0 15V 15V 0V 15V high imp LIN1,2,3 HIN1,2,3 15V 15V >VITRP 15V 0 (note 2) 0 0 15V 15V 0V 0V high imp 0 0 Notes: A Cross Conduction logic prevents LGO1,2,3 and HGO1,2,3 for each channel from turning on simultaneously. 1. UVCL is not latched, when VCL>UVCL, FAULT returns to high impedance. 2. When ITRP < VITRP, FAULT returns to high-impedance after RST pin becomes greater then 8V (@VCL= 15V). 6 IXA531 HIN1,2,3 HIN1,2,3 LIN1,2,3 EN ITRP FLT RST HO1,2,3 LO1,2,3 Fig. 3. (5) Timing Diagram Fig. Timing Diagram EN 50% t EN 90% LO1,2,3 HO1,2,3 Fig. Fig.4. (6)ENABLE EnableTiming TimingWaveforms Waveforms LIN1,2,3 50% 50% HIN1,2,3 PWMIN LIN1,2,3 HIN1,2,3 50% 50% ton toff tr PWMOUT 90% HO1,2,3 tf 90% 10% 10% LO1,2,3 Fig. 5. Switching Time Definitions 7 IXA531 LIN1,2,3 50% 50% HIN1,2,3 LIN1,2,3 HIN1,2,3 50% 50% LO1,2,3 HO1,2,3 DT DT (8) Deadtime Waveforms Fig.Fig. 6. Deadtime Waveforms RST VRST,th+ 50% 50% 50% ITRP FLT 50% 50% t FLT t FLCLR OUTPUT 90% t ITRP Fig.Fig. 7. ITRP / RST/Waveforms (9) ITRP RST Waveforms t FILIN t FILIN on on off off on off HIN / LIN HO / LO high low Fig. 8. ENABLE Timing Waveforms Fig. (10) Input Filter Diagram 8 IXA531 VCL VCL VCL VCH VCH1 750K Low to HIN1 hin1 5V LOGIC to VCL CMOS VCL en1 750K LIN1 lin1 Level Shift , & Anti-Cross Conduction Logic h01 Out Rst In Isolation iO1 600mA Gate Driver HGO1 UVCC Detect HS HS1 Isolated High Side VCL VCL VCL High In VCH VCH2 750K Low to HIN2 hin2 5V LOGIC to VCL CMOS VCL en2 750K LIN2 lin2 Level Shift , & Anti-Cross Conduction Logic h02 Out Rst In Isolation iO2 600mA Gate Driver HGO2 UVCC Detect HS HS2 Isolated High Side VCL VCL VCL High In VCH VCH3 750K Low to HIN3 hin3 5V LOGIC to VCL CMOS VCL en3 750K LIN3 lin3 Isolation Level Shift , & Anti-Cross Conduction Logic High In h03 Out Rst In iO3 600mA Gate Driver HGO3 UVCC Detect HS HS3 Isolated High Side VCL VCL VCL UVCL EN In Low to High Delay Equalizer Out 600mA Gate Driver LGO1 In Low to High Delay Equalizer Out 600mA Gate Driver LGO2 In Low to High Delay Equalizer Out 600mA Gate Driver LGO3 OUT Detect 50K VCL ITRP + S - 50K Set Dominant R + 0.5 V - Latch QB VCL RST N FLT LS 1 N DG Fig. (9) IXA531 Block Diagram 9 IXA531 Fig. 10. Pin Diagram for the IXA531S10 48-Lead MLP Quad Package 0.2760.002 [7.000.05] 0.2760.002 [7.000.05] 0.0390.002 [1.000.05] 0.0150.001 [0.380.03] 0.0090.001 [0.230.03] 0.0300.001 [0.750.03] 0.020 [0.50] HIN3 HIN2 HIN1 VCL NC NC NC VCH1 HGO1 HS1 NC Fig. 11. Pin Diagram for the IXA531L4 44-Lead PLCC package 6 5 4 3 2 1 44 43 42 41 40 NC LS 7 39 NC LIN1 8 38 NC LIN2 9 37 VCH2 LIN3 10 36 HGO2 NC 11 35 HS2 FLT 12 34 NC NC 13 33 NC ITRP 14 32 NC NC 15 31 VCH3 EN 16 30 HGO3 RST 17 29 HS3 IXA531L4 23 24 25 26 27 28 LGO2 LGO1 NC NC NC 22 LGO3 21 LS 20 NC 19 DG NC 18 NC IXA531S10 10 IXA531 Fig. 12. 44-Lead PLCC Outline Diagram IXYS Corporation 3540 Bassett St; Santa Clara, CA 95054 Tel: 408-982-0700; Fax: 408-496-0670 e-mail: sales@ixys.net www.ixys.com IXYS Semiconductor GmbH Edisonstrasse15 ; D-68623; Lampertheim Tel: +49-6206-503-0; Fax: +49-6206-503627 e-mail: marcom@ixys.de 11