Preliminary Data Sheet
IXA531
First Release
Copyright © IXYS CORPORATION 2005
500mA 3-Phase Bridge Driver
Applications
• Driving MOSFETs and IGBTs in half-bridge circuits
• High voltage, high side and low side drivers
• Motor Controls
• Switch Mode Power Supplies (SMPS)
• DC to DC Converters
• Class D Switching Amplifiers
Warning: The IXA531 is ESD sensitive.
DS99187A(12/05)
Features
• Fully operational to +650V
• Tolerant of negative transient voltages
• dV/dt immune (50V/ns)
• Latch-up protected over entire operating range
• Fault-current shutdown for all drive outputs
• User selectable delay or latching function for
clearing of the FAULT signal, independent
user controlled clearing of the FAULT signal
is also available
• UVLO protection for all drive outputs
• Enable signal capable of disabling all driver outputs
• 3 half-bridge driver pairs (independent)
• 3.3V logic compatible
• Cross-conduction prevention logic,
220 ns - 360ns Phase leg deadtime
• Peak output current: 600mA Pull-up/Source,
600mA Pull-down/Sink
• Wide operating supply voltage range: 8.0V to 35V
• Capacitive load drive capability: 1250pF in < 100ns
• Matched, low propagation delay times
• Low supply current
• Monolithic construction ___
• Fault monitoring is accompanied by a FLT
signal indication, with programmable reset or user
selectable latched protection
• Target package power dissipation capability is 2.0W.
• Full level of function available from -55°C to + 125°C
• Available in 48-Lead 7mm x 7mm MLP Quad
package and 44-Lead PLCC package
General Description
The IXA531 is a monolithic, 3-phase, MOSFET/IGBT
gate driver consisting of three independent, high and low
side output channels. In addition to the six inputs,
which are CMOS/TTL Compatible, for the three
corresponding high side and three low side outputs,
there are dedicated lines for FAULT, ENABLE and
RESET. Overload/Short Circuit protection is
implemented by sensing a voltage across a shunt or low
value resistor which carries load current. Upon
Overload/Short Circuit detection, all outputs are
disabled. Likewise ENABLE (EN) pin, when LOW under
abnormal operating conditions, affords soft shut down of
outputs. FAULT(FLT) signal‘s status indicates that shut
down has occurred either due to Overload/Short Circuit
in driven MOSFET/IGBT or Under Voltage on VCL.
Clearing of FAULT (FLT) signal and restoration of
normal operation ensue automatically after a
programmed delay using an RC Network wired at RST
(RESET) pin. Matched propagation delays ensure
proper operation even at very high switching
frequencies. Absence of cross conduction in output
stages removes possibility of shoot through in driven
power MOSFETs or IGBTs.
Part Package
IXA531S10 48L - SSLGA
IXA531L4 44L - PLCC
Ordering Information
1
2
IXA531
SYMBOL FUNCTION DESCRIPTION
_______
HIN1,2,3 HS Input High side Input signal, TTL or CMOS compatible; HGO1,2,3 out of phase
_______
LIN1,2,3 LS Input Low side Input signal, TTL or CMOS compatible; LGO1,2,3 out of phase
EN Enable Chip enable. When driven high, both outputs go low.
DG Ground Logic Reference Ground
VCH1,2,3 Supply Voltage High Side Power Supply
HGO1,2,3 Output High side driver output
HS1,2,3 Return High side voltage return
VCL Supply Voltage Low side and Logic fixed power supply. This power supply provides power for
all outputs. Voltage range is from 8.0 to 35V.
LGO1,2,3 Output Low side driver output
LS Low side return Low side driver return
___
FLT Fault Indicates Low-Side under voltage or Over Current Trip
ITRP Trip Input for over current shutdown
RST Delay after trip Externally connected RC network decide FAULT CLEAR delay.
Fig. 1. Single Phase Application
Pin Description And Configuration
HIN2 HS2 HIN3 VCH3
HG03
LIN2 HG02 LGO2 LIN3 HS3
LGO3
DG
ITRP
RST
LIN1
VCL
HIN1
FLT
VCL
HIN1
LIN1
FLT
EN EN HS1
LGO1
LS
up to + 650 V
VCH1
HGO1 To
Load
VCH2
UVSEL
IXA531
3
IXA531
VCL VCL
HIN1 HIN1
LIN1 LIN1
FLT FLT
EN EN
HIN2 HIN2 HIN3 HIN3
LIN2 LIN2 LIN3 LIN3
RST
ITRP
DG
GND
VCH1
HGO1
HS1
UVSEL
LGO1
LS
VCH2 VCH3
HGO2 HGO3
HS2 HS3
LGO2 LGO3
up to + 650 V
IXA531S10
PH1
To Load
PH2 PH3
To Load To Load
Fig. 2. 3-Phase Application for the IXA531.
4
IXA531
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to LS. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions
Symbol Definition Min. Max. Units
VCH1,2,3 High side floating supply voltage VHS1,2,3 + 12 VHS1,2,3 + 35 V
VHS1,2,3 High side floating supply offset voltage - 200 650 V
VHGO1,2,3 High side floating output voltage VHS1,2,3 VCH1,2,3 V
VLGO1,2,3 Low side output voltage 0 VCL V
VCL Low side and logic fixed supply voltage 12 35 V
VDG Logic Supply offset voltage VLS - 0.3 VLS + 0.3 V
VFLT FAULT output voltage VDG VCL V
VRST RST input voltage VDG VCL V
VITRP ITRP input voltage VDG VCL V
_______ _______
VIN Logic input voltage HIN1,2,3, LIN1,2,3, EN VDG or VLS VCL V
TA Ambient temperature -40 125 OC
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute
values referenced to LS. The VHS offset rating is tested with all supplies baised at 15V differential.
Symbol Definition Min. Max. Units
VCH High side floating supply voltage , (VCH1,2,3) -200 650 V
VHS High side floating supply offset voltage , (VHS1,2,3)V
CH1,2,3 - 35 VCH1,2,3 + 0.3 V
VHGO High side floating output voltage , (VHGO1,2,3)V
HS1,2,3– 0.3 VCH1,2,3 + 0.3 V
VCL Low side and logic fixed supply voltage 8.0 35 V
VDG Logic Supply offset voltage VLS - 0.7 VLS + 0.7 V
VLGO Low side output voltage - 0.3 VCL + 0.3 V
_______ _______ Lower of
VIN Input voltage HIN1,2,3, LIN1,2,3, ITRP, RST , EN VDG – 0.3 (VDG + 35) or V
(VCL + 0.3)
VFLT FAULT output voltage VDG – 0.3 VCL + 0.3 V
dV/dt Allowable offset voltage slew ratelew rate 50 V/ns
PDPackage power dissipation@ TA ≤ +25OC 2.0 W
RthJA Thermal resistance, junction to ambient 63 K/W
T
JJunction temperature 125 OC
TSStorage temperature -55 150 OC
TLLead temperature (soldering, 10 seconds) 300 OC
5
IXA531
Static Electrical Characteristics
VBIAS (VCL, VCH1,2,3) = 15V unless otherwise specified. The VIN, VTH and IIN parameters are referenced to DG and are
applicable to all six channels . The VO and IO parameters are referenced to LS and VHS1,2,3 and are applicable to the
respective output leads: HGO1,2,3
and LGO1,2,3.
Symbol Definition Min. Typ. Max. Units Test Conditions
VINL Logic “0” input voltage HIN1,2,3; LIN1,2,3 0.8 V
VINH Logic “1” input voltage HIN1,2,3; LIN1,2,3 3.0 V
VEN,TH+ EN positve going threshold 3.0 V
VEN,TH - EN negative going threshold 0.8 V
VITRP, TH+ ITRP positve going threshold 0.37 0.46 0.55 V
VITRP, HYS ITRP input hysteresis .07 V
VRST,TH+ RST positive going threshold 8 V
VRST, HYS RST input hysteresis 3 V
VOH1,2,3 High level output voltage, VCH - VHGO or VCL- VLGO 0.9 1.4 V I0=20mA
VOL1,2,3 Low level output voltage, VHGO or VLGO 0.4 0.6 V I0=20mA
VCLUV+ VCL supply under-voltage positive going threshold 10.6 11.1 11.6 V
VCHUV+ VCH
supply under-voltage positive going threshold 10.6 11.1 11.6 V
VCLUV- VCL
supply under-voltage negaitive going threshold 10.4 10.9 11.4 V
VCHUV- VCH
supply under-voltage negaitive going threshold 10.4 10.9 11.4 V
VCLUVH VCL
supply under-voltage lockout hysteresis 0.2 V
VCHUVH VCH supply under-voltage lockout hysteresis 0.2 V
ILK Offset supply leakage current 50 μAV
CH1,2,3=
VHS1,2,3=600 V
IQVCH Quiescent VCH supply current 70 120 μAV
IN=0V or 5V
IQVCL Quiescent VCL supply current 1.6 2.3 mA VIN=0V or 5V
VIN Input clamp voltage (HIN,LIN,ITRP,EN) 4.9 V IIN = 100μA
ILIN+or
IIN+ Logic “1“ Input bias current for LIN1,2,3 200 300 μAV
LIN = 5V
ILIN-or
IIN- Logic “0“ Input bias current for LIN1,2,3 100 220 μAV
LIN = 0V
IHIN+or
IIN+ Logic “1“ Input bias current for HIN1,2,3 200 300 μAV
HIN = 5V
IHIN-or
IIN- Logic “0“ Input bias current for HIN1,2,3 100 220 μAV
HIN = 0V
IITRP+ “high” ITRP input bias current 30 100 μAV
ITRP = 5V
IITRP- “low” ITRP input bias current 0 1 μAV
ITRP = 0V
IEN+ “high” ENABLE input bias current 30 100 μAV
EN = 5V
IEN- “low” ENABLE input bias current 0 1 μAV
EN = 0V
IRST RST input bias current 0 1 μAV
RST = 0Vor 15V
IGO+ Output high short circuit pulsed current 600 mA V0=0V,PW <10 μs
IGO- Output low short circuit pulsed current 600 mA V0=15V,PW<10μs
RON, RST RST low on resistance 50 100 Ω
RON, FLT FLT low on resistance 50 100 Ω
6
IXA531
Dynamic Electrical Characteristics
VCL = VCH = VBIAS = 15V, VHS1,2,3 = VDG = VLS, TA = 25°C and CL = 1000pF unless otherwise specified.
Notes: A Cross Conduction logic prevents LGO1,2,3 and HGO1,2,3 for each channel from turning on
simultaneously.
1. UVCL is not latched, when VCL>UVCL, FAULT returns to high impedance.
2. When ITRP < VITRP, FAULT returns to high-impedance after RST pin becomes greater then 8V
(@VCL= 15V).
Symbol Definition Min. Typ. Max. Units Test Conds.
ton Turn-on propagation delay 300 425 550 nS VIN=0V & 5V
toff Turn-off propagation delay 250 400 550 nS VIN=0V & 5V
trTurn-on rise time 125 190 nS ----
tfTurn-on fall time 50 75 nS ----
tEN ENABLE low to output shutdown 300 450 600 nS VIN , VEN = 0 V
propagation delay or 5 V
tITRP ITRP to output shutdown propagation delay 500 750 1000 nS VITRP=5V
tbl ITRP blanking time 100 150 nS VIN=0V or 5V
VITRP = 5V
tFLT ITRP to FAULT propagation delay 400 600 800 nS V IN = 0V or 5V
VITRP = 5V
tFILIN Input filter time (HIN, LIN, EN) 100 200 nS VIN = 0V & 5V
tFLCLR FAULT clear time RST=2meg, C=1nF 1.3 1.65 2 mS VIN = 0V or 5V
VITRP=0V
DT Dead time 220 290 360 nS VIN = 0V & 5V
MT Matching delay ON and OFF 40 75 nS External Dead
MDT Matching delay, max (ton , toff) - min (ton , toff)25 70 nS Time
(ton,toff are applicable to all 3 channels) >400nsec
PM Output pulse width matching, PWMIN-PWMOUT 40 75 nS
VCL VCH ITRP ENABLE FAULT LGO1,2,3 HGO1,2,3
<UVCL X X X 0(note 1) 0 0
15V <UVCH 0V 15V high imp LIN1,2,3 0
15V 15V 0V 15V high imp LIN1,2,3 HIN1,2,3
15V 15V >VITRP 15V 0 (note 2) 0 0
15V 15V 0V 0V high imp 0 0
7
IXA531
LO1,2,3
HO1,2,3
FLT
RST
ITRP
EN
HIN1,2,3
LIN1,2,3
HIN1,2,3
Fi
g
. (5) Timin
g
Dia
g
ram
50%
EN
EN
t
LO1,2,3
HO1,2,3
90%
Fi
g
. (6) Enable Timin
g
Waveforms
t
90%
f
t
off
50%
PWM
IN
50%
50%
OUT
90%
PWM
50%
t
on
t
r
10%10%
LO1,2,3
HO1,2,3
LIN1,2,3
HIN1,2,3
HIN1,2,3
LIN1,2,3
Fig. 3. Timing Diagram
Fig. 4. ENABLE Timing Waveforms
Fig. 5. Switching Time Definitions
8
IXA531
FLT
Fi
g
. (10) Input Filter Dia
g
ram
low
Fig. (9) ITRP / RST Waveforms
FILIN
high
HO / LO
HIN / LIN
on off
t
on
FLT
OUTPUT
t
ITRP
t
50%
90%
off on off
FILIN
t
FLCLR
t
50%
ITRP
50%
RST
50%
HO1,2,3
LO1,2,3
Fi
g
. (8) Deadtime Waveforms
DT
50%
RST,th+
V
DT
50%
50%
HIN1,2,3
LIN1,2,3
HIN1,2,3
LIN1,2,3
50%
50%
Fig. 6. Deadtime Waveforms
Fig. 7. ITRP / RST Waveforms
Fig. 8. ENABLE Timing Waveforms
9
IXA531
Fig. (9) IXA531 Block Diagram
1
RST
600mA
Gate
Driver
Gate
600mA
Driver
Gate
600mA
Driver
Isolated Hi
g
h Side
Isolated Hi
g
h Side
Isolated Hi
g
h Side
HS3
HGO3
VCH3
HS2
HGO2
VCH2
HS1
HGO1
VCH1
iO2
h02
en2
lin1
en1
hin1
iO3
h03
lin3
en3
hin3
lin2
hin2
iO1
h01
VCL
VCL
VCL
VCL
VCL
VCL
VCH
VCL
600mA
Driver
Gate
HS
UVCC
Detect
In
Low to High
Isolation
Out
Rst
VCH
VCL
600mA
Driver
Gate
HS
UVCC
Detect
In
In
Low to High
Isolation
Out
Rst
VCL
CMOS
to VCL
Level Shift , &
Logic
Conduction
Anti-Cross
5V LOGIC
VCL
5V LOGIC
Level Shift , &
CMOS
to VCL
Logic
Conduction
Anti-Cross
VCH
VCL
600mA
Driver
Gate
HS
UVCC
Detect
In
In
Low to High
Isolation
Out
Rst
VCL
5V LOGIC
Anti-Cross
Level Shift , &
to VCL CMOS
Logic
Conduction
Isolated High Side
Isolated High Side
Isolated High Side
HS3
HGO3
VCH3
HS2
HGO2
VCH2
HS1
HGO1
VCH1
iO2
h02
en2
lin1
en1
hin1
iO3
h03
lin3
en3
hin3
lin2
hin2
iO1
h01
VCL
VCL
VCL
VCL
VCL
VCL
VCH
VCL
600mA
Driver
Gate
HS
UVCC
Detect
In
Low to High
Isolation
Out
Rst
VCH
VCL
600mA
Driver
Gate
HS
UVCC
Detect
In
Low to High
Isolation
Out
Rst
VCL
CMOS
to VCL
Level Shift , &
Logic
Conduction
Anti-Cross
5V LOGIC
VCL
5V LOGIC
Level Shift , &
CMOS
to VCL
Logic
Conduction
Anti-Cross
VCH
VCL
600mA
Driver
Gate
HS
UVCC
Detect
In
In
Low to High
Isolation
Out
Rst
VCL
5V LOGIC
Anti-Cross
Level Shift , &
to VCL CMOS
Logic
Conduction
HIN1
LIN1
HIN2
LIN2
HIN3
LIN3
EN
ITRP
FLT
DG
S
RQB
Set
Dominant
Latch
+
-
N
N
VCL
OUT
UVCL
Detect
VCL
LGO1
LGO2
LGO3
In
In
In
In
In
In Out
Out
Out
Low to High
Equalizer
Delay
Low to High
Delay
Equalizer
Low to High
Delay
Equalizer
LS
-
0.5 V
+
VCLVCL
50K
VCLVCL
50K
VCLVCL
750K
750K
750K
750K
750K
750K
10
IXA531
0.276±0.002 [7.00±0.05]
0.276±0.002 [7.00±0.05]
0.039±0.002 [1.00±0.05]
0.030±0.001 [0.75±0.03]
0.009±0.001 [0.23±0.03]
0.015±0.001 [0.38±0.03]
0.020 [0.50]
Fig. 10. Pin Diagram for the IXA531S10 48-Lead MLP Quad Package
Fig. 11. Pin Diagram for the IXA531L4 44-Lead PLCC package
NC
39
7
NC
21
RST 17
DG
NC
NC
1918 20
FLT
14
ITRP
EN
NC
16
15
NC 13
12
LIN3
NC 11
10
LIN1
LIN2 9
8
28
NC
NC
LS
LGO2
LGO3
22 23 24
NC
LGO1
NC
2625 27
29 HS3
IXA531S10
VCH3
HGO3
NC
32
31
30
33
34
NC
NC
HGO2
VCH2
35
36
HS2
38
37
NC
HIN2
56 4
HIN3
HIN1
NC
40
32144
VCL
NC
NC
NC
42
43 41
HGO1
VCH1
HS1
IXA531L4
LS
11
IXA531
Fig. 12. 44-Lead PLCC Outline Diagram
IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
e-mail: sales@ixys.net
www.ixys.com
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: marcom@ixys.de
