VFC110
PDS-861B
®
High-Frequency
VOLTAGE-TO-FREQUENCY CONVERTER
APPLICATIONS
●INTEGRATING A/D CONVERSION
●PROCESS CONTROL
●VOLTAGE ISOLATION
●VOLTAGE-CONTROLLED OSCILLATOR
●FM TELEMETRY
FEATURES
●HIGH-FREQUENCY OPERATION:
4MHz FS max
●EXCELLENT LINEARITY:
±0.02% typ at 2MHz
●PRECISION 5V REFERENCE
●DISABLE PIN
●LOW JITTER
DESCRIPTION
The VFC110 voltage-to-frequency converter is a third-
generation VFC offering improved features and per-
formance. These include higher frequency operation,
an on-board precision 5V reference and a Disable
function.
The precision 5V reference can be used for offsetting
the VFC transfer function, as well as exciting trans-
ducers or bridges. The Enable pin allows several
VFCs’ outputs to be paralleled, multiplexed, or simply
to shut off the VFC. The open-collector frequency
output is TTL/CMOS-compatible. The output may be
isolated by using an opto-coupler or transformer.
Internal input resistor, one-shot and integrator capaci-
tors simplify applications circuits. These components
are trimmed for a full-scale output frequency of 4MHz
at 10V input. No additional components are required
for many applications.
The VFC110 is packaged in plastic and ceramic
14-pin DIPs. Industrial and military temperature range
gradeouts are available.
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
2
14
Input Common
IN
V
112
I
IN
V
OUT
11
Comparator
One-Shot
V
REF
–V
S
Analog Ground
413
5V
3C
OS
6
8
Digital Ground
OUT
f
10
+V
S
7
Enable
5
© 1988 Burr-Brown Corporation PDS-861B Printed in U.S.A. October, 1993
SBVS021
2
®
VFC110
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
SPECIFICATIONS
At TA = +25°C and VS = ±15V, unless otherwise noted.
VFC110BG VFC110AG/SG/AP
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
VOLTAGE-TO-FREQUENCY OPERATION
Nonlinearity(1): fFS = 100kHz COS = 2.2nF, RIN = 44kΩ0.005 0.01 0.01 0.05 %FS
fFS = 1MHz COS = 150pF, RIN = 40kΩ0.01 0.05 0.1 %FS
fFS = 2MHz COS = 56pF, RIN = 34kΩ0.02 * %FS
fFS = 4MHz COS = (Int), RIN = (Int) 1 * %FS
Gain Error, f = 1MHz COS = 150pF, RIN = 40kΩ5*%
Gain Drift, f = 1MHz Specified Temp Range 50 100 ppm/°C
Relative to VREF Specified Temp Range 50 100 ppm/°C
PSRR VS = ±8V to ±18V 0.05 0.1 %/V
INPUT
Full Scale Input Current 250 500 * * µA
IB– (Inverting Input) 15 60 20 100 nA
IB+ (Non-Inverting Input) 250 * nA
VOS 33mV
V
OS Drift Specified Temp Range 35 * µV/°C
INTEGRATOR AMPLIFIER OUTPUT
Output Voltage Range RL = 2kΩ–0.2 +VS – 4 * * V
Output Current Drive 5 20 * * mA
Capacitive Load No Oscillations 10 10 nF
COMPARATOR INPUT
IB (Input Bias Current) –5 * µA
Trigger Voltage ±50 * mV
Input Voltage Range –5 +VS**V
OPEN COLLECTOR OUTPUT
VO Low 0.4 * V
ILEAKAGE 0.1 1 * * µA
Fall Time 25 * ns
Delay to Rise 25 * ns
Settling Time To Specified Linearity for a One Pulse of New Frequency Plus 1µs
Full-Scale Input Step
REFERENCE VOLTAGE
Voltage 4.97 5 5.03 * * * V
Voltage Drift 20 50 ppm/°C
Load Regulation IO = 0 to 10mA 2 10 * * mV
PSRR VS = ±8V to ±18V 5 * mV/V
Current Limit Short Circuit 15 20 * mA
ENABLE INPUT
VHIGH (fOUT Enabled) Specified Temp Range 2 * V
VLOW (fOUT Disabled) Specified Temp Range 0.4 * V
IHIGH 0.1 * µA
ILOW 1*µA
POWER SUPPLY
Voltage, ±VS±8±15 ±18 * * * V
Current 13 16 * * mA
TEMPERATURE RANGE
Specified
AG, BG, AP –25 +85 * * °C
SG –55 +125 °C
Storage
AG, BG, SG –65 +150 * * °C
AP –40 +125 * * °C
* Same specifications as VFC110BG.
NOTE: (1) Nonlinearity measured from 1V to 10V input.
3
®
VFC110
TEMPERATURE
PRODUCT PACKAGE RANGE
VFC110AG Ceramic DIP –25°C to +85°C
VFC110BG Ceramic DIP –25°C to +85°C
VFC110SG Ceramic DIP –55°C to +125°C
VFC110AP Plastic DIP –25°C to +85°C
Input Common
Analog Common
V
Comparator In
+V
NC
f
Out
Enable
Digital Ground
1
2
3
4
5
6
7
14
13
12
11
10
9
8
S
IN
IN
I
V
REF
+5V
S
–V
OS
C
OUT
OUT
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Top View DIP Power Supply Voltages (+VS to –VS) ................................................40V
fOUT Sink Current............................................................................50mA
Comparator In Voltage .......................................................... –5V to +VS
Enable Input........................................................................... +VS to –VS
Integrator Common-Mode Voltage.................................. –1.5V to +1.5V
Integrator Differential Input Voltage ................................ +0.5V to –0.5V
Integrator Out (short-circuit)..................................................... Indefinite
VREF Out (short-circuit)..............................................................Indefinite
Operating Temperature Range
G Package ................................................................ –55°C to +125°C
P Package................................................................... –40°C to +85°C
Storage Temperature
G Package ................................................................ –60°C to +150°C
P Package................................................................. –40°C to +125°C
Lead Temperature (soldering, 10s)............................................. +300°C
PACKAGE INFORMATION
PACKAGE DRAWING
PRODUCT PACKAGE NUMBER(1)
VFC110AG 14-Pin Ceramic DIP 169
VFC110BG 14-Pin Ceramic DIP 169
VFC110SG 14-Pin Ceramic DIP 169
VFC110AP 14-Pin Plastic DIP 010
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ORDERING INFORMATION
4
®
VFC110
FREQUENCY COUNT REPEATABILITY
vs COUNTER GATE TIME
1ms Time
0.001
Frequency Repeatability (%)
0.0001
0.0002
0.0004
0.0006
0.0008
10ms 100ms 1s
17
Repeatability (Bits)
18
19
f
FS
= 1MHz
f
FS
= 100kHz
JITTER vs FULL SCALE FREQUENCY
10k Full Scale Frequency (Hz)
500
400
300
200
100
0
Jitter (ppm)
100k 1M 10M
TYPICAL FULL SCALE GAIN DRIFT
vs FULL SCALE FREQUENCY
10k Full Scale Frequency (Hz)
1000
100
10
Full Scale Frequency (ppm/°C)
100k 1M 10M
A Grade,
S Grade B Grade
REFERENCE VOLTAGE
vs REFERENCE LOAD CURRENT
0Output Current (mA)
5.01
5
4.99
4.98
4.97
4.96
V
REF
(V)
246810121416182022
Short Circuit
Current Limit
QUIESCENT CURRENT vs TEMPERATURE
–50 Temperature (°C)
18
16
14
12
10
8
6
4
2
0
Quiescent Current (mA)
I
Q
+
–25 0 25 50 75 100 125
I
Q
–
FULL-SCALE FREQUENCY
vs EXTERNAL ONE-SHOT CAPACITOR
10pF External One-Shot Capacitor
100pF 1nF 10nF 100nF
10M
1M
100k
10k
Full Scale Frequency (Hz)
R
IN
= 40kΩ
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±15V, unless otherwise noted.
This graph describes the low frequency stability of the VFC110:
the ratio of the 1σ point of the distribution of 100 runs (where
each mean frequency came from 1000 readings for each gate
time) to the overall mean frequency.
Jitter is the ratio of the 1σ value of the distribution of the period
(1/fOUT, max) to the mean of the period.
5
®
VFC110
NONLINEARITY vs FULL SCALE FREQUENCY
10 Full Scale Frequency (Hz)
1
0.1
0.01
0.001
Typical Nonlinearity (% of FSR)
4
10
5
10
6
10
7
NONLINEARITY vs INPUT VOLTAGE
0Input Voltage (V)
0.02
0.01
0
–0.01
–0.02
1MHz FS Linearity Error (% of FSR)
12345678910
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
4MHz FS Linearity Error (% of FSR)
f
FS
= 4MHz
f
FS
= 1MHz
OPERATION
Figure 1 shows the connections required for operation at a
full-scale output frequency of 4MHz. Only power supply
bypass capacitors and an output pull-up resistor, RPU, are
required for this mode of operation. A 0V to 10V input
voltage produces a 0Hz to 4MHz output frequency. The
internal input resistor, one-shot and integrator capacitors set
the full-scale output frequency. The input is applied to the
summing junction of the integrator amplifier through the
25kΩ internal input resistor. Pin 14 (the non-inverting ampli-
fier input) should be referred directly to the negative side of
VIN. The common-mode range of the integrating amplifier is
limited to approximately –1V to +1V referred to analog
ground. This allows the non-inverting input to Kelvin-sense
the common connection of VIN, easily accommodating any
FIGURE 1. 4MHz Full-Scale Operation.
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
ground-drop errors. The input impedance loading VIN is
equal to the input resistor—approximately 25kΩ.
OPERATION AT LOWER FREQUENCIES
The VFC110 can be operated at lower frequencies simply by
limiting the input voltage to less than the nominal 10V full-
scale input. To maintain a 10V FS input and highest accu-
racy, however, external components are required (see Table
I). Small adjustments may be required in the nominal values
indicated. Integrator and one-shot capacitors are added in
parallel to internal capacitors. Figure 2 shows the connec-
tions required for 100kHz full scale output. The one-shot
capacitor, COS, should be connected to logic ground. The
one-shot connection (pin 6) is not short-circuit protected.
Short-circuits to ground may damage the device.
2
14
IN
V
11211
One-Shot
V
REF
–V
S
Analog Ground
413
NC
36
8
Logic Ground
OUT
f
10
+V
S
7
NC
5
NC
50pF*
NC
PU
R
680Ω
–15V
+15V V
L
+5V
0 to 4MHz
25kΩ*
0 to
+10V
* Nominal Values (±20%)
6
®
VFC110
The integrator capacitor’s value does not directly affect the
output frequency, but determines the magnitude of the volt-
age swing on the integrator’s output. Using a CINT equal to
COS provides an integrator output swing from 0V to approxi-
mately 1.5V.
COMPONENT SELECTION
Selection of the external resistor and capacitor type is impor-
tant. Temperature drift of an external input resistor and one-
shot capacitor will affect temperature stability of the output
frequency. NPO ceramic capacitors will normally produce
the best results. Silver-mica types will result in slightly
higher drift, but may be adequate in many applications. A
low temperature coefficient film resistor should be used for
RIN.
The integrator capacitor serves as a “charge bucket,” where
charge is accumulated from the input, VIN, and that charge is
drained during the one-shot period. While the size of the
bucket (capacitor value) is not critical, it must not leak.
Capacitor leakage or dielectric absorption can affect the
linearity and offset of the transfer function. High-quality
ceramic capacitors can be used for values less than 0.01µF.
Use caution with higher value ceramic capacitors. High-k
ceramic capacitors may have voltage nonlinearities which
can degrade overall linearity. Polystyrene, polycarbonate, or
mylar film capacitors are superior for high values.
PULL-UP RESISTOR
The VFC110’s frequency output is an open-collector transis-
tor. A pull-up resistor should be connected from fOUT to the
logic supply voltage, +VL. The output transistor is On during
the one-shot period, causing the output to be a logic Low.
The current flowing in this resistor should be limited to 8mA
to assure a 0.4V maximum logic Low. The value chosen for
the pull-up resistor may depend on the full-scale frequency
and capacitance on the output line. Excessive capacitance on
fOUT will cause a slow, rounded rising edge at the end of an
output pulse. This effect can be minimized by using a pull-
up resistor which sets the output current to its maximum of
8mA. The logic power supply can be any positive voltage up
to +VS.
ENABLE PIN
If left unconnected, the Enable input will assume a logic
High level, enabling operation. Alternatively, the Enable
input may be connected directly to +VS. Since an internal
pull-up current is included, the Enable input may be driven
by an open-collector logic signal.
A logic Low at the Enable input causes output pulses to
cease. This is accomplished by interrupting the signal path
through the one-shot circuitry. While disabled, all circuitry
remains active and quiescent current is unchanged. Since no
reset current pulses can occur while disabled, any positive
input voltage will cause the integrator op amp to ramp
negatively and saturate at its most negative output swing of
approximately –0.7V.
FULL-SCALE
FREQUENCY, fFS RIN COS CINT
4MHz * * *
2MHz 34kΩ56pF *
1MHz 40kΩ150pF *
500kHz 58kΩ330pF 2nF
100kHz 44kΩ2.2nF 10nF
50kHz 88kΩ2.2nF 0.1µF
10kHz 44kΩ22nF 0.1µF
* Use internal component only.
The values given were determined empirically to give the optimal perform-
ance, taking into consideration tradeoffs between linearity and jitter for each
given full scale frequency of operation. The capacitors listed were chosen
from standard values of NPO ceramic type capacitors while the resistor
values were rounded off. Larger CINT values may improve linearity, but may
also increase frequency noise.
EXTERNAL COMPONENTS
TABLE I. Component Selection Table.
FIGURE 2. 100kHz Full-Scale Operation.
2
IN
V
11211
One-Shot
V
REF
–V
S
413
NC
3 6
8
OUT
f
10
+V
S
7
5
PU
R
+V
L
0 to 100kHz
C
2.2nF
OS
High = Enable
Low = Disable
10nF
C
INT
0 to +10V
Gain Trim
5kΩ44kΩ
R
IN
NC
14
7
®
VFC110
reset current. The equation of current balance is
IIN = IREF • Duty Cycle
VIN/RIN = IREF • fOUT • TO
where TO is the one-shot period and fOUT is the oscillation
frequency.
Integrator
Output
(Pin 12)
0V
f
OUT
1/f
OUT
T
OS
Effect of
Smaller C
INT
When the Enable input receives a logic High (greater than
+2V), a reset current cycle is initiated (causing fOUT to go
Low). The integrator ramps positively and normal operation
is established. The time required for the output frequency to
stabilize is equal to approximately one cycle of the final
output frequency plus 1µs.
Using the Enable input, several VFCs’ outputs can be con-
nected to a single output line. All disabled VFCs will have a
high output impedance; one active VFC can then transmit on
the output line. Since the disabled VFCs are not oscillating,
they cannot interfere or “lock” with the operating VFC.
Locking can occur when one VFC operates at nearly the
same frequency as—or a multiple of—a nearby VFC.
Coupling between the two may cause them to lock to the
same or exact multiple frequency. It then takes a small
incremental input voltage change to unlock them. Locking
cannot occur when unneeded VFCs are disabled.
REFERENCE VOLTAGE
The VREF output is useful for offsetting the transfer function
and exciting sensors. Figure 3 shows VREF used to offset the
transfer function of the VFC110 to achieve a bipolar input
voltage range. Sub-surface zener reference circuitry is used
for low noise and excellent temperature drift. Output current
is specified to 10mA and current-limited to approximately
20mA. Excessive or variable loads on VREF can decrease
frequency stability due to internal heating.
MEASURING THE OUTPUT FREQUENCY
To complete an integrating A/D conversion, the output
frequency of the VFC110 must be counted. Simple fre-
quency counting is accomplished by counting output pulses
for a reference time (usually derived from a crystal oscilla-
PRINCIPLE OF OPERATION
The VFC110 uses a charge-balance technique to achieve
high accuracy. The heart of this technique is an analog
integrator formed by the integrator op amp, feedback
capacitor CINT, and input resistor RIN. The integrator’s
output voltage is proportional to the charge stored in CINT.
An input voltage develops an input current of VIN/RIN,
which is forced to flow through CINT. This current charges
CINT, causing the integrator output voltage to ramp nega-
tively.
When the output of the integrator ramps to 0V, the
comparator trips, triggering the one-shot. This connects
the reference current, IREF, to the integrator input during
the one-shot period, TOS. This switched current causes the
integrator output to ramp positively until the one-shot
period ends. Then the cycle starts again.
The oscillation is regulated by the balance of current (or
charge) between the input current and the time-averaged
FIGURE 3. Offsetting the Frequency Output.
2
NC
IN
V
11211
One-Shot
V
REF
413
5V
3 6
8
OUT
f
7
5
PU
R
C
OS
R
1
14
NC
+5V+15V
10
–15V
R
2
8
®
VFC110
tor). This can be implemented with counter/timer peripheral
chips available for many popular microprocessor families.
Many micro-controllers have counter inputs that can be
programmed for frequency measurement.
Since fOUT is an open-collector device, the negative-going
edge provides the fastest logic transition. Clocking the counter
on the falling edge will provide the best results in noisy
environments.
Frequency can also be measured by accurately timing the
period of one or more cycles of the VFC’s output. Frequency
must then be computed since it is inversely proportional to
the measured period. This measurement technique can pro-
vide higher measurement resolution in short conversion
times. It is the method used in most high-performance
laboratory frequency counters. It is usually necessary to
offset the transfer function so 0V input causes a finite
frequency out. Otherwise the output period (and therefore the
conversion time) approaches infinity.
FREQUENCY NOISE
Frequency noise (small random variation in the output
frequency) limits the useful resolution of fast frequency
measurement techniques. Long measurement time averages
the effect of frequency noise and achieves the maximum
useful resolution. The VFC110 is designed to minimize
frequency noise and allows improved useful resolution with
short measurement times. The typical curve “Frequency
Count Repeatability vs Counter Gate Time” shows the effect
of noise as the counter gate time is varied. It shows the one
standard deviation (1σ) count variation (as a percentage of
FS counts) versus counter gate time.
FREQUENCY-TO-VOLTAGE CONVERSION
The VFC110 can also be connected as a frequency-to-
voltage converter (Figure 4). Input frequency pulses are
applied to the comparator input. A negative-going pulse
crossing 0V initiates a reference current pulse which is
averaged by the integrator op amp. The values of the one-
shot capacitor and feedback resistor (same as RIN) are deter-
mined with Table I. The input frequency pulse must not
remain negative for longer than the duration of the one-shot
period. Figure 4 shows the required timing to assure this. If
the negative-going input frequency pulses are longer in
duration, the capacitive coupling circuit shown can be used.
Level shift or capacitive coupling circuitry should not pro-
vide pulses which go lower than –5V or damage to the
comparator input may occur.
This frequency-to-voltage converter operates by averaging
(filtering) the reference current pulses triggered on every
falling edge at the frequency input. Voltage ripple with a
frequency equal to the input will be present in the output
voltage. The magnitude of this ripple voltage is inversely
proportional to the integrator capacitor. The ripple can be
made arbitrarily small with a large capacitor, but at the
sacrifice of settling time. The R-C time constant of CINT and
RIN determine the settling behavior. A better compromise
between output ripple and settling time can be achieved by
adding a low-pass filter following the voltage output.
FIGURE 4. Frequency-to-Voltage Conversion.
2
11211
One-Shot
V
REF
413
NC
3 6
7
5
C
OS
14
NC
10
C
INT
R
IN
V
OUT
= 0 to 10V
NC
–V
S
8NC
+V
S
2.2kΩ
4.7kΩ
–V
S
1kΩ
f
IN
f
IN
1nF
12kΩ
+V
S
Long Pulses OK
TTL
1/10f
FS
max
PACKAGING INFORMATION
ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY
VFC110AG OBSOLETE CDIP SB JD 14
VFC110AG2 OBSOLETE CDIP SB JD 14
VFC110AP ACTIVE PDIP N 14 25
VFC110BG OBSOLETE CDIP SB JD 14
VFC110BG1 OBSOLETE CDIP SB JD 14
VFC110SG OBSOLETE CDIP SB JD 14
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 3-Oct-2003
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