TM
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FEATURES
APPLICATIONS
DESCRIPTION
PVDD − Supply Voltage − V
0
10
20
30
40
50
60
70
80
90
100
110
120
0 4 8 12 16 20 24 28 32
PO − Output Power − W
8 Ω
4 Ω
TC = 75°C
THD+N @ 10%
6 Ω
G002
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
STEREO DIGITAL AMPLIFIER POWER STAGE
requires a simple passive LC demodulation filter todeliver high-quality, high-efficiency audio amplification•2×100 W at 10% THD+N Into 4- ΩBTL
(1)
with proven EMI compliance. This device requires two•2×80 W at 10% THD+N Into 6- ΩBTL
power supplies, at 12 V for GVDD and VDD, and at32 V for PVDD. The TAS5142 does not require•2×65 W at 10% THD+N Into 8- ΩBTL
power-up sequencing due to internal power-on reset.•4×40 W at 10% THD+N Into 3- ΩSE
The efficiency of this digital amplifier is greater than•4×30 W at 10% THD+N Into 4- ΩSE
90% into 6 Ω, which enables the use of smaller•1×160 W at 10% THD+N Into 3- ΩPBTL
power supplies and heatsinks.•1×200 W at 10% THD+N Into 2- ΩPBTL
(1)
The TAS5142 has an innovative protection systemintegrated on-chip, safeguarding the device against a•>100 dB SNR (A-Weighted)
wide range of fault conditions that could damage the•<0.1% THD+N at 1 W
system. These safeguards are short-circuit protection,•Two Thermally Enhanced Package Options:
overcurrent protection, undervoltage protection, and– DKD (36-pin PSOP3)
overtemperature protection. The TAS5142 has a newproprietary current-limiting circuit that reduces the– DDV (44-pin HTSSOP)
possibility of device shutdown during high-level music•High-Efficiency Power Stage (>90%) With
transients. A new programmable overcurrent detector140-m ΩOutput MOSFETs
allows the use of lower-cost inductors in the•Power-On Reset for Protection on Power Up
demodulation output filter.Without Any Power-Supply Sequencing
BTL OUTPUT POWER vs SUPPLY VOLTAGE•Integrated Self-Protection Circuits IncludingUndervoltage, Overtemperature, Overload,Short Circuit•Error Reporting•EMI Compliant When Used WithRecommended System Design•Intelligent Gate Drive
•Mini/Micro Audio System•DVD Receiver•Home Theater
The TAS5142 is a third-generation, high-perform-ance, integrated stereo digital amplifier power stagewith an improved protection system. The TAS5142 iscapable of driving a 4- Ωbridge-tied load (BTL) at up
(1) It is not recommended to drive 200 W (total power) into theto 100 W per channel with low integrated noise at the
DDV package continuously. For multichannel systems thatoutput, low THD+N performance, and low idle power
require two channels to be driven at full power with thedissipation.
DDV package option, it is recommended to design thesystem so that the two channels are in two separateA low-cost, high-fidelity audio system can be built
devices.using a TI chipset, comprising a modulator (e.g.,
PurePath Digital™TAS5508) and the TAS5142. This system only
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PurePath Digital, PowerPad are trademarks of Texas Instruments.All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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GENERAL INFORMATION
Terminal Assignment
1
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8
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35
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20
19
GVDD_B
OTW
SD
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
VDD
GVDD_C
GVDD_A
BST_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
BST_D
GVDD_D
DKD PACKAGE
(TOP VIEW)
P0018-01
1
2
3
4
5
6
7
8
9
10
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12
13
14
15
16
17
18
19
20
21
22
GVDD_B
OTW
NC
NC
SD
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
NC
NC
VDD
GVDD_C
DDV PACKAGE
(TOP VIEW)
GVDD_A
BST_A
NC
PVDD_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
PVDD_D
NC
BST_D
GVDD_D
44
43
42
41
40
39
38
37
36
35
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29
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23
P0016-02
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the deviceplaced in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
The TAS5142 is available in two thermally enhanced packages:•36-pin PSOP3 package (DKD)•44-pin HTSSOP PowerPad™ package (DDV)
Both package types contain a heat slug that is located on the top side of the device for convenient thermalcoupling to the heatsink.
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MODE Selection Pins for Both Packages
Package Heat Dissipation Ratings
(1)
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
GENERAL INFORMATION (continued)
MODE PINS
PWM INPUT OUTPUT CONFIGURATION PROTECTION SCHEMEM3 M2 M1
0 0 0 2N
(1)
AD/BD modulation 2 channels BTL output BTL mode
(2)
0 0 1 Reserved0 1 0 1N
(1)
AD modulation 2 channels BTL output BTL mode
(2)
0 1 1 1N
(1)
AD modulation 1 channel PBTL output PBTL mode. Only PWM_A input is used.Protection works similarly to BTL mode
(2)
. Onlydifference in SE mode is that OUT_X is Hi-Z1 0 0 1N
(1)
AD modulation 4 channels SE output
instead of a pulldown through internal pulldownresistor.1011 1 0 Reserved111
(1) The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specificmode.
(2) An overload protection (OLP) occurring on A or B causes both channels to shut down. An OLP on C or D works similarly. Global errorslike overtemperature error (OTE), undervoltage protection (UVP), and power-on reset (POR) affect all channels.
PARAMETER TAS5142DKD TAS5142DDV
R
θJC
(°C/W)—2 BTL or 4 SE channels (8 transistors) 1.28 1.28R
θJC
(°C/W)—1 BTL or 2 SE channel(s) (4 transistors) 2.56 2.56R
θJC
(°C/W)—(1 transistor) 8.6 8.6Pad area
(2)
80 mm
2
36 mm
2
(1) JC is junction-to-case, CH is case-to-heatsink.(2) R
θCH
is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. TheR
θCH
with this condition is 0.8°C/W for the DKD package and 1.8°C/W for the DDV package.
3
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ABSOLUTE MAXIMUM RATINGS
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
over operating free-air temperature range unless otherwise noted
(1)
TAS5142
VDD to AGND –0.3 V to 13.2 VGVDD_X to AGND –0.3 V to 13.2 VPVDD_X to GND_X
(2)
–0.3 V to 50 VOUT_X to GND_X
(2)
–0.3 V to 50 VBST_X to GND_X
(2)
–0.3 V to 63.2 VVREG to AGND –0.3 V to 4.2 VGND_X to GND –0.3 V to 0.3 VGND_X to AGND –0.3 V to 0.3 VGND to AGND –0.3 V to 0.3 VPWM_X, OC_ADJ, M1, M2, M3 to AGND –0.3 V to 4.2 VRESET_X, SD, OTW to AGND –0.3 V to 7 VMaximum continuous sink current ( SD, OTW) 9 mAMaximum operating junction temperature range, T
J
0°C to 125°CStorage temperature –40°C to 125°CLead temperature, 1,6 mm (1/16 inch) from case for 10 seconds 260°CMinimum pulse duration, low 50 ns
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
ORDERING INFORMATION
T
A
PACKAGE DESCRIPTION
0°C to 70°C TAS5142DKD 36-pin PSOP30°C to 70°C TAS5142DDV 44-pin HTSSOP
For the most current specification and package information, see the TI Web site at www.ti.com.
4
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Terminal Functions
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
TERMINAL
FUNCTION
(1)
DESCRIPTIONNAME DKD NO. DDV NO.
AGND 9 11 P Analog groundBST_A 35 43 P HS bootstrap supply (BST), external capacitor to OUT_A requiredBST_B 28 34 P HS bootstrap supply (BST), external capacitor to OUT_B requiredBST_C 27 33 P HS bootstrap supply (BST), external capacitor to OUT_C requiredBST_D 20 24 P HS bootstrap supply (BST), external capacitor to OUT_D requiredGND 8 10 P GroundGND_A 32 38 P Power ground for half-bridge AGND_B 31 37 P Power ground for half-bridge BGND_C 24 30 P Power ground for half-bridge CGND_D 23 29 P Power ground for half-bridge DGVDD_A 36 44 P Gate-drive voltage supply requires 0.1- µF capacitor to AGNDGVDD_B 1 1 P Gate-drive voltage supply requires 0.1- µF capacitor to AGNDGVDD_C 18 22 P Gate-drive voltage supply requires 0.1- µF capacitor to AGNDGVDD_D 19 23 P Gate-drive voltage supply requires 0.1- µF capacitor to AGNDM1 13 15 I Mode selection pinM2 12 14 I Mode selection pinM3 11 13 I Mode selection pinNC – 3, 4, 19, 20, 25, – No connect. Pins may be grounded.42OC_ADJ 7 9 O Analog overcurrent programming pin requires resistor to groundOTW 2 2 O Overtemperature warning signal, open-drain, active-lowOUT_A 33 39 O Output, half-bridge AOUT_B 30 36 O Output, half-bridge BOUT_C 25 31 O Output, half-bridge COUT_D 22 28 O Output, half-bridge DPVDD_A 34 40, 41 P Power supply input for half-bridge A requires close decoupling of0.1- µF capacitor to GND_A.PVDD_B 29 35 P Power supply input for half-bridge B requires close decoupling of0.1- µF capacitor to GND_B.PVDD_C 26 32 P Power supply input for half-bridge C requires close decoupling of0.1- µF capacitor to GND_C.PVDD_D 21 26, 27 P Power supply input for half-bridge D requires close decoupling of0.1- µF capacitor to GND_D.PWM_A 4 6 I Input signal for half-bridge APWM_B 6 8 I Input signal for half-bridge BPWM_C 14 16 I Input signal for half-bridge CPWM_D 16 18 I Input signal for half-bridge DRESET_AB 5 7 I Reset signal for half-bridge A and half-bridge B, active-lowRESET_CD 15 17 I Reset signal for half-bridge C and half-bridge D, active-lowSD 3 5 O Shutdown signal, open-drain, active-lowVDD 17 21 P Power supply for digital voltage regulator requires 0.1- µF capacitorto GND.VREG 10 12 P Digital regulator supply filter pin requires 0.1- µF capacitor to AGND.
(1) I = input, O = output, P = power
5
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SYSTEM BLOCK DIAGRAM
2nd-Order L-C
Output Filter
for Each
Half-Bridge
Bootstrap
Capacitors
2-Channel
H-Bridge
BTL Mode
System
Microcontroller
OUT_A
OUT_B
OUT_C
OUT_D
BST_A
BST_B
BST_C
BST_D
RESET_AB
RESET_CD
System
Power
Supply
Hardwire
Mode
Control
PVDD
GVDD (12 V)/VDD (12 V)
GND
Hardwire
OC Limit
M1
M3
PVDD
Power
Supply
Decoupling
32 V
12 V
GND
VAC
PWM_A
PWM_C
PWM_D
PWM_B
VALID
M2
Left-
Channel
Output
Right-
Channel
Output
Input
H-Bridge 1
Input
H-Bridge 2
GVDD
VDD
VREG
Power Supply
Decoupling
4
PVDD_A, B, C, D
GND_A, B, C, D
GVDD_A, B, C, D
4 4
VDD
GND
VREG
AGND
OC_ADJ
Bootstrap
Capacitors
2nd-Order L-C
Output Filter
for Each
Half-Bridge
SD
OTW
Output
H-Bridge 2
Output
H-Bridge 1
OTW
SD
TAS5508
B0047-01
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
6
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FUNCTIONAL BLOCK DIAGRAM
Temp.
Sense
M1
M2
RESET_AB
SD
OTW
AGND
OC_ADJ
VREG VREG
VDD
M3
Power
On
Reset
Under-
voltage
Protection
GND
PWM_D OUT_D
GND_D
PVDD_D
BST_D
Timing Gate
Drive
PWM
Rcv.
Overload
Protection Isense
GVDD_D
RESET_CD
4
Protection
and
I/O Logic
PWM_C OUT_C
GND_C
PVDD_C
BST_C
Timing Gate
Drive
Ctrl.
PWM
Rcv.
GVDD_C
PWM_B OUT_B
GND_B
PVDD_B
BST_B
Timing Gate
Drive
Ctrl.
PWM
Rcv.
GVDD_B
PWM_A OUT_A
GND_A
PVDD_A
BST_A
Timing Gate
Drive
Ctrl.
PWM
Rcv.
GVDD_A
Ctrl.
BTL/PBTL−Configuration
Pulldown Resistor
BTL/PBTL−Configuration
Pulldown Resistor
BTL/PBTL−Configuration
Pulldown Resistor
BTL/PBTL−Configuration
Pulldown Resistor
Internal Pullup
Resistors to VREG
B0034-02
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
7
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RECOMMENDED OPERATING CONDITIONS
AUDIO SPECIFICATIONS (BTL)
AUDIO SPECIFICATIONS (Single-Ended Output)
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
MIN TYP MAX UNIT
PVDD_X Half-bridge supply DC supply voltage 0 32 34 VSupply for logic regulators and gate-driveGVDD_X DC supply voltage 10.8 12 13.2 VcircuitryVDD Digital regulator input DC supply voltage 10.8 12 13.2 VR
L
(BTL) 3 4Output filter: L = 10 µH, C = 470 nF.R
L
(SE) Load impedance Output AD modulation, switching 2 3 Ωfrequency > 350 kHzR
L
(PBTL) 1.5 2L
Output
(BTL) 5 10Minimum output inductance underL
Output
(SE) Output-filter inductance 5 10 µHshort-circuit conditionL
Output
(PBTL) 5 10F
PWM
PWM frame rate 192 384 432 kHzT
J
Junction temperature 0 125 °C
PVDD_X = 32 V, GVDD = VDD = 12 V, BTL mode, R
L
= 4 Ω, audio frequency = 1 kHz, AES17 filter, F
PWM
= 384 kHz, casetemperature = 75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5508 PWM processorwith an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditionsunless otherwise specified.
TAS5142PARAMETER TEST CONDITIONS UNITMIN TYP MAX
R
L
= 4 Ω, 10% THD, clipped input
100signal
R
L
= 6 Ω, 10% THD, clipped input
80signal
R
L
= 8 Ω, 10% THD, clipped input
65 WsignalP
O
Power output per channel, DKD package
R
L
= 4 Ω, 0 dBFS, unclipped input
80signal
R
L
= 6 Ω, 0 dBFS, unclipped input
60signal
R
L
= 8 Ω, 0 dBFS, unclipped input
50signal
0 dBFS 0.3%THD+N Total harmonic distortion + noise
1 W 0.1%V
n
Output integrated noise A-weighted 140 µVSNR Signal-to-noise ratio
(1)
A-weighted 102 dBA-weighted, input level = –60 dBFS
102using TAS5508 modulatorDNR Dynamic range dBA-weighted, input level = –60 dBFS
110using TAS5518 modulatorP
idle
Power dissipation due to idle losses (IPVDD_X) P
O
= 0 W, 4 channels switching
(2)
2 W
(1) SNR is calculated relative to 0-dBFS input level.(2) Actual system idle losses are affected by core losses of output inductors.
PVDD_X = 32 V, GVDD = VDD = 12 V, SE mode, R
L
= 4 Ω, audio frequency = 1 kHz, AES17 filter, F
PWM
= 384 kHz, casetemperature = 75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5086 PWM processorwith an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions
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AUDIO SPECIFICATIONS (PBTL)
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
AUDIO SPECIFICATIONS (Single-Ended Output) (continued)PVDD_X = 32 V, GVDD = VDD = 12 V, SE mode, R
L
= 4 Ω, audio frequency = 1 kHz, AES17 filter, F
PWM
= 384 kHz, casetemperature = 75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5086 PWM processorwith an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditionsunless otherwise specified.
unless otherwise specified.
TAS5142PARAMETER TEST CONDITIONS UNITMIN TYP MAX
R
L
= 3 Ω, 10% THD, clipped input
40signal
R
L
= 4 Ω, 10% THD, clipped input
30signalP
O
Power output per channel, DKD package WR
L
= 3 Ω, 0 dBFS, unclipped input
30signal
R
L
= 4 Ω, 0 dBFS, unclipped input
20signal
0 dBFS 0.2%THD+N Total harmonic distortion + noise
1 W 0.1%V
n
Output integrated noise A-weighted 90 µVSNR Signal-to-noise ratio
(1)
A-weighted 100 dBA-weighted, input level = –60 dBFSDNR Dynamic range 100 dBusing TAS5508 modulatorP
idle
Power dissipation due to idle losses (IPVDD_X) P
O
= 0 W, 4 channels switching
(2)
2 W
(1) SNR is calculated relative to 0-dBFS input level.(2) Actual system idle losses are affected by core losses of output inductors.
PVDD_X = 32 V, GVDD = VDD = 12 V, PBTL mode, R
L
= 3 Ω, audio frequency = 1 kHz, AES17 filter, F
PWM
= 384 kHz, casetemperature = 75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5508 PWM processorwith an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditionsunless otherwise specified.
TAS5142PARAMETER TEST CONDITIONS UNITMIN TYP MAX
R
L
= 3 Ω, 10% THD, clipped input
160signal
R
L
= 2 Ω, 10% THD, clipped input
200signalP
O
Power output per channel, DKD package WR
L
= 3 Ω, 0 dBFS, unclipped input
120signal
R
L
= 2 Ω, 0 dBFS, unclipped input
150signal
0 dBFS 0.2%THD+N Total harmonic distortion + noise
1 W 0.1%V
n
Output integrated noise A-weighted 140 µVSNR Signal-to-noise ratio
(1)
A-weighted 102 dBA-weighted, input level = –60 dBFS
102using TAS5508 modulatorDNR Dynamic range dBA-weighted, input level = –60 dBFS
110using TAS5518 modulatorP
idle
Power dissipation due to idle losses (IPVDD_X) P
O
= 0 W, 1 channel switching
(2)
2 W
(1) SNR is calculated relative to 0-dBFS input level.(2) Actual system idle losses are affected by core losses of output inductors.
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ELECTRICAL CHARACTERISTICS
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
R
L
= 4 Ω, F
PWM
= 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditionsunless otherwise specified.
TAS5142PARAMETER TEST CONDITIONS UNITMIN TYP MAX
Internal Voltage Regulator and Current Consumption
Voltage regulator, only used as aVREG VDD = 12 V 3 3.3 3.6 Vreference node
Operating, 50% duty cycle 7 17IVDD VDD supply current mAIdle, reset mode 6 1150% duty cycle 5 16IGVDD_X Gate supply current per half-bridge mAReset mode 0.3 150% duty cycle, without output filter or load 15 25 mAIPVDD_X Half-bridge idle current
Reset mode, no switching 7 25 µA
Output Stage MOSFETs
T
J
= 25°C, includes metallization resistance,R
DSon,LS
Drain-to-source resistance, LS 140 155 m ΩGVDD = 12 VT
J
= 25°C, includes metallization resistance,R
DSon,HS
Drain-to-source resistance, HS 140 155 m ΩGVDD = 12 V
I/O Protection
Undervoltage protection limit,V
uvp,G
9.8 VGVDD_XV
uvp,hyst
(1)
250 mVOTW
(1)
Overtemperature warning 115 125 135 °CTemperature drop needed belowOTW
HYST
(1)
OTW temp. for OTW to be inactive 25 °Cafter the OTW eventOTE
(1)
Overtemperature error 145 155 165 °COTE-
OTE-OTW differential 30 °COTW
differential
(1)
A reset event must occur for SD toOTE
HYST
(1)
25 °Cbe released following an OTE event.OLPC Overload protection counter F
PWM
= 384 kHz 1.25 msResistor—programmable, high-end,I
OC
Overcurrent limit protection 7.9 9.7 11.4 AR
OCP
= 18 k ΩI
OCT
Overcurrent response time 210 nsR
OCP
OC programming resistor range Resistor tolerance = 5% 18 69 k ΩConnected when RESET is active to provideInternal pulldown resistor at theR
PD
bootstrap capacitor charge. Not used in SE 2.5 k Ωoutput of each half-bridge
mode
Static Digital Specifications
V
IH
High-level input voltage 2 VPWM_A, PWM_B, PWM_C, PWM_D, M1,M2, M3, RESET_AB, RESET_CDV
IL
Low-level input voltage 0.8 VLeakage Input leakage current –10 10 µA
OTW/SHUTDOWN (SD)
Internal pullup resistance, OTW toR
INT_PU
20 26 32 k ΩVREG, SD to VREG
Internal pullup resistor 3 3.3 3.6V
OH
High-level output voltage VExternal pullup of 4.7 k Ωto 5 V 4.5 5V
OL
Low-level output voltage I
O
= 4 mA 0.2 0.4 VFANOUT Device fanout OTW, SD No external pullup 30 Devices
(1) Specified by design
10
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION
PVDD − Supply Voltage − V
0
10
20
30
40
50
60
70
80
90
100
110
120
0 4 8 12 16 20 24 28 32
PO − Output Power − W
8 Ω
4 Ω
TC = 75°C
THD+N @ 10%
6 Ω
G002
PO − Output Power − W
101
THD+N − Total Harmonic Distortion + Noise − %
0.01
0.1
10
1
TC = 75°C
PVDD = 32 V
One Channel
100
4 Ω6 Ω
8 Ω
G001
PVDD − Supply Voltage − V
0
10
20
30
40
50
60
70
80
90
100
110
120
0 4 8 12 16 20 24 28 32
PO − Output Power − W
8 Ω
4 Ω
TC = 75°C
6 Ω
G003
PO − Output Power − W
0
10
20
30
40
50
60
70
80
90
100
0 20 40 60 80 100 120 140 160 180 200 220
Efficiency − %
6 Ω4 Ω
TC = 25°C
8 Ω
G004
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWERvs vsOUTPUT POWER SUPPLY VOLTAGE
Figure 1. Figure 2.
UNCLIPPED OUTPUT POWER SYSTEM EFFICIENCYvs vsSUPPLY VOLTAGE OUTPUT POWER
Figure 3. Figure 4.
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PO − Output Power − W
0
5
10
15
20
25
30
35
40
0 20 40 60 80 100 120 140 160 180 200 220
Power Loss − W
6 Ω
4 Ω
8 Ω
TC = 25°C
G005
TC − Case Temperature − °C
0
10
20
30
40
50
60
70
80
90
100
110
120
130
10 20 30 40 50 60 70 80 90 100 110 120
PO − Output Power − W
8 Ω
4 Ω
THD+N @ 10%
6 Ω
G006
f − Frequency − kHz
−150
−140
−130
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 2 4 6 8 10 12 14 16 18 20 22
Noise Amplitude − dBr
TC = 75°C
G007
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
SYSTEM POWER LOSS SYSTEM OUTPUT POWERvs vsOUTPUT POWER CASE TEMPERATURE
Figure 5. Figure 6.
NOISE AMPLITUDE
vsFREQUENCY
Figure 7.
12
www.ti.com
TYPICAL CHARACTERISTICS, SE CONFIGURATION
PO − Output Power − W
101
THD+N − Total Harmonic Distortion + Noise − %
0.01
0.1
10
1
TC = 75°C
Digital Gain = 3 dB
3 Ω
4 Ω
50
G008
PVDD − Supply Voltage − V
0
5
10
15
20
25
30
35
40
45
50
0 4 8 12 16 20 24 28 32
PO − Output Power − W
4 Ω
TC = 75°C
THD+N @ 10%
3 Ω
G009
TC − Case Temperature − °C
0
5
10
15
20
25
30
35
40
45
50
55
60
10 20 30 40 50 60 70 80 90 100 110 120
PO − Output Power − W
4 Ω
THD+N @ 10%
3 Ω
G010
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWERvs vsOUTPUT POWER SUPPLY VOLTAGE
Figure 8. Figure 9.
OUTPUT POWER
vsCASE TEMPERATURE
Figure 10.
13
www.ti.com
TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
PO − Output Power − W
101
THD+N − Total Harmonic Distortion + Noise − %
0.01
0.1
10
1
TC = 75°C
Digital Gain = 3 dB
2 Ω
3 Ω
200100
G011
PVDD − Supply Voltage − V
0
20
40
60
80
100
120
140
160
180
200
220
0 4 8 12 16 20 24 28 32
PO − Output Power − W
3 Ω
TC = 75°C
THD+N @ 10%
2 Ω
G012
150
160
170
180
190
200
210
220
230
240
250
10 20 30 40 50 60 70 80 90 100 110 120
TC − Case Temperature − °C
PO − Output Power − W
THD+N @ 10%
2 Ω
3 Ω
G013
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWERvs vsOUTPUT POWER SUPPLY VOLTAGE
Figure 11. Figure 12.
SYSTEM OUTPUT POWER
vsCASE TEMPERATURE
Figure 13.
14
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TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
Figure 14. Typical Differential (2N) BTL Application With AD Modulation Filters
15
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TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
Figure 15. Typical Non-Differential (1N) BTL Application With AD Modulation Filters
16
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PVDD/2
PVDD/2
PVDD/2
PVDD/2
VALID
GVDD 10 Ω
10 Ω
10 µF
100 nF
GVDD 1 Ω
100 nF
Shutdown
PWM1_P1
PWM2_P
PWM3_P
PWM4_P
PWM_A
PWM_C
OTW
RESET_AB
M2
M3
RESET_CD
VDD
GVDD_C
GVDD_B
PWM_D
VREG
M1
SD
AGND
PWM_B
OC_ADJ
GND
GND_C
OUT_A
BST_A
OUT_B
BST_B
PVDD_B
PVDD_A
BST_C
PVDD_C
OUT_C
GND_A
GND_B
OUT_D
PVDD_D
BST_D
36
35
34
33
23
19
20
21
22
24
25
26
27
28
32
31
30
29
GND_D
GVDD_D
GVDD_A
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
Microcontroller
39 kΩ
100 nF
33 nF
33 nF
33 nF
33 nF
100 nF
50 V
100 nF
50 V
100 nF
50 V
1000 µF
50 V
PVDD
10 µH@10 A
3.3 Ω
10 nF
50 V
10 nF
50 V 1000 µF
50 V
PVDD
3.3 Ω
100 nF
50 V 47 µF
50 V
47 µF
50 V
47 µF
50 V
10 µF100 nF
100 nF
100 nF
10 µH@10 A
TAS5142DKD
0 Ω
Optional
TAS5508
10 Ω
10 Ω
47 µF
50 V
10 µH@10 A
10 µH@10 A
10 nF
50 V
3.3 Ω
100 nF
100 V
10 nF @ 50 V
3.3 Ω
100 nF
100 V
1 µF
50 V
A
B
C
D
220 µF
50 V
220 µF
50 V
PVDD
D
C
2.7 kΩ
10 nF
50 V
3.3 Ω
100 nF
100 V
10 nF @ 50 V
3.3 Ω
100 nF
100 V
1 µF
50 V
220 µF
50 V
220 µF
50 V
PVDD
10 nF
50 V
3.3 Ω
100 nF
100 V
10 nF @ 50 V
3.3 Ω
100 nF
100 V
1 µF
50 V
220 µF
50 V
220 µF
50 V
PVDD
10 nF
50 V
3.3 Ω
100 nF
100 V
10 nF @ 50 V
3.3 Ω
100 nF
100 V
1 µF
50 V
220 µF
50 V
220 µF
50 V
PVDD
2.7 kΩ
2.7 kΩ
2.7 kΩ
A
B
S0071-01
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
Figure 16. Typical SE Application
17
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VALID
GVDD 10 Ω
10 Ω
10 µF
100 nF
GVDD 1 Ω
100 nF
Shutdown
PWM1_P PWM_A
PWM_C
OTW
RESET_AB
M2
M3
RESET_CD
VDD
GVDD_C
GVDD_B
PWM_D
VREG
M1
SD
AGND
PWM_B
OC_ADJ
GND
GND_C
OUT_A
BST_A
OUT_B
BST_B
PVDD_B
PVDD_A
BST_C
PVDD_C
OUT_C
GND_A
GND_B
OUT_D
PVDD_D
BST_D
36
35
34
33
23
19
20
21
22
24
25
26
27
28
32
31
30
29
GND_D
GVDD_D
GVDD_A
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
Microcontroller
30 kΩ
100 nF
33 nF
33 nF
33 nF
100 nF
50 V
100 nF
50 V
100 nF
50 V
1000 µF
50 V
PVDD
10 µH@10 A
3.3 Ω
10 nF
50 V
10 nF
50 V 1000 µF
50 V
PVDD
3.3 Ω
100 nF
50 V 47 µF
50 V
47 µF
50 V
47 µF
50 V
10 µF100 nF
100 nF
100 nF
10 µH@10 A
TAS5142DKD
0 Ω
Optional
TAS5508
10 Ω
10 Ω
47 µF
50 V
10 µH@10 A
10 µH@10 A
33 nF
PWM1_M
470 nF
63 V
10 nF
50 V
10 nF
50 V
3.3 Ω
3.3 Ω
100 nF
100 V
100 nF
100 V
S0070-03
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
Figure 17. Typical Differential (2N) PBTL Application With AD Modulation Filters
18
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VALID
GVDD 10 Ω
10 Ω
10 µF
100 nF
GVDD 1 Ω
100 nF
Shutdown
PWM1 PWM_A
PWM_C
OTW
RESET_AB
M2
M3
RESET_CD
VDD
GVDD_C
GVDD_B
PWM_D
VREG
M1
SD
AGND
PWM_B
OC_ADJ
GND
GND_C
OUT_A
BST_A
OUT_B
BST_B
PVDD_B
PVDD_A
BST_C
PVDD_C
OUT_C
GND_A
GND_B
OUT_D
PVDD_D
BST_D
36
35
34
33
23
19
20
21
22
24
25
26
27
28
32
31
30
29
GND_D
GVDD_D
GVDD_A
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
Microcontroller
30 kΩ
100 nF
33 nF
33 nF
33 nF
100 nF
50 V
100 nF
50 V
100 nF
50 V
1000 µF
50 V
PVDD
10 µH@10 A
3.3 Ω
10 nF
50 V
10 nF
50 V 1000 µF
50 V
PVDD
3.3 Ω
100 nF
50 V 47 µF
50 V
47 µF
50 V
47 µF
50 V
10 µF100 nF
100 nF
100 nF
10 µH@10 A
TAS5142DKD
0 Ω
Optional
TAS5508
10 Ω
10 Ω
47 µF
50 V
10 µH@10 A
10 µH@10 A
33 nF
470 nF
63 V
10 nF
50 V
10 nF
50 V
3.3 Ω
3.3 Ω
100 nF
100 V
100 nF
100 V
No connect
No connect
No connect
S0070-04
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
Figure 18. Typical Non-Differential (1N) PBTL Application
19
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THEORY OF OPERATION
POWER SUPPLIES
SYSTEM POWER-UP/POWER-DOWN
Powering Up
Powering Down
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
Special attention should be paid to the power-stagepower supply; this includes component selection,PCB placement, and routing. As indicated, eachTo facilitate system design, the TAS5142 needs only
half-bridge has independent power-stage supply pinsa 12-V supply in addition to the (typical) 32-V
(PVDD_X). For optimal electrical performance, EMIpower-stage supply. An internal voltage regulator
compliance, and system reliability, it is important thatprovides suitable voltage levels for the digital and
each PVDD_X pin is decoupled with a 100-nFlow-voltage analog circuitry. Additionally, all circuitry
ceramic capacitor placed as close as possible torequiring a floating voltage supply, e.g., the high-side
each supply pin. It is recommended to follow the PCBgate drive, is accommodated by built-in bootstrap
layout of the TAS5142 reference design. Forcircuitry requiring only a few external capacitors.
additional information on recommended power supplyIn order to provide outstanding electrical and
and required components, see the applicationacoustical characteristics, the PWM signal path
diagrams given previously in this data sheet.including gate drive and output stage is designed as
The 12-V supply should be from a low-noise,identical, independent half-bridges. For this reason,
low-output-impedance voltage regulator. Likewise, theeach half-bridge has separate gate drive supply
32-V power-stage supply is assumed to have low(GVDD_X), bootstrap pins (BST_X), and power-stage
output impedance and low noise. The power-supplysupply pins (PVDD_X). Furthermore, an additional pin
sequence is not critical as facilitated by the internal(VDD) is provided as supply for all common circuits.
power-on-reset circuit. Moreover, the TAS5142 is fullyAlthough supplied from the same 12-V source, it is
protected against erroneous power-stage turnon duehighly recommended to separate GVDD_A,
to parasitic gate charging. Thus, voltage-supply rampGVDD_B, GVDD_C, GVDD_D, and VDD on the
rates (dV/dt) are non-critical within the specifiedprinted-circuit board (PCB) by RC filters (see
range (see the Recommended Operating Conditionsapplication diagram for details). These RC filters
section of this data sheet).provide the recommended high-frequency isolation.Special attention should be paid to placing alldecoupling capacitors as close to their associatedpins as possible. In general, inductance between the SEQUENCEpower supply pins and decoupling capacitors must beavoided. (See reference board documentation foradditional information.)
The TAS5142 does not require a power-up sequence.For a properly functioning bootstrap circuit, a small The outputs of the H-bridges remain in a high-imped-ceramic capacitor must be connected from each ance state until the gate-drive supply voltagebootstrap pin (BST_X) to the power-stage output pin (GVDD_X) and VDD voltage are above the(OUT_X). When the power-stage output is low, the undervoltage protection (UVP) voltage threshold (seebootstrap capacitor is charged through an internal the Electrical Characteristics section of this datadiode connected between the gate-drive power--sheet). Although not specifically required, it issupply pin (GVDD_X) and the bootstrap pin. When recommended to hold RESET_AB and RESET_CD inthe power-stage output is high, the bootstrap a low state while powering up the device. This allowscapacitor potential is shifted above the output an internal circuit to charge the external bootstrappotential and thus provides a suitable voltage supply capacitors by enabling a weak pulldown of thefor the high-side gate driver. In an application with half-bridge output.PWM switching frequencies in the range from 352
When the TAS5142 is being used with TI PWMkHz to 384 kHz, it is recommended to use 33-nF
modulators such as the TAS5508, no specialceramic capacitors, size 0603 or 0805, for the
attention to the state of RESET_AB and RESET_CDbootstrap supply. These 33-nF capacitors ensure
is required, provided that the chipset is configured assufficient energy storage, even during minimal PWM
recommended.duty cycles, to keep the high-side power stage FET(LDMOS) fully turned on during the remaining part ofthe PWM cycle. In an application running at areduced switching frequency, generally 192 kHz, the
The TAS5142 does not require a power-downbootstrap capacitor might need to be increased in
sequence. The device remains fully operational asvalue.
long as the gate-drive supply (GVDD_X) voltage andVDD voltage are above the undervoltage protection(UVP) voltage threshold (see the Electrical
20
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Use of TAS5142 in High-Modulation-Index
ERROR REPORTING
Overcurrent (OC) Protection With Current
DEVICE PROTECTION SYSTEM
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
Characteristics section of this data sheet). Although temperature has dropped or the supply voltage hasnot specifically required, it is a good practice to hold increased. For highest possible reliability, recoveringRESET_AB and RESET_CD low during power down, from an overload fault requires external reset of thethus preventing audible artifacts including pops or device (see the Device Reset section of this dataclicks. sheet) no sooner than 1 second after the shutdown.
When the TAS5142 is being used with TI PWMmodulators such as the TAS5508, no special
Capable Systemsattention to the state of RESET_AB and RESET_CD
This device requires at least 50 ns of low time on theis required, provided that the chipset is configured as
output per 384-kHz PWM frame rate in order to keeprecommended.
the bootstrap capacitors charged. As an example, ifthe modulation index is set to 99.2% in the TAS5508,this setting allows PWM pulse durations down to 20The SD and OTW pins are both active-low,
ns. This signal, which does not meet the 50-nsopen-drain outputs. Their function is for
requirement, is sent to the PWM_X pin and thisprotection-mode signaling to a PWM controller or
low-state pulse time does not allow the bootstrapother system-control device.
capacitor to stay charged. In this situation, the lowvoltage across the bootstrap capacitor can cause aAny fault resulting in device shutdown is signaled by
failure of the high-side MOSFET transistor, especiallythe SD pin going low. Likewise, OTW goes low when
when driving a low-impedance load. The TAS5142the device junction temperature exceeds 125 °C (see
device requires limiting the TAS5508 modulationthe following table).
index to 96.1% to keep the bootstrap capacitorSD OTW DESCRIPTION
charged under all signals and loads.0 0 Overtemperature (OTE) or overload (OLP) or
Therefore, TI strongly recommends using a TI PWMundervoltage (UVP)
processor, such as TAS5508 or TAS5086, with the0 1 Overload (OLP) or undervoltage (UVP)
modulation index set at 96.1% to interface with1 0 Junction temperature higher than 125°C
TAS5142.(overtemperature warning)1 1 Junction temperature lower than 125°C and noOLP or UVP faults (normal operation)
Limiting and Overload DetectionNote that asserting either RESET_AB or RESET_CD
The device has independent, fast-reacting currentlow forces the SD signal high, independent of faults
detectors with programmable trip threshold (OCbeing present. TI recommends monitoring the OTW
threshold) on all high-side and low-side power-stagesignal using the system microcontroller and
FETs. See the following table for OC-adjust resistorresponding to an overtemperature warning signal by,
values. The detector outputs are closely monitored bye.g., turning down the volume to prevent further
two protection systems. The first protection systemheating of the device resulting in device shutdown
controls the power stage in order to prevent the(OTE).
output current from further increasing, i.e., it performsa current-limiting function rather than prematurelyTo reduce external component count, an internal
shutting down during combinations of high-levelpullup resistor to 3.3 V is provided on both SD and
music transients and extreme speaker loadOTW outputs. Level compliance for 5-V logic can be
impedance drops. If the high-current situationobtained by adding external pullup resistors to 5 V
persists, i.e., the power stage is being overloaded, a(see the Electrical Characteristics section of this data
second protection system triggers a latchingsheet for further specifications).
shutdown, resulting in the power stage being set inthe high-impedance (Hi-Z) state. Current limiting andoverload protection are independent for half-bridgesThe TAS5142 contains advanced protection circuitry A and B and, respectively, C and D. That is, if thecarefully designed to facilitate system integration and bridge-tied load between half-bridges A and B causesease of use, as well as to safeguard the device from an overload fault, only half-bridges A and B are shutpermanent failure due to a wide range of fault down.conditions such as short circuits, overload,
•For the lowest-cost bill of materials in terms ofovertemperature, and undervoltage. The TAS5142
component selection, the OC threshold measureresponds to a fault by immediately setting the power
should be limited, considering the power outputstage in a high-impedance (Hi-Z) state and asserting
requirement and minimum load impedance.the SD pin low. In situations other than overload, the
Higher-impedance loads require a lower OCdevice automatically recovers when the fault
threshold.condition has been removed, i.e., the junction
21
www.ti.com
Undervoltage Protection (UVP) and Power-On
DEVICE RESET
Overtemperature Protection
TAS5142
SLES126B – DECEMBER 2004 – REVISED MAY 2005
•The demodulation-filter inductor must retain at put into thermal shutdown, resulting in all half-bridgeleast 5 µH of inductance at twice the OC outputs being set in the high-impedance (Hi-Z) statethreshold setting. and SD being asserted low. OTE is latched in thiscase. To clear the OTE latch, both RESET_AB andUnfortunately, most inductors have decreasing
RESET_CD must be asserted. Thereafter, the deviceinductance with increasing temperature and
resumes normal operation.increasing current (saturation). To some degree, anincrease in temperature naturally occurs whenoperating at high output currents, due to core losses
Reset (POR)and the dc resistance of the inductor's copper
The UVP and POR circuits of the TAS5142 fullywinding. A thorough analysis of inductor saturation
protect the device in any power-up/down andand thermal properties is strongly recommended.
brownout situation. While powering up, the PORSetting the OC threshold too low might cause issues
circuit resets the overload circuit (OLP) and ensuressuch as lack of enough output power and/or
that all circuits are fully operational when theunexpected shutdowns due to too-sensitive overload
GVDD_X and VDD supply voltages reach 9.8 Vdetection.
(typical). Although GVDD_X and VDD areindependently monitored, a supply voltage dropIn general, it is recommended to follow closely the
below the UVP threshold on any VDD or GVDD_Xexternal component selection and PCB layout as
pin results in all half-bridge outputs immediately beinggiven in the Application section.
set in the high-impedance (Hi-Z) state and SD beingFor added flexibility, the OC threshold is
asserted low. The device automatically resumesprogrammable within a limited range using a single
operation when all supply voltages have increasedexternal resistor connected between the OC_ADJ pin
above the UVP threshold.and AGND. (See the Electrical Characteristics sectionof this data sheet for information on the correlationbetween programming-resistor value and the OC
Two reset pins are provided for independent controlthreshold.) It should be noted that a properly
of half-bridges A/B and C/D. When RESET_AB isfunctioning overcurrent detector assumes the
asserted low, all four power-stage FETs in half--presence of a properly designed demodulation filter at
bridges A and B are forced into a high-impedancethe power-stage output. Short-circuit protection is not
(Hi-Z) state. Likewise, asserting RESET_CD lowprovided directly at the output pins of the power stage
forces all four power-stage FETs in half-bridges Cbut only on the speaker terminals (after the
and D into a high-impedance state. Thus, both resetdemodulation filter). It is required to follow certain
pins are well suited for hard-muting the power stage ifguidelines when selecting the OC threshold and an
needed.appropriate demodulation inductor:OC-Adjust Resistor Values Max. Current Before OC Occurs
In BTL modes, to accommodate bootstrap charging(k Ω) (A)
prior to switching start, asserting the reset inputs low22 9.4
enables weak pulldown of the half-bridge outputs. Inthe SE mode, the weak pulldowns are not enabled,27 8.6
and it is therefore recommended to ensure bootstrap39 6.4
capacitor charging by providing a low pulse on the47 6
PWM inputs when reset is asserted high.69 4.7
Asserting either reset input low removes any faultinformation to be signalled on the SD output, i.e., SDis forced high.The TAS5142 has a two-level temperature-protection
A rising-edge transition on either reset input allowssystem that asserts an active-low warning signal
the device to resume operation after an overload( OTW) when the device junction temperature
fault.exceeds 125 °C (nominal) and, if the device junctiontemperature exceeds 155 °C (nominal), the device is
22
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TAS5142DDV ACTIVE HTSSOP DDV 44 35 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TAS5142DDVG4 ACTIVE HTSSOP DDV 44 35 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TAS5142DDVR ACTIVE HTSSOP DDV 44 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TAS5142DDVRG4 ACTIVE HTSSOP DDV 44 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TAS5142DKD ACTIVE HSSOP DKD 36 29 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TAS5142DKDG4 ACTIVE HSSOP DKD 36 29 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TAS5142DKDR ACTIVE HSSOP DKD 36 500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TAS5142DKDRG4 ACTIVE HSSOP DKD 36 500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Apr-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TAS5142DDVR HTSSOP DDV 44 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1
TAS5142DKDR HSSOP DKD 36 500 330.0 24.4 14.7 16.4 4.0 20.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5142DDVR HTSSOP DDV 44 2000 367.0 367.0 45.0
TAS5142DKDR HSSOP DKD 36 500 337.0 343.0 41.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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