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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
FEATURES
GENERAL FEA TURES
• 4,194,304 x 16 wo rd structure
• Sector Structure
- 128 Equal Secto rs with 32K wo rd each
• Extra 128-wo rd sector for security
- Features f acto ry lo c ked and identifiab le, and custo mer lo c kable
• Secto r Groups Pro tection / Chip Unpro tect
- Pro vides secto r gro up protect functio n to prevent pro gram o r erase o peratio n in the pro tected sector gro up
- Pro vides chip unpro tect functio n to allow co de changing
- Pro vides tempo rary secto r gro up unprotect function for co de changing in previo usly pro tected sector gro ups
• Single Power Supply Operation
- 2.7 to 3.6 vo lt f o r read, erase, and pro gram o peratio ns
• Latch-up pro tected to 250mA from -1V to Vcc + 1V
• Low Vcc write inhibit : Vcc <= 1.5V
• Co mpatible with JEDEC standard
- Pino ut and so ftware co mpatible to single power supply Flash
PERFORMANCE
• High Perfo rmance
- Fast access time: 90/120ns
- F ast program time: 11us/wo rd (typical)
- F ast er ase time: 0.9s/sector, 45s/chip (typical)
• Low Power Consumption
- Low active read current: 9mA (typical) at 5MHz
- Low standby current: 0.2uA (typical)
• Minimum 100,000 erase/pro gram cycle
• 20 years data retentio n
SOFTW ARE FEA TURES
• Erase Suspend/ Erase Resume
- Suspends secto r erase o peration to read data fro m or program data to ano ther secto r which is not being erased
• Status Reply
- Data# Po lling & To ggle bits pro vide detectio n of pro gram and erase o peration co mpletion
• Support Co mmon Flash Interface (CFI)
HARDWARE FEA TURES
• Ready/Busy# (RY/BY#) Output
- Pro vides a hardware method o f detecting program and erase operatio n co mpletion
• Hardware Reset (RESET#) Input
- Pro vides a hardware metho d to reset the internal state machine to read mo de
• ACC input pin
- Pro vides accelerated pro gram capability
• WP# pin
- Write pro tect the first secto r regardless o f secto r pro tect/unpro tect status
PACKAGE
• 48-Pin TSOP
• 63-Ball CSP
•All Pb-free devices are RoHS Compliant
•All non RoHS Compliant devices are not recommeded for new design in
64M-BIT [4M x 16] CMOS EQUAL SECTOR
FLASH MEMORY
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
PIN CONFIGURATION
48 TSOP
63 Ball CSP (Top Vie w , Ball Do wn)
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RESET#
ACC
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
V I/O
GND
Q15
Q7
Q14
Q6
Q13
Q5
Q12
Q4
V
CC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX29LV640BU
A13
A9
WE#
RY/
BY#
A7
A3
A
* Ball are shorted together via the substrate but not connected to the die.
8
7
6
5
4
3
2
1
BCDEF GHJK LM
A12
NC NC
A8
RE-
SET#
ACC
A17
A4
A14
A10
A21
A18
A6
A2
A15
A11
A19
A20
A5
A1
A16
Q7
Q5
Q2
Q0
A0
V I/O
Q14
Q12
Q10
Q8
CE#
Q15
Q13
VCC
Q11
Q9
OE#
GND
Q6
Q4
Q3
Q1
GND
NC* NC*
NC* NC*
12.0 mm
11.0 mm
NC*
NC*
NC NC
NC* NC*
NC* NC*
NC*
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
PIN DESCRIPTION LOGIC SYMBOL
16
Q0-Q15
RY/BY#
A0-A21
V I/O
ACC
WP#
CE#
OE#
WE#
RESET#
22
SYMBOL PIN NAME
A0~A21 Address Input
Q0~Q15 16 Data Inputs/Outputs
CE# Chip Enable Input
WE# Write Enable Input
OE# Output Enable Input
RESET# Hardware Reset Pin, Active Low
WP# Hardware Write Protect Input
R Y/BY# Read/Busy Output
VCC +3.0V single power supply
ACC Hardware Acceleration Pin
GN D Device Ground
N C Pin No t Connected Internally
V I/O Input/Output buffer (2.7V~3.6V) this
input sho uld be tied directly to VC C
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH V OLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q15
A0-AM
AM: MSB address
CE#
OE#
WE#
RESET#
ACC
WP#
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Table 1. BLOCK STRUCTURE
Sector A21 A20 A19 A18 A 17 A16 A15 16-bit Address Range
(in hexadecimal)
SA0 0 0 0 0 0 0 0 000000-007FFF
SA1 0 0 0 0 0 0 1 008000-00FFFF
SA2 0 0 0 0 0 1 0 010000-017FFF
SA3 0 0 0 0 0 1 1 018000-01FFFF
SA4 0 0 0 0 1 0 0 020000-027FFF
SA5 0 0 0 0 1 0 1 028000-02FFFF
SA6 0 0 0 0 1 1 0 030000-037FFF
SA7 0 0 0 0 1 1 1 038000-03FFFF
SA8 0 0 0 1 0 0 0 040000-047FFF
SA9 0 0 0 1 0 0 1 048000-04FFFF
SA10 0 0 0 1 0 1 0 050000-057FFF
SA11 0 0 0 1 0 1 1 058000-05FFFF
SA12 0 0 0 1 1 0 0 060000-067FFF
SA13 0 0 0 1 1 0 1 068000-06FFFF
SA14 0 0 0 1 1 1 0 070000-077FFF
SA15 0 0 0 1 1 1 1 078000-07FFFF
SA16 0 0 1 0 0 0 0 080000-087FFF
SA17 0 0 1 0 0 0 1 088000-08FFFF
SA18 0 0 1 0 0 1 0 090000-097FFF
SA19 0 0 1 0 0 1 1 098000-09FFFF
SA20 0 0 1 0 1 0 0 0A0000-0A7FFF
SA21 0 0 1 0 1 0 1 0A8000-0AFFFF
SA22 0 0 1 0 1 1 0 0B0000-0B7FFF
SA23 0 0 1 0 1 1 1 0B8000-0BFFFF
SA24 0 0 1 1 0 0 0 0C0000-0C7FFF
SA25 0 0 1 1 0 0 1 0C8000-0CFFFF
SA26 0 0 1 1 0 1 0 0D0000-0D7FFF
SA27 0 0 1 1 0 1 1 0D8000-0DFFFF
SA28 0 0 1 1 1 0 0 0E0000-0E7FFF
SA29 0 0 1 1 1 0 1 0E8000-0EFFFF
SA30 0 0 1 1 1 1 0 0F0000-0F7FFF
SA31 0 0 1 1 1 1 1 0F8000-0FFFFF
SA32 0 1 0 0 0 0 0 100000-10FFFF
SA33 0 1 0 0 0 0 1 108000-10FFFF
SA34 0 1 0 0 0 1 0 110000-117FFF
SA35 0 1 0 0 0 1 1 118000-11FFFF
SA36 0 1 0 0 1 0 0 120000-127FFF
SA37 0 1 0 0 1 0 1 128000-12FFFF
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Sector A21 A20 A19 A18 A1 7 A16 A15 16-bit Address Range
(in hexadecimal)
SA38 0 1 0 0 1 1 0 130000-137FFF
SA39 0 1 0 0 1 1 1 138000-13FFFF
SA40 0 1 0 1 0 0 0 140000-147FFF
SA41 0 1 0 1 0 0 1 148000-14FFFF
SA42 0 1 0 1 0 1 0 150000-157FFF
SA43 0 1 0 1 0 1 1 158000-15FFFF
SA44 0 1 0 1 1 0 0 160000-167FFF
SA45 0 1 0 1 1 0 1 168000-16FFFF
SA46 0 1 0 1 1 1 0 170000-177FFF
SA47 0 1 0 1 1 1 1 178000-17FFFF
SA48 0 1 1 0 0 0 0 180000-187FFF
SA49 0 1 1 0 0 0 1 188000-18FFFF
SA50 0 1 1 0 0 1 0 190000-197FFF
SA51 0 1 1 0 0 1 1 198000-19FFFF
SA52 0 1 1 0 1 0 0 1A0000-1A7FFF
SA53 0 1 1 0 1 0 1 1A8000-1AFFFF
SA54 0 1 1 0 1 1 0 1B0000-1B7FFF
SA55 0 1 1 0 1 1 1 1B8000-1BFFFF
SA56 0 1 1 1 0 0 0 1C0000-1C7FFF
SA57 0 1 1 1 0 0 1 1C8000-1CFFFF
SA58 0 1 1 1 0 1 0 1D0000-1D7FFF
SA59 0 1 1 1 0 1 1 1D8000-1DFFFF
SA60 0 1 1 1 1 0 0 1E0000-1E7FFF
SA61 0 1 1 1 1 0 1 1E8000-1EFFFF
SA62 0 1 1 1 1 1 0 1F0000-1F7FFF
SA63 0 1 1 1 1 1 1 1F8000-1FFFFF
SA64 1 0 0 0 0 0 0 200000-207FFF
SA65 1 0 0 0 0 0 1 208000-20FFFF
SA66 1 0 0 0 0 1 0 210000-217FFF
SA67 1 0 0 0 0 1 1 218000-21FFFF
SA68 1 0 0 0 1 0 0 220000-227FFF
SA69 1 0 0 0 1 0 1 228000-22FFFF
SA70 1 0 0 0 1 1 0 230000-237FFF
SA71 1 0 0 0 1 1 1 238000-23FFFF
SA72 1 0 0 1 0 0 0 240000-247FFF
SA73 1 0 0 1 0 0 1 248000-24FFFF
SA74 1 0 0 1 0 1 0 250000-257FFF
SA75 1 0 0 1 0 1 1 258000-25FFFF
SA76 1 0 0 1 1 0 0 260000-267FFF
SA77 1 0 0 1 1 0 1 268000-26FFFF
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Sector A21 A20 A19 A18 A17 A16 A15 16-bit Address Range
(in hexadecimal)
SA78 1 001110 270000-277FFF
SA79 1 001111 278000-27FFFF
SA80 1 010000 280000-287FFF
SA81 1 010001 288000-28FFFF
SA82 1 010010 290000-297FFF
SA83 1 010011 298000-29FFFF
SA84 1 010100 2A0000-2A7FFF
SA85 1 010101 2A8000-2AFFFF
SA86 1 010110 2B0000-2B7FFF
SA87 1 010111 2B8000-2BFFFF
SA88 1 011000 2C0000-2C7FFF
SA89 1 011001 2C8000-2CFFFF
SA90 1 011010 2D0000-2D7FFF
SA91 1 011011 2D8000-2DFFFF
SA92 1 011100 2E0000-2E7FFF
SA93 1 011101 2E8000-2EFFFF
SA94 1 011110 2F0000-2F7FFF
SA95 1 011111 2F8000-2FFFFF
SA96 1 100000 300000-307FFF
SA97 1 100001 308000-30FFFF
SA98 1 100010 310000-317FFF
SA99 1 100011 318000-31FFFF
SA100 1 100100 320000-327FFF
SA101 1 100101 328000-32FFFF
SA102 1 100110 330000-337FFF
SA103 1 100111 338000-33FFFF
SA104 1 101000 340000-347FFF
SA105 1 101001 348000-34FFFF
SA106 1 101010 350000-357FFF
SA107 1 101011 358000-35FFFF
SA108 1 101100 360000-367FFF
SA109 1 101101 368000-36FFFF
SA110 1 101110 370000-377FFF
SA111 1 101111 378000-37FFFF
SA112 1 110000 380000-387FFF
SA113 1 110001 388000-38FFFF
SA114 1 110010 390000-397FFF
SA115 1 110011 398000-39FFFF
SA116 1 110100 3A0000-3A7FFF
SA117 1 110101 3A8000-3AFFFF
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Sector A21 A20 A19 A18 A1 7 A16 A15 16-bit Address Range
(in hexadecimal)
SA118 1 1 1 0 1 1 0 3B0000-3B7FFF
SA119 1 1 1 0 1 1 1 3B8000-3BFFFF
SA120 1 1 1 1 0 0 0 3C0000-3C7FFF
SA121 1 1 1 1 0 0 1 3C8000-3CFFFF
SA122 1 1 1 1 0 1 0 3D0000-3D7FFF
SA123 1 1 1 1 0 1 1 3D8000-3DFFFF
SA124 1 1 1 1 1 0 0 3E0000-3E7FFF
SA125 1 1 1 1 1 0 1 3E8000-3EFFFF
SA126 1 1 1 1 1 1 0 3F0000-3F7FFF
SA127 1 1 1 1 1 1 1 3F8000-3FFFFF
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
T able 2. BUS OPERA TION--1
Notes:
1. All secto rs will be unpro tected if WP#/A CC=Vhv.
2. The first sector is protected if WP#/A CC=Vil.
3. When WP#/ACC = Vih, the pro tection conditio ns of the first sector depend o n previo us protectio n conditions."Secto r/
Secto r Blo ck Pro tection and Unprotectio n" describes the protect and unpro tect method.
4. Q0~Q15 are input (DIN) or output (DOUT) pins acco rding to the requests of command sequence, secto r protection,
or data po lling algorithm.
5. In Word Mo de, the addresses are AM to A0.
6. AM: MSB of address.
Mode Select RE- CE# WE# OE# Address Data ACC WP#
SET# (I/O)
Q0~Q15
Device Reset L X X X X HighZ X X
Standby Mo de Vcc±Vcc±X X X HighZ H X
0.3V 0.3V
Output H L H H X HighZ X X
Disable
Read Mode H L H L AIN DOUT X X
Write (Note1) H L L H AIN DIN X No te3
Accelerate H L L H AIN DIN Vhv Note3
Program
Temporary Vhv X X X AIN DIN X H
Sector-Group
Unprotect
Se cto r- Group Vhv L L H Secto r Address, DIN, DOUT X H
Pro tect (Note2) A6=L, A1=H,
A0=L
Chip Vhv L L H Sector Address, DIN, DOUT X H
Unprotect A6=H, A1=H,
(Note2) A0=L
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
BUS OPERA TION--2
Item Control Input AM A1 1 A 8 A 5
CE# WE# OE# to to A9 to A6 to A1 A0 Q0~Q15
A12 A10 A7 A2
Sector Lock Status L H L SA x Vhv x L x H L 01h or
Verification 00h
(Note1)
Read Silico n ID L H L x x Vhv x L x L L C2H
Manufacturer Code
Read Silico n ID L H L x x Vhv x L x L H 22D7H
Device Code
Read Indicator Bit L H L x x Vhv x L x H H (Note2)
(Q7) Fo r Security
Sector
Notes:
1. Sector unpro tected code:00h. Sector pro tected code:01h.
2. Facto ry lo cked co de: WP# pro tects highest address sector: XX98H
WP# pro tects lowest address secto r: XX88H
F actory unlo cked code: WP# pro tects highest address sector: XX18H
WP# pro tects lowest address secto r: XX08H
3. AM: MSB of address.
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
WRITE COMMANDS/COMMAND SEQUENCES
To write a co mmand to the de vice, system m ust drive WE# and CE# to Vil, and OE# to Vih. In a command cycle, all
address are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising edge of CE#
and WE#.
Figure 1 illustrates the A C timing wavefo rm of a write co mmand, and Table 3 defines all the valid command sets o f the
device. System is not allowed to write invalid commands no t defined in this datasheet. Writing an invalid command will
bring the device to an undefined state.
REQUIREMENTS FOR READING ARRAY DA T A
Read array actio n is to read the data stored in the array . While the memo ry device is in powered up o r has been reset,
it will auto matically enter the status of read array. If the micropro cessor wants to read the data sto red in the arra y , it has
to drive CE# (device enab le co ntrol pin) and OE# (Output co ntro l pin) as Vil, and input the address o f the data to be
read into address pin at the same time. After a per iod of read cycle (Tce or Taa), the data being read out will be
displayed o n output pin fo r micro processor to access. If CE# or OE# is Vih, the output will be in tri-state, and there will
be no data displa yed on output pin at all.
After the memo ry device co mpletes embedded o peratio n (automatic Erase o r Pro gram), it will auto matically return to
the status o f read arra y, and the device can read the data in any address in the arra y. In the pro cess o f erasing, if the
de vice receiv es the Er ase suspend command, erase o peration will be stopped tempo r arily after a perio d of time no
mo re than Tready and the device will return to the status o f read array. At this time, the device can read the data stored
in any address e xcept the sector being erased in the arra y. In the status of erase suspend, if user wants to read the
data in the secto rs being er ased, the device will o utput status data onto the o utput. Similarly, if pro gram command is
issued after erase suspend, after program operation is completed, system can still read array data in any address
e xcept the sectors to be erased.
The device needs to issue reset co mmand to enable read array operatio n again in order to arbitrarily read the data in
the arra y in the following two situatio ns:
1. In pro gram o r erase o peratio n, the programming o r erasing failure causes Q5 to go high.
2. The de vice is in auto select mode o r CFI mode.
In the two situations above, if reset command is not issued, the device is not in read array mode and system must
issue reset co mmand befo re reading array data.
ACCELERA TED PROGRAM OPERA TION
he device o ffers accelerated program operatio ns through
the ACC function. This is one of two functions provided by the ACC pin. This function is primarily intended to allow
faster manufacturing thro ughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned accelerated pro gram mo de,
temporarily unpro tects any protected secto rs , and uses the higher voltage o n the pin to reduce the time required f or
program operations. Removing VHH from the ACC pin must not be at VHH for operations other than accelerated
pro gramming, o r device damage may result.
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
RESET# OPERA TION
Driving RESET# pin low fo r a perio d mo re than Trp will reset the device back to read mo de. If the device is in pro gram
o r erase o peratio n, the reset operatio n will take at mo st a period o f Tready for the device to return to read arra y mode.
Bef o re the de vice returns to read array mo d e, the R Y/BY# pin remains low (b usy status).
When RESET# pin is held at GND±0.3V, the device consumes standby current(Isb).Howe ver, device dr aws larger
current if RESET# pin is held at Vil b ut not within GND±0.3V.
It is reco mmended that the system to tie its reset signal to RESET# pin of flash memory , so that the flash memo ry will
be reset during system reset and allows system to read bo ot co de fro m flash memo ry.
SECTOR GROUP PROTECT OPERA TION
When a sector group is protected, program or erase operation will be disabled on these sectors. MX29LV640BU
pro vides two metho ds for sector group pro tection.
Once the sector group is protected, the sector group remains protected until next chip unprotect, or is temporarily
unpro tected by asserting RESET# pin at Vhv . Refer to tempo rary secto r gro up unprotect o peration fo r further details.
The first method is by applying Vhv on RESET# pin. Refer to Figure 13 for timing diagram and Figure 14 for the
algo rithm f or this method.
The o ther method is asserting Vhv on A9 and OE# pins, with A6 and CE# at Vil. The pro tection o peratio n begins at the
f alling edge o f WE# and terminates at the rising edge. Co ntact Macro nix f o r details.
CHIP UNPROTECT OPERA TION
MX29LV640BU pro vides two metho ds fo r chip unpro tect. The chip unpro tect operatio n unpro tects all sectors within the
de vice. It is recommended to pro tect all secto rs bef o re activ ating chip unpro tect mo de . All secto rs gr o ups are unpro-
tected when shipped fro m the facto ry.
The first metho d is by applying Vhv o n RESET# pin. Refer to Figure 13 fo r timing diagram and Figure 14 for algorithm
o f the operation.
The other method is asserting Vhv o n A9 and OE# pins, with A6 at Vih and CE# at Vil (see Tab le 2). The unprotect
o peratio n begins at the f alling edge o f WE# and terminates at the rising edge. Co ntact Macro nix fo r details.
TEMPORAR Y SECTOR GROUP UNPROTECT OPERA TION
System can apply RESET# pin at Vhv to place the device in temporar y unprotect mode. In this mode, previously
pro tected sectors can be programmed o r erased just as it is unprotected. The devices returns to normal operation once
Vhv is remo v ed fro m RESET# pin and previo usly pro tected secto rs are again pro tected.
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
WRITE PROTECT (WP#)
This Write Pro tect functio n pro vides a hardware pro tectio n metho d on the first secto r without using VID .
If the system asserts VIL on the WP# pin, the de vice disab le pro gram and er ase functio n in the first sector indepen-
dently o f whether tho se secto rs were pro tected o r unpro tect using the method described in "Secto r Gro up Pro tectio n
and Unprotect".
If the system asser ts VIH on the WP# pin, the device reverts to whether the first sector was previously set to be
pro tected or unpro tected using the method described in "Sector Group Pro tection and Unpro tect".
AUTOMA TIC SELECT OPERA TION
When the device is in Read array mode, erase-suspended read array mo de o r CFI mode, user can issue read silico n
ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs
continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will output Macronix
Manuf acture ID C2H. When A0 is high, device will o utput De vice ID . In read silico n ID mo de, issuing reset co mmand
will reset device bac k to read array mo de o r erase-suspended read array mo de.
Ano ther way to enter read silico n ID is to apply high vo ltage o n A9 pin with CE#, OE#, A6 and A1 at Vil. While the high
v o ltage o f A9 pin is discharged, device will automatically leav e read silico n ID mo de and go back to read arra y mo de
or erase-suspended read arra y mo d e. When A0 is Lo w , de vice will output Macro nix Manuf acture ID C2. When A0 is
high, de vice will output Device ID.
VERIFY SECTOR GROUP PROTECT ST A TUS OPERATION
MX29LV640BU pro vides hardware secto r protectio n against Pro gram and Erase o peration fo r pro tected sectors. The
secto r pro tect status can be read thro ugh Secto r Pro tect V erify co mmand. This metho d requires Vhv o n A9 pin, Vih o n
WE# and A1 pins, Vil o n CE#, OE#, A6 and A0 pins , and sector address o n A12 to A21 pins . If the read o ut data is
01H, the designated secto r is protected. Oppositely , if the read o ut data is 00H, the designated secto r is not pro tected.
SECURITY SECTOR FLASH MEMOR Y REGION
The Security Sector region is an extra memo ry space o f 128 words in length. The security sectors can be lo cked upo n
shipping from factor y, or it can be locked by customer after shipping. Customer can issue Security Sector Factor y
Protect Verify and/o r Security Sector Pro tect Verify to query the lo c k status of the de vice.
In facto ry-locked device, security secto r regio n is protected when shipped fro m factory and the security silico n secto r
indicato r bit is set to "1". In customer lo ckable device, security secto r region is unpro tected when shipped from facto ry
and the security silico n indicator bit is set to "0".
Factory Locked: Security Sector Programmed and Protected at the Factory
In a facto ry locked device, the security silico n region is permanently locked after shipping from facto ry. The device will
have a 8-wo rd ESN in the security region. In unifo rm de vice : 000000h - 000007h (fo r MX29LV640BU).
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Customer Lockable: Security Sector NOT Programmed or Protected at the Factory
When the security feature is no t required, the security regio n can act as an extra memo ry space. The security silico n
secto r can be read, pro grammed, o r erased just as no rmal secto rs with the same endurance limitatio ns.
Security silico n secto r can also be protected by two methods. Note that once the security silicon sector is pro tected,
there is no wa y to unprotect the security silico n sector and the co ntent of it can no lo nger be altered.
The first metho d is to write a three-cycle command of Enter Security Regio n, and then fo llow the secto r group protect
algo rithm as illustrated in Figure 14, e xcept that RESET# pin ma y at either Vih o r Vhv.
The o ther method is to write a three-cycle command o f Enter Security Region, and then follow the alternate metho d o f
sector pro tect with A9, OE# at Vhv.
After the security silico n is lo ck ed and verified, system must write Exit Security Sector Region o r go thro ugh a power
cycle, o r issue a hardw are reset to return the de vice to read no rmal arra y mo de.
DA T A PROTECTION
To avo id accidental erasure o r pro gramming o f the device, the device is auto matically reset to read array mode during
pow er up. Besides, o nly after successful co mpletio n o f the specified co mmand sets will the de vice begin its erase o r
program operation.
Other features to protect the data fro m accidental alternatio n are described as fo llowed.
LOW VCC WRITE INHIBIT
The device refuses to accept any write command when Vcc is less than VLKO. This prevents data from spuriously
altered. The de vice auto matically resets itself when Vcc is low er than VLK O and write cycles are igno red until Vcc is
greater than VLKO. System must pro vide proper signals on control pins after Vcc is larger than VLKO to avo id uninten-
tio nal program o r erase operation
WRITE PULSE "GLITCH" PRO TECTION
CE#, WE#, OE# pulses sho rter than 5ns are treated as glitches and will no t be regarded as an effectiv e write cycle.
LOGICAL INHIBIT
A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is igno red when either CE# at Vih,
WE# a Vih, o r OE# at Vil.
POWER-UP SEQUENCE
Upo n power up, MX29LV640BU is placed in read array mode. Furthermo re, program or erase operation will begin o nly
after successful co mpletio n o f specified co mmand sequences .
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MX29LV640BU
POWER-UP WRITE INHIBIT
When WE#, CE# is held at Vil and OE# is held at Vih during pow er up , the device igno res the first command o n the
rising edge of WE#.
PO WER SUPPLY DECOUPLING
A 0.1uF capacito r sho uld be connected between the Vcc and GND to reduce the no ise effect.
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
T ABLE 3. MX29L V640BU COMMAND DEFINITIONS
Notes:
1. Facto ry lo cked co de: WP# pro tects highest address secto r: XX98H
WP# pro tects lowest address secto r: XX88H
F actory unlo cked co de: WP# pro tects highest address secto r: XX18H
WP# pro tects lowest address secto r: XX08H
S ilic on ID Device
ID
y
Sector
Factory Protect
Verify
1s t Bus Cy c A ddr A ddr XXX 555 555 555 555 555 555
Data Data F0 AA AA AA AA AA AA
2nd Bus Cy c A ddr 2AA 2A A 2AA 2AA 2AA 2A A
Data 55 55 55 55 55 55
3rd Bus Cy c A ddr 555 555 555 555 555 555
Data 90 90 90 90 88 90
4t h B us Cy c A ddr X 00 X01 X03 (Sector)
X02 XXX
Data C2H 22D7H (Note1) 00/01 0
5t h B us Cy c A ddr
Data
6t h B us Cy c A ddr
Data
Exit
Security
Sector
Automatic Select
Enter Sec urity
S ec t or Region
Command Read
Mode Reset
Mode
1s t B us Cy c A ddr 555 555 555 55 XX XX
Data AA AA AA 98 B0 30
2nd B us Cy c A ddr 2A A 2A A 2A A
Data 55 55 55
3rd B us Cy c A ddr 555 555 555
Data A0 80 80
4t h B us Cy c A ddr A ddr 555 555
Data Data AA AA
5t h B us Cy c A ddr 2AA 2A A
Data 55 55
6t h B us Cy c A ddr 555 S ec t or
Data 10 30
Erase
Resume
ProgramCommand Chip
Erase Sector
Erase CFI
Read Erase
Suspend
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
RESET
In the f ollowing situations, e x ecuting reset co mmand will reset device back to read arra y mode:
•Amo ng erase command sequence (before the full command set is co mpleted)
•Secto r erase time-o ut perio d
•Erase fail (while Q5 is high)
•Among program command sequence (before the full command set is completed, erase-suspended program in-
cluded)
•Pro gram fail (while Q5 is high, and erase-suspended pro gram fail is included)
•Read silico n ID mo de
•Secto r protect verify
•CFI mo de
While de vice is at the status o f prog ram fail o r erase f ail (Q5 is high), user must issue reset co mmand to reset device
back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode, user must
issue reset command to reset de vice back to read arra y mode.
When the device is in the progress of pro gramming (not program fail) or erasing (not erase fail), de vice will ignore reset
command.
AUTOMA TIC SELECT COMMAND SEQUENCE
A uto matic Select mo de is used to access the manufacturer ID , de vice ID and to verify whether o r no t secured silico n
is lo cked and whether or no t a sector is pro tected. The automatic select mo de has fo ur co mmand cycles. The first two
are unlo ck cycles, and fo llowed by a specific co mmand. The fo urth cycle is a normal read cycle, and user can read at
any address any number of times witho ut entering ano ther co mmand sequence. The reset co mmand is necessary to
e xit the A utomatic Select mode and back to read arra y. The f ollowing tab le shows the identification code with corre-
sponding address.
Address Data (Hex) Representation
Manufacturer ID X00 C 2
Device ID X0 1 22D7 Top/Bo ttom Boot Sector
Secured Silico n X03 98/18, 88/08 Factory locked/unlocked
Secto r Pro tect Verify (Secto r address) X 02 00/01 Unprotected/protected
There is an alternative metho d to that shown in Table 2, which is intended for EPROM pro grammers and requires Vhv
o n address bit A9.
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
AUTOMA TIC PROGRAMMING
The MX29LV640BU can pro vide the user pro gram functio n by the fo rm o f Wo rd-Mo de. As lo ng as the users enter the
right cycle defined in the Table.3 (including 2 unlock cycles and A0H), any data user inputs will automatically be
pro grammed into the array .
Once the pro gram function is executed, the internal write state contro ller will automatically ex ecute the algorithms and
timings necessary fo r pro gram and verificatio n, which includes generating suitable pro gram pulse, verifying whether
the threshold vo ltage of the programmed cell is high enough and repeating the pro gram pulse if any o f the cells does not
pass verificatio n. Meanwhile, the internal co ntro l will pro hibit the pro gramming to cells that pass verificatio n while the
other cells fail in verification in order to avoid over-programming. With the inter nal wr ite state controller, the device
requires the user to write the pro gram co mmand and data only.
Pro gramming will o nly change the bit status from "1" to "0". That is to say, it is impo ssible to co nvert the bit status fro m
"0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not
successfully pro grammed to "0".
Any co mmand written to the device during programming will be ignored except hardware reset, which will terminate the
program o peration after a period of time no more than T ready. When the embedded program algo rithm is complete or the
pro gram o peratio n is terminated by hardware reset, the device will return to the reading array data mo de.
The typical chip pro gr am time at ro o m temperature o f the MX29LV640BU is less than 45 seco nds.
When the embedded program o peration is on going, user can co nfirm if the embedded operation is finished or no t by the
following metho ds:
Status Q7 Q6 Q5 RY/BY#*2
In progress*1 Q7# To ggling 0 0
Finished Q7 Sto p toggling 0 1
Exceed time limit Q7# Toggling 1 0
*1: The status "in progress" means both program mo de and erase-suspended program mo de.
*2: RY/BY# is an o pen drain o utput pin and should be weakly co nnected to VDD thro ugh a pull-up resistor .
*3: When an attempt is made to program a protected sector, Q7 will o utput its complement data o r Q6 continues to
toggle for about 1us or less and the device returns to read array state witho ut programing the data in the protected
sector.
*4: The Q5 failure co ndition may appear if the system tries to program a to a "1" lo cation that is previo usly programmed
to "0". Only an erase o peration can change a "0" back to a "1".
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MX29LV640BU
SECTOR ERASE
Secto r Erase is to erase all the data in a secto r with "1" and "0" as all "1". It requires six command cycles to issue. The
first two cycles are "unlock cycles", the third o ne is a configuratio n cycle, the f o urth and fifth are also "unlock cycles"
and the sixth cycle is the secto r erase command. After the secto r erase co mmand sequence is issued, there is a time-
o ut perio d of 50us counted internally . During the time-out perio d, additional sector address and sector erase co mmand
can be written multiply. Once user enters ano ther sector erase co mmand, the time-o ut perio d o f 50us is reco unted. If
user enters any co mmand other than sector erase or erase suspend during time-o ut perio d, the erase command would
be abor ted and the device is reset to read array condition. The number of sectors could be from one sector to all
secto rs. After time-o ut perio d passing by, additio nal erase co mmand is not accepted and erase embedded o peratio n
begins.
During secto r er asing, all commands will no t be accepted except hardware reset and erase suspend and user can
check the status as chip erase.
When the embedded chip erase o peratio n is on going, user can confirm if the embedded o peration is finished or no t by
the fo llowing methods:
Status Q7 Q6 Q5 Q2 RY/BY#
In pro gress 0 To ggling 0 Toggling 0
Finished 1 1 1 1 1
Exceed time limit 0 Toggling 1 Toggling 0
CHIP ERASE
Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the actio n in, and the first two
cycles are "unlo ck" cycles , the third o ne is a co nfiguration cycle, the fourth and fifth are also "unlo ck" cycles , and the
sixth cycle is the chip erase operatio n.
During chip erasing, all the co mmands will not be accepted except hardware reset or the wo rking voltage is too low that
chip erase will be interrupted. After Chip Erase, the chip will return to the state o f Read Arra y.
*1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible to
ano ther secto r address to be erased. When Q3=1, the de vice is in erase o peratio n and o nly er ase suspend is valid.
*2: R Y/BY# is open drain output pin and sho uld be weakly co nnected to VDD through a pull-up resisto r.
*3: When an attempt is made to erase a protected secto r, Q7 will o utput its complement data o r Q6 co ntinues to toggle
f o r 100us o r less and the de vice returned to read arra y status witho ut erasing the data in the pro tected secto r .
When the embedded erase o peration is o n go ing, user can confirm if the embedded o peratio n is finished or no t by the
fo llowing metho ds:
Status Q7 Q6 Q5 Q3 Q2 RY/BY#*2
Time-out period 0 Toggling 0 0 Toggling 0
In pro gress read in erase secto r 0 To ggling 0 1 Toggling 0
read in non-erase secto r 0 To ggling 0 1 Stop Toggling 0
Finished 1 1 1 1 1 1
Exceed time limit 0 Toggling 1 1 Toggling 0
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
When the device has suspended er asing, user can e x ecute the co mmand sets e xcept secto r erase and chip erase ,
such as read silico n ID , secto r pro tect v erify, pro gram, CFI query and erase resume.
SECTOR ERASE RESUME
Secto r erase resume co mmand is valid o nly when the device is in erase suspend state. After erase resume, user can
issue another erase suspend command, but there sho uld be a 4mS interval between erase resume and the next erase
suspend. If user issue infinite suspend-resume loo p, or suspend-resume exceeds 1024 times, the time fo r erasing will
increase.
Status Q7 Q6 Q5 Q3 Q2 RY/BY#
Erase suspend read in erase suspended secto r 1 No to ggle 0 N/A Toggle 1
Erase suspend read in no n-erase suspended secto r Data Data Data Data Data 1
Erase suspend pro gram in no n-erase suspended sector Q7# To ggle 0 N/A N/A 0
SECTOR ERASE SUSPEND
During sector erasure, secto r erase suspend is the o nly valid co mmand. If user issue erase suspend co mmand in the
time-o ut perio d o f sector erasure, device time-o ut perio d will be o ver immediately and the device will go back to erase-
suspended read array mode. If user issue erase suspend co mmand during the sector erase is being operated, device
will suspend the o ngo ing erase o peratio n, and after the Tready1 (<=20us) suspend finishes and the device will enter
erase-suspended read array mo de. User can judge if the device has finished erase suspend through Q6, Q7, and RY/
BY#.
After device has entered erase-suspended read array mo de, user can read o ther secto rs not at erase suspend by the
speed o f Taa; while reading the secto r in erase-suspend mo de, device will o utput its status. User can use Q6 and Q2
to judge the secto r is erasing or the erase is suspended.
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
T able 4-1. CFI mode: Identification Data V alues
(All values in these tables are in hexadecimal)
T able 4-2. CFI Mode: System Interface Data V alues
QUER Y COMMAND AND COMMON FLASH INTERFACE (CFI) MODE
MX29LV640BU features CFI mode. Host system can retrieve the operating characteristics, structure and vendor -
specified informatio n such as identifying info rmation, memory size, wo rd configuratio n, operating voltages and timing
informatio n of this device by CFI mo de. The device enters the CFI Query mode when the system writes the CFI Query
co mmand, 98H, to address 55H any time the device is ready to read array data. The system can read CFI info rmatio n
at the addresses given in Table 4. A reset co mmand is required to exit CFI mo de and go back to ready arra y mo de o r
erase suspend mode. The system can write the CFI Query command only when the device is in read mode, erase
suspend, standby mo de o r auto matic select mo de.
Description Address (h) Data (h)
(Word Mode)
Query-unique ASCII string "QRY" 1 0 0051
11 0052
12 0059
Primary vendor command set and control interface ID code 1 3 0002
14 0000
Address for primary algorithm extended query table 1 5 0040
16 0000
Alternate vendor command set and control interface ID code 1 7 0000
18 0000
Address for alternate algorithm extended query table 19 0000
1A 0000
Description Address (h) Data (h)
(Word Mode)
Vcc supply minimum program/erase voltage 1B 0027
Vcc supply maximum program/erase voltage 1 C 0036
VPP supply minimum program/erase voltage 1 D 0000
VPP supply maximum program/erase voltage 1E 0000
Typical timeout per single word write, 2n us 1F 0004
Typical timeout for maximum-size buffer write, 2n us 2 0 0000
Typical timeout per individual block erase, 2n ms 2 1 000A
Typical timeout for full chip erase, 2n ms 2 2 0000
Maximum timeout for word write, 2n times typical 23 0005
Maximum timeout for buffer write, 2n times typical 24 0000
Maximum timeout per individual block erase, 2n times typical 2 5 0004
Maximum timeout for chip erase, 2n times typical 26 0000
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
T able 4-3. CFI Mode: Device Geometry Data V alues
Description Address (h) Data (h)
(Word Mode)
Device size = 2n in number of bytes 27 0017
Flash device interface description (02=asynchronous x8/x16) 2 8 0002
29 0000
Maximum number of bytes in buffer write = 2n (not support) 2A 0000
2B 0000
Number of erase regions within device 2 C 0002
Index for Erase Bank Area 1 2D 0007
[2E,2D] = # of same-size sectors in region 1-1 2E 0000
[30, 2F] = sector size in multiples of 256-bytes 2F 0020
30 0000
Index for Erase Bank Area 2 31 007E
32 0000
33 0000
34 0001
Index for Erase Bank Area 3 35 0000
36 0000
37 0000
38 0000
Index for Erase Bank Area 4 39 0000
3A 0000
3B 0000
3C 0000
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
T able 4-4. CFI Mode: Primary V endor-Specific Extended Query Data V alues
Description Address (h) Data (h)
(Word Mode)
Query - Primary extended table, unique ASCII string, PRI 4 0 0050
41 0052
42 0049
Major version number, ASCII 4 3 0031
Minor version number, ASCII 4 4 0031
Unlock recognizes address (0= recognize, 1= don't recognize) 4 5 0000
Erase suspend (2= to both read and program) 4 6 0002
Sector protect (N= # of sectors/group) 4 7 0004
Temporary sector unprotect (1=supported) 48 0001
Sector protect/Chip unprotect scheme 49 0004
Simultaneous R/W operation (0=not supported) 4A 0000
Burst mode (0=not supported) 4B 0000
Page mode (0=not supported) 4C 0000
Maximum acceleration supply (0= not supported), [D7:D4] for volt, 4 D 00B5
[D3:D0] for 100mV
Minimum acceleration supply (0= not supported), [D7:D4] for volt, 4E 00C5
[D3:D0] for 100mV
Top/Bottom boot block indicator 4 F 0002/
02h=bottom boot device 03h=top boot device 0003
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
ABSOLUTE MAXIMUM STRESS RATINGS
Surrounding Temperature with Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +125oC
Storage Temperature . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 oC to +150oC
V oltage Range
Vcc . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
A9, OE#, ACC and RESET# . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +12.5 V
The other pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to Vcc +0.5 V
Output Short Circuit Current (less than o ne second) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA
OPERATING TEMPERATURE AND VOLTAGE
Commercial (C) Grade
Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial (I) Grade
Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40°C to +85°C
VCC Supply Voltages
VCC range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to 3.6 V
25
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
DC CHARACTERISTICS
Symbol Description Min Typ Max Remark
Iilk Input Leak ± 1.0uA
Iilk9 A9 Leak 35uA A9=12.5V
Iolk Output Leak ± 1.0uA
Icr1 Read Current(5MHz) 9mA 16mA CE#=Vil,
OE#=Vih
Icr2 Read Current(1MHz) 2mA 4mA CE#=Vil,
OE#=Vih
Icw Write Current 26mA 30mA CE#=Vil,
OE#=Vih,
WE#=Vil
Isb Standby Current 0.2uA 15uA Vcc=Vcc max,
o ther pin disable
Isbr Reset Current 0.2uA 15uA Vcc=Vccmax,
Reset# enable,
o ther pin disable
Isbs Sleep Mo de Current 0.2uA 15uA
Icp1 Accelerated Pgm Current, 5mA 10mA CE#=Vil,
ACC pin OE#=Vih,
Icp2 Accelerated Pgm Current, 15mA 30mA CE#=Vil,
Vcc pin OE#=Vih,
Vil Input Low V oltage -0.5V 0.8V
Vih Input High V oltage 0.7xVcc Vcc+0.3V
Vhv V ery High V o ltage fo r hardware 11.5V 12.5V
Protect/Unprotect/Accelerated
Program/Auto Select/Temporary
Unprotect
V o l Output Low Voltage 0.45V Io l=4.0mA
V oh1 Ouput High V oltage 0.85xVcc Ioh1=-2mA
V oh2 Ouput High V oltage Vcc-0.4V Io h2=-100uA
Vlko Low VCC Lock-Out Voltage 1.5V
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
SWITCHING TEST CIRCUITS
Test Condition
Output Lo ad : 1 TTL gate
Output Lo ad Capacitance,CL : 30pF
Rise/Fall Times : 5ns
In/Out reference levels :1.5V
SWITCHING TEST WAVEFORMS
1.5V 1.5V
Test Points
3.0V
0.0V OUTPUT
INPUT
R1=6.2K ohm
R2=2.7K ohm
TESTED DEVICE
DIODES=IN3064
OR EQUIVALENT
CL
R1
Vcc
0.1uF R2 +3.3V
27
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
AC CHARACTERISTICS
Symbol Description Min Typ Max Unit
Taa V alid data o utput after address 90/120 ns
Tce V alid data o utput after CE# lo w 90/120 ns
Toe V alid data o utput after OE# low 35/50 ns
Tdf Data output flo ating after OE# high 30/30 ns
Toh Output ho ld time fro m the earliest rising edge o f address, 0 ns
CE#, OE#
Trc Read perio d time 90/120 ns
Twc Write perio d time 90/120 ns
Tcwc Command write perio d time 90/120 ns
Tas Address setup time 0 ns
Ta h Address ho ld time 45/50 ns
Tds Data setup time 45/50 ns
Tdh Data ho ld time 0 ns
Tvcs Vcc setup time 50 us
Tcs Chip enable Setup time 0 ns
Tch Chip enable ho ld time 0 ns
To es Output enable setup time 0 ns
Toeh Read 0 ns
To e h Output enable ho ld time Toggle & 10 ns
Data# Polling
Tw s WE# setup time 0 ns
Tw h WE# hold time 0 ns
Tcep CE# pulse width 45/50 ns
Tceph CE# pulse width high 3 0 ns
Tw p WE# pulse width 35/50 ns
Twph WE# pulse width high 3 0 ns
Tbusy Pro g ram/Erase activ e time b y R Y/BY# 90 ns
Tghwl Read reco ver time bef ore write 0 ns
Tghel Read reco ver time befo re write 0 ns
T whwh1 Program operation 11 us
Twhwh1 Acc Program o peration 7 us
Twhwh2 Sector Erase Operation 1.6 sec
Tbal Secto r Add ho ld time 5 0 us
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 1. COMMAND WRITE OPERA TION
Addresses
CE#
OE#
WE#
DIN
Tds
Tah
Data
Tdh
Tcs Tch
Tcwc
Twph
Twp
Toes
Tas
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
VA
V A: Valid Address
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
READ/RESET OPERATION
Figure 2. READ TIMING W A VEFORMS
Addresses
CE#
OE#
Taa
WE#
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Voh
Vol
HIGH Z HIGH Z
D ATA V alid
Toe
Toeh Tdf
Tce
Trc
Outputs
Toh
ADD V alid
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 3. RESET# TIMING W AVEFORM
AC CHARACTERISTICS
Item Description Setup Speed Unit
Trp 1 RESET# Pulse Width (During Auto matic Algorithms) MIN 1 0 us
Trp 2 RESET# Pulse Width (NO T During Auto matic Algorithms) MIN 5 00 ns
Trh RESET# High Time Befo re Read MIN 5 0 ns
Tr b1 R Y/BY# Recovery Time (to CE#, OE# go low) MIN 0 ns
Tready1 RESET# PIN Low (During Automatic Algorithms) MAX 2 0 us
to Read or Write
Tready2 RESET# PIN Low (NOT During Auto matic MAX 500 ns
Algo rithms) to Read o r Write
Trh
Trb1
Trp2
Trp1
Tready2
Tready1
RY/BY#
CE#, OE#
RESET#
Reset Timing NOT during Automatic Algorithms
Reset Timing during Automatic Algorithms
RY/BY#
CE#, OE#
RESET#
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
ERASE/PROGRAM OPERATION
Figure 4. AUTOMA TIC CHIP ERASE TIMING W A VEFORM
Twc
Address
OE#
CE#
55h
2AAh SA
10h
In
Progress Complete
VA VA
Tas Tah
SA: 555h for chip erase
Tghwl
Tch
Twp
Tds Tdh
Read Status
Last 2 Erase Command Cycle
Tbusy Trb
Tcs Twph
WE#
Data
RY/BY#
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 5. AUTOMA TIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
YES
NO Data=FFh ?
Write Data 10H Address 555H
Write Data 55H Address 2AAH
Data# Polling Algorithm or
Toggle Bit Algorithm
Auto Chip Erase Completed
33
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 6. A UTOMATIC SECTOR ERASE TIMING W A VEFORM
Twc
Address
OE#
CE#
55h
2AAh Sector
Address 1
Sector
Address 0
30h
In
Progress Complete
VA VA
30h
Sector
Address n
Tas
Tah
Tbal
Tghwl
Tch
Twp
Tds Tdh
Twhwh2
Read Status
Last 2 Erase Command Cycle
Tbusy Trb
Tcs Twph
WE#
Data
RY/BY#
30h
34
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 7. A UTOMA TIC SECT OR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
Write Data 30H Sector Address
Write Data 55H Address 2AAH
Data# Polling Algorithm or
Toggle Bit Algorithm
Auto Sector Erase Completed
NO
Last Sector
to Erase
YES
YES
NO
Data=FFh
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P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 8. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
Toggle Bit checking Q6
not toggled
ERASE SUSPEND
YES
NO
Write Data 30H
Continue Erase
Reading or
Programming End
Read Array or
Program
Another
Erase Suspend ? NO
YES
YES
NO
ERASE RESUME
36
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 9. AUTOMA TIC PROGRAM TIMING W A VEFORMS
Address
OE#
CE#
A0h
555h PA
PD Status DOUT
VA VA
Tas Tah
Tghwl
Tch
Twp
Tds Tdh
Twhwh1
Last 2 Read Status CycleLast 2 Program Command Cycle
Tbusy Trb
Tcs Twph
WE#
Data
RY/BY#
Figure 10. Accelerated Program Timing Diagram
WP#/ACC
250nS 250nS
Vhv
Tvhh
(11.5V ~ 12.5V)
Vil or Vih Vil or Vih
37
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 11. CE# CONTROLLED WRITE TIMING W A VEFORM
Address
OE#
CE#
A0h
555h PA
PD Status DOUT
VA VA
Tas Tah
Tghwl
Tcep
Tds Tdh
Twhwh1 or Twhwh2
Tbusy
Tceph
WE#
Data
RY/BY#
38
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 12. A UTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Program Data/Address
Write Data A0H Address 555H
YES
Read Again Data:
Program Data?
YES
Auto Program Completed
Data# Polling Algorithm or
Toggle Bit Algorithm
next address
Last Word to be
Programed
No
No
39
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
SECTOR GROUP PROTECT/CHIP UNPROTECT
Figure 13. SECTOR GROUP PROTECT/CHIP UNPROTECT W A VEFORM (RESET# Control)
150uS: Sector Protect
15mS: Chip Unprotect
1us
Vhv
Vih
Data
SA, A6
A1, A0
CE#
WE#
OE#
VA VA VA
Status
VA: valid address
40h60h60h
Verification
RESET#
40
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 14-1. IN-SYSTEM SECTOR GROUP PRO TECT WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 60h
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 40h
Read at Sector Address
with [A6,A1,A0]:[0,1,0]
Wait 150us
Reset
PLSCNT=1
Temporary Unprotect Mode
RESET#=Vih
Write RESET CMD
Sector Protect Done
Device fail
Temporary Unprotect Mode
Retry Count +1
First CMD=60h?
Data=01h?
Retry Count=25?
Yes
YesYes
Yes
No
No
No
No
Protect another
sector?
41
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 14-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv
Write [A6,A1,A0]:[1,1,0]
data: 60h
Write [A6,A1,A0]:[1,1,0]
data: 40h
Read [A6,A1,A0]:[1,1,0]
Wait 15ms
Temporary Unprotect
Write reset CMD
Chip Unprotect Done
Retry Count +1
Device fail
All sectors
protected?
Data=00h?
Retry Count=1000?
Yes
Yes
No
No
Yes
Protect All Sectors
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect
First CMD=60h?
Yes
No
No
42
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 15. TEMPORAR Y SECTOR GROUP UNPROTECT WA VEFORMS
T able 5. TEMPORARY SECT OR GROUP UNPROTECT
Parameter Alt Description Condition Speed Unit
Trpvhh Tvidr RESET# Rise Time to Vhv and Vhv Fall Time to RESET# MIN 500 ns
Tvhhwl Trsp RESET# Vhv to WE# Low MIN 4 us
RESET#
CE#
WE#
RY/BY#
Trpvhh
12V
Vhv
0 or Vih Vil or Vih
Tvhhwl
Trpvhh
Program or Erase Command Sequence
43
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 16. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART
Start
Apply Reset# pin Vhv Volt
Enter Program or Erase Mode
(1) Remove Vhv Volt from Reset#
(2) RESET# = Vih
Completed Temporary Sector
Unprotected Mode
Mode Operation Completed
Notes:
1. Temporary unpro tect all protected sectors Vhv=11.5~12.5V.
2. After leaving tempo rary unpro tect mode, the previo usly pro tected sectors are again pro tected.
44
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 17. SILICON ID READ TIMING W A VEFORM
Taa
Tce
Taa
Toe
Toh Toh
Tdf
DATA OUT
00C2H 22D7H
Vhv
Vih
Vil
A9
ADD
CE#
A1
OE#
WE#
A0
DATA OUT
DATA
Q0-Q7
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
45
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
WRITE OPERATION STATUS
Figure 18. DA T A# POLLING TIMING W A VEFORMS (DURING AUTOMA TIC ALGORITHMS)
Tdf
Tce
Tch
Toe
Toeh
Toh
CE#
OE#
WE#
Q7
Q0-Q6
RY/BY#
Tbusy
Status Data Status Data
Status Data Complement True Valid Data
Taa
Trc
Address
VAVA
High Z
High Z
Valid DataTrue
46
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 19. DA TA# POLLING ALGORITHM
Read Q7~Q0 at valid address
(Note 1)
Read Q7~Q0 at valid address
Start
Q7 = Data# ?
Q5 = 1 ?
Q7 = Data# ?
(Note 2)
FAIL Pass
No
No
No
Yes
Yes
Yes
Notes:
1 . For programming, valid address means pro gram address.
F o r erasing, valid address means erase secto rs address .
2. Q7 sho uld be rechec ked ev en Q5="1" because Q7 ma y change simultaneo usly with Q5.
47
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 20. TOGGLE BIT TIMING W A VEFORMS (DURING AUTOMA TIC ALGORITHMS)
Tdf
Tce
Tch
Toe
Toeh
Taa
Trc
Toh
Address
CE#
OE#
WE#
Q6/Q2
RY/BY#
Tbusy
Valid Status
(first read)
Valid Status
(second read) (stops toggling)
Valid Data
VA VA
VA
VA : Valid Address
VA
Valid Data
48
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
Figure 21. T OGGLE BIT ALGORITHM
Notes:
1. Read to ggle bit twice to determine whether or no t it is to ggling.
2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
Read Q7-Q0 Twice
Q5 = 1?
Read Q7~Q0 Twice
PGM/ERS fail
Write Reset CMD PGM/ERS Complete
Q6 Toggle ?
Q6 Toggle ?
NO
(Note 1)
YES
NO
NO
YES
YES
Start
49
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is reco mmended fo r the supply v o ltages and the co ntro l signals at device power-up .
If the timing in the figure is igno red, the device may not oper ate correctly.
Figure A. AC Timing at Device Power-Up
Symbol Parameter Min. Max. Unit
Tvr Vcc Rise Time 20 500000 us/V
Tr Input Signal Rise Time 2 0 us/V
Tf Input Signal F all Time 2 0 us/V
Vcc
ADDRESS
CE#
WE#
OE#
DATA
Tvr
Taa
Tr or Tf Tr or Tf
Tce
Tf
Vcc(min)
GND
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Voh High Z
Vol
WP#/ACC
Valid
Ouput
Valid
Address
Tvcs
Tr
Toe
Tf Tr
50
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
MIN. MAX.
Input Voltage voltage difference with GND on all pins except I/O pins -1.0V 13.5V
Input Voltage voltage difference with GND on all I/O pins -1.0V Vcc + 1.0V
Vcc Current -100mA +100mA
All pins included except Vcc. Test conditions: Vcc = 3.0V, one pin per testing
LIMITS
PARAMETER MIN. TYP. MAX. UNITS
Chip Erase Time 4 5 65 sec
Sector Erase Time 0. 9 1 5 sec
Erase/Program Cycles 100,000 Cycles
Chip Programming Time 4 5 140 sec
Accelerated Word Program Time 7 210 us
Word Program Time 1 1 300 us
LATCH-UP CHARACTERISTICS
ERASE AND PROGRAMMING PERFORMANCE
Parameter Symbol Parameter Description Test Set TYP MAX UNIT
CIN2 Control Pin Capacitance VIN=0 7.5 9 pF
COUT Output Capacitance VOUT=0 8.5 1 2 pF
CIN Input Capacitance VIN=0 6 7.5 pF
TSOP PIN CAPACITANCE
51
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
ORDERING INFORMATION
PART NO. ACCESS TIME Ball Pitch/ PACKAGE Remark
(ns) Ball size
MX29LV640BUTC-90 90 48 Pin TSOP Commercial grade
(Normal Type) Note 1
MX29LV640BUTC-12 120 48 Pin TSOP Commercial grade
(Normal Type) Note 1
MX29LV640BUTI-90 90 48 Pin TSOP Industrial grade
(Normal Type) Note 1
MX29LV640BUTI-12 120 48 Pin TSOP Industrial grade
(Normal Type) Note 1
MX29LV640BUXBC-90 90 0.8mm/0.3mm 63 Ball CSP Commercial grade
Note 1
MX29LV640BUXBC-12 120 0.8mm/0.3mm 63 Ball CSP Commercial grade
Note 1
MX29LV640BUXBI-90 90 0.8mm/0.3mm 63 Ball CSP Industrial grade
Note 1
MX29LV640BUXBI-12 120 0.8mm/0.3mm 63 Ball CSP Industrial grade
Note 1
MX29 LV640BUTC-9 0G 90 48 Pin TSOP Commercial grade
(Normal Type) Pb-free
MX29 LV640BUTC-1 2G 120 48 Pin TSOP Commercial grade
(Normal Type) Pb-free
MX29LV640BUTI-90G 90 48 Pin TSOP Industrial grade
(Normal Type) Pb-free
MX29LV640BUTI-12G 120 48 Pin TSOP Industrial grade
(Normal Type) Pb-free
MX29LV640BUXBC-90G 90 0.8mm/0.3mm 63 Ball CSP Commercial grade
Pb-free
MX29LV640BUXBC-12G 120 0.8mm/0.3mm 63 Ball CSP Commercial grade
Pb-free
MX29LV640BUXBI-90G 90 0.8mm/0.3mm 63 Ball CSP Industrial grade
Pb-free
MX29LV640BUXBI-12G 120 0.8mm/0.3mm 6 3 Ball CSP Industrial grade
Pb-free
No te 1: The part no. is no t reco mmended fo r ne w design in.
52
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
PART NAME DESCRIPTION
MX 29 LV 90B U T C G
OPTION:
G: Lead-free package
SPEED:
90: 90ns
TEMPERATURE RANGE:
C: Commercial (0˚CC to 70˚ C
PACKAGE:
T: TSOP
X: FBGA (CSP)
BOOT BLOCK TYPE:
U: Uniform
REVISION:
B
DENSITY & MODE:
640: 64M x8/x16 Boot Block
LV: 3V
TYPE:
DEVICE:
29:Flash
XE - 0.4mm Ball
640
53
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
PACKAGE INFORMATION
54
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
55
P/N:PM1081 REV. 1.5, FEB. 26, 2008
MX29LV640BU
REVISION HISTORY
Revision No. Description Page Date
1.0 1. Removed "Preliminary" P1 MAR/08/2005
1.1 1. Datasheet format changed All AUG/15/2006
1. 2 1. Data modification All AUG/24/2006
1. 3 1. Added statement P56 NOV/06/2006
1.4 1. Added recommedation for non RoHS compliant devices P1,51 JAN/24/2007
2. Modified sector erase resume: 400us --> 4ms P 20
1.5 1. Modified Figure 11. CE# Controlled Write Timing Waveform P37 FEB/26/2008
MX29LV640BU
56
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Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure
of a single component co uld cause death, personal injury, severe physical damage , or other substantial harm to persons or
proper ty, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix
and its suppliers will not be liable to y ou and/o r any third party for any claims, injuries or damages that may be incurred due
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