PIC16C712T-04I/P - Microchip Technology

 1999 Microchip Technology Inc. Preliminary DS41106A-page 1

Devices included in this Data Sheet:

• PIC16C712 • PIC16C716

Microcontrolle r Core Features:

• High-performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program

branches which are two cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• Interrupt capability

(up to 7 internal/external interrupt sources)

• Eight level deep hardware stack

• Direct, indirect and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) and

Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Brown-out detection circuitry for

Brown-out Reset (BOR)

• Pr ogrammable code -protection

• Power saving SLEEP mode

• Selectable oscillator options

• Low-power, high-speed CMOS EPROM

technology

• Fully static design

• In-Circuit Serial Programming (ICSP)

• Wide operating vo ltage range: 2.5V to 5.5V

• High Sink/Source Current 25/25 mA

• Commercial, Industrial and Extended temper ature

ranges

• Low-power consumption:

- < 2 mA @ 5V, 4 MHz

- 22.5 µA typical @ 3V, 32 kHz

-< 1 µA typical standby current

Pin Di agrams

Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler

can be incremented during sleep via external

crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period

• Capture, Compare, PWM module

• Capture is 16-bit, max. resolution is 12.5 ns,

Compare is 16-bit, max. resolution is 200 ns,

PWM maximum resolut ion is 10-bit

• 8-bit mul ti-c ha nnel Analog-to -D igi tal converter

Device Program

Memory Data Memory

PIC16C712 1K 128

PIC16C716 2K 128

PIC16C712

RA2/AN2

RA4/T0CKI

RB0/INT

RB1/T1OSO/T1CKI

RA0/AN0

OSC1/CLKIN

RB7

RB6

18-pin PDIP, SOIC, Windowed CERDIP

MCLR/VPP

RA3/AN3/VREF

RB2/T1OSI

RB3/CCP1 RB4

RB5

RA1/AN1

VDD

OSC2/CLKOUT

VSS

PIC16C716 PIC16C712

RA2/AN2

RA4/T0CKI

RB0/INT

RB1/T1OSO/T1CKI

RA0/AN0

OSC1/CLKIN

RB7

RB6

20-pin SSOP

MCLR/VPP

RA3/AN3/VREF

RB2/T1OSI

RB3/CCP1 RB4

RB5

RA1/AN1

VDD

OSC2/CLKOUT

VSS

PIC16C716

VSS VDD

PIC16C712/716

8-Bit CMOS Microcontrollers with A/D Converter

and Capture/Compare/PWM

PIC16C712/716

DS41106A-page 2 Preliminary  1999 Microchip Technology Inc.

PIC16C7XX FAMILY OF DEVICES

Key Features

PICmicro™ Mid-Range Reference Manual

(DS33023) PIC16C712 PIC16C716

Operating Frequency DC - 20 MHz DC - 20 MHz

Resets (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST)

Program Memory (14-bit words) 1K 2K

Data Memory (bytes) 128 128

Interrupts 7 7

I/O Ports Ports A,B Ports A,B

Timers 3 3

Capture/Compare/PWM modules 1 1

8-bit Analog-to-Digital Module 4 input channels 4 input channels

PIC16C710 PIC16C71 PIC16C711 PIC16C712 PIC16C715 PIC16C716 PIC16C72A PIC16C73B

Clock Maximum Frequency

of Operation (MHz) 20 20 20 20 20 20 20 20

Memory

EPROM Program

Memory

(x14 words)

512 1K 1K 1K 2K 2K 2K 4K

Data Memory (bytes) 36 36 68 128 128 128 128 192

Peripherals

Timer Module(s) TMR0 TMR0 TMR0 TMR0

TMR1

TMR2

TMR0 TMR0

TMR1

TMR2

TMR0

TMR1

TMR2

TMR0

TMR1

TMR2

Capture/Compare/

PWM Module(s) ——— 1 — 1 1 2

Serial Port(s)

(SPI/I2C, USART) — — — — — — SPI/I2CSPI/I

2C,

USART

A/D Converter (8-bit)

Channels 444 4 4 455

Features

Interrupt Sources 4 4 4 7 4 7 8 11

I/O Pins 13 13 13 13 13 13 22 2 2

Voltage Range (Volts) 2.5-6.0 3.0-6.0 2.5-6.0 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5

In-Circuit Serial

Programming Yes Yes Yes Yes Yes Yes Yes Yes

Brown-out Reset Yes — Yes Yes Yes Yes Yes Yes

Packages 18-pin DIP,

SOIC;

20-pin SSOP

18-pin DIP,

SOIC 18-pin DIP,

SOIC;

20-pin SSOP

18-pin DIP,

SOIC;

20-pin SSOP

18-pin DIP ,

SOIC;

20-pin SSO P

18-pin DIP,

SOIC;

20-pin SSOP

28-pin SDIP,

SOIC, SSOP 28-pin SDIP,

SOIC

 1999 Microchip Technology Inc. Preliminary DS41106A-page 3
PIC16C712/716
Table of Contents
1.0 Device Overv iew......... ...... ................. ................. ............................ ................. ....................................................5
2.0 Memory Organization..........................................................................................................................................9
3.0 I/O Ports............................................................................................................................................................21
4.0 Timer0 Module...................................................................................................................................................29
5.0 Timer1 Module...................................................................................................................................................31
6.0 Timer2 Module...................................................................................................................................................36
7.0 Capture/Compare/PWM (CCP) Module(s)........................................................................................................39
8.0 Analog-to-Digital Converter (A/D) Module.........................................................................................................45
9.0 Special Features of the CPU.............................................................................................................................51
10.0 Instruction Set Summary...................................................................................................................................67
11.0 Development Support........................................................................................................................................69
12.0 Electrical Characteris tic s............. ................. ................. ................. ................. ..................................................75
13.0 DC and AC Characteristics Graphs and Tables................................................................................................91
14.0 Packaging Information.......................................................................................................................................93
Revision History ...........................................................................................................................................................99
Conversi on Cons id erat ion s ......... ................. ................. ............................ ............................ .. .....................................99
Migration from Base-line to Mid-Range Devices ..........................................................................................................99
Index...........................................................................................................................................................................101
On-Line Support..........................................................................................................................................................105
Reader Response.......................................................................................................................................................106
PIC16C712/716 Product Identification System...........................................................................................................107
To Our Valued Customers
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PIC16C712/716

DS41106A-page 4 Preliminary  1999 Microchip Technology Inc.

NOTES:

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 5

1.0 DEVICE OVERVIEW

This document contains device-specific information.

Additional information may be found in the PICmicro™

Mid-Range Reference Manual, (DS33023), which may

be obtained from your local Microchip Sales Represen-

tative or downloaded from the Microchip website. The

Reference Manual should be considered a comple-

mentary docu ment to this dat a sheet, and is highly rec-

ommended reading for a better understanding of the

device architecture and operation of the peripheral

modules.

There are two devices (PIC16C712, PIC16C716) cov-

ered by this datasheet.

Figure 1-1 is the block diagram for both devices. The

pinouts are listed in Table 1-1.

FIGURE 1-1: PIC16C712/7 16 BLOCK DIAGRAM

EPROM

Program

Memory

13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr 7

RAM Addr(1) 9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR VDD, VSS

PORTA

PORTB

RB0/INT

RB1/T1OSO/T1CKI

RB2/T1OSI

RB3/CCP1

RB4

RB5

RB6

RB7

Brown-out

Reset

Note 1: Higher order bits are from the STATUS register.

CCP1 A/D

Timer0 Timer1 Timer2

RA4/T0CKI

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

1K X 14

128 x 8

2K x 14

PIC16C712/716

DS41106A-page 6 Preliminary  1999 Microchip Technology Inc.

TABLE 1-1 PIC16C712/716 PINOUT DESCRIPTION

Pin PIC16C712/716 Pin Buffer

Name DIP, SOIC SSOP Type Type Description

MCLR/VPP

MCLR

VPP

44 I

ST Master clear (reset) input. This pin is an

active low reset to the device.

Programming voltage input

OSC1/CLKIN

OSC1

CLKIN

16 18 I

CMOS

Oscillator crystal input or external clock

source input. ST buffer when configured in

RC mode . CMOS otherwise.

External clock sou rce input.

OSC2/CLKOUT

OSC2

CLKOUT

15 17 O

—

Oscillator crystal output. Connects to

crystal or resonator in crystal oscillator

mode.

In RC mode, OSC2 pin outputs CLKOUT

which has 1/4 the frequency of OSC1, and

denotes the instruction cycle rate.

PORTA is a bi-directional I/O port.

RA0/AN0

RA0

AN0

17 19 I/O

ITTL

Analog Digi tal I/O

Analog input 0

RA1/AN1

RA1

AN1

18 20 I/O

ITTL

Analog Digi tal I/O

Analog input 1

RA2/AN2

RA2

AN2

11I/O

ITTL

Analog Digi tal I/O

Analog input 2

RA3/AN3/VREF

RA3

AN3

VREF

22I/O

TTL

Analog

Digital I/O

Analog input 3

A/D Reference Voltage input.

RA4/T0CKI

RA4

T0CKI

33I/O

ST/OD

Digital I/O. Open drain when configured

as output.

Timer0 external clock input

Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

OD = Open drain output

SM = SMBus compatible input. An external resistor is required if this pin is used as an output

NPU = N-channel pull-up PU = Weak internal pull-up

No-P diode = No P-diode to VDD AN = Anal og input or output

I = input O = output

P = Power L = LCD Driver

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 7

PORTB is a bi-directional I/O port. PORTB

can be software programmed for internal

weak pul l-u ps on all inputs.

RB0/INT

RB0

INT

67I/O

ITTL

ST Digital I/O

External Interrupt

RB1/T1OSO/T1CKI

RB1

T1OSO

T1CKI

I/O

TTL

—

Digital I/O

Timer1 oscillator output. Connects to

crystal in oscillator mode.

Timer1 external clock input.

RB2/T1OSI

RB2

T1OSI

89I/O

ITTL

—Digital I/O

Timer1 oscillator input. Connects to

crystal in oscillator mode.

RB3/CCP1

RB3

CCP1

910I/O

I/O TTL

ST Digital I/O

Capture1 input, Compare1 output, PWM1

output.

RB4 10 12 I/O TTL Digital I/O

Interrupt on change pin.

RB5 11 12 I/O TTL Digital I/O

Interrupt on change pin.

RB6 12 13 I/O

TTL

Digital I/O

Interrupt on change pin.

ICSP programming clock.

RB7 13 14 I/O

I/O

TTL

Digital I/O

Interrupt on change pin.

ICSP programming data.

VSS 5 5, 6 P — Ground reference for logic and I/O pins.

VDD 14 15, 16 P — Positive supply for logic and I/O pins.

Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

OD = Open drain output

SM = SMBus compatible input. An external resistor is required if this pin is used as an output

NPU = N-channel pull-up PU = Weak internal pull-up

No-P diode = No P-diode to VDD AN = Analog input o r output

I = input O = output

P = Power L = LCD Driver

TABLE 1-1 PIC16C712/716 PINOUT DESCRIPTION (Cont.’d)

Pin PIC16C712/716 Pin Buffer

Name DIP, SOIC SSOP Type Type Description

PIC16C712/716

DS41106A-page 8 Preliminary  1999 Microchip Technology Inc.

NOTES:

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 9

2.0 MEMORY ORGANIZATION

There are two memory blocks in each of these

PICmicro® microcontroller devices. Each block (Pro-

gram Memory and Data Memory) has its own bus so

that concurrent access can occur.

Addit ional inf ormation on de vic e memory ma y be f oun d

in the PICmicro Mid-Range Reference Manual,

(DS33023).

2.1 Pr ogram Memory Organization

The PIC16C712/716 has a 13-bit program counter

capable of addressing an 8K x 14 program memory

space. PIC16C712 has 1K x 14 words of program

memory and PIC16C716 has 2K x 14 words of prog ram

memory. Accessing a location above the physically

implemented address will cause a wraparound.

The reset vector is at 0000h and the interrupt vector is

at 0004h.

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK OF THE

PIC16C712

FIGURE 2-2: PROGRAM MEMORY MAP

AND STACK OF PIC16C716

PC<12:0>

0000h

0004h

0005h

03FFh

1FFFh

Stack Level 1

Stack Level 8

Reset Ve ctor

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

0400h

User Memory

Space

PC<12:0>

0000h

0004h

0005h

07FFh

0800h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

User Memory

Space

PIC16C712/716

DS41106A-page 10 Preliminary  1999 Microchip Technology Inc.

2.2 Data Memory Organization

The data memory is partitioned into multiple banks

which contain the General Purpose Registers and the

Special Function Registers. Bits RP1 and RP0 are the

bank select bits.

= 00 → Bank0

= 01 → Bank1

= 10 → Bank2 (not implemented)

= 11 → Bank3 (not implemented)

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Functio n Regis ters . Abo v e the Sp ecial Functi on Regi s-

ters are General Purpose Registers, implemented as

static RAM. All implemented banks contain special

function registers. Some “high use” special function

registers from one bank may be mirrored in another

bank for code reduction and quicker access.

2.2.1 GENERAL PURPOSE REGISTER FILE

The register file can be accessed either directly, or indi-

rectly through the File Select Register FSR

(Section 2.5).

FIGURE 2-3: REGISTER FILE MAP

RP1(1) RP0 (STATUS<6:5>)

Note 1: Maintain this bit clear to ensure upward compati-

bility with future products.

Unimplemented data memory locations,

read as ’0’.

Note 1: Not a physical register.

File

Address File

Address

00h INDF(1) INDF(1) 80h

01h TMR0 OPTION_REG 81h

02h PCL PCL 82h

03h STATUS STATUS 83h

04h FSR FSR 84h

05h PORTA TRISA 85h

06h PORTB TRISB 86h

07h DATACCP TRISCCP 87h

08h 88h

09h 89h

0Ah PCLATH PCLATH 8Ah

0Bh INTCON INTCON 8Bh

0Ch PIR1 PIE1 8Ch

0Dh 8Dh

0Eh TMR1L PCON 8Eh

0Fh TRM1H 8Fh

10h T1CON 90h

11h TRM2 91h

12h T2CON PR2 92h

13h 93h

14h 94h

15h CCPR1L 95h

16h CCPR1H 96h

17h CCP1CON 97h

18h 98h

19h 99h

1Ah 9Ah

1Bh 9Bh

1Ch 9Ch

1Dh 9Dh

1Eh ADRES 9Eh

1Fh ADCON0 ADCON1 9Fh

20h

General

Purpose

Registers

96 Bytes

General

Purpose

Registers

32 Bytes

A0h

BFh

C0h

7Fh FFh

Bank 0 Bank 1

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 11

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the

desired operation of the device. These registers are

implemented as static RAM. A list of these registers is

give in Table 2-1.

The sp ecial fu nction register s can b e class ified in to tw o

sets; core (CPU) a nd periphe ral. Those reg isters asso-

ciated with the core functions are described in detail in

this section. Those related to the operation of the

peripheral features are described in detail in that

peripheral feature section.

TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on all

other resets

(4)

Bank 0

00h INDF(1) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h PCL(1) Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

03h STATUS(1) IRP(4) RP1(4) RP0 TO PD ZDCCrr01 1xxx rr0q quuu

04h FSR(1) Indirect data memory address pointer xxxx xxxx uuuu uuuu

05h PORTA(5,6) ———

(7) PORTA Data Latch when written: PORTA pins when read --xx xxxx --xu uuuu

06h PORTB(5,6) PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu

07h DATACCP —(7) —(7) —(7) —(7) —(7) DCCP —(7) DT1CK xxxx xxxx xxxx xuxu

08h-09h —Unimplemented — —

0Ah PCLATH(1,2) ——— Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

0Bh INTCON(1) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 —ADIF—— — CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

0Dh —Unimplemented — —

0Eh TMR1L Holding register for the L east Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

11h TMR2 Timer2 module’s register 0000 0000 0000 0000

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

13h-14h

15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu

16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu

17h CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

18h-1Dh —Unimplemented — —

1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ’0’,

Shaded locations are unimplemented, read as ’0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents

are transferred to the upper byte of the program counter.

3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

4: The IRP and RP1 bits are reserved. Alwa ys maintain these bits clear.

5: On any device reset, these pins are configured as inputs.

6: This is the value that will be in the port output latch.

7: Reserved bits; Do Not Use.

PIC16C712/716

DS41106A-page 12 Preliminary  1999 Microchip Technology Inc.

Bank 1

80h INDF(1) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

81h OPTION_

REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

82h PCL(1) Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

83h STATUS(1) IRP(4) RP1(4) RP0 TO PD ZDCCrr01 1xxx rr0q quuu

84h FSR(1) Indirect data memory address pointer xxxx xxxx uuuu uuuu

85h TRISA ———

(7) PORTA Data Direction Register --x1 1111 --x1 1111

86h TRISB PORTB Data Direction Register 1111 1111 1111 1111

87h TRISCCP —(7) —(7) —(7) —(7) —(7) TCCP —(7) TT1CK xxxx x1x1 xxxx x1x1

88h-89h —Unimplemented — —

8Ah PCLATH(1,2) ——— Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

8Bh INTCON(1) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

8Ch PIE1 —ADIE—— — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000

8Dh —Unimplemented — —

8Eh PCON ——— — ——PORBOR ---- --qq ---- --uu

8Fh-91h —Unimplemented — —

92h PR2 Timer2 Period Register 1111 1111 1111 1111

93h-9Eh —Unimplemented — —

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ’0’,

Shaded locations are unimplemented, read as ’0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents

are transferred to the upper byte of the program counter.

3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

4: The IRP and RP1 bits are reserved. Alwa ys maintain these bits clear.

5: On any device reset, these pins are configured as inputs.

6: This is the value that will be in the port output latch.

7: Reserved bits; Do Not Use.

TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on all

other resets

(4)

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 13

2.2.2.1 STATUS REGISTER

The STATUS register, shown in Figure 2-4, contains

the arithmeti c status of th e ALU , the RESET statu s and

the bank select bits for data memory.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disab led . The se bi ts ar e set o r clea red a ccordi ng to the

device logi c. Fur t her more, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will cl ea r th e up p er- t hr ee

bits an d set the Z bit. This lea v e s the STATUS regist er

as 000u u1uu (where u = unchang ed).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register because these instructions do not

aff ect the Z, C or DC bits from the STATUS regist er . F or

other instructions, not affecting any status bits, see the

"Instruction Set Summary."

FIGURE 2-4: STATUS REGISTER (ADDRESS 03h, 83h)

Note 1: These devices do not use bits IRP and

RP1 (STATUS<7:6>). Maintain these bits

clear to ensure upward compatibility with

future products.

Note 2: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in sub-

traction. See the SUBLW and SUBWF

instructions for examples.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: IRP: R egister Bank Select bit (used for in dire ct add ressing)

1 = Bank 2, 3 (100 h - 1FFh) - not implemented, maintain cl ear

0 = Bank 0, 1 (00h - FFh) - not implemented, maintain clear

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

01 = Bank 1 (80h - FFh)

00 = Bank 0 (0 0h - 7F h)

Each bank is 128 bytes

Note: RP1 = not implemented, maintain clear

bit 4: TO: Time-out bit

1 = After power-up, CLRWDT instructi on, or SLEEP instructi on

0 = A WDT time-out occurred

bit 3: PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By executi on of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF in st ructions) (for borrow the polarity is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the most significant bit of the result occurred

0 = No carry-out from the most significant bit of the result occurred

Note: F or b orro w the polari ty is reversed. A subtr act io n is executed b y adding the two’s complem en t of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of

the source register.

PIC16C712/716

DS41106A-page 14 Preliminary  1999 Microchip Technology Inc.

2.2.2.2 OPTION_REG REGISTER

The OPTION_REG register is a readable and writable

the TMR0 prescaler/WDT postscaler (single assign-

abl e regist er kno wn als o as th e prescale r), the External

INT Inte rrupt, TMR0 and t he w eak pull-up s on PORTB.

FIGURE 2-5: OPTION_REG REGISTER (ADDRESS 81h)

Note: To achieve a 1:1 pres caler assi gnment for

the TMR0 register, assign the prescaler to

the Watchdog Timer.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORT B pull-u ps are enabled b y ind iv idu al port latch va lue s

bit 6: INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

bit 5: T0CS: TMR0 Clock Source Sele ct bit

1 = Transition on RA4/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3: PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 15

2.2.2.3 INTCON REGISTER

The I NTCON Regi ster i s a rea dab le a nd w ritabl e regi s-

ter which contains various enable and flag bits for the

TMR0 register overflow, RB Por t change and External

RB0/INT pin interrupts.

FIGURE 2-6: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

Note: Interrupt fl ag b its get s et wh en a n in terrupt

conditi on occ urs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

bit 6: PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5: T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4: IINTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt

bit 3: RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2: T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit 1: INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

bit 0: RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state

PIC16C712/716

DS41106A-page 16 Preliminary  1999 Microchip Technology Inc.

2.2.2.4 PIE1 REGISTER

This register contains the individual enable bits for the

peripheral interrupts.

FIGURE 2-7: PIE1 REGISTER (ADDRESS 8Ch)

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

—ADIE — — — CCP1IE TMR2IE TMR1IE R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as ‘0’

bit 6: ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt

bit 5-3: Unimplemented: Read as ‘0’

bit 2: CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 17

2.2.2.5 PIR1 R EGISTER

This register contains the individual flag bits for the

peripheral interrupts.

FIGURE 2-8: PIR1 REGISTER (ADDRESS 0Ch)

Note: Interrupt fl ag b its get s et wh en a n in terrupt

conditi on occ urs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

—ADIF — — — CCP1IF TMR2IF TMR1IF R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as ‘0’

bit 6: ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion is not c omplete

bit 5-3: Unimplemented: Read as ‘0’

bit 2: CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 r egister capture occurre d (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 register did not overflow

PIC16C712/716

DS41106A-page 18 Preliminary  1999 Microchip Technology Inc.

2.2.2.6 PCON REGISTER

The Power Control (PCON) register contains a flag bit

to allow differentiation between a Power-on Reset

(POR) to an external MCLR Reset or WDT Reset.

These devices contain an additional bit to differentiate

a Brown-out Reset condition from a Power-on Reset

condition.

FIGURE 2-9: PCON REGISTER (ADDRESS 8Eh)

Note: If the BODEN configuration bit is set, BOR

is ’1’ on Power-on Reset. If the BODEN

configuration bit is clear, BOR is unknown

on Power-on Reset.

The BOR status bit is a "don't care" and is

not necessarily predictab le if the brown-out

circuit is disabled (the BODEN configura-

tion bit is clear). BOR must then be set by

the user and checked on subsequent

resets to see if it is clear, indicating a

brown -out has occurred.

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q

————— —PORBOR R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-2: Unimplemented: Read as ’0’

bit 1: POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0: BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 19

2.3 PCL and PCLATH

The program counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 13 bits

wide. The low byte is called the PCL register. This reg-

ister is readable and writable. The high byte is called

the PCH register. This register contains the PC<12:8>

bits and is no t directly readab le or writable. All update s

to the PCH register go through the PCLATH register.

2.3.1 STACK

The stac k allo ws a co mbination o f up to 8 pr ogram ca lls

and interrupts to occur. The stack contains the return

address from this branch in program execution.

Midrange devices have an 8 level deep x 13-bit wide

hardware stack. The stack space is not part of either

program or data space and the stack pointer is not

readab le or writab le . The PC is PUSHed on to the stac k

when a CALL instruction is executed or an interrupt

causes a branch. The stack is POPed in the event of a

RETURN, RETLW or a RETFIE instruction execution.

PCLATH is not modified when the stack is PUSHed or

POPed.

After t he stac k has been PUSHe d eight t imes , the nin th

push overwrites th e value that w as s tored fro m the firs t

push. The tenth pus h overwrites the sec ond pus h (an d

so on).

2.4 Program Memory Paging

The CALL and GOTO instructions provide 11 bits of

address to allow branching within any 2K program

memory page . When d oing a CALL or GOTO instruction,

the upper bit of the address is provided by

PCLATH<3>. When doing a CALL or GOTO instr u cti on ,

the user must ensure that the page select bit is pro-

gr am m ed so that the des ire d prog r am me mo ry page is

address ed. If a retu rn from a CALL inst ruct ion (o r int er-

rupt) is executed, the entire 13-bit PC is pushed onto

the stack. Therefore, manipulation of the PCLATH<3>

bit is not required for the return instructions (which

POPs the address from the stack).

PIC16C712/716

DS41106A-page 20 Preliminary  1999 Microchip Technology Inc.

2.5 Indirect Addressing, INDF and FSR

Registers

The IN DF r egist er is not a physical r e gis ter. Addre ss-

ing INDF actually addresses the register whose

address is contained in the FSR register (FSR is a

pointer

). This is in dir ec t ad dressi ng .

EXAMPLE 2-1: INDIRECT ADDRESSING

• Register file 05 contains the value 10h

• Register file 06 contains the value 0Ah

• Load the value 05 into the FSR register

• A read of the INDF reg ist er will return the v alue of

10h

• Increment the value of the FSR register by one

(FSR = 06)

• A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF register indirectly results in a

no-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 20h-2Fh

using indirect addressing is shown in Example 2-2.

EXAMPLE 2-2: HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

movlw 0x20 ;initialize pointer

movwf FSR ; to RAM

NEXT clrf INDF ;clear INDF register

incf FSR ;inc pointer

btfss FSR,4 ;all done?

goto NEXT ;NO, clear next

CONTINUE

: ;YES, continue

An effective 9-bit add res s is o btai ne d by concatenating

the 8-bit F SR regist er and the IRP b it (STATUS<7>), as

shown in Figure 2-10. However, IRP is not used in the

PIC16C712/716.

FIGURE 2-10: DIRECT/INDIRECT ADDRESSING

Note 1: For register file map detail see Figure 2-3.

2: Maintain clear for upward compatibility with future products.

3: Not implemented.

Data

Memory(1)

Indirect AddressingDirect Addressing

bank select location select

RP1:RP0 6 0

from opcode IRP FSR register

bank select location select

00 01 10 11

Bank 0 Bank 1 Bank 2 Bank 3

FFh

80h

7Fh

00h

17Fh

100h

1FFh

180h

(3) (3)

(2) (2)

 1998 Microchip Technology Inc. Preliminary DS41106A-page 21

PIC16C712/716

3.0 I/O PORTS

Some pins for these I/O ports are multiplexed with an

alternate function for the peripheral features on the

device. In general, when a peripheral is enabled, that

pin may not be used as a general purpose I/O pin.

Addit ion al information on I/O po rts ma y be found in the

PICmicro™ Mid-Range Reference Manual,

(DS33023).

3.1 PORTA and the TRISA Register

PORTA is a 5-bit wide bi-directional port. The corre-

sponding data direction register is TRISA. Setting a

TRISA b it (=1 ) wi ll m ake t he corres pondi ng PORTA pin

an input, (i.e., put the corresponding output driver in a

hi-impedance mode). Clearing a TRISA bit (=0) will

mak e the corresp onding POR TA pin an ou tput, (i.e. , put

the contents of the output latch on the selected pin).

Reading the PORTA register reads the status of the

pins whereas writing to it will write to the port latch. All

write operations are read-modify-write operations.

Therefore a write to a port implies that the port pins are

read, the v al ue is modifi ed, and then w ritten to th e p ort

data latch.

Pin RA4 is multiplexed with the Timer0 module clock

input to become the RA4/T0CKI pin. The RA4/T0CKI

pin is a Schmit t Trigger inp ut and an open d r a in ou tpu t.

All other RA port pins have TTL input levels and full

CMOS out put drivers.

POR TA pins, RA3:0, are m ultiplex ed with analog inputs

and analog VREF input. The operation of each pin is

selected by clearing/setting the control bits in the

ADCON1 register (A/D Control Register1).

The TRISA register controls the direction of the RA

pins, even when they are being used as analog inputs.

The user m ust ensure the bits in the TRISA register are

maintained set when using them as analog inputs.

EXAMPLE 3-1: INITIALIZING PORTA

BCF STATUS, RP0 ;

CLRF PORTA ; Initialize PORTA by

; clearing output

; data latches

BSF STATUS, RP0 ; Select Bank 1

MOVLW 0xEF ; Value used to

; initialize data

; direction

MOVWF TRISA ; Set RA<3:0> as inputs

; RA<4> as outputs

BCF STATUS, RP0 ; Return to Bank 0

Note: On a Power-on Reset, these pins are con-

figured as analog inputs and read as '0'.

FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA0

DATA

BUS

PORT

TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

VSS

VDD

I/O pin

Analog

input

mode

TTL

Input

Buffer

To A/D Converter

VSS

VDD

PIC16C712/716

DS41106A-page 22 Preliminary  1998 Microchip Technology Inc.

FIGURE 3-2: BLOCK DIAGRAM OF RA4/T0CKI PIN

TABLE 3-1 PORTA FUNCTIONS

TABLE 3-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit# Buffer Function

RA0/ AN0 bit0 TTL Input/output or analog input

RA1/ AN1 bit1 TTL Input/output or analog input

RA2/ AN2 bit2 TTL Input/output or analog input

RA3/AN3/VREF bit3 TTL Input/output or analog input or VREF

RA4/T0CKI bit4 ST Input/output or external clock input for Timer0

Output is open drain type

Legend: TTL = TTL input, ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR

Value on all

other resets

05h PORTA — — —(1) RA4 RA3 RA2 RA1 RA0 --xx xxxx --xu uuuu

85h TRISA — — —(1) PORTA Data Direction Register --11 1111 --11 1111

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by

PORTA.

Note 1: Reserved bits; Do Not Use.

DATA

BUS

PORT

TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

Input

Buffer

VSS

I/O Pin

TMR0 Clock Input

VSS

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 23

3.2 PORTB and the TRISB Register

PORTB is an 8-bit wide bi-directional port. The corre-

sponding data direction register is TRISB. Setting a

TRISB bit (= 1) will mak e the corres ponding POR TB pin

an input, (i.e., put the corresponding output driver in a

hi-impedance mode). Clearing a TRISB bit (=0) will

make the corresponding PORTB pin an output, (i.e.,

put the contents of the output latch on the selected pin).

EXAMPLE 3- 1: INITIALIZING PORTB

BCF STATUS, RP0 ;

CLRF PORTB ; Initialize PORTB by

; clearing output

; data latches

BSF STATUS, RP0 ; Select Bank 1

MOVLW 0xCF ; Value used to

; initialize data

; direction

MOVWF TRISB ; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. Thi s is per-

formed by c lea ring bit R BPU (OPTION_REG<7> ). The

weak pu ll-up i s automa tically tur ned off wh en the p ort

pin is configured as an output. The pull-ups are dis-

abled on a Power-on Reset.

FIGURE 3-3: BLOCK DIAGRAM OF RB0 PIN

Data Latch

RBPU(1) P

VDD

DATA BUS

WR PORT

WR TRIS

RD TRIS

RD PORT

weak

pull-up

RD PORT

RB0/INT

I/O

TTL

Input

Buffer

Schmitt Trigger

Buffer

TRIS Latch

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

VSS

VDD

PIC16C712/716

DS41106A-page 24 Preliminary  1999 Microchip Technology Inc.

PORTB pins RB3:RB1 are multiplexed with several

peripheral functions (Table 3-3). PORTB pins RB3:RB0

have Schmitt Trigger input buffers.

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTB pin. Some

periph erals override the TRIS bit to make a pin an ou t-

put, while other peripherals override the TRIS bit to

make a pin an input. Since the TRIS bit override is in

effect while the peripheral is enabled, read-modify-

write instructions (BSF, BCF, XORWF) with TRISB as

destina tion sh ould be a v oided. Th e user should ref er to

the corresponding peripheral section for the correct

TRIS bit settings.

Four of PORTB’s pins, RB7:RB4, have an interrupt on

change feature. Only pins configured as inputs can

cause t his interrupt to occur (i.e . an y RB7:RB4 pin con-

figured as an output is excluded from the interrupt on

change comparison). The input pins, RB7:RB4, are

compar ed w ith th e o ld value latche d o n the last read of

PORTB. The “mismatch” outputs of RB7:RB4 are

OR’ed together to generate the RB Port Change Inter-

rupt with flag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The

user , in th e interrupt service routine , can clear the inter-

rupt in the following manner:

a) Any read or write of PORTB will end the mis-

match condition.

b) Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit RBIF to be cleared.

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PO RTB is only used for the inter rupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

FIGURE 3-4: BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN

TTL Buffer

TRISB<1>

PORTB<1>

TRISCCP<0>

DATACCP<0>

RB1/T1OSO/T1CKI

DATA BUS

WR TRISB

T1OSCEN

RD PORTB

TMR1CS

DATACCP

TRISCCP

PORTB

T1CLKIN ST

Buffer

VDD

weak

pull-up

RBPU(1)

T1OSCEN

T1CS

VSS

VDD

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 25

FIGURE 3-5: BLOCK DIAGRAM OF RB2/T1OSI PIN

FIGURE 3-6: BLOCK DIAGRAM OF RB3/CCP1 PIN

VDD

weak

pull-up

TTL Buffer

TRISB<2>

PORTB<2>

DATA BUS

WR PORTB

WR TRISB

T1OSCEN

RD PORTB

RB1/T1OSO/T1CKI

RBPU(1)

T1OSCEN

VSS

VDD

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

TRISB<3>

PORTB<3>

TRISCCP<2>

DATACCP<2>

RB3/CCP1

DATA BUS

RD PORTB

CCPON

TTL Bu ffer

CCPOUT

CCPIN

CCPON

DATACCP

TRISCCP

PORTB

TRISB

CCP

Output

Mode

VDD

weak

pull-up

RBPU(1)

CCPON

VSS

VDD

Note 1: To enable weak pull-ups, s et th e ap pr opriate TRIS b it(s)

and clear the RBPU bit (OPTION_REG<7>).

PIC16C712/716

DS41106A-page 26 Preliminary  1999 Microchip Technology Inc.

FIGURE 3-7: BLOCK DIAGRAM OF RB7:RB4 PINS

TABLE 3-3 PORTB FUNCTIONS

Name Bit# Buffer Function

RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software

programmable weak pull-up.

RB1/T1OS0/

T1CKI bit1 TTL/ST(1) Input/outpu t pin or Timer 1 os cilla tor outpu t, or Tim er 1 cl oc k input. Internal

software programmable weak pull-up. See Timer1 section for detailed

operation.

RB2/T1OSI bit2 TTL/ST(1) Input/outpu t pin or T imer 1 os cilla tor in put. Internal s oftw are prog ram mab le

weak pull-up. See Timer1 section for detailed operation.

RB3/CCP1 bit3 TTL/ST(1) Input/outpu t pin or Captu re 1 input , or Compare 1 output, or PWM1 output.

Internal software programmable weak pull-up. See CCP1 section for

detailed operation.

RB4 bit4 TTL Input/o utput pi n (wit h interrupt on chang e). Internal so ftw are prog ra mmab l e

weak pul l-u p.

RB5 bit5 TTL Input/o utput pi n (wit h interrupt on chang e). Internal so ftw are prog ra mmab l e

weak pul l-u p.

RB6 bit6 TTL/ST(2) Input/outpu t pin (w ith in terrupt on ch ange). In ternal softw are prog rammable

weak pull-up. Serial programming clock.

RB7 bit7 TTL/ST(2) Input/outpu t pin (w ith in terrupt on ch ange). In ternal softw are prog rammable

weak pull-up. Serial programming data.

Legend: TTL = TTL input, ST = Schmitt Tr igger input

Note1: This buffer is a Schmitt Trigger input when configured as the external interrupt or peripheral input.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

Data Latch

From other

RBPU(1) P

VDD

I/O

DATA BUS

WR PORT

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD PORT

RB7:RB4 pins

weak

pull-up

RD PORT

Latch

TTL

Buffer

RB7:RB6 in serial programming mode Q3

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

VSS

VDD

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 27

TABLE 3-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on all

other resets

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

86h TRISB PORTB Data Direction Register 1111 1111 1111 1111

81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

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NOTES:

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 29

4.0 T IMER0 MODULE

The Timer0 module ti mer/counter h as the f ollow ing f ea-

tures:

• 8-bit timer/counter

• Readable and writable

• Internal or external clock select

• Edge select for external clock

• 8-bit softwa re programmable prescaler

• Interrupt on overflow from FFh to 00h

Figure 4-1 is a simplified block diagram of the Timer0

module.

Additional infor mation on timer modules is available in

the PICmicro™ Mid-Range Reference Manual,

(DS33023).

4.1 Timer0 Operation

Timer0 can operate as a timer or as a counter.

Timer mode is selected by clearing bit T0CS

(OPTION_REG<5>). In timer mode, the Timer0 mod-

ule wi ll i nc rem ent eve ry instruct ion cy cl e (w it hou t pres-

caler). If the TMR0 register is written, the increment is

inhibited for the following two instruction cycles. The

use r can work around this by writing an adjusted value

to the TMR0 register.

Counter mode is selected by setting bit T0CS

(OPTION_REG<5>). In counter mode, Timer0 will

increment on every rising or falling edge of pin

RA4/T0CKI. The incrementing edge is determined by

the Timer0 Source Edge Select bit T0SE

(OPTION_REG <4 >). Cl eari ng b it T0SE sel ec ts the ris-

ing edge. Restrictions on the external clock input are

discussed below.

When an e xternal clock inp ut is used f or Timer0 , it must

meet certain requirements. The requirements ensure

the e xternal cloc k can b e synchron ized with the internal

phase clock (TOSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

Additional information on external clock requirements

is available in the PICmicro™ Mid-Range Reference

Manu al, (DS330 23).

4.2 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module or as a postscaler for the Watchdog

Timer, respectively (Figure 4-2). For simplicity, this

counter is being referred to as “prescaler” throughout

this data sheet. Note that there is only one prescaler

av ailab le, which is mutually e xclusiv ely shared betwee n

the Timer0 module and the Watchdog Timer. Thus, a

prescaler assignment for the Timer0 module means

that there is no prescaler for the Watchdog Timer and

vice-versa.

The prescaler is not readable or writable.

The PSA and PS2:PS0 bits (OPTION_REG<3:0>)

determine the prescaler a ssignment an d prescale ratio .

Clearing bit PSA wil l assign t he presc aler to the Ti mer0

module. When the prescaler is assigned to the Timer0

module, prescale values of 1:2, 1:4, ..., 1:256 are

selectable.

Setting bit PSA will assign the prescaler to the Watch-

dog Timer (WDT). When the prescaler is assigned to

the WDT, prescale values of 1:1, 1:2, ..., 1:128 are

selectable.

When assigned to the Timer0 module, all instructions

writing to the TM R0 register (e .g. CLRF 1, MOVWF 1,

BSF 1,x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the WDT.

FIGURE 4-1: TIMER0 BLOCK DIAGRAM

Note: Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler

count, but will not change the prescaler

assignment.

Note1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).

2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).

RA4/T0CKI

T0SE(1)

T0CS(1)

FOSC/4

Programmable

Prescaler(2)

Sync with

Internal

clocks TMR0

PSout

(2 cycle delay)

PSout

Data Bus

PSA(1)

PS2, PS1, PS0(1)Se t inter rupt

flag bit T0IF

on ov erfl ow

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DS41106A-page 30 Preliminary  1999 Microchip Technology Inc.

4.2.1 SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under software con-

trol, i.e., it can be changed “on the fly” during program

execution.

4.3 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows f rom FFh to 00h . This overflow se ts bit

T0IF (INTCON<2>). The interrupt can be masked by

clearing bit T0IE (INTCON<5>). Bit T0IF must be

cleared in s oftwa re b y th e Tim er0 mo dule interrupt s er-

vice routine before re-enabling this interrupt. The

TMR0 interrupt cannot awaken the processor from

SLEEP since the timer is shut off during SLEEP.

FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TABLE 4-1 REGISTERS ASSOCIATED WITH TIMER0

Note: To avoid an unin tended device RES ET, a

specific instruction sequence (shown in

the PICmicro™ Mid-Range Reference

Manual, DS33023) must be executed

when ch anging the prescale r assignme nt

from Timer0 to the WDT. This sequence

must be followed even if the WDT is dis-

abled.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on all

other resets

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

85h TRISA — — —(1) Bit 4 PORTA Data Direction Register --11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

Note 1: Reserved bit; Do Not Use.

RA4/T0CKI

T0SE

CLKOUT (=Fosc/4)

SYNC

Cycles TMR 0 r e g

8-bit Prescaler

8 - to - 1MUX

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

PSA

WDT Enable bit

Data Bus

Set flag bit T0IF

on Overflow

PSA

T0CS

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 31

5.0 T IMER1 MODULE

The Tim er1 module timer/count er has the f ollo wing f ea-

tures:

• 16-bit timer/counter

(Two 8-bit registers; TMR1H and TMR1L)

• Readable and writable (Both registers)

• Internal or external clock select

• Interrupt on overflow from FFFFh to 0000h

• Reset from CCP module trigger

Timer1 has a control register, shown in Figure 5-1.

Timer1 can be enabled/disabled by setting/clearing

control bit TMR1O N (T1CO N<0 >).

Figure 5-2 is a simplified block diagram of the Timer1

module.

Additional infor mation on timer modules is available in

the PICmicro™ Mid-Range Reference Manual,

(DS33023).

5.1 Timer1 Operation

Timer1 can operate in one of these modes:

•As a timer

• As a synchronous counter

• As an asynchronous counter

The operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>).

In timer mode, Timer1 increments every instruction

cycle. In coun ter mo de, it in creme nts on every ri sing

edge of the external clock input.

When the Timer1 oscillator is enabled (T1OSCEN is

set), the RB2/T1OSI and RB1/T1OSO/T1CKI pins

become inputs. That is, the TRISB<2:1> value is

ignored.

Timer1 a lso has an in ternal “reset input ”. This reset can

be generated by the CCP module (Section 7.0).

FIGURE 5-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-6: Unimplemented: Read as ’0’

bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 = 1:8 P rescale value

10 = 1:4 P rescale value

01 = 1:2 P rescale value

00 = 1:1 P rescale value

bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit

1 = Oscillator is enabled

0 = Oscillator is shut off

Note: The oscillator inver ter and feedback resistor are turned off to eliminate power drain

bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1

1 = Do not synchronize external clock input

0 = Synchronize external clock input

TMR1CS = 0

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1: TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin RB1/T1OSO/T1CKI (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0: TMR1ON: Timer1 On bit

1 = Enables Tim er1

0 = Stops Timer1

PIC16C712/716

DS41106A-page 32 Preliminary  1999 Microchip Technology Inc.

FIGURE 5-2: TIMER1 BLOCK DIAGRAM

5.2 Timer1 Module and PORTB Operation

When Timer1 is configured as timer running from the

main oscillator, PORTB<2:1> operate as normal I/O

lines. When Timer1 is configured to function as a

counter however, the clock so urc e sel ec tion may affec t

the operation of PORTB<2:1>. Multiplexing details of

the Timer1 clock selection on POR TB are shown in Fig-

ure 3-4 and Figure 3-5.

The clock source for Timer1 in the counter mode can

be from one of the following:

1. External circuit connected to the

RB1/T1OSO/T1CKI pin

2. Firmware controlled DATACCP<0> bit, DT1CKI

3. Timer1 oscillator

Tab le 5-1 sho ws the detail s of Timer1 m ode selec tions ,

control bit settings, TMR1 and PORTB operations.

TMR1H TMR1L

T1OSC T1SYNC

TMR1CS

T1CKPS1:T1CKPS0 SLEEP input

T1OSCEN

Enable

Oscillator(1) FOSC/4

Internal

Clock

TMR1ON

on/off

Prescaler

1, 2, 4, 8 Synchronize

det

Synchronized

clock input

RB1/T1OSO/T1CKI

RB2/T1OSI

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

Set flag bit

TMR1IF on

Overflow TMR1

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 33

TABLE 5-1 TMR1 MODULE AND PORTB OPERATION

TMR1

Module

Mode Clock Source Control Bits TMR1 Module Operation PORTB<2:1> Operation

Off N/A T1CON = --xx 0x00 Off PORTB<2:1> function as normal

I/O

Timer F os c/4 T1 C O N = --xx 0 x 0 1 TMR1 modu le us es the main

oscillator as clock source.

TMR1ON can t urn on or turn off

Timer1.

PORTB<2:1> function as normal

I/O

Counter

External circuit T1CON = --xx 0x11

TR1SCCP = ---- -x-1 TMR1 module uses the e x ternal

signal on the

RB1/T1OSO/T1CKI pin as a

clock source. TMR1ON can turn

on or turn off Timer1. DT1CK

can read the signal on the

RB1/T1OSO/T1CKI pin.

PORTB<2> functions as normal

I/O. PORTB<1> always reads 0

when configured as input . If

PORTB<1> is configured as out-

put, readin g PO RTB<1> will read

the data latch. Writing to

PORTB<1> will always store the

result in the data latch, but not to

the RB1/T1OSO/T1CKI pin. If

the TMR1CS bit is cleared

(TMR1 rever ts to the timer

mode), then pin PORTB<1> will

be driven with the value in the

data latch.

Firmware T1CON = --xx 0x11

TR1SCCP = ---- -x-0 DATACCP<0> bit drives

RB1/T1OSO/T1CKI and pro-

duces the TMR1 clock source.

TMR1ON can t urn on or turn off

Timer1. The DATACCP<0> bit,

DT1CK, can read and write to

the RB1/T1OSO/T1CKI pin.

Timer1 oscillator T1CON = --xx 1x11 RB1/T1OSO/T1CKI and

RB2/T1OSI are configured as a

2 pin crystal oscillator.

RB1/T1OSI/T1CKI is the clock

input for TMR1. TMR1ON can

turn on or turn off Timer1.

DATACCP<1> bit, DT1CK,

alw a ys rea ds 0 as in put and ca n

not write to the

RB1/T1O S O/ T1C K1 pin .

POR TB<2:1> alw ays read 0

when configured as inputs. If

PORTB<2:1> are con fig ured as

output s, read ing PORTB<2 :1>

will read th e data latche s. Writing

to PORTB<2:1> will always store

the result in the data latches, but

not to the RB2/T1OSI and

RB1/T1OSO/T1CKI pins. If the

TMR1CS and T1OSCEN bits are

cleared (TMR1 reverts to the

timer mode and TMR1 oscillator

is d i sabled), then pin

PORTB<2:1> will be driven with

the value in the data latches.

PIC16C712/716

DS41106A-page 34 Preliminary  1999 Microchip Technology Inc.

5.3 Timer1 Oscillator

A crystal oscill ator circuit is b uilt in betw een pins T1OSI

(input) and T1OSO (amplifier output). It is enabled by

setting control b it T1OSCEN (T1CON<3>). The osc illa-

tor is a low power oscillator rated up to 200 kHz. It will

continue to run during SLEEP. It is primarily intended

for a 32 kHz crystal. Table 5-2 shows the capacitor

selection for the Timer1 oscillator.

The Timer1 oscillator is identical to the LP oscillator.

The user must provide a software time delay to ensure

proper oscillator start-up.

TABLE 5-2 CAPACITOR SELECTION FOR

THE TIMER1 OSCILLATOR

5.4 Timer1 Interrupt

The TMR1 Register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

TMR1 interrupt, if enabled, is generated on overflow

which is latched in interrupt flag bit TMR1IF (P IR1<0>).

This inte rrupt can be enab led/d isab led by setting/c lear-

ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).

5.5 Resetting Timer1 using a CCP Trigger

Output

If the CCP module is configured in compare mode to

generate a “special event trigger" (CCP1M3:CCP1M0

= 1011), this signal will reset Timer1 and star t an A/D

conversion (if the A/D module is enabled).

Timer1 must be configured for either timer or synchro-

niz ed counter m ode to tak e adv antage of th is f eature . If

Timer1 is running in asynchronous counter mode, this

reset operation may not work.

In the e v ent that a write to Timer1 coi ncides with a spe-

cial event trigger from CCP1, the write will take prece-

dence.

In this mode of oper ation, the CCPR1H:CC PR1L regis -

ters pair effectively becomes the period register for

Timer1.

TABLE 5-3 REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Osc Type Freq C1 C2

LP 32 kHz 33 pF 33 pF

100 kHz 15 pF 15 pF

200 kHz 15 pF 15 pF

Thes e values are for design guidanc e only.

Note 1: Higher capacitance increases the stability

of oscillator but also increases the start-up

time.

2: Since each resonator/crystal has its own

characteristics, the user should consult the

resonato r /c rystal man ufacturer f or app ropri-

ate values of external components.

Note: The special event triggers from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR

Value on

all other

resets

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 —ADIF — — — CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000

8Ch PIE1 —ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

07h DATACCP — — — — — DCCP —DT1CK

---- -x-x ---- -u-u

87h TRISCCP — — — — — TCCP —TT1CK

---- -1-1 ---- -1-1

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 35

NOTES:

PIC16C712/716

DS41106A-page 36 Preliminary  1999 Microchip Technology Inc.

6.0 T IMER2 MODULE

The Timer2 module timer has the following features:

• 8-bit timer (TMR2 register)

• 8-bit period register (PR2)

• Readable and writable (Both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

• Inter rupt on TMR2 match of PR2

Timer2 has a control register, shown in Figure 6-1.

Timer2 c an be s hut off by clearing con trol bi t T MR 2ON

(T2CON<2>) to minimize power consumption.

Figure 6-2 is a simplified block diagram of the Timer2

module.

Additional infor mation on timer modules is available in

the PICmicro™ Mid-Range Reference Manual,

(DS33023).

FIGURE 6-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)

FIGURE 6-2: TIMER2 BLOCK DIAGRAM

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 T OUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as '0'

bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale

0001 = 1:2 Postscale

0010 = 1:3 Postscale

0011 = 1:4 Postscale

0100 = 1:5 Postscale

0101 = 1:6 Postscale

0110 = 1:7 Postscale

0111 = 1:8 Postscale

1000 = 1:9 Postscale

1001 = 1:10 Post scale

1010 = 1:11 Post scale

1011 = 1:12 Post scale

1100 = 1:13 Post scale

1101 = 1:14 Post scale

1110 = 1:15 Post scale

1111 = 1:16 Post scale

bit 2: TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

Comparator

TMR2

Sets flag

TMR2 reg

output

Reset

Postscaler

Prescaler

PR2 reg

FOSC/4

1:1 1:16

1:1, 1:4, 1:16

bit TMR2IF

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 37

6.1 Timer2 Operation

Timer2 can be used as the PWM time-base for PWM

mode of the CCP module.

The TMR2 register is readable and writable, and is

cleared on any device reset.

The input clock (FOSC/4) has a prescale option of 1:1,

1:4 or 1:16, selected by control bits

T2CKPS1:T2CKPS0 (T2CON<1: 0>).

The match output of TMR2 goes through a 4-bit

postscaler (which gives a 1:1 to 1:16 scaling inclusive)

to generate a TMR2 interrupt (latched in flag bit

TMR2IF, (PIR1<1>)).

The prescaler and postscaler counters are cleared

when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device reset (Power-on Reset, MCLR reset,

Watchdog Timer reset, or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

6.2 Timer2 Interrupt

The Timer2 module has an 8-bit period register PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readab le and writable register . The PR2 register is ini-

tialized to FFh upon reset.

TABLE 6-1 REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR

Value on

all other

resets

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 —ADIF — — —CCP1IF TMR2IF TMR1IF -00- -000 0000 -000

8Ch PIE1 —ADIE — — —CCP1IE TMR2IE TMR1IE -0-- -000 0000 -000

11h TMR2 Timer2 module’s register 0000 0000 0000 0000

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

92h PR2 Timer2 Period Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.

PIC16C712/716

DS41106A-page 38 Preliminary  1999 Microchip Technology Inc.

NOTES:

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 39

7.0 CAPTURE/COMPARE/PWM

(CCP) MODULE(S)

Each CCP (Capture/Compare/PWM) module contains

a 16-bit register, which can operate as a 16-bit capture

master/slave Duty Cycle register. Table 7-1 shows the

timer resources of the CCP module modes.

Capture/Compare/PWM Register 1 (CCPR1) is com-

prised of two 8-bit registers: CCPR1L (low byte) and

CCPR1H (high byte). The CCP1CON register controls

the operation of CCP1. All are readable and writable.

Additional infor mation on the CCP module is available

in the PICmicro™ Mid-Range Reference Manual,

(DS33023).

TABLE 7-1 CCP MODE - TIMER

RESOURCE

FIGURE 7-1: CCP1CON REGISTER (ADDRESS 17h)

FIGURE 7-2: TRISCCP Register (ADDRESS 87h)

CCP Mode Time r Resource

Capture

Compare

PWM

Timer1

Timer2

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 R = Readable bit

W =Writable bit

U = Unimplemented bit, read

as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7-6: Unim plemented: Read as '0'

bit 5-4: DC1B1:DC1B0: PWM Least Significant bits

Capture Mode: Unused

Compare Mode: Unused

PWM Mode: These bi ts are the two LSb s of t he PWM duty cyc le. Th e e igh t M Sbs are found in CC PR 1L .

bit 3-0: CCP1M3:CCP1M0: CCP1 Mode Select bits

0000 = Capture/Compare/PWM off (resets CCP1 module)

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode, set output on match (CCP1IF bit is set)

1001 = Compare mo de , clear output on match (CCP1IF bit is set)

1010 = Com pare mode , generate so ftware in terrupt on match (C CP1IF bit is set, CC P1 pin is unaff ected )

1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D

conversion (if A/D module is enabled))

11xx = PWM mode

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

———— —TCCP—TT1CKR =Readable bit

W =Writable bit

U = Unimplemented bit, read

as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7-3: Reserved bits; Do Not Use

bit 2: TCCP - Tri state control bit for CCP

0 = Output pin driven

1 = Output pin tristated

bit 1: Reserved bit; Do Not Use

bit 0: TT1CK - Tri state control bit for T1CKI pin

0 = T1CKI pin is an output

1 = T1CKI pin is an input

PIC16C712/716

DS41106A-page 40 Preliminary  1999 Microchip Technology Inc.

7.1 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the

16-bit v alue of th e TMR1 register wh en an ev ent oc curs

on pin RB3/CCP1. An event is defined as:

• every falling edge

• every rising edge

• every 4th rising edge

• every 16th rising edge

An event is selected by control bits CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the inter-

rupt request flag bit CCP1IF (PIR1<2>) is set. It must

be clea red in softw are. If anot her capture occu rs befo re

the value in register CCPR1 is read, the old captured

value will be lost.

FIGURE 7-3: CAPTURE MODE OP ERATION

BLOC K DIAGRAM

7.1.1 CCP PIN CONFIGURATION

In Capture mode, the CCP output must be disabled by

setting the TRISCCP<2> bit.

7.1.2 TIMER1 MODE SELECTION

Timer1 m ust be runni ng in timer m ode or s ynchr oniz ed

counter mode for the CCP module to use the capture

feature. In asynchronous counter mode, the capture

operation may not work.

7.1.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE (PIE1<2>) clear to avoid false interrupts and

should clear the flag bit CCP1IF following any such

change in operating mode.

7.1.4 CCP PRESCALER

There are four prescaler settings, specified by bits

CCP1M3:CCP1M0. Whenever the CCP module is

turned off, or the CCP module is not in capture mode,

the prescaler counter is cleared. This means that any

reset will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared, therefore the first capture may be from

a non-zero prescaler. Example 7-1 shows the recom-

mended method for switching between capture pres-

calers. This example also clears the prescaler counter

and will not generate the “false” interrupt.

EXAMPLE 7-1: CHANGIN G BETWEEN

CAPTURE PRESCALERS

CLRF CCP1CON ;Turn CCP module off

MOVLW NEW_CAPT_PS ;Load the W reg with

; the new prescaler

; mode value and CCP ON

MOVWF CCP1CON ;Load CCP1CON with this

; value

Note: If the RB3/CCP1 is configu red as an output

by clearing the TRISCCP<2> bi t, a write to

the DCCP bit can cause a capture condi-

tion.

CCPR1H CCPR1L

TMR1H TMR1L

Set flag bit CCP1IF

(PIR1<2>)

Capture

Enable

Q’s CCP1CON<3:0>

RB3/CCP1

Prescaler

÷ 1, 4, 16

and

edge detect

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 41

7.2 Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RB3/CCP1 pin is

either:

•driven High

• driven Low

• remain s Unchanged

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the

same time, interrupt flag bit CCP1IF is set.

FIGURE 7-4: COMPARE MODE

OPERATION BLOCK

DIAGRAM

7.2.1 CCP PIN CONFIGURATION

The user m ust configure the RB3/CCP1 pin as the CCP

output by clearing the TRISCCP<2> bit.

7.2.2 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

7.2.3 SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen the CCP1

pin is not aff ec ted. Onl y a CC P interrupt is gener ated ( if

enabled).

7.2.4 SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated

which may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

eff ec tiv el y be a 16-b it prog ram mab le period register f or

Timer1.

The spe cial e vent trigger out put of CC P1 also s tarts an

A/D conversion (if the A/D module is enabled).

TABLE 7-2 REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

CCPR1H CCPR1L

TMR1H TMR1L

Comparator

ROutput

Logic

Special Ev ent Trigger

Set flag bit CCP1IF

(PIR1<2>)

match

RB3/CCP1

TRISCCP<2> CCP1CON<3:0>

Mode Select

Output Enable

Special event trigger will:

reset Time r1 , but no t se t inte rr u pt flag bit T M R1IF (PIR1<0>),

and set bit GO/DONE (ADCON0<2>)

which starts an A/D conversion

Note: Clear ing the CCP1C ON register will force

the RB3 /CCP1 compare output la tch to th e

def ault low le vel. This is neither the POR TB

I/O data latch nor the DATACCP latch.

Note: The special event trigger from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Val ue on

POR,

BOR

Value on

all other

resets

07h DATACCP — — — — — DCCP — TT1CK xxxx xxxx xxxx xuxu

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 —ADIF — — — CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu

10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu

16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu

17h CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

87h TRISCCP — — — — — TCCP — TT1CK xxxx x1x1 xxxx x1x1

8Ch PIE1 —ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000

Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.

PIC16C712/716

DS41106A-page 42 Preliminary  1999 Microchip Technology Inc.

7.3 PWM Mode

In Pulse Width Modulation (PWM) mode, the CCP1 pin

produces up to a 10-bit resolution PWM output. Since

the CCP1 pin is m ultiple xed w ith the POR TB data l atch,

the TRISCCP<2> bit must be cleared to make the

CCP1 pin an output.

Figure 7-5 sho ws a simplified block diagram of the CCP

module in PWM mode.

F or a step by step proce dure on ho w t o set up the C CP

module for PWM operation, see Section 7.3.3.

FIGURE 7-5: SIMPLIFIED PWM BLOCK

DIAGRAM

A PWM output (Figure 7-6) has a time base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

FIGURE 7-6: PWM OUTPUT

7.3.1 PWM PERIOD

The PWM period is specified by writing to the PR2 reg-

ister. The PWM period can be calculated using the fol-

lowing formula:

PWM period = [(PR2) + 1] • 4 • TOSC •

(TMR2 prescale value)

PWM frequency is defined as 1 / [PWM period].

When TMR 2 is equal to PR2, the f ollo wing three e v ents

occur on the next increment cycle:

•TMR2 is cleared

• The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)

• The PWM duty cycle is latched from C CPR1L into

CCPR1H

7.3.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10- bit resol uti on i s available. The C CPR1 L con tai ns

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •

Tosc • (TMR2 prescale value)

CCPR1L and CC P1CON <5:4> c an be writ ten to at an y

time, but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are

used to d ouble buffer the PWM duty cyc le. Th is d oubl e

buffering is essential for glitchless PWM operation.

When the CCPR1H and 2-bit latch match TMR2 con-

catenated with an internal 2-bit Q clock or 2 bits of the

TMR2 prescaler, the CCP1 pin is cleared.

Maximum PWM re solution (bits) for a given PWM

frequency:

For an example PWM period and duty cycle calcula-

tion, see the PICmicro™ Mid-Range Reference

Manu al, (DS330 23).

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is neither the PORTB I/O

data latch nor the DATA CC P latc h.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty cycle registers CCP1CON<5:4>

Clear Timer,

CCP1 pin and

latch D.C.

TRISCCP<2>

RB3/CCP1

Note 1: 8-bit timer is concatenated with 2-bi t internal Q clock

or 2 bits of the prescaler to create 10-bit time-base.

Period = PR2+1

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle (CCPR1H)

TMR2 = PR2

Note: The Tim er2 p ost sc ale r (s ee Se ction 6.0) is

not us ed in t he det erm inati on of t he PWM

frequenc y. Th e postscaler c ould be us ed to

have a servo update rate at a different fre-

quency than the PWM output.

Note: If the PWM duty cycle value is longer than

the PWM period the CCP1 pin will not be

cleared.

log( FPWM

log(2)

FOSC )bits=

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 43

7.3.3 SET-UP FOR PWM OPERATION

The followi ng steps sh ould be ta ken wh en configu ring

the CCP module for PWM operation:

1. Set the PWM period b y wri ting to t he PR2 regi s-

ter.

2. Set the PWM duty cycle by writing to the

CCPR1L register and CCP1CON<5:4> bits.

3. Make the CCP1 pin an output by clearing the

TRIS CCP< 2 > bi t .

4. Set the TMR2 prescale v alue and enab le Timer2

by writing to T2CON.

5. Configure the CCP1 module f or PWM operation.

TABLE 7-3 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

TABLE 7-4 REGISTERS ASSOCIATED WITH PWM AND TIMER2

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescaler (1, 4, 16) 16 4 1 1 1 1

PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 5.5

Addres s Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR

Value on

all other

resets

07h DATACCP — — — — — DCCP —DT1CK

xxxx xxxx xxxx xuxu

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 —ADIF — — — CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000

11h TMR2 Timer2 module’s regis ter 0000 0000 0000 0000

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

15h CCPR1L Capture/Compare/PWM r egister 1 (LSB) xxxx xxxx uuuu uuuu

16h CCPR1H Captur e/Compar e/ PWM r egister1 ( MSB) xxxx xxxx uuuu uuuu

17h CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

87h TRISCCP — — — — — TCCP —TT1CK xxxx x1x1 xxxx x1x1

8Ch PIE1 —ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000

92h PR2 Timer2 module’s period register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.

PIC16C712/716

DS41106A-page 44 Preliminary  1999 Microchip Technology Inc.

7.4 CCP1 Module and PORTB Operation

When the CCP module is disabled, PORTB<3> oper-

ates as a normal I/O pin. When the CCP module is

enabled, PORTB<3> operation is affected. Multiplex-

ing details of the CCP1 module are shown on

PORTB<3>, refer to Figure 3.6.

Table 7-5 below shows the effects of the CCP module

operation on PORTB<3> .

TABLE 7-5 CCP1 MODULE AND PORTB OPERATION

CCP1

Module

Mode Control Bits CCP1 Module Operation PORTB<3> Operation

Off CCP1CON = --xx 0000 Off PORTB<3> functions as normal I/O.

Capture CCP1CON = --xx 01xx

TR1SCCP = ---- -1-x The CCP1 module will capture an event

on the RB3/CCP1 pin which is driven by

an external circuit. The DCCP bit can

read the signal on the RB3/CCP1 pin.

PORTB<3> always reads 0 when config-

ured as input. If PORTB<3> is config-

ured as output, reading PORTB<3> will

read the data latch. Writing to

POR T B<3> wil l alw ays store th e res ult in

the data latch, but it does not drive the

RB3/CCP1 pin.

CCP1CON = --xx 01xx

TR1SCCP = ---- -0-x The CCP1 module will capture an event

on the RB3/CCP1 pin which is driven by

the DCCP bit. The DCCP bit can read

the signal on the RB3/CCP1 pin.

Compare CCP1CON = --xx 10xx

TR1SCCP = ---- -0-x The CCP1 module produces an output

on the RB3/CCP1 pin when a compare

even t occurs. The DCCP bit can read

the signal on the RB3/CCP1 pin.

PWM CCP1CON = --xx 11xx

TR1SCCP = ---- -0-x The CCP1 module produces the PWM

signal on the RB3/CCP1 pin. The DCCP

bit can read the sig nal on th e RB3/CC P1

pin.

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 45

8.0 ANALOG-TO-DIGITAL

CONV ERTER (A/D) MODULE

The analog-to-digital (A/D) converter module has four

inputs.

The A/D allows conversion of an analog input signal to

a corresponding 8-bit digital number (refer to Applica-

tion Note AN546 for use of A/D Converter). The output

of the sample and hold is the input into the converter,

which generates the result via successive approxima-

tion. The analog reference voltage is software select-

abl e to eithe r the de vice’s positiv e sup ply v oltage (VDD)

or the voltage level on the RA3/A N3/VREF pin.

The A/D conv erter has a un ique f eature of b eing ab le to

oper ate while the devic e is in SLEEP mode. To opera te

in sleep, the A/D conversion clock must be derived from

the A/D’s internal RC oscillator.

Addition al inf ormation on the A/D module is a vai labl e in

the PICmicro™ Mid-Range Reference Manual,

(DS33023).

The A/D module has three registers. These registers

are: • A/D Result Register (ADRES)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

A device reset forces all registers to their reset state.

This forces the A/D module to be turned off, and any

conv e r si on is abo rted.

The ADCON0 register, shown in Figure 8-1, controls

the operation of the A/D module. The ADCON1 regis-

ter , shown i n Figure 8-2, configur es the f unctions of th e

port pins. The port pins can be configured as analog

inputs (R A3 c an als o be a voltage reference) or as dig-

ital I/O.

FIGURE 8-1: ADCON0 REGISTER (ADDRESS 1Fh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADONR =Readable bit

W =Writable bit

U =Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits

00 = FOSC/2

01 = FOSC/8

10 = FOSC/32

11 = FRC (clock derived from the internal ADC RC oscillator)

bit 5-3: CHS2:CHS0: Analog Channel Select bits

000 = channel 0, (RA0/AN0)

001 = channel 1, (RA1/AN1)

010 = channel 2, (RA2/AN2)

011 = channel 3, (RA3/AN3)

1xx = reserved, do not use

bit 2: GO/DONE: A/D Conversion Status bit

If ADON = 1

1 = A/D conversion in progress (setting this bit starts the A/D conversion)

0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conver-

sion is complete)

bit 1: Unimplemented: Read as '0'

bit 0: ADON: A/D On bit

1 = A/D converter module is operating

0 = A/D converter module is shutoff and consumes no operating current

PIC16C712/716

DS41106A-page 46 Preliminary  1999 Microchip Technology Inc.

FIGURE 8-2: ADCON1 REGISTER (ADDRESS 9Fh)

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCFG2 PCFG1 PCFG0 R =Readable bit

W =Writable bit

U =Unimplemented bit,

read as ‘0’

- n = Value at POR

reset

bit7 bit0

bit 7-3: Unimplemented: Read as '0'

bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits

A = Analog input

D = Digital I/O

PCFG2:PCFG0 RA0 RA1 RA2 RA3 VREF

0x0 AAAA VDD

0x1 AAAVREF RA3

100 AADA VDD

101 AADVREF RA3

11x DDDD VDD

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 47

The ADRES register c ontains t he result of the A /D con-

version. When the A/D conversion is complete, the

result is loaded into the ADRES register , the GO/DONE

bit (A DCO N0< 2>) i s cl eared and t he A /D in te rr upt flag

bit ADIF is set. The block diagram of the A/D module is

shown in Figure 8-3.

The v a lue t hat is in the ADRES register is not modifie d

for a Powe r-on R ese t. Th e ADR ES re gis ter will co ntai n

unknown data after a Power-on Reset.

After the A/D module has been configured as desired,

the selected channel must be acquired before the con-

version is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 8.1.

After this acqui sitio n time has e lapse d, the A/D c on v er-

sion can be started. The following steps should be fol-

lowed for doing an A/D conversio n:

1. Configure the A/D module:

• Configure analog pins/voltage reference/

and digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. W a it the requ ired acqu is itio n tim e .

4. Start conversion:

• Set GO/DONE bit (ADCON0)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

• Waiting for the A/D interrupt

6. Read A/D Result register (ADRES), clear bit

ADIF if required.

7. F or the ne xt con version , go to step 1 or step 2 as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2TAD is

required before ne xt acq ui sit ion st arts.

FIGURE 8-3: A/D BLOCK DIAGRAM

(Input voltage)

VIN

VREF

(Reference

voltage)

VDD

PCFG2:PCFG0

CHS2:CHS0

000 or

010 or

110 or 111

001 or

011 or

101

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

011

010

001

000

A/D

Converter

100 or

PIC16C712/716

DS41106A-page 48 Preliminary  1999 Microchip Technology Inc.

8.1 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 8-4. The source

impeda nce (RS) and the internal sampli ng s witch (R SS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD). The

sour ce impe dan ce a ff ects the of fset voltage at the ana-

log input (due to pin leakage current). The maximum

recommended impedance for analog sources is 10

kΩ. After the analog input channel is selected

(changed) this acquisition must be done before the

conversion can be started.

To calculate the minimum acquisition time, TACQ, see

the PICmicro™ Mid-Range Reference Manual,

(DS33023). This equation calculates the acquisition

time to wi thin 1/2 LSb error (512 steps f or the A/D). Th e

1/2 LS b er ror i s th e max imum erro r all o w ed for the A/D

to meet its specified accuracy.

FIGURE 8-4: ANALOG INPUT MODEL

Note: When the conversion is started, the hold-

ing capacitor is disconnected from the

input pin.

CPIN

Rs ANx

5 pF

VDD

VT = 0.6V

VT = 0.6V I leakage

RIC ≤ 1k

Sampling

Switch

SS RSS

CHOLD

= DAC capacitance

VSS

Sampling Switch

567891011

(kΩ)

VDD

= 51.2 pF

± 500 nA

Legend CPIN

I leakage

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 49

8.2 Selecting the A/D Conversion Clock

The A/D conversion time per bit is defined as TAD. The

A/D conversion requires 9.5TAD per 8-bit conversion.

The source of the A/D conversion clock is software

selectable. The four possible options for TAD are:

•2T

OSC

•8TOSC

•32TOSC

• Interna l RC oscillator

For cor rect A /D co nversions, t he A/D conversion cl ock

(TAD) must be sel ected to ensur e a mi nimu m TAD time

of 1.6 µs.

Table 8-1 shows the resultant TAD times derived from

the device operating frequencies and the A/D clock

sour ce se lec ted .

8.3 Configuring Analog Port Pins

The ADCON1 and TRISA registers control the opera-

tion of the A/D port pins. The port pins that are desire d

as analog inputs must have their corresponding TRIS

bits set (input). If the TRIS bit is cleared (output), the

digital output level (VOH or VOL) will be conver ted.

The A/D operation is independent of the state of the

CHS2:CHS0 bits and the TRIS bits.

TABLE 8-1 TAD vs. DEVICE OPERATING FREQUENCIES

Note 1: When reading the port register, all pins

configured as analog input channels will

read as cleared (a low level). Pins config-

ured as digital inputs, will convert an ana-

log input. Analog levels on a digitally

configured input will not affect the conver-

sion accuracy.

Note 2: Analog l e v el s on an y pin t hat is defi ned a s

a digital input (including the AN3:AN0

pins), may cause the input buffer to con-

sume current that is out of the devices

specification.

AD Clock Source (TAD) De v ice Fr equ enc y

Operation ADCS1:ADCS0 20 MHz 5 MHz 1.25 MHz 333.33 kHz

2TOSC 00 100 ns(2) 400 ns(2) 1.6 µs6 µs

8TOSC 01 400 ns(2) 1.6 µs6.4 µs24 µs(3)

32TOSC 10 1.6 µs6.4 µs25.6 µs(3) 96 µs(3)

RC(5) 11 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1)

Legend: Shaded cells are outside of recommended range.

Note1: The R C source has a typical TAD time of 4 µs.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for

sleep operation only.

5: For ex tended voltage devices (LC), please refer to Electrical Specifications section.

PIC16C712/716

DS41106A-page 50 Preliminary  1999 Microchip Technology Inc.

8.4 A/D Conversions

8.5 Use of the CCP Trigger

An A/D c on ve rsi on can be sta rted b y the “s pecia l e v e nt

trigger” of the CCP1 module. This requires that the

CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-

gr am m ed as 1011 and that th e A/D mod ul e is e nabled

(ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, star ting the A/D conversion,

and the Timer1 counter will be reset to zero. Timer1 is

reset to au tomat icall y repe at the A/D acquisi tion p eriod

with minim al softw are ov erhea d (movi ng the ADRES to

the desired location). The appropriate analog input

channel must be s elected an d the minim um acqu isition

done before the “special event trigger” sets the

GO/DONE bit (starts a conversion).

If the A/D module is not enabled (ADON is cleared),

then the “special event trigger” will be ignored by the

A/D module, but will still reset the Timer1 counter.

TABLE 8-2 SUMMARY OF A/D REGISTERS

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

Address Name Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR,

BOR

Value on all

other Resets

05h PORTA — — —(1) RA4 RA3 RA2 RA1 RA0 --xx xxxx --xu uuuu

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 —ADIF — —— CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000

1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0

85h TRISA — — —(1) PORTA Data Direction Register ---1 1111 ---1 1111

8Ch PIE1 —ADIE — —— CCP1IE TMR2IE TMR1IE -0-- -000 -0-- 0000

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.

Note 1: Reserved bits; Do Not Use.

 1999 Microchip Technology Inc. Preliminary DS41106A-page 51

PIC16C712/716

9.0 SPECIAL FEATURES OF THE

CPU

The PIC16C712/716 devices have a host of features

intended to maximize system reliability, minimize cost

through elimination of external components, provide

power saving operating modes and offer code protec-

tion. Th ese are:

• OSC Selection

• Reset

- Power-on Reset (POR)

- P o wer-up Tim er (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID locations

• In-Circuit Serial Programming™ (ICSP)

These devices have a Watchdog Timer, which can be

shut off only through configuration bits. It runs off its

own RC oscillator for added reliability. There are two

timers that offer necessary delays on powe r-up. One is

the Oscillator Start-up Timer (OST), intended to keep

the chi p in rese t until th e crystal osci llator is stab le. Th e

other is the Pow er-u p Ti me r ( PWRT), which pro vi des a

fixed delay on power-up only and is designed to keep

the part in reset w hile t he po wer sup ply stab iliz es . Wi th

these two timers on-chip, most applications need no

external reset circuitry.

SLEEP mode is designed to offer a very low current

pow er-down m ode. The user can w ake-up from SLEEP

through external reset, Watchdog Timer Wake-up, or

through an interrupt. Se veral oscill ator opti ons are als o

made available to allow the part to fit the application.

The RC oscillator option save s system cost, while the

LP crystal option saves power. A set of configuration

bits are used to select various options.

Addition al information on special features is availab le in

the PICmicro™ Mid-Range Reference Manual,

(DS33023).

9.1 Configuration Bits

The con figur ati on bits c an be progr a mmed (read as '0')

or left unprogrammed (read as '1') to select various

device configurations. These bits are mapped in pro-

gram memory location 2007h.

The user will note that address 2007h is beyond the

user program memory space. In fact, it belongs to the

special test/configuration memory space (2000h -

3FFF h), whic h can be ac cessed on ly dur ing progra m-

ming.

PIC16C712/716

DS41106A-page 52 Preliminary  1999 Microchip Technology Inc.

FIGURE 9-1: CONFIGURATION WORD

CP1 CP0 CP1 CP0 CP1 CP0 —BODENCP1CP0 PWRTE WDTE FOSC1 FOSC0 Register:CONFIG

Address2007h

bit13 bit0

bit 13-8, 5-4: CP1:CP0: Code Protection bits (2)

Code Protection for 2K Program memory (PIC16C716)

11 = Programming code protection off

10 = 0400h - 07FFh code protected

01 = 0200h - 07FFh code protected

00 = 0000h - 07FFh code protected

bit 13-8, 5-4:

Code Protection for 1K Program memory (PIC16C712)

11 = Programming code protection off

10 = Programming code protection off

01 = 0200h - 03FFh code protected

00 = 0000h - 03FFh code protected

bit 7: Unimplemented: Read as ’1’

bit 6: BODEN: Brown-out Reset Enable bit (1)

1 = BOR enabled

0 = BOR disabled

bit 3: PWRTE: Power-up Timer Enable bit (1)

1 = PWRT disabled

0 = PWRT enabled

bit 2: WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator

10 = HS oscillator

01 = XT oscillator

00 = LP oscillator

Note 1:Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.

Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.

2:All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

 1999 Microchip Technology Inc. Preliminary DS41106A-page 53

PIC16C712/716

9.2 Oscillator Configurations

9.2.1 OSCILLATOR TYPES

The PIC16CXXX can be operated in four diff erent oscil-

lator modes. The user can program two configuration

bits (FOSC1 and FOSC0) to select one of these four

modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC Resistor/Capacitor

9.2.2 CRYSTAL OSCILLATOR/CERAMIC

RESONATORS

In XT, LP or HS modes, a crystal or ceramic resonator

is connected to the OSC1/CLKIN and OSC2/CLKOUT

pins to establish oscillation (Figure 9-2). The

PIC16CXXX oscilla tor design requires the use of a par-

allel cut crystal. Use of a series cut crystal may give a

frequency out of the crystal manufacturers specifica-

tions. When in XT, LP or HS modes, the device can

have an external clock source to drive the

OSC1/CLKIN pin (Figure 9-3).

FIGURE 9-2: CRYSTAL/CERAMI C

RESONATOR OPERATION

(HS, XT OR LP

OSC CONFIGURATION)

FIGURE 9-3: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP

OSC CONFIGURATION)

Note 1: See Table 9-1 and Table 9-2 for recom-

mended values of C1 and C2.

2: A series resistor (RS) may be required for

AT strip cut crystals.

3: RF varies with the crystal chosen.

C1(1)

C2(1)

XTALOSC2

OSC1

RF(3) SLEEP

logic

PIC16C7XX

RS(2)

internal

OSC1

OSC2

Open

Clock from

ext. system PIC16C7XX

TABLE 9-1 CERAMIC RESONATORS

TABLE 9-2 CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Ranges Tested:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

68 - 100 pF

15 - 68 pF

68 - 100 pF

15 - 68 pF

HS 8.0 MHz

16.0 MHz 10 - 68 pF

10 - 22 pF 10 - 68 pF

10 - 22 pF

These values are for design guidance only. See

notes at bottom of page.

Osc Type Crystal

Freq Cap. Range

C1 Cap. Range

LP 32 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 200 kHz 47-68 pF 47-68 pF

1 MHz 15 pF 15 pF

4 MHz 15 pF 15 pF

HS 4 MHz 15 pF 15 pF

8 MHz 15-33 pF 15 -33 pF

20 MHz 15-33 pF 15-33 pF

These values are for design g uidance onl y. See

notes at bottom of page.

Note1: Recommended values of C1 and C2 are

identical to the ranges tested (Table 9-1).

2: Higher capacitance increases the stability

of the oscilla tor, but also i ncreas es the start-

up time.

3: Since each resonator/crystal has its own

characteristics, the user should consult the

resonator/c rystal manufacturer for appropri-

ate values of external components.

4: Rs may be required in HS mode, as well as

XT mode to avoid overdriving crystals with

low drive level specification.

PIC16C712/716

DS41106A-page 54 Preliminary  1999 Microchip Technology Inc.

9.2.3 RC OSCILLATOR

For timing insensitive applications, the “RC” device

option offers additional cost savings. The RC oscillator

frequency is a fu nction of the supply voltage, the resis-

tor (REXT) and capacitor (CEXT) values and the operat-

ing temperature. In addition to this, the oscillator

frequency will var y from unit to unit due to normal pro-

cess parameter variation. Furthermore, the difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

CEXT values. The user also needs to take into account

variation due to tolerance of external R and C compo-

nents used. Figure 9-4 shows how the R/C combina-

tion is connected to the PIC16CXXX.

FIGURE 9-4: RC OSCILLATOR MODE

OSC2/CLKOUT

Cext

Rext

PIC16C7XX

OSC1

Fosc/4

Internal

clock

VDD

VSS

Recommended values: 3 kΩ ≤ Rext ≤ 100 kΩ

Cext > 20pF

9.3 Reset

The PIC16CXXX differentiates between various kinds

of reset:

• Power-on Reset (POR)

•MCLR

reset during normal operation

•MCLR reset during SLEEP

• WDT Reset (during normal operation)

• WDT Wake-up (during SLEEP)

• Brown-out Reset (BOR)

Some registers are not aff ected in an y reset condition;

their status is unknow n on POR and unchanged in any

other reset. Most other registers are reset to a “reset

state” on Power-on Reset (POR), on the MCLR and

WDT Reset, on MCLR reset during SLEEP and

Brown-out Reset (BOR). They are not affected by a

WDT Wake-up, which is viewed as the resumption of

normal operation. The TO and PD bits are set or

cleared differently in different reset situations as indi-

cated in Table 9-4. These bits are used in software to

determine the nature of the re set. See Table 9-6 for a

full description of reset states of all registers.

A simplifi ed b loc k diag ram of the on-ch ip res et circui t is

shown in Figure 9-6.

The PICmicro microcontrollers have a MCLR noise fil -

ter in the MCLR reset path. The filter will detect and

ignore small pulses.

It should be noted that a WDT Reset

does not drive

MCLR pin low.

 1999 Microchip Technology Inc. Preliminary DS41106A-page 55

PIC16C712/716

9.4 Power-On Reset (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (to a level of 1.5V - 2.1V). To take

advantage of the POR, just tie the MCLR pin directly (or

through a resistor) to VDD. This will eliminate external

RC components usually needed to create a Power-on

Reset. A maximum rise time for VDD is specified

(par ameter D004 ). For a s low rise ti me, see F igure 9-5.

When the device starts normal operation (exits the

reset co ndi tion), device operati ng p ar am ete rs (voltage,

frequency, temperature,...) must be met to ensure oper-

ation. If these conditions are not met, the device must

be held in reset until the operating conditions are met.

Brown-out Reset ma y be used to meet the sta rt-up con-

ditions.

FIGURE 9-5: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

Note1: External P ower-on Reset circuit is required

only if V DD power-up s lope is too slo w . The

diode D helps discharge the capacitor

quickl y when VDD powers down.

2: R < 40 kΩ is recommended to make sure

that voltag e drop across R does not vi olate

the device’s electrical specification.

3: R1 = 100Ω to 1 kΩ will limit any current

flowing into MCLR from external capacitor

C in the event of MCLR/VPP pin break -

down due to Electrostatic Discharge

(ESD) or Electrical Overstress (EOS).

VDD

MCLR

PIC16C7XX

VDD

9.5 Power-up Timer (PWRT)

The Power-up Timer provides a fixed nominal time-out

(param eter #33 ), on po w er-up onl y, from the POR. The

Power-up Timer operates on an internal RC oscillator.

The chi p is k e pt in reset a s long as the PW R T i s act iv e .

The PWRT’ s time delay allows VDD to rise to an accept-

able level. A configuration bit is provided to enable/dis-

able the PWRT.

The pow er- up time dela y will vary from chip to ch ip due

to VDD, temperature, and process variation. See DC

parameters for details.

9.6 Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWR T dela y is ov er (parameter #3 2). This ensures that

the crystal osci llator or resonato r has started and stabi-

lized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

9.7 Brown-Out Reset (BOD)

The PIC16C712/716 members have on-chip Bro wn-out

Reset circuitry. A configu ration bit, BODEN, can disable

(if clear/programmed) or enable (if set) the Brown-out

Reset circuitry. If VDD falls below 4.0V, refer to VBOR

parameter D005(VBOR) for a time greater than param-

eter (TBOR) in Table 12-6. The brown-out situation will

reset the ch ip . A reset is not gu arantee d to occur if VDD

falls below 4.0V for less than parameter (TBOR).

On any reset (Power-on, Brown-out, Watchdog, etc.)

the chip will remain in Reset until VDD rises above

VBOR. The P ow er-up Ti mer will no w be i nv oke d and wil l

keep the chip in reset an additional 72 ms.

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Po wer-up Tim er will be r e-initiali zed. O nce VDD

rises above VBOR, the Power-Up Timer will execute a

72 ms reset. The Power-up Timer should always be

enabled when Brown-out Reset is enabled. Figure 9-7

shows typical Brown-out situations.

For operations where the desired brown-out voltage is

other than 4V, an external brown-out circuit must be

used. F igure 9-8, 9-9 and 9-10 s how e xamples o f ext er-

nal brown-out protection circuits.

PIC16C712/716

DS41106A-page 56 Preliminary  1999 Microchip Technology Inc.

FIGURE 9-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

FIGURE 9-7: BROWN-OUT SITUATIONS

External

Reset

MCLR

VDD

OSC1

WDT

Module

VDD rise

detect

OST/PWRT

On-chip

RC OSC

WDT

Time-out

Po wer-on Reset

OST

10-bit Ripple counter

PWRT

Chip_Reset

10-bit Ripple counter

Reset

Enable OST

Enable PWRT

SLEEP

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

Brown-out

Reset BODEN

(1)

PWRT

BODEN See Table 9-3 for time -out

situations.

72 ms

VBOR

VDD

Internal

Reset

VBOR

VDD

Internal

Reset 72 ms

<72 ms

72 ms

VBOR

VDD

Internal

Reset

 1999 Microchip Technology Inc. Preliminary DS41106A-page 57

PIC16C712/716

FIGURE 9-8: EXTERNAL BROWN-OUT

PROTEC TION CIRCUIT 1

FIGURE 9-9: EXTERNAL BROWN-OUT

PROTEC TION CIRCUIT 2

Note1: This circuit will activ ate res et when VDD

goes below (Vz + 0.7V) where

Vz = Zener voltage.

2: Internal Brown-out Reset circuitry

should be disabled when using this cir-

cuit.

VDD 33k

10k

40k

VDD

MCLR

PIC16C7XX

Note1: This bro w n-out ci rcuit is less e xpe nsiv e ,

albeit les s a cc urate . Tran si sto r Q 1 t urns

off when VDD is below a certain level

such that:

2: Internal brown-out reset should be dis-

abled when using this circuit.

3: Resistors should be adjusted for the

characteristics of the transistor.

VDD x R1

R1 + R2 = 0.7 V

VDD

R2 40k

VDD

MCLR

PIC16C7XX

FIGURE 9-10: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 3

9.8 Time-out Sequence

On pow er-up the time-o ut se que nce is as f ol lows: Firs t

PWR T time-ou t is in vok ed after the POR time de lay has

expired. Then OST is a ctivate d. Th e total time -out w ill

v ary based on osc il lat or c on f ig ur ati on and the status of

the PWRT. For example, in RC mode with the PWRT

disabled, there will be no time-out at all. Figure 9-11,

Figure 9-12, and Figure 9-13 depict time-out

sequences on power-up.

Since the time-outs occu r from the POR puls e, if MCLR

is k ept lo w lon g enoug h, the time -outs wil l e xpire . The n

bringing MCLR high will begin execution immediately

(Figure 9-13). This is useful for testing pur poses or to

synchronize more than one PIC16CXXX de vice operat-

ing in parallel.

Table 9-5 shows the reset conditions for some special

function registers , whil e Tabl e 9-6 sh ows the reset co n-

ditions for all the registers.

9.9 Power Control/Status Register

(PCON)

The Power Control/Status Register, PCON has two

bits.

Bit0 is Bro wn-out Reset Sta tus bit, BOR. If the BODEN

configuration bit is set, BOR is ’1’ on Power-on Reset.

If the BODEN configuration bit is clear, BOR is

unknown on Power-on Reset.

The BOR status bit is a "don't care" and is not neces-

sarily predictable if the bro wn-out circuit is disab led (the

BODEN configuration bit is clear). BOR must then be

set by the user and checked on subsequent resets to

see if it is clear, indicating a brown-out has occurred.

Bit1 is POR (P ower-on Reset Status bit). It is cleared on

a Power-on Reset and unaffected otherwise. The user

must set this bit following a Power-on Reset.

This brown-out protection circuit employs

Microchip Technology’s MCP809 microcontroller

supervisor. The MCP8XX and MCP1XX families

of supervisors provide push-pull and open

collector outputs with both high and low active

reset pins. There are 7 different trip point

selections to accommodate 5V and 3V systems

MCLR

PIC16C7XX

VDD

Vss

RST

MCP809

VDD

bypass

capacitor

PIC16C712/716

DS41106A-page 58 Preliminary  1999 Microchip Technology Inc.

TABLE 9-3 TIME-OUT IN VARIOUS SITUATIONS

TABLE 9-4 STATUS BITS AND THEIR SIGNIFICANCE

TABLE 9-5 RESET CONDITION FOR SPECIAL REGISTERS

Oscillator Co nfigu ration Power-up Brown-out Wake-up from

SLEEP

PWRTE = 0 P WRTE = 1

XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC

RC 72 ms —72 ms —

POR BOR TO PD

0x11Power-on Reset

0x0xIllegal, TO is set on POR

0xx0Illegal, PD is set on POR

1011Brown-out Reset

1101WDT Reset

1100WDT Wake-up

11uuMCLR Reset during normal operation

1110MCLR Reset during SLEEP or interrupt wake-up from SLEEP

Condition Program

Counter STATUS

Power-on Reset 000h 0001 1xxx ---- --0x

MCLR Reset during normal operation 000h 000u uuuu ---- --uu

MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu

WDT Reset 000h 0000 1uuu ---- --uu

WDT Wake-up PC + 1 uuu0 0uuu ---- --uu

Brown-o ut Rese t 000h 0001 1uuu ---- --u0

Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu

Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.

Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

 1999 Microchip Technology Inc. Preliminary DS41106A-page 59

PIC16C712/716

TABLE 9-6 INITIALIZATION CONDITIONS FOR ALL REGISTERS OF THE PIC16C712/716

Brown-out Reset MCLR Resets

WDT Reset Wake-up via WDT or

Interrupt

Wxxxx xxxx uuuu uuuu uuuu uuuu

INDF N/A N/A N/A

TMR0 xxxx xxxx uuuu uuuu uuuu uuuu

PCL 0000h 0000h PC + 1(2)

STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3)

FSR xxxx xxxx uuuu uuuu uuuu uuuu

PORTA(4) --0x 0000 --xx xxxx --xu uuuu

PORTB(5) xxxx xxxx uuuu uuuu uuuu uuuu

DATACCP ---- -x-x ---- -u-u ---- -u-u

PCLATH ---0 0000 ---0 0000 ---u uuuu

INTCON 0000 -00x 0000 -00u uuuu -uuu(1)

PIR1 ---- 0000 ---- 0000 ---- uuuu(1)

-0-- 0000 -0-- 0000 -u-- uuuu(1)

TMR1L xxxx xxxx uuuu uuuu uuuu uuuu

TMR1H xxxx xxxx uuuu uuuu uuuu uuuu

T1CON --00 0000 --uu uuuu --uu uuuu

TMR2 0000 0000 0000 0000 uuuu uuuu

T2CON -000 0000 -000 0000 -uuu uuuu

CCPR1L xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1H xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON --00 0000 --00 0000 --uu uuuu

ADRES xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 0000 00-0 0000 00-0 uuuu uu-u

OPTION_REG 1111 1111 1111 1111 uuuu uuuu

TRISA --11 1111 --11 1111 --uu uuuu

TRISB 1111 1111 1111 1111 uuuu uuuu

TRISCCP xxxx x1x1 xxxx x1x1 xxxx xuxu

PIE1 ---- 0000 ---- 0000 ---- uuuu

-0-- 0000 -0-- 0000 -u-- uuuu

PCON ---- --0q ---- --uq ---- --uq

PR2 1111 1111 1111 1111 1111 1111

ADCON1 ---- -000 ---- -000 ---- -uuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition

Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

3: See Table 9-5 for reset value for specific condition.

4: On any device reset, these pins are configured as inputs.

5: This is the value that will be in the por t output latch.

PIC16C712/716

DS41106A-page 60 Preliminary  1999 Microchip Technology Inc.

FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

FIGURE 9-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 9-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

 1999 Microchip Technology Inc. Preliminary DS41106A-page 61

PIC16C712/716

9.10 Interrupts

The PIC16C712/716 devices have up to 7 sources of

interrupt. The interrupt control register (INTCON)

records individual interrupt requests in flag bits. It also

has individual and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared ) all in terrupts . W hen bit GIE is enab le d, and a n

interrupt’ s flag bit and mas k bit are set, the interrupt wil l

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in vari-

ous registers. Individual interrupt bits are set,

regardless of the status of the GIE bit. The GIE bit is

cleared on reset.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enabl es interrupts.

The RB0/INT pin interrupt, the RB po rt change interrupt

and the TMR0 overflow interrupt flags are contained in

the INTCON register.

Note: Indiv id ual int errupt fla g bits are se t rega rd-

les s of the status of their corresponding

mask bit or the GIE bit.

The peripheral interrupt flags are contained in the spe-

cial function regi sters, PIR1 and PIR2. The correspond-

ing interrupt enable bits are contained in special

function registers, PIE1 and PIE2, and the peripheral

interrupt enab le bit i s co nta ine d i n speci al function re g-

ister, INTCON.

When an interrupt is responded to, the GIE bit is

cleared to disable any further interrupt, the return

address is pu sh ed onto the sta ck and the PC is lo ade d

with 0004h. Once in the interrupt service routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid recursive interrupt s.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs. The latency

is the s am e for one or two cy cl e instructions. I ndi vidual

interrupt flag bits are set, regardless of the status of

their corresponding mask bit or the GIE bit.

FIGURE 9-14: INTERRUPT LOGIC

ADIF

ADIE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

T0IF

T0IE

INTF

INTE

RBIF

RBIE

GIE

PEIE

Wake -up (If in SLEEP mode)

Interrupt to CPU

PIC16C712/716

DS41106A-page 62 Preliminary  1999 Microchip Technology Inc.

9.10.1 INT INTERRUPT

External interrupt on RB0/INT pin is edge triggered,

either rising if bit INTEDG (OPTION_REG<6>) is set,

or falling if the INTEDG bit is clear. When a valid edge

appears on the RB0/INT pin, flag bit INTF

(INTCON<1>) is set. This interrupt can be disabled by

clearing enable bit INTE (INTCON<4>). Flag bit INTF

must be cleare d in softw are in th e interrupt service ro u-

tine before re-enabling this interrupt. The INT interrupt

can w ake-up the processor fr om SLEEP, if bit I NTE was

set prior to going in to SLEEP. The status of global int er-

rupt enable bit GIE decides whether or not the proces-

sor br anche s to t he i nter rup t vecto r following wa ke-up.

See Section 9.13 for details on SLEEP mode.

9.10.2 TMR0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will set

flag bit T0IF (INTCON<2>). The interrupt can be

enabled/disabled by setting/clearing enable bit T0IE

(INTCON<5>). (Section 4.0)

9.10.3 PORTB INTCON CHANGE

An input change on PORTB<7:4> sets flag bit RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit RBIE (INTCON<4>).

(Section 3.2)

9.11 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key reg-

isters during an interrupt, (i.e., W register and STATUS

Example 9-1 stores and restores the W and STATUS

registers. The register, W_TEMP, must be defined in

each ban k and m ust be def ined at the same offs et from

the bank base address (i.e., if W_TEMP is defined at

0x20 in bank 0, i t m u st als o b e d efi ned at 0xA0 i n ba nk

1).

The example:

a) Stores the W register.

b) Stores the STATUS register in bank 0.

c) Stores the PCLATH register.

d) Executes the interrupt service routine code

(User-generated).

e) Restores the STATUS register (and bank select

bit).

f) Restores the W and PCLATH registers.

EXAMPLE 9-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero

SWAPF STATUS,W ;Swap status to be saved into W

CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0

MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register

MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3

MOVWF PCLATH_TEMP ;Save PCLATH into W

CLRF PCLATH ;Page zero, regardless of current page

BCF STATUS, IRP ;Return to Bank 0

MOVF FSR, W ;Copy FSR to W

MOVWF FSR_TEMP ;Copy FSR from W to FSR_TEMP

:(ISR)

MOVF PCLATH_TEMP, W ;Restore PCLATH

MOVWF PCLATH ;Move W into PCLATH

SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W

;(sets bank to original state)

MOVWF STATUS ;Move W into STATUS register

SWAPF W_TEMP,F ;Swap W_TEMP

SWAPF W_TEMP,W ;Swap W_TEMP into W

 1999 Microchip Technology Inc. Preliminary DS41106A-page 63

PIC16C712/716

9.12 Watchdog Timer (WDT)

The Watchdog Timer is as a free running, on-chip, RC

oscillator which does not require any external compo-

nents . T his RC os cilla tor is s epar ate from the R C osci l-

lator of the OSC1/CLKIN pin. That means that the WDT

will run, even if the clock on the OSC1/CLKIN and

OSC2/CLKOUT pins of the device have been stopped,

for ex ample, by execution of a SLEEP instruction.

During normal operation, a WDT time-out generates a

device RESET (W atchdog Timer Reset). If the de vice is

in SLEEP mode, a WDT time-out causes the device to

wake-up and continue with normal operation (Watch-

dog Timer W ake-up). The T O bit in the STATUS register

will be cleared upon a Watchdog Timer time-out.

The WDT can be permanently disabled by clearing

configuration bit WDTE (Section 9.1).

WDT time-out period values may be found in the Elec-

trical Specifications section under TWDT (parameter

#31). Values for the WDT prescaler (actually a

postscaler, but shared with the Timer0 prescaler) may

be assigned using the OPTION_REG register.

Note: The CLRWDT and SLEEP instructions clear

the WDT an d th e postsc al er, if as si gn ed to

the WDT, and prev ent it from timing out and

generating a device RESET condition.

Note: When a CLRWDT instruction is executed

and the prescaler is assigned to the WDT,

the prescaler count will be cleared, but the

presc al er ass ig nme nt is not changed.

FIGURE 9-15: WATCHDOG TIMER BLOCK DIA GRAM

FIGURE 9-16: SUMMARY OF WATCHDOG TIMER REGISTERS

Address Name Bits 13:8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2007h Config. bits (1) —BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0

81h OPTION_REG N/A RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

Legend: Shaded cells are not used by the Watchdog Timer.

Note1: See Figure 9-1 for operation of these bits.

From TMR0 Clock Source

(Figure 4-2)

To TMR0 (Figure 4-2)

Postscaler

WDT Timer

WDT

Enable Bit

PSA

8 - to - 1 MUX PS2:PS0

MUX PSA

WDT

Time-out

Note: PSA and PS2:PS0 are bits in the OPTION_REG register.

PIC16C712/716

DS41106A-page 64 Preliminary  1999 Microchip Technology Inc.

9.13 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but

ke eps running , the PD bit (STATUS<3>) is clea red, th e

TO (STATUS<4>) bit is set, and the oscillator driver is

tur ned off. The I/O por ts maint ain the st atus they had,

before the SLEEP instruction was executed (driving

high, low, or hi-impedance).

For lowest current consumption in this mode, place all

I/O pins at either VDD or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down

the A/D and the d isab le external clocks. Pull all I/O pins ,

that are hi-impedance inputs, high or low externally to

avoid s wi tc hin g c urre nts ca us ed by flo ati ng inputs . Th e

T0CKI input should also be at VDD or VSS for lowest

current consumption. The contribution from on-chip

pull-ups on PORTB should be considered.

The MCLR pin must be at a logic high level (VIHMC).

9.13.1 WAKE-UP FROM SLEEP

The device can wake up from SLEEP through one of

the following events:

1. External reset input on MCLR pin.

2. Watchdog Timer Wake-up (if WDT was

enabled).

3. Interrupt from INT pin, RB port change, or s ome

peripheral interrupts.

External MCLR Reset will cause a device reset. All

other events are considered a continuation of program

execution and cause a "wake-up". The TO and PD bits

in the STATUS register can be used to determine the

cause of device reset. The PD bit, which is set on

power-up, is cleared when SLEEP is invoked. The TO

bit is cleared if a WDT time-out occurred (and caused

wake-up).

The following peripheral interrupts can wake the device

from SLEEP:

1. TMR1 interrupt. Timer1 must be operating as

an asynchronous counter.

2. CCP capture mode interrupt.

3. Special event trigger (Timer1 in asynchronous

mode using an external clock).

Other peripherals cannot generate interrupts, since

during SLEEP, no on-chip clocks are present.

When th e SLEEP inst ruction is being ex ecuted, the ne xt

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

inte rrup t ena ble bit mus t be set (enabled ). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instr uct ion . If t he GIE bi t is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

ru pt ad dress (00 04h ). In ca ses wh ere the execution of

the instruction following SLEEP is not desirable, the

user shoul d have a NOP after the SLEEP instruction.

9.13.2 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and inte rrupt flag bit se t, one o f the f o llo wing w ill o ccur:

• If the interrupt occurs before the execution of a

SLEEP instruction, the SLEEP instruction wi ll com -

plete as a NOP. Therefore, the WDT and WDT

pos tscaler wi ll not be cleared, the TO bit will not

be set and PD bits will not be cleare d.

• If the interrupt occurs during or after the execu-

tion of a SLEEP instruction, the device will imme-

diately wake up from slee p. The SLEEP instruction

will be completely executed before the wake-up.

Therefore, the WDT and WDT postscaler will be

cleared, the TO bit will be set and the PD bit will

be cleared.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instru ction executed , test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDT inst ruc-

tion should be executed before a SLEEP instruction.

 1999 Microchip Technology Inc. Preliminary DS41106A-page 65

PIC16C712/716

FIGURE 9-17: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

PC PC+1 PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

TOST(2)

PC+2

Note 1: XT, HS or LP oscillator mode assumed.

2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.

3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.

4: CLKOUT is not available in these osc modes, but shown here for timing reference.

9.14 Progr am Verification/Code Protection

If the code protection bit(s) have not been pro-

grammed, the on-chip program memory can be read

out for verificati on purposes.

9.15 ID Locations

F our memory locatio ns (2000h - 2003h) are designate d

as ID locations where the user can store checksum or

other code-identification numbers. These locations are

not accessible during normal execution, but are read-

able and writable during program/verify. It is recom-

mended that only the 4 least significant bits of the ID

location are used.

For ROM devices, these values are submitted along

with the ROM code.

Note: Microchip does not recommend code pro-

tecting windowed devices.

9.16 In-Circuit Serial Pr ogramming™

PIC16CXXX microcontrollers can be serially pro-

grammed while in the end application circuit. This is

simply d one with two lin es f or cloc k a nd data, a nd three

other line s for pow er , ground and the prog ramming v olt-

age. This all ows c ustomers to manufacture boards with

unprogrammed devices, and then program the micro-

controller just before shipping the product. This also

allows the most recent firmware or a custom firmware

to be programmed.

For complete details on serial programming, please

refer to the In-Circuit Serial Programming (ICSP™)

Guide, (DS30277).

PIC16C712/716

DS41106A-page 66 Preliminary  1999 Microchip Technology Inc.

NOTES:

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 67

10.0 INSTRUCTION SET SUMMARY

Each PIC16CXXX instruction is a 14-bit word divided

into an OPCODE which specifies the instruction type

and one or more operands which further specify the

operation of the instruction. The PIC16CXXX instruc-

tion set summary in Table 10-2 lists byte-oriented, bit-

oriented, a nd literal and contr ol operat ions. Tabl e 10-

1 shows the opcode fie l d descriptions.

For byte-oriented instructions, ’f’ represents a file reg-

ister designator and ’d’ represents a destination desig-

nator. The file register designator specifies which file

The desti nation designator specifies where the result of

the operation is to be placed. If ’d’ is zero, the result is

placed in the W regi ster . If ’d ’ is one , the result i s placed

in the file register specified in the instruction.

For bit-oriented instructions, ’b’ represents a bit field

design ator whic h s el ec ts t he num ber of th e bit affected

by the operation, while ’f’ represents the number of the

file in which the bit is located.

For literal and control operations, ’k’ represents an

eigh t or eleven bit constant or l iteral value.

TABLE 10-1 OPCODE FIELD

DESCRIPTIONS

The ins truc ti o n se t is hig hl y orthog on a l an d is group ed

into three basic categories:

•Byte-oriented operations

•Bit-oriented operations

•Literal and cont r ol operations

All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the pro-

gram counter is changed as a result of an instruction.

In thi s case, t he execut ion takes t wo instruc tio n cycl es

with the second cycle ex ecuted as a NOP. One instruc-

tion cycle consists of four oscillator periods. Thus, for

an osci llator frequ ency of 4 MHz, the normal instructio n

e xecution time i s 1 µs . If a con dition al test is true or the

program counter is changed as a result of an instruc-

tion, the instruction execution time is 2 µs.

Table 10-2 lists the instructions recognized by the

MPASM assembler .

Figur e 10-1 sh ows the g eneral f ormats that th e instruc-

tions can have.

All examples use the following format to represent a

hexadecimal number:

0xhh

where h signifies a hexadecimal digit.

FIGURE 10-1: GENERAL FORMAT FOR

INSTRUCTIONS

A description of each instruction is available in the

PICmicro™ Mid-Range Reference Manual,

(DS33023).

Field Description

fRegister file address (0x00 to 0x7F)

WWorking register (accumulator)

bBit address within an 8-bit file register

kLiteral field, constant data or label

xDon’t care location (= 0 or 1)

The assembler will generat e code with x = 0. I t is t he

recommended form of use for compatibility with all

Microchip software tools.

dDestination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1

PC Program Counter

TO Time-out bit

PD Power-down bit

ZZero bit

DC Digit Carry bit

CCarry bit

Note: To maintain upward compatibility with

future PIC16CXXX products, do not use

the OPTION and TRIS instructions.

Byte-oriented file register operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 7-bit file register address

Bit-oriented file register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

13 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

PIC16C712/716

DS41106A-page 68 Preliminary  1999 Microchip Technology Inc.

TABLE 10-2 PIC16CXXX INSTRUCTION SET

Mnemonic,

Operands Description Cycles 14-Bit Opcode Stat us

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Add W and f

AND W with f

Clear f

Clear W

Compleme nt f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0000

dfff

lfff

0xx0

dfff

ffff

0011

ffff

0000

ffff

C,DC,Z

1,2

1,2,3

1,2

1,2,3

1,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if C lear

Bit Test f, Skip if Set

1 (2)

00bb

01bb

10bb

11bb

bfff

ffff

1,2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move lit eral to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into standby mode

Subtract W from literal

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C,DC,Z

TO,PD

C,DC,Z

Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external

devi ce , the data will be written back with a ’ 0’.

2: If this instruction is e x ecuted on the T MR0 register (and, where applicable , d = 1), the prescaler will be cleared if assigned

to the Timer0 Module.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

 1999 Microchip Technology Inc. Preliminary DS41106A-page 69

PIC16C712/716

11.0 DEVELOPMENT SUPPORT

11.1 Developme nt Tools

The PICmicro microcontrollers are supported with a

full r an ge of hardw are and softw are d e velopment to ols:

• MPLAB -ICE Real-Time In -Circuit Emula tor

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX

In-Circuit Emulator

•PRO MATE

 II Universal Programmer

• PICSTART Plus Entry -Level Prototype

Programmer

• SIMICE

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

• MPLAB SIM Software Simulator

• MPLAB-C17 (C Compiler)

• Fuzzy Logic Development System

(

fuzzy

TECH−MP)

•KEELOQ® Evaluation Kits and Programmer

11.2 MPLAB-ICE: High Performance

Universal In-Circuit Emulator with

MPLAB IDE

The MPLAB-ICE Universal In-Circuit Emulator is

inte nded to provi de t he pr oduc t developm ent en gin eer

with a complete microcontroller design tool set for

PICmicro microcontroll ers (MCUs). M PLAB-ICE is su p-

plied with the MPLAB Integrated Development Environ-

ment (IDE), which allows editing, “make” and

download, and source debugging from a single envi-

ronment.

Interchangeable processor modules allow the system

to be easily reconfigured for emulation of different pro-

cessors. The universal architecture of the MPLAB-ICE

allows expansion to support all new Microchip micro-

controllers.

The MPLAB-ICE Emulator System has been designed

as a real-time emulation system with advanced fea-

tures that are generally found on more expensive devel-

opment tools. The PC compatible 386 (and higher)

machine platform and Microsoft Windows 3.x or

Windows 95 environment were chosen to best make

these features available to you, the end user.

MPLAB-ICE is available in two versions.

MPLAB-I CE 1000 is a basic , low-c ost em ulat or syste m

with si mple trac e capabili ties. It shares proce ssor mod-

ules with the MPLAB-ICE 2000. This is a full-featured

emul ator sys tem with e nhanced trace , trigger, and da ta

monitoring features. Both systems will operate across

the entire op erating s peed range of the PICm icro MCU .

11.3 ICEPIC: Low-Cost PICmicro

In-Circuit Emulator

ICEPIC is a low-cost in-circuit emulator solution for the

Microchip PIC12CXXX, PIC16C5X and PIC16CXXX

families of 8-bit OTP microcontrollers.

ICEPIC is designed to operate on PC-compatible

machines ranging from 386 through Pentium based

machines under Windows 3.x, Windows 95, or Win-

dow s NT e n v iro nm en t. ICEPIC fe atur es re al ti me, non-

intrusive emulation.

11.4 PRO MATE II: Universal Programmer

The PRO MATE II Universal Programmer is a full-fea-

tured programmer capable of operating in stand-alone

mode as well as PC-hosted mode. PRO MATE II is CE

compliant.

The PRO MATE II has programmable VDD and VPP

supplies which allows it to verify programmed memory

at VDD mi n an d V DD max for maximum reliability. It has

an LCD display for displaying error messages, keys to

enter commands and a modular detachable socket

assembly to support various package types. In stand-

alone mode the PRO MATE II can read, verify or pro-

gram PIC12CXXX, PIC14C000, PIC16C5X,

PIC16CXXX and PIC17CXX devices. It can also set

configuration and code-protect bits in this mode.

11.5 PICSTART Plus Entry Level

Development System

The PICSTART programmer is an easy-to-use, low-

cost prototype programmer. It connects to the PC via

one of the COM (RS-232) ports. MPLAB Integrated

Development Environment software makes using the

programmer simple and efficient. PICSTART Plus is not

recommended for production programming.

PICSTART Plus supports all PIC12 CXXX, PIC14C000,

PIC16C5X, PIC16CXXX and PIC17CXX devices with

up to 40 pins. Larger pin count devices such as the

PIC16C923, PIC16C924 and PIC17C756 may be sup-

ported with an adapter socket. PICSTART Plus is CE

compliant.

PIC16C712/716

DS41106A-page 70 Preliminary  1999 Microchip Technology Inc.

11.6 SIMICE Entry-Level Hardware

Simulator

SIMICE is an entry-level hardware development sys-

tem designed to operate in a PC-based environment

with Microchip’s simulator MPLAB™-SIM. Both SIM-

ICE and MPLAB-SIM run under Microchip Technol-

ogy’s MPLAB Integrated Development Environment

(IDE) softw are. Specific ally, SIMICE provides h ardware

simulation for Microchip’s PIC12C5XX, PIC12CE5XX,

and PIC1 6C5X families of PIC micro 8-bit m icrocontro l-

lers. SIMICE works in conjunction with MPLAB-SIM to

provide non-real-time I/O port emulation. SIMICE

enables a developer to run simulator code for driving

the target system. In addition, the target system can

provide input to the simulator code. This capability

allows for simple and interactive debugging without

having to manually generate MPLAB-SIM stimulus

files. SIMICE is a valuable debugging tool for entry-

level system development.

11.7 PICDEM-1 Low-Cost PICmicro

Demonstration Board

The PICDEM-1 is a simple board which demonstrates

the capabilities of several of Microchip’s microcontrol-

lers. The microcontrollers supported are: PIC16C5X

(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,

PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and

PIC17C44. All necessary hardware and software is

included to run basic demo programs. The users can

program the sample microcontrollers provided with

the PICDEM-1 board, on a PRO MATE II or

PICSTART-Plus programmer, and easily test firm-

ware. The user can also connect the PICDEM-1

board to the MPLAB-ICE em ulator and dow nlo a d t h e

firmware to the emulator for testing. Additional proto-

type area is available for the user to build some addi-

tional hardware and connect it to the microcontroller

socket(s). Some of the features include an RS-232

interface, a potentiometer for simulated analog input,

push-button switches and eight LEDs connected to

PORTB.

11.8 PICDEM-2 Low-Cost PIC16CXX

Demonstration Board

The PICDEM-2 is a simple demonstration board that

supports the PIC16C62, PIC16C64, PIC16C65,

PIC16C73 and PIC16C74 microcontrollers. All the

necessary hardware and software is included to

run the basic demonstration programs. The user

can program the sample microcontrollers provided

with the PICDEM-2 board, on a PRO MATE II pro-

grammer or PICSTART-Plus , an d easily tes t firmware .

The MPLAB-ICE emulator may also be used with the

PICDEM-2 board to test firmware. Additional prototype

area has been provided to the user for adding addi-

tional ha rdware and connectin g it to the mic rocontroll er

soc ke t(s). Some of th e f eatures inc lude a R S-232 inter-

face, push-button switches, a potentiometer for simu-

lated analog input, a Serial EEPROM to demonstrate

usage of th e I2C bu s and separ ate hea ders f or connec -

tion to an LCD module and a keypad.

11.9 PICDEM-3 Low-Cost PIC16CXXX

Demonstration Board

The PICDEM-3 is a simple demonstration board that

supports the PIC16C923 and PIC16C924 in the PLCC

package. It will also support future 44-pin PLCC

microc ont roll ers w ith a LCD Mo dul e . All the ne ces -

sary hardware and software is included to run the

basic demonstration programs. The user can pro-

gram the sample microcontrollers provided with

the PI CDE M-3 bo ar d, on a P RO MAT E II pr ogram-

mer or PICSTART Plus with an adapter socket, and

easily test firmware. The MPLAB-ICE emulator may

also be used with the PICDEM-3 board to test firm-

ware. Addit ional protot ype a rea has been provided to

the us er for adding ha rdware and con necti ng it to the

microcontroller socket(s). Some of the f eatures inc lude

an RS-232 interface, push-button switches, a potenti-

ometer for simulated analog input, a thermistor and

separate headers for connection to an external LCD

module and a k e y pad. Als o pro vide d on th e PICDEM -3

board is an LCD panel, with 4 commons and 12 seg-

ments, that is capable of displaying time, temperature

and day of the w e ek . Th e P I CD EM-3 provide s a n add i-

tional RS-232 interface and Windows 3.1 software for

showing the demulti plex ed LCD signals on a PC . A sim-

ple serial interface allows the user to construct a hard-

ware demultiplexer for the LCD signals.

 1999 Microchip Technology Inc. Preliminary DS41106A-page 71

PIC16C712/716

11.10 MPLAB Integrated Development

Environment Software

The MPLAB IDE Software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. MPLAB is a windows based application

which contains:

• A full featured editor

• Three operating modes

-editor

-emulator

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Exten si ve on-l ine help

MPLAB allows you to:

• Edit your source files (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro tools (automatically updates all

project information)

• Debug using:

- source files

- absolute listing file

The ability to use MPLAB with Microchip’s simulator

allows a consistent platform and the ability to easily

switch from the low cost simulator to the full featured

emulator with minimal retraining due to development

tools.

11.11 Assembler (MPASM)

The MPASM Universal Macro Assembler is a PC-

hosted symbolic assembler. It supports all microcon-

troller series including the PIC12C5XX, PIC14000,

PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, condi-

tional assemb l y, and se v eral source and listing f ormats.

It generates various object code formats to support

Microchip's development tools as well as third party

programmers.

MPASM allows full symbolic debugging from MPLAB-

ICE, Microchip’s Universal Emulator System.

MPASM has the following features to ass is t i n d evelop-

ing software for specific use applications.

• Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the files (Object, Listing, Symbol, and

special) required for symbolic debug with

Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source

and listing formats.

MPASM provides a rich directive language to support

programming of the PICmicro. Directives are helpful in

making the de velo pment of y our asse mble s ource code

shorter and more maintainable.

11.12 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code

development in a PC host environment. It allows the

user to simulate the PICmicro series microcontrollers

on an instruction level. On any given instruction, the

user may examine or modify any of the data areas or

provide external stimulus to any of the pins. The input/

output radix can be set by the user and the execution

can be perf ormed in; single step , ex ecute until break, or

in a trace mode.

MPLAB-SIM fully supports symbolic debugging using

MPLAB-C17 and MPASM. The Software Simulator

off ers the lo w cost fle xib ility to de v elop and deb ug cod e

outside of the laboratory environment making it an

excellent multi-project software development tool.

11.13 MPLAB- C17 Comp iler

The MPLAB-C17 Code Development System is a

complete ANSI ‘C’ compiler and integrated develop-

ment en vironment for M icrochip’ s PIC1 7CXXX famil y of

microcontrollers. The compiler provides powerful inte-

gration capabilities and ease of use not found with

other co mpi le rs .

For easier source level debugging, the compiler pro-

vides symbol information that is compatible with the

MPLAB IDE memory display.

11.14 Fuzzy Logic Development System

(

fuzzy

TECH-MP)

fuzzy

TECH-MP fuzzy logic development tool is avail-

able in two versions - a low cost introductory version,

MP Explorer, for designers to gain a comprehensive

working kno w ledge of fuz zy l ogic sys tem d esign ; and a

full-featured version,

fuzzy

TECH-MP, Edition for imple-

menting more complex systems.

Both versions include Microchip’s

fuzzy

LAB demon-

str ati on b oar d for hands-on experience with fuz zy lo gi c

system s im ple me nta tion .

11.15 SEEVAL Evaluation and

Pr ogramming System

The SEEVAL SEEPROM Designer’s Kit supports all

Microchip 2-wire and 3-wire Serial EEPROMs. The kit

includes everything necessary to read, write, erase or

program special features of any Microchip SEEPRO M

product including Smart Serials and secure serials.

The Total Endurance Disk is included to aid in trade-

off ana lysi s and rel iabil ity ca lcula tions . The tota l kit ca n

significantly reduce time-to-market and result in an

optimized system.

PIC16C712/716

DS41106A-page 72 Preliminary  1999 Microchip Technology Inc.

11.16 KEELOQ Evaluation and

Programming Tools

KEELOQ evaluation and programming tools support

Microc hips HCS Secure D ata Product s. The HC S ev al-

uation kit includes an LCD display to show changing

codes, a decoder to decode transmissions, and a pro-

gramming interface to program test transmitters.

 1999 Microchip Technology Inc. Preliminary DS41106A-page 73

PIC16C712/716

TABLE 11-1 DEVE LOPMENT TOOLS FROM MICROCHIP

PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX 24CXX

25CXX

93CXX

HCS200

HCS300

HCS301

Emulat or Product s

MPLAB™-ICE

ICEPIC Low-Cost

In-Cir c uit Emulator

Software Tools

MPLAB

Integrated

Development

Environment

MPLAB C17*

Compiler

fuzzy

TECH-MP

Explorer/Edition

Fuzzy Logic

Dev. Tool

Total En duranc e

Software Model

Programmers

PICSTARTPlus

Low-Cost

Universal Dev. Kit

PRO MATE II

Universal

Programmer

KEELOQ

Programmer

Demo Boards

SEEVAL

Designers Kit

SIMICE

PICDEM-14A

PICDEM-1

PICDEM-2

PICDEM-3

KEELOQ®

Evaluation Kit

KEELOQ

Transponde r Kit

PIC16C712/716

DS41106A-page 74 Preliminary  1999 Microchip Technology Inc.

NOTES:

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 75

12.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†)

Ambient temperature under bias.............................................................................................................-55°C to +125°C

Storage temperature.............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V

Voltage on MCLR with respect to VSS (Note 2)..........................................................................................0V to +13.25V

Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V

Total power dissipation (Note 1)(PDIP and SOIC)....................................................................................................1.0W

Total power dissipation (Note 1)(SSOP) .................................................................................................................0.65W

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20 mA

Output clamp current, IOK (VO < 0 or VO > V DD)..............................................................................................................±20 mA

Maximu m out put current sunk by any I/O pin................. ............................ ............................ ............ .....................25 mA

Maximu m out put current so urced b y an y I/O pin ........... ..... ...... ...... ............................ .......................... ..................25 mA

Maximum current sunk by PORTA and PORTB (combined).................................................................................200 mA

Maximum current sourced by PORTA and PORTB (combined)............................................................................200 mA

Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

Note 2: Volta ge s pi kes below VSS at the MCLR/VPP pin , in duc in g c urren ts greater than 80 m A, may cause latch-up.

Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather

than pulling this pin directly to VSS.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

de vic e. Th is is a s tress r ating o nly and functional oper atio n of the device at those or an y o ther cond itions abo v e t hose

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC16C712/716

DS41106A-page 76 Preliminary  1999 Microchip Technology Inc.

FIGURE 12-1: PIC16C712/716 VOLTAGE-FREQUENCY GRAPH, -40°C < TA < +125°C

FIGURE 12-2: PIC16LC712/716 VOLTAGE-FREQUENCY GRAPH, 0°C < TA < +70°C

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

Frequency (MHz)

VDD

(Volts)

2.0

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

4 10

Frequency (MHz)

VDD

(Volts)

2.0

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 77

12.1 DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended)

PIC16C712/716-20 (Commercial, Industrial, Extended)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤+70°C for commercial

-40°C ≤ TA ≤+85°C for industrial

-40°C ≤ TA ≤+125°C for e xt ended

P aram

No. Sym Characteristic Min Typ† Max Units Conditions

D001

D001A VDD Supply Voltage 4.0

VBOR*-

-5.5

5.5 V

V BOR enabled (Note 7)

D002* VDR RAM Data Retention Voltage(1) -1.5-V

D003 VPOR VDD Start Voltage to ensure inter-

nal Power-on Reset signal -VSS - V See section on Power-on Reset for details

D004*

D004A* SVDD VDD Rise Rate to ensure internal

Power-on Reset signal 0.05

TBD -

-V/ms PWRT enabled (PWRTE bit clea r)

PWRT disabled (PWRTE bit set)

See section on Pow er-on Reset f or details

D005 VBOR Brown-out Reset

voltage trip point 3.65 - 4.35 V BODEN bit set

D010

D013 IDD Supply Current(2,5) -

-0.8

4.0 2.5

8.0 mA

mA FOSC = 4 MHz, VDD = 4.0V

FOSC = 20 MHz, VDD = 4.0V

D020

D021

D021B

IPD Power-down Current(3,5) -

10.5

1.5

2.5

µA

VDD = 4.0V, WDT enabled,-40°C to +85°C

VDD = 4.0V, WDT disabled, 0°C to +70°C

VDD = 4.0V, WDT disabled,-40°C to +85°C

VDD = 4.0V, WDT disabled,-40°C to +12 5°C

D022*

D022A* ∆IWDT

∆IBOR

Module Differentia l Current(6)

Wat chdog Timer

Brown-out Reset -

-6.0

TBD 20

200 µA

µAWDTE bit set, VDD = 4.0V

BODEN bit set, VDD = 5.0V

1A FOSC LP Oscillator Operating F r equency

RC Oscillator Operating Frequency

XT Oscillator Operating Frequency

HS Oscillator Operating Frequenc y

—

200

KHz

MHz

All temperatures

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operati ng voltage and frequency. Other factors such as I/O pin loading and

switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-

sumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the

part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc mode, current through Re xt is not included. The current through the resistor can be estimated by the f ormula Ir =

VDD/2Rext (mA) with Rext in kOhm.

5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for

design guidance only. This is not tested.

6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base

IDD or IPD measurement.

7: This is the voltage where the device enters the Bro wn-out Reset. When BOR is enabled, the device will operate correctly to

this trip point.

PIC16C712/716

DS41106A-page 78 Preliminary  1999 Microchip Technology Inc.

12.2 DC Characteristics: PIC16LC712/716-04 (Commercial, Industrial)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤+70°C for commercial

-40°C ≤ TA ≤+85°C for industrial

Param

No. Sym Characteristic Min Typ† Max Units Conditions

D001 VDD Supply Voltage 2.5

VBOR*-

-5.5

5.5 V

V BOR enabled (Note 7)

D002* VDR RAM Data Retention Voltage(1) -1.5-V

D003 VPOR VDD Start Voltage to ensure inter-

nal Power-on Reset signal -VSS - V See section on Power-on Reset for details

D004*

D004A* SVDD VDD Rise Rate to ensure internal

Power-on Reset signal 0.05

TBD -

-V/ms PWRT enabled (PWRTE bit clear)

PWRT disabled (PWRTE bit set)

See section on Power-on Reset for details

D005 VBOR Brown-out Reset

v oltage trip point 3.65 - 4.35 V BODEN bit set

D010

D010A

IDD Supply Curr e nt(2,5) -

2.0

22.5

3.8

µA

XT, RC osc modes

FOSC = 4 MHz, VDD = 3.0V (Note 4)

LP osc mode

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

D020

D021

D021A

IPD Power-do wn Curre nt(3,5) -

7.5

0.9

µA

VDD = 3.0V, WDT enabled, -40°C to +85°C

VDD = 3.0V, WDT disabled, 0°C to +70°C

VDD = 3.0V, WDT disabled, -40°C to +85°C

D022*

D022A* ∆IWDT

∆IBOR

Module Di ffere ntial Current(6)

Watchdog Timer

Brown-out Reset -

-6.0

TBD 20

200 µA

µAWDTE bit set, VDD = 4.0V

BODEN bit set, VDD = 5.0V

1A FOSC LP Oscillator Operating Frequency

RC Oscillator Operating Frequency

XT Oscillator Operating Frequency

HS Oscillator Operating Frequency

—

200

KHz

MHz

All temperatures

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note1: Th is is the limit to which VDD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operati ng voltage and frequency. Other factors such as I/O pin loading and

switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-

sumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the

part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc mode, current through Rex t is not included. The current through the resistor can be estimated by the formula Ir

= VDD/2Rext (mA) with Rext in kOhm.

5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is

for design guidance only. This is not tested.

6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base

IDD or IPD measurement.

7: This is the v oltage where the de vice enters the Brown-out Reset. When BOR is enabled, the de vice will operate correctly to

this trip point.

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 79

12.3 DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended)

PIC16C712716-20 (Commercial, Industrial, Extended)

PIC16LC712/716-04 (Commercial, Industrial)

DC CHARACTERIS TICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤+70°C for commercial

-40°C ≤ TA ≤+85°C for industri al

-40°C ≤ TA ≤+125°C for extended

Operating voltage VDD range as described in DC spec Section 12.1

and Sect ion 12.2

Param

No. Sym Characteristic Min Typ† Max Units Conditions

Input Low Voltage

VIL I/O ports

D030

D030A with TTL buffer VSS

VSS -

-0.8V

0.15VDD V

V4.5V ≤ VDD ≤ 5.5 V

otherwise

D031 with Schmitt Trigger buffer VSS -0.2VDD V

D032 MCLR, OSC1 (in RC mode) Vss - 0.2VDD V

D033 OSC1 (in XT, HS and LP

modes) Vss - 0.3VDD VNote1

Input High Voltage

VIH I/O ports -

D040 with TTL buffer 2.0 - VDD V4.5V ≤ VDD ≤ 5.5V

D040A 0.25VDD

+ 0.8V -VDD Votherwise

D041 with Schmitt Trigger buffer 0.8VDD -VDD V For entire VDD range

D042 MCLR 0.8VDD -VDD V

D042A OSC1 (XT, HS and LP modes) 0.7VDD -VDD VNote1

D043 OSC1 (in RC mode) 0.9VDD -VDD V

Input Leakage Current (Notes

2, 3)

D060 IIL I/O ports - - ±1µAVss ≤ VPIN ≤ VDD,

Pin at hi-impedance

D061 MCLR, RA4/T0CKI - - ±5µAVss ≤ VPIN ≤ VDD

D063 OSC1 - - ±5µAVss ≤ VPIN ≤ VDD,

XT, HS and LP osc modes

D070 IPURB PORTB weak pull-up current 50 250 400 µAVDD = 5V, VPIN = VSS

Output Low Voltage

D080 VOL I/O ports - - 0.6 V IOL = 8.5 mA, VDD = 4.5V,

-40°C to +85°C

--0.6VIOL = 7.0 mA, VDD = 4.5V,

-40°C to +125°C

D083 OSC2/CLKOUT

(RC osc mode) --0.6VIOL = 1.6 mA, VDD = 4.5V,

-40°C to +85°C

--0.6VI

OL = 1.2 mA, VDD = 4.5V,

-40°C to +125°C

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Not e 1 : In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmi-

cro be driven with external clock in RC mode.

2: The leakage current on the MCL R /VPP pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input volt-

ages.

3: Negative current is defined as current sourced by the pin.

PIC16C712/716

DS41106A-page 80 Preliminary  1999 Microchip Technology Inc.

Output High Voltage

D090 VOH I/O ports (Note 3) VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V,

-40°C to +85°C

VDD-0.7 - - V IOH = -2.5 mA, VDD = 4.5V,

-40°C to +125°C

D092 OSC2/CLKOUT (RC osc

mode) VDD-0.7 - - V IOH = -1.3 mA, VDD = 4.5V,

-40°C to +85°C

VDD-0.7 - - V IOH = -1.0 mA, VDD = 4.5V,

-40°C to +125°C

D150* VOD Open-Drain High Voltage - - 8.5 V RA4 pin

Capacitive Loading Specs

on Output Pins

D100 COSC2 OSC2 pin - - 15 pF In XT, HS and LP modes when

external clock is used to drive

OSC1.

D101 CIO All I/O pins and OSC2 (in RC

mode) --50pF

DC CHARACTERI STICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤+70°C for commercial

-40°C ≤ TA ≤+85°C for industri al

-40°C ≤ TA ≤+125°C for extended

Operating voltage VDD range as described in DC spec Section 12.1

and Sect ion 12.2

Param

No. Sym Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Not e 1 : In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmi-

cro be driven with external clock in RC mode.

2: The leakage current on the MCL R /VPP pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input volt-

ages.

3: Negative current is defined as current sourced by the pin.

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 81

12.4 AC (Timing) Characteristics

12.4.1 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created

using one of the following formats:

1. TppS2ppS

2. TppS

TFFrequency TTime

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKOUT rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O port t1 T1CKI

mc MCLR wr WR

Uppercase let ters and their meanings:

SFFall PPeriod

HHigh RRise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-impedance

PIC16C712/716

DS41106A-page 82 Preliminary  1999 Microchip Technology Inc.

12.4.2 TIMING CONDITIONS

The temperature and voltages specified in Table 12-1

apply to all timing specifications, unless otherwise

noted. Figure 12-1 specifies the load conditions for the

timing specific ations .

TABLE 12-1 TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC

FIGURE 12-1: LOAD CONDITIONS FOR DEVI CE TIMING SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤+70°C for commercial

-40°C ≤ TA ≤+85°C for industrial

-40°C ≤ TA ≤+125°C for extended

Operating voltage VDD range as described in DC spec Section 12.1 and Section 12.2.

LC part s operate for commercial/industrial temp’s only.

VDD/2

VSS

RL=464Ω

CL= 50 pF for all pins except OSC2/CLKOUT

15 pF for OSC2 output

Load condition 1 Load condition 2

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 83

12.4.3 TIMING DIAG RAMS AND SP ECIFICATIONS

FIGURE 12-2: EXTERNAL CLOCK TIMING

TABLE 12-2 EXTERNAL CLOCK TIMING REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

1A FOSC External CLKIN Frequency

(Note 1) DC — 4 MHz RC and XT osc modes

DC — 4 MHz HS osc mode (-04)

DC — 20 MHz HS osc mode (-20)

DC — 200 kHz LP osc mode

Oscillator Frequency

(Note 1) DC — 4 MHz RC osc mode

0.1 — 4 MHz XT osc mode

4 — 20 MHz HS osc mode

5 — 200 kHz LP osc mode

OSC External CLKIN Period

(Note 1) 250 — — ns RC and XT osc modes

250 — — ns HS osc mode (-04)

50 — — ns HS osc mode (-20)

5— —µs LP osc mode

Oscillator Period

(Note 1) 250 — — ns RC osc mode

250 — 10,000 ns XT osc mode

250 — 250 ns HS osc mode (-04)

50 — 250 ns HS osc mode (-20)

5— —µs LP osc mode

CY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC

3* TosL,

TosH External Clock in (OSC1) High or

Low Time 100 — — ns XT oscillator

2.5 — — µs LP oscillator

15 — — ns HS oscillator

4* TosR,

TosF External Clock in (OSC1) Rise or

Fall Time — — 25 ns XT oscillator

— — 50 ns LP osc illator

— — 15 ns HS osc illator

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5 V, 25°C u nle ss oth erwise sta ted . These par ameters are for design guidance o nly

and are not tested.

Note1: Instructi on cycl e pe riod (TCY) equals four times the in put oscil lat or tim e-b as e pe riod. All specified v a lu es are

based on char ac terization data for that partic ular oscil lat or type unde r st andard o pera ting co ndi tions wi th the

devic e execu tin g c ode. Exceeding t hes e s pe cif ied li mi ts m ay result i n an uns ta b l e o sc ill ato r ope r ati on and/or

higher th an e xp ected current c onsumpt ion. All de vic es are tested to oper ate at " min." values with an external

clock applied to the OSC1/CLKIN pin.

When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.

344

Q4 Q1 Q2 Q3 Q4 Q1

OSC1

CLKOUT

PIC16C712/716

DS41106A-page 84 Preliminary  1999 Microchip Technology Inc.

FIGURE 12-3: CLKOUT AND I/O TIMING

TABLE 12-3 CLKOUT AND I/O TIMING REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

10* TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns Note 1

11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns Note 1

12* TckR CLKOUT rise time — 35 100 ns Note 1

13* TckF CLKOUT fall time — 35 100 ns Note 1

14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1

15* TioV2c kH Port in valid before CLKOUT ↑ Tosc + 200 — — ns Note 1

16* TckH2ioI Port in hold after CLKO UT ↑ 0 — — ns Note 1

17* TosH2ioV OSC1↑ (Q1 cycle) to P ort out valid — 50 150 ns

18* TosH2ioI OSC1↑ (Q2 cycle) to Port input

invalid (I/O in hold time) Standard 100 — — ns

18A* Extended (LC) 200 — — ns

19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns

20* TioR Port output rise time Standard — 10 40 ns

20A* Extended (LC) — — 80 ns

21* TioF Port output fall time Standard — 10 40 ns

21A* Extended (LC) — — 80 ns

22††* TINP INT pin high or low time TCY ——ns

23††* TRBP RB7:RB4 change INT high or low time TCY ——ns

* T h ese parame ters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unles s otherwi se stat ed. Thes e par ame ters are f o r design guidan ce only

and are not tested.

†† These parameters are asynchronous events not related to any internal clock edge.

Note1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

Note: Refer to Figure 12-1 for load conditions.

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

13 14

20, 21

19 18

old value new value

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 85

FIGURE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

FIGURE 12-5: BROWN-OUT RESET TIMING

TABLE 12-4 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET REQUIREMENTS

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2 ——

µsVDD = 5V, -40°C to +125°C

31* TWDT Watchdog Timer Time-out P eriod

(No Prescaler) 71833ms

VDD = 5V, -40°C to +125°C

32 TOST Oscillation Start-up Timer Per iod — 102 4 TOSC ——

TOSC = OSC1 period

33* TPWRT Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C

34 TIOZ I/O Hi-impedance from MCLR

Low or WDT reset ——2.1

µs

35 TBOR Brown-out Reset Pulse Width 100 — — µsVDD ≤ BVDD (D005)

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

RESET

Watchdog

Timer

RESET

I/O Pins

Note: Refer to Figure 12-1 for load conditions.

VDD BVDD

PIC16C712/716

DS41106A-page 86 Preliminary  1999 Microchip Technology Inc.

FIGURE 12-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

TABLE 12-5 TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet

parameter 42

With Prescaler 1 0 — — ns

41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet

parameter 42

With Prescaler 1 0 — — ns

42* Tt0P T0C K I Peri od No Prescaler TCY + 40 — — ns

With Prescaler Greater of:

20 or TCY + 40

— — ns N = prescale value

(2, 4,.. ., 25 6 )

45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet

parameter 47

Synchronous,

Prescaler =

2,4,8

Standard 15 — — ns

Extended (LC) 25 — — ns

Asynchronous Standard 30 — — ns

Extended (LC) 50 — — ns

46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet

parameter 47

Synchronous,

Prescaler =

2,4,8

Standard 15 — — ns

Extended (LC) 25 — — ns

Asynchronous Standard 30 — — ns

Extended (LC) 50 — — ns

47* Tt1P T 1CKI input period Synchronous Standard Greater of:

30 OR TCY + 40

— — ns N = prescale value

(1, 2, 4, 8)

Extended (LC) Greater of:

50 OR TCY + 40

N = presca le value

(1, 2, 4, 8)

Asynchronous Standard 60 — — ns

Extended (LC) 100 — — ns

Ft1 Timer1 oscillator input freque ncy range

(oscillator enabled by sett ing bit T1OSCEN) DC — 200 kHz

48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc — 7Tosc —

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note: Refer to Figure 12-1 for load conditions.

T0CKI

T1OSO/T1CKI

TMR0 or

TMR1

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 87

FIGURE 12-7: CAPTURE/COMPARE/PWM TIMINGS

TABLE 12-6 CAPTURE/COMPARE/PWM REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

50* TccL CCP1 input low

time No Prescaler 0.5TCY + 20 ——ns

With Prescaler Standard 10 — — ns

Extended (LC) 20 — — ns

51* TccH CCP1 input high

time No Prescaler 0.5TCY + 20 — — ns

With Prescaler Standard 10 — — ns

Extended (LC) 20 — — ns

52* TccP CCP1 input period 3TCY + 40

N— — ns N = prescale value

(1,4, or 16)

53* TccR CCP1 output rise time Standard — 10 25 ns

Extended (LC) — 25 45 ns

54* TccF CCP1 output fall time Standard — 10 25 ns

Extended (LC) — 25 45 ns

* Thes e parameters are character ized but not tested.

† D ata in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note: Refer to Figure 12-1 for load conditions.

CCP1

(Capture Mode)

50 51

CCP1

53 54

(Compare or PWM Mode)

PIC16C712/716

DS41106A-page 88 Preliminary  1999 Microchip Technology Inc.

TABLE 12-7 A/D CONVERTER CHARACTERISTICS:

PIC16C712/716-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)

PIC16C712/716-20 (COMMERCIAL, INDUSTRIAL, EXTENDED)

PIC16LC712/716-04 (COMMERCIAL, INDUSTRIAL)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

A01 NRResolution — — 8-bits bit VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A02 EABS Total Absolute error ——< ± 1 LSb VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A03 EIL Integral linearity error — — < ± 1 LSb VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A04 EDL Differential linearity error — — < ± 1 LSb VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A05 EFS Full scale error — — < ± 1 LSb VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A06 EOFF Offset er ror — — < ± 1 LSb VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A10 — Monotonicity — guaranteed

(Note 3) ——VSS ≤ VAIN ≤ VREF

A20 VREF Reference voltage 2.5V — VDD + 0.3 V

A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V

A30 ZAIN Recommended impedance of

analog voltage source — — 10.0 kΩ

A40 IAD A/D conv ersion current

(VDD)Standard — 180 — µA Average current consump-

tion when A/D is on.

(Note 1)

Extended (LC) — 90 — µA

A50 IREF VREF input current (Note 2) 10

—

1000

µA

During VAIN acquisition.

Based on differential of

VHOLD to VAIN to charge

CHOLD, see Section 9 .1 .

During A/D Conversion

cycle

2: * These parameters are characterized but not tested.

3: † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are

for design guidance only and are not tested.

Note 1: When A/D is off, it will not consume any current other than minor leakage current.

The power-down current spec includes any such leakage from the A/D module.

2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.

3: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 89

FIGURE 12-8: A/D CONVERSION TIMING

TABLE 12-8 A/D CONVERSION REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D clock period Standard 1.6 ——

µsTOSC based, VREF ≥ 3.0V

Extended (LC) 2.0 — — µsT

OSC based, VREF full range

Standard 2.0 4.0 6.0 µs A/D RC Mode

Extended (LC) 3.0 6.0 9.0 µs A/D RC Mode

131 TCNV Conv ersion time (not including S/H time)

(Note 1) 11 — 11 TAD

132 TACQ Acquisition time Note 2

—

µs

µs The minimum time is the amplifier

settling time. This may be used if

the "new" input voltage has not

changed by more than 1 LSb (i.e.,

20.0 mV @ 5.12V) from the last

sampled voltage (as stated on

CHOLD).

134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected

as RC, a time of TCY is added

before the A/D clock start s. This

allows the SLEEP instruction to be

executed.

135 TSWC Switching from convert → sample time 1.5 § — — TAD

:* These parameters are characterized but not tested.

:† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

:§ This specification ensured by design.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 9.1 for min conditions.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(TOSC/2) (1)

7 6543210

Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This

allows the SLEEP instruction to be executed.

1 Tcy

134

PIC16C712/716

DS41106A-page 90 Preliminary  1999 Microchip Technology Inc.

NOTES:

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 91

13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

The graphs and tables provided in this section are for design guidance and are not tested.

In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD

range). This is for information only and devices are guaranteed to operate properly only within the specified range.

The data presented in this section is a statistical summar y of data collected on units from different lots over a period

of time and matrix samples. ’Typical’ represents the mean of the distribution at 25°C. ’Max’ or ’min’ represents

(mean + 3σ) or (mean - 3σ) respectively, where σ is standard deviation, over the whole temperature range.

Graphs and Tables not available at this time.

PIC16C712/716

DS41106A-page 92 Preliminary  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. Preliminary DS41106A-page 93

PIC16C712/716

14.0 PAC K A GING INFORMATION

14.1 Package Marking Information

18-Lead SOIC

AABBCDE

Example

PIC16C712

XXXXXXXXXXXXXXXXX

AABBCDE

18-Lead PDIP Example

PIC16C716-04/P

Example18-Lead CERDIP Windowed

XXXXXXXX

AABBCDE

16C716

AABBCDE

XXXXXXXXXX

20-Lead SSOP

-20I/SS025

PIC16C712

Example

Legend: MM...M Microchip part number information

XX...X Customer specific information*

AA Year code (last 2 digits of calendar year)

BB Week code (week of January 1 is week ‘01’)

C Facility code of the plant at which wafer is manufactured

O = Outside Vendor

C = 5” Line

S = 6” Line

H = 8” Line

D Mask revision number

E Assembly code of the plant or country of origin in which

part was assembled

Note: In the e v ent the full Micr ochi p part number cannot be mark ed on one line ,

it will be carried over to the next line thus limiting the number of available

characters for customer specific information.

9917HAT

9917CAT

9910/SAA

9917SBP

*Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask

rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with

your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.

XXXXXXXX

XXXXXXXXXXXX

XXXXXXXXXXXXXXXXX

/JW

-20/SO

PIC16C712/716

DS41106A-page 94 Preliminary  1999 Microchip Technology Inc.

Package Type: K04-007 18-Lead Plastic Dual In-line (P) – 300 mil

* Controlling Parameter.

†Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”

‡Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

JEDEC equivalent: MS-001 AC

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX

PCB Row Spacing 0.300 7.62

Number of Pins n 18 1 8

Pitch p 0.100 2.54

Lower Lead Width B 0.013 0.018 0.023 0.33 0.46 0.58

Upper Lead Width B1†0.055 0.060 0.065 1.40 1.52 1.65

Shoulder Radius R 0.000 0.005 0.010 0.00 0.13 0.25

Lead Thickness c 0.005 0.010 0.015 0.13 0.25 0.38

Top to Seating Plane A 0.110 0. 155 0.155 2.79 3. 94 3.94

Top of Lead to Seating Plane A1 0. 075 0.095 0. 115 1.91 2.41 2.92

Base to Seating Plane A2 0.000 0.020 0.020 0.00 0.51 0.51

Tip to Seating Plane L 0.125 0.130 0.135 3.18 3. 30 3.43

Package Length D‡0.890 0.895 0.900 22.61 22.73 22.86

Molded Package Width E‡0.245 0.255 0.265 6.22 6.48 6.73

Radius to Radius Width E1 0.230 0.250 0.270 5.84 6.35 6.86

Over all Row Spacing eB 0.310 0.349 0.387 7.87 8.85 9.83

Mold Draft Angle Top α5 10 15 5 10 15

Mold Draft Angle Bottom β5 10 15 5 10 15

 1999 Microchip Technology Inc. Preliminary DS41106A-page 95

PIC16C712/716

Package Type: K04-010 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil

* Controlling Parameter.

JEDEC equivalent: MO-036 AE

MIN

Window Length

Window Width

Overall Row Spacing

Radius to Radius Width

Package Width

Package Length

Tip to Seating Plane

Base to Seating Plane

Top of Lead to Seating Plane

Top to Seating Plane

Lead Thickness

Shoulder Radius

Upper Lead Width

Lower Lead Width

Number of Pins

PCB Row Spacing

Dimension Limits

Pitch

Units

0.15

7.24

7.87

0.76

3.33

4.83

0.30

0.38

1.52

0.53

2.59

0.200

0.140

0.385

0.270

0.298

0.900

0.138

0.023

0.111

0.183

0.190

0.130

0.345

0.125

0.255

0.285

0.880

0.015

0.091

0.175

0.210

0.150

0.425

0.150

0.285

0.310

0.920

0.030

0.131

0.190

0.010

0.013

0.055

0.019

0.100

0.300

NOM

0.016

0.008

0.010

0.050

0.098

INCHES* MAX

0.021

0.012

0.015

0.060

0.102

22.86

0.19

0.13

8.76

6.48

7.24

22.35

3.18

0.00

2.31

4.45

0.2

0.14

9.78 10.80

0.21

3.49

6.86

7.56

0.57

2.82

4.64

3.81

23.37

NOM

MILLIMETERS

MIN

0.20

0.25

1.27

0.41

2.49

MAX

0.47

0.25

0.32

1.40

2.54

7.62

PIC16C712/716

DS41106A-page 96 Preliminary  1999 Microchip Technology Inc.

Package Type: K04-051 18-Lead Plastic Small Outline (SO) – Wide, 300 mil

0.014

0.009

0.010

0.011

0.005

0.010

0.394

0.292

0.450

0.004

0.048

0.093

MIN

nNumber of Pins

Mold Draft Angle Bottom

Mold Draft Angle To p

Lower Lead Width

Chamfer Distance

Outside Dimension

Molded Package Width

Molded Package Length

Overall Pack. Height

Lead Thickness

Radius Centerline

Foot Angle

Foot Length

Gull Wing Radius

Shoulder Radius

Standoff

Shoulder Height

B†

E‡

D‡

Dimension Limits

Pitch

Units

p1818

012

12 15

0.020

0.017

0.011

0.015

0.016

0.005

0.407

0.296

0.456

0.008

0.058

0.099

0.029

0.019

0.012

0.020

0.021

0.010

0.419

0.299

0.462

0.011

0.068

0.104

012

12 15

0.42

0.27

0.38

0.41

0.13

0.50

10.33

7.51

11.58

0.19

1.47

2.50

0.25

0.36

0.23

0.25

0.28

0.13

10.01

7.42

11.43

0.10

1.22

2.36

0.74

0.48

0.30

0.51

0.53

0.25

10.64

7.59

11.73

0.28

1.73

2.64

INCHES*

0.050

NOM MAX 1.27

MILLIMETERS

MIN NOM MAX

45°

* Controlling Parameter.

†Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”

‡Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

JEDEC equiv alent: MS-013 AB

 1999 Microchip Technology Inc. Preliminary DS41106A-page 97

PIC16C712/716

Package Type: K04-072 20-Lead Plastic Shrink Small Outine (SS) – 5.30 mm

MIN

pPitch

Mold Draft Angle Bottom

Mold Draft Angle Top

Lower Lead Width

Radius Centerline

Gull Wing Radius

Shoulder Radius

Outsid e Dimension

Molded Package Width

Molded Package Length

Shoulder Height

Ov erall Pack. Height

Lead Thickness

Foot Angle

Foot Length

Standoff

Number of Pins

B†

E‡

D‡

Dimension Limits

Units

0.650.026

510

0.012

0.007

0.005

0.020

0.005

0.306

0.208

0.283

0.005

0.036

0.073

0.301

0.010

0.005

0.000

0.015

0.005

0.205

0.278

0.002

0.026

0.068

0.311

0.015

0.009

0.010

0.025

0.010

0.212

0.289

0.008

0.046

0.078

510

7.65

0.25

0.13

0.00

0.38

0.13

5.20

7.07

0.05

0.66

1.73

7.907.78

0.32

0.18

0.13

0.51

0.13

0.38

0.22

0.25

0.64

0.25

5.29

7.20

0.13

1.86

0.91

5.38

7.33

0.21

1.99

1.17

NOM

INCHES MAX NOM

MILLIMETERS*

MIN MAX

* Controlling Parameter.

†Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”

‡Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

JEDEC equivalent: MO-150 AE

 1999 Microchip Technology Inc. Preliminary DS41106A-page 98

PIC16C712/716

NOTES:

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 99

APPENDIX A: REVISION HISTORY

APPENDIX B: CONV ERSION

CONSIDERATIONS

There are no previous versions of this device.

APPENDIX C: MIGRATION FROM

BASE-LINE TO

MID-RANGE DEVICES

This section discusses how to migrate from a baseline

device (i.e., PIC16C5X) to a mid-range device (i.e.,

PIC16CXXX).

The following are the list of modifications over the

PIC16C5X microcontroller family:

1. Instruction word length is increased to 14-bits.

This allows larger page sizes both in program

memory (2K no w as opposed t o 512 bef ore) and

before).

2. A PC high latch register (PCLATH) is added to

handle program memory paging. Bits PA2, PA1,

PA0 are removed from STATUS register.

3. Data memory paging is redefined slightly.

STATUS register is modified.

4. Four new instructions have been added:

RETURN, RETFIE, ADDLW, and SUBLW.

Two instructions TRIS and OPTION are being

phased out although they are kept for compati-

bility with PIC16C5 X.

5. OPTION_REG and TRIS registers are made

addressable.

6. Interrupt capability is added. Interrupt vector is

at 0004h.

7. Stack size is increased to 8 deep.

8. Reset vector is changed to 0000h.

9. Reset of all registers is revisited. Five different

reset (a nd wak e-u p) types are re cog ni z e d. Re g-

isters are reset differently.

10. Wake up from SLEEP through interrupt is

added.

11. Two separate timers, Oscillator Start-up Timer

(OST) and Power-up Timer (PWRT) are

included for more reliable power-up. These tim-

ers a re inv oke d selectiv ely to a v oid unneces sary

delays on power-up and wake-up.

12. PORTB has weak pull-ups and interrupt on

change feature.

13. T0CKI pin is also a port pin (RA4) now.

14. FSR is made a full eight bit register.

15. “In- circuit serial prog rammi ng” is m ade poss ible .

The user ca n progr am PIC16CXX de vi ces usin g

only five pins: VDD, VSS, MCLR/VPP, RB6 (c lock )

and RB7 (data in/out).

16. PCON status register is added with a Power-on

Reset status bit (POR).

17. Code protection scheme is enhanced such that

portions of the program memory can be pro-

tected, while the remainder is unprotected.

18. Brown-out protection circuitry has been added.

Controlled by configuration word bit BODEN.

Brown-out reset ensures the device is placed in

a reset condition if VDD dips below a fixed set-

point.

To convert code wr itten for PIC16C5X to PIC16CXXX,

the user should take the following steps:

1. Remove any program memory page select

operat ion s (PA2, PA1, PA0 bits) for CALL, GOTO.

2. Revisit any computed jump operations (write to

PC or add to PC, etc.) to make sure page bits

are set properly under the new scheme.

3. Eliminate any data memory page switching.

Redefine data variables to reallocate them.

4. Verify all writes to STATUS, OPTION, and FSR

registers since these have changed.

5. Change reset vector to 0000h.

Version Date Revision Description

A 2/99 This is a new data sheet. Howev er ,

the device s describ ed in this da ta

sheet are the upgrades to the

devices found in the

PIC16C6X

Data Sheet

, DS30234, and the

PIC16C7X Data Shee t

, DS30390.

PIC16C712/716

DS41106A-page 100 Preliminary  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. Preliminary DS41106A-page 101
PIC16C712/716
INDEX 
A
A/D ..................................................................................... 45
A/D Converter Enable (ADIE Bit) ...............................16
A/D Converter Flag (ADIF Bit)  .............................17, 47
A/D Converter Interrupt, Configuring  .........................47
ADCON0 Register ................................................11, 45
ADCON1 Register ..........................................1 2, 45, 46
ADRES Register ............................................11, 45, 47
Analog Port Pins, Configuring ....................................49
Block Diag ram ........ .............. ................... ...................47
Block Diagram, Analog Input Model ...........................48
Channel Select (CHS2:CHS0 Bits) ............................45
Clock Select (ADCS1:ADCS0 Bits) ............................45
Configuring the Module ..............................................47
Conversion Clock (TAD) .............................................49
Conversion Status (GO/DONE Bit) ......................45, 47
Conversions ...............................................................50
Converter Characteristics ..........................................88
Module On/Off (ADON Bit) .........................................45
Port Configuration Control (PCFG2:PCFG0 Bits) ......46
Sampling Requirements .......................... .. .. ....... .. .... ..48
Special Event Trigger (CCP) ................................41, 50
Timing Dia g r a m .............. ................... ............... ..........89
Absolute Maximum Ratings ...............................................75
ADCON0 Register ........................................................11, 45
ADCS1:ADCS0  Bits .............................. .....................45
ADON Bit ...................................................................45
CHS2:CHS0 Bits ........................................................45
GO/DONE Bit  .......................................................45, 47
ADCON1 Register ..................................................1 2, 45, 46
PCFG2: PCFG0  Bits ... ................... ........................... ..46
ADRES Register ....................................................11, 45, 47
Architecture
PIC16C62B/PIC16C72A Block Diagram ......................5
Assembler
MPASM Assembler ....................................................71
B
Banking, Data Memory  ................................................10, 13
Brown-Out Detect (BOD)  ...................................................55
Brown-out Reset (BOR) ...................................51, 54, 58, 59
BOR Enable (BODEN Bit)  ..........................................52
BOR Status  (BO R  Bit) ........ ............................ ............18
Timing Dia g r a m .............. ................... ............... ..........85
C
Capture (CCP Module)  ......................... .. .... .... .. ......... .. .... ..40
Block Diag ram ........ .............. ................... ...................40
CCP Pin Configuration ...............................................40
CCPR1H:CCPR1L Registers .....................................40
Changing Between Capture Prescalers .....................40
Softwa re In terrupt  ............ ................... ............... ........40
Timer1 Mode Selection ..............................................40
Capture/Compare /P WM ( CCP)  ................... ............... ........39
CCP1CON Register .............................................11, 39
CCPR1H Register ................................................11, 39
CCPR1L Register  ................................................11, 39
Enable (CCP1IE Bit) ..................................................16
Flag (CCP1IF Bit) .......................................................17
Timer Resources ........................................................39
Timing Dia g r a m .............. ................... ............... ..........87
CCP1CON Regis ter ................. ................... ............... ........39
CCP1M3:CCP1M0 Bits .... ............... ............... ............39
CCP1X:CCP1Y Bits ..... ............... ................... ............39
Code Protection ........................................................... 51, 65
CP1:CP0 Bits ....... ............... ....................... ................ 52
Compare (CCP Module) ................... .... .... .. ......... .... .... .. .... 41
Block Diag ram ............... ................... ................... ...... 41
CCP Pin Configuration  .............................................. 41
CCPR1H:CCPR1L Registers  .................................... 41
Softwar e  In terrup t ..................... ....................... .......... 41
Special Event Trigger .................................... 34, 41, 50
Timer1 Mode Selection  . ............................................. 41
Configuration Bits .............................................................. 51
Conversion Considerations ................................................ 99
D
Data Memor y ................... ................... ................... ............ 10
Bank Select (RP1:RP0 Bits) ................................ 10, 13
General Purpose Registers  ....................................... 10
Register File Map  ............. .................. ............... ........ 10
Special Function Registers ........................................ 11
DC Characteristics ....................................................... 77, 79
Development Support ........................................................ 69
Development Tools  ............................................................ 69
Direct Add ressing .......... ................... ....................... .......... 20
E
Electrical Characteristics  ................................................... 75
Errata ................................................................................... 3
External Power-on Reset Circuit ........................................ 55
F
Family of Devices
PIC16C7XX ................................................................. 2
Firmware Instructions ........................................................ 67
Fuzzy Logic Dev. System (
fuzzy
TECH-MP) ................... 71
I
I/O Ports  ... ....................... ....................... ....................... .... 21
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 69
ID Locations ................................................................. 51, 65
In-Circuit Serial Programming (ICSP) .......................... 51, 65
Indirect Addressing ............................................................ 20
FSR Register ................................................. 10, 11, 20
INDF Register ............................................................ 11
Instruction Format .............................................................. 67
Instruction Set .................................................................... 67
Summary Ta b l e  ....... ............... ....................... ............ 68
INTCON Register ......................................................... 11, 15
GIE Bi t ...... ................................ ........................... ...... 15
INTE Bi t ......... ....................... ....................... .............. 15
INTF Bit   ................. ................... ....................... .......... 15
PEIE Bi t ......... ....................... ....................... .............. 15
RBIE Bit ..................................................................... 15
RBIF Bit ............................................................... 15, 24
T0IE Bi t ................ ........................... ....................... .... 1 5
T0IF Bit  ... ............... ....................... ................... .......... 15
Interrupt Sources ......................................................... 51, 61
A/D Conversion Complete ......................................... 47
Block Diag ram ............... ................... ................... ...... 61
Capture Comp le te (CCP)  ......... .......... ............... ........ 40
Compare Complete (CCP)  ..... ...... ...... ........... ............ 41
Interrupt on Change (RB7:RB4 )  ....................... .. .... .. 24
RB0/INT Pin, External  ............................................... 62
TMR0 Overflow .................................................... 30, 62
TMR1 Overflow .................................................... 31, 34
TMR2 to PR2 Match .................................................. 37
TMR2 to PR2 Match (PWM) ................................ 36, 42
Interrupts, Context Saving During ...................................... 62
Interrupts, Enable Bits

PIC16C712/716
DS41106A-page 102 Preliminary  1999 Microchip Technology Inc.
A/D Converter Enable (ADIE Bit) ...............................16
CCP1 Enable (CCP1IE Bit) ..................................16, 40
Global Interrupt Enable (GIE Bit) .........................15, 61
Interrupt on Change (RB7:RB4) 
Enable (RBIE Bit) ........ .........................................15, 62
Peripheral Interrupt Enable (PEIE Bit)  .......................15
RB0/INT Enable (INTE Bit)  ........................................15
TMR0 Overflow Enable (T0IE Bit) ..............................15
TMR1 Overflow Enable (TMR1IE Bit) ........................16
TMR2 to PR2 Match Enable (TMR2IE Bit)  ................16
Interrupts, Flag Bits
A/D Converter Flag (ADIF Bit)  .............................17, 47
CCP1 Flag (CCP1IF Bit) ................................17, 40, 41
Interrupt on Change (RB7:RB4) 
Flag (RBIF Bit) ...............................................15, 24, 62
RB0/INT Flag (INTF Bit)  .............................................15
TMR0 Overflow Flag (T0IF Bit) ............................15, 62
TMR1 Overflow Flag (TMR1IF Bit)  ............................17
TMR2 to PR2 Match Flag (TMR2IF Bit) .....................17
K
KeeLoq Evaluation and Programming Tools ...................72
M
Master Clear (MCLR)
MCLR Reset, Normal Operation ....................54, 58, 59
MCLR Reset, SLEEP .....................................5 4, 58, 59
Memory Organization
Data Memor y  ........ ............... ................... ...................10
Program Memory .........................................................9
MPLAB Integrated Development Environment Software  ...71
O
OPCODE Field Descriptions ..............................................67
OPTION_REG Register ...............................................12, 14
INTEDG Bi t ......... ................... ....................... .............14
PS2:PS0 Bits  .......................................................14, 29
PSA Bit  .................................................................14, 29
RBPU Bit .............................. ................... ...................14
T0CS Bit  ...............................................................14, 29
T0SE Bit ...............................................................14, 29
Oscillator Configuration ................................................51, 53
HS ........................................................................53, 58
LP .........................................................................53, 58
RC ..................................................................53, 54, 58
Selection (FOSC1:FOSC0 Bits) .................................52
XT  ........................................................................53, 58
Oscillato r, Timer1 .... .......... ........... .......... ........... .......... .31, 34
Oscillat o r, WDT ............. ............... .......... ............... .............63
P
Packaging ..........................................................................93
Paging, Program Memory ..............................................9, 19
PCON Register  ............................................................18, 57
BOR Bit ......................................................................18
POR Bit ......................................................................18
PICDEM-1 Low-Cost PICmicro Demo Board .....................70
PICDEM-2 Low-Cost PIC16CXX Demo Board  ..................70
PICDEM-3 Low-Cost PIC16CXX X Demo Boar d ................70
PICSTART Plus Entry Level Development System  ........69
PIE1 Register ...............................................................12, 16
ADIE Bit  .....................................................................16
CCP1IE Bit .................................................................16
TMR1IE Bit .................................................................16
TMR2IE Bit .................................................................16
Pin Functions
MCLR/Vpp ................................................................... 6
RA0/AN0 ...................................................................... 6
RA1/AN1 ...................................................................... 6
RA2/AN2 ...................................................................... 6
RA3/AN3/Vref .............................................................. 6
RA4/T0CKI .................................................................. 6
RB0/INT ....................................................................... 7
RB1 .............................................................................. 7
RB2 .............................................................................. 7
RB3 .............................................................................. 7
RB4 .............................................................................. 7
RB5 .............................................................................. 7
RB6 .............................................................................. 7
RB7 .............................................................................. 7
Vdd .............................................................................. 7
Vss ............................................................................... 7
Pinout Descriptions
PIC16C62B/PIC16C72A .............................................. 6
PIR1 Register  .............................................................. 11, 17
ADIF Bi t .......... ....................... ........................ ............ 17
CCP1IF Bit  ................................ .................. ............... 17
TMR1IF Bit ................................................................. 17
TMR2IF Bit ................................................................. 17
Pointer, FSR ...................................................................... 20
PORTA
Initialization ................................................................ 21
PORTA Register .................................................. 11, 21
RA3:RA0 and RA5 Port Pins ..................................... 21
RA4/T0CKI Pin  ...... ................... .............. ................... 22
TRISA Register .................................................... 12, 21
PORTB
Initialization ................................................................ 23
PORTB Register .................................................. 11, 23
Pull-up Enable (RBPU Bit)  ......................................... 14
RB0/INT Edge Select (INTEDG Bit)  .......................... 14
RB0/INT Pin, External ................................................ 62
RB3:RB0 Port Pins .................................................... 23
RB7:RB4 Interrupt on Change .............. .. .... ....... .. .... .. 62
RB7:RB4 Interrupt on Change Enable (RBIE Bit)  15, 62
RB7:RB4 Interrupt on Change 
Flag (RBIF Bit) ............................................... 15, 24, 62
RB7:RB4 Port Pins .................................................... 26
TRISB Register .................................................... 12, 23
PORTC
Block Diagram .....................................................24, 25
TRISC Register .......................................................... 12
Postscaler, Timer2
Select (TOUTPS3:TOUTPS0 Bits) ............................ 36
Postscaler, WDT ................................................................ 29
Assignment (PSA Bit) .......................................... 14, 29
Block Diagram ........................................................... 30
Rate Select (PS2:PS0 Bits) ................................. 14, 29
Switching Between Timer0 and WDT .................... .... 30
Power-on Reset (POR) .............................. 51, 54, 55, 58, 59
Oscillator Start-up Timer (OST) ..................... ...... 51, 55
POR Status  (POR Bit)  .................. ................... .......... 18
Power Control (PCON) Register ................................ 57
Power-down (PD Bit) ........................................... 13, 54
Power-on Reset Circuit, External ............................... 55
Power-up Timer (PWRT) ..................................... 51, 55
PWRT Enable (PWRT E Bit)  ......................................52
Time-o ut (TO Bit) ................................................. 13, 54
Time-out Sequence  ... .. .... .... .. ....... .... .... .. .... ....... .... .. .. 57
Time-out Sequence on Power-up .............................. 60
Timing Diagram .........................................................85

 1999 Microchip Technology Inc. Preliminary DS41106A-page 103
PIC16C712/716
Presca le r, Capture  ............................ .................. ...............40
Presca le r, Timer0 ......... .............. ............... ................... ......29
Assignment (PSA Bit)  ..........................................14, 29
Block Diag ram ........ .............. ................... ...................30
Rate Select (PS2:PS0 Bits)  .................................14, 29
Switching Between Timer0 and WDT ... .. .... ......... .... ..30
Presca le r, Timer1 ......... .............. ............... ................... ......32
Select (T1CKPS1:T1CKPS0 Bits) ............................ ..31
Presca le r, Timer2 ......... .............. ............... ................... ......42
Select (T2CKPS1:T2CKPS0 Bits) ............................ ..36
PRO MA TE  II Universal Programmer  .............................69
Product Identification System  ..........................................107
Program Counter
PCL Register ........................................................11, 19
PCLATH Register  ..........................................11, 19, 62
Reset Conditions ........................................................58
Program Memory .................................................................9
Inter rupt Vec to r ............................... ....................... ......9
Paging ....................................................................9, 19
Program Memory Map .................................................9
Reset Vec to r .......................... ................... ...................9
Program Verification  ..........................................................65
Programming, Device Instructions .....................................67
PWM (CCP Module)  ..........................................................42
Block Diag ram ........ .............. ................... ...................42
CCPR1H:CCPR1L Registers .....................................42
Duty Cycle .............. .............. ................... ............... ....42
Example Frequencies/Resolutions  ............................43
Output Dia g ram ........ ................... .............. .................42
Period .........................................................................42
Set-Up for PWM Operation ........................................43
TMR2 to PR2 Match  ............................................36, 42
TMR2 to PR2 Match Enable (TMR2IE Bit)  ................16
TMR2 to PR2 Match Flag (TMR2IF Bit) .....................17
Q
Q-Clock ..............................................................................42
R
RAM. 
See
 Data Memory
Register File ..................... ................... ................... ............10
Register File Map ...... ........... ................... ............... ............10
Reset ............................................................................51, 54
Block Diag ram ........ .............. ................... ...................56
Reset Conditions for All Registers .............................59
Reset Conditions for PCON Register .........................58
Reset Conditions for Program Counter ......................58
Reset Conditions for STATUS Register .....................58
Timing Dia g r a m .............. ................... ............... ..........85
Revision History .................................................................99
S
SEEVAL Evaluation and Programming System ..............71
SLEEP  ...................................................................5 1, 54, 64
Softwa re Simulator (MPLAB -SIM)  . ............... .....................71
Special Features of the CPU  .............................................51
Special Function Registers ................................................11
Speed, Operating ................... .. .. .... ..... .... .. .. .... .. .. ....... .. .... .. ..1
Stack ..................................................................................19
STATUS Register  ..................................................11, 13, 62
C Bit ........ ................... ................... ................... ..........13
DC Bit .........................................................................13
IRP Bit  ............... ............................ ........................... ..13
PD Bit ...................................................................13, 54
RP1:RP0 Bits ............................................................. 13
TO Bit ...................................................................13, 54
Z Bit ............................................................................13
T
T1CON Register .......................................................... 11, 31
T1CKPS1:T1CKPS0 Bits ........ ....................... ............ 31
T1OSCEN Bi t  .............. ....................... ................... .... 31
T1SYNC Bit ....... ....................... ........................... ...... 31
TMR1CS Bit ................... ................... ....................... .. 31
TMR1ON Bit .............................................................. 31
T2CON Register .......................................................... 11, 36
T2CKPS1:T2CKPS0 Bits ........ ....................... ............ 36
TMR2ON Bit .............................................................. 36
TOUTPS3:TOUTPS0 Bits  ......................................... 36
Timer0 ............................................................................... 29
Block Diag ram ............... ................... ................... ...... 29
Clock Source Edge Select (T0SE Bit)  ................. 14, 29
Clock Source Select (T0CS Bit)  .......................... 14, 29
Overflow Enable (T0IE Bit) ........................................ 15
Overflow Flag (T0IF Bit)  ...................................... 15, 62
Overflow Interrupt ................................................ 30, 62
Timing Dia g ram ................ .................. ............... ........ 86
TMR0 Register  .......................................................... 11
Timer1 ............................................................................... 31
Block Diag ram ............... ................... ................... ...... 32
Capacitor Selection  ................................................... 34
Clock Source Select (TMR1CS Bit) ........................... 31
External Clock Input Sync (T1SYNC Bit) .... ...... .. ...... . 3 1
Module On/Off (TMR1ON Bit)  ................................... 31
Oscillator .............................................................. 31, 34
Oscillato r Enabl e (T1OSCEN Bit) .............. .......... ...... 31
Overflow Enable (TMR1IE Bit)  ........... ....... .... .... .. .... .. 16
Overflow Flag (TMR1IF Bit) ....................................... 17
Overflow Interrupt ................................................ 31, 34
Special Event Trigger (CCP) ............................... 34, 41
T1CON Register .................................................. 11, 31
Timing Dia g ram ................ .............. ................... ........ 86
TMR1H Register .................................................. 11, 31
TMR1L Register  .................................................. 11, 31
Timer2
Block Diag ram ............... ................... ................... ...... 36
PR2 Register ................................................. 12, 36, 42
T2CON Register .................................................. 11, 36
TMR2 Register  .................................................... 11, 36
TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 16
TMR2 to PR2 Match Flag (TMR2IF Bit)  .................... 17
TMR2  to  PR 2  M atch Interrupt .. .. ...... .. ..... .. ..... 3 6, 3 7 , 4 2
Timing Diagrams
Time-out Sequence on Power-up .................... .... .... .. 60
Wake-up from SLEEP via Interrupt  ........................... 65
Timing Diagrams and Specifications  . ................................ 83
A/D Conver sion  ...................... ................... .............. .. 89
Brown-out Reset (BOR) ............................................. 85
Capture/Compar e /P WM ( CCP)  ........ ............... .......... 87
CLKOUT and I/O ....................................................... 84
External Clock  ........................................................... 83
Oscillato r Start-up Timer (OST) ......................... ...... .. 85
Power-up Timer (PWRT) ........................................... 85
Reset ......................................................................... 85
Timer0 and Timer1 .................................................... 86
Watchdog Timer (WDT) ............................................. 85
W
W Register ......................................................................... 62
Wake-up from SLEEP .................................................. 51, 64
Interrupts  ............................................................. 58, 59
MCLR Reset ........ ............... ................... .................... 59
Timing Dia g ram ................ .............. ................... ........ 65
WDT Reset ...... ................... ................... .................. .. 59

PIC16C712/716
DS41106A-page 104 Preliminary  1999 Microchip Technology Inc.
Watchdog Timer (WDT)  ................................ ...... .... .... .51, 63
Block Diag ram ................ ................... .................. .......63
Enable (WDTE Bit) . ..............................................52, 63
Programming Considerations ....................................63
RC Oscillator ..............................................................63
Time-o u t Pe riod  ........ ........................ .........................63
Timing Dia g r a m ... ........... ................... .................. .......85
WDT Reset, Normal Operation ......................54, 58, 59
WDT Reset, SLEEP .......................................5 4, 58, 59
WWW, On-Line Support  . ......................................................3

 1999 Microchip Technology Inc. Preliminary DS41106A-page 105

PIC16C712/716

Systems Information and Upgrade Hot Line

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip’s development systems software products.

Plus, this line provides information on how customers

can receive any currently available upgrade kits.The

Hot Line Numbers are:

1-800-755-2345 for U.S. and most of Canada, and

1-480-786-7302 for the rest of the world.

Trademarks: The Microchip name, logo, PIC, PICmicro,

PICSTART, PICMASTER and PRO MATE are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

Flex

ROM, MPLAB and

fuzzy-

LAB are trademarks and SQTP is a service mark of Micro-

chip in the U.S.A.

All other trademarks mentioned herein are the property of

their respective companies.

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip

World W ide Web (WWW) site.

The we b site is used b y Mic rochi p as a mean s to mak e

files and infor mation easily available to customers. To

vie w the site , the user must ha v e access to the Internet

and a web browser, such as Netscape or Microsoft

Explorer. Files are also available for FTP download

from our FTP site.

Connecting to the Microchip Internet Web Site

The Microchip web site is available by using your

favorite Internet browser to attach to:

www.microchip.com

The file transfer site is available by using an FTP ser-

vice to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of

services. Users may download files for the latest

Development Tools, Data Sheets, Application Notes,

User’s Guides, Articles and Sample Programs. A vari-

ety of Microchip specific business information is also

available, including listings of Microchip sales offices,

distributors and factory representatives. Other data

available for consideration is:

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked

Questions

• Design Tips

•Device Errata

• Job Posting s

• Mi c rochip Consultant Progra m Mem ber Listing

• Links to other useful web sites related to

Microchip Products

• Conferences for products, Development Sys-

tems, technical information and more

• Listing of seminars and events

981103

PIC16C712/716

DS41106A-page 106 Preliminary  1999 Microchip Technology Inc.

READER RESPONSE

It is our i ntention to provide you w ith the bes t d ocu me nta tion poss ible to ensure suc ce ssful use of your Microchi p pro d-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578.

Please list the following information, and use this outline to provide us with your comments about this Data Sheet.

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this data sheet easy to follow? If not, why?

4. What additions to the data sheet do you think would enhance the structure and subject?

5. What deletions from the data sheet could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

8. How would you improve our software, systems, and silicon products?

To: Technical Publications Manager

RE: Reader Response Total Pages Sent

From: Name

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Address

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Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

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FAX: (_____ _) ____ ___ __ - _____ ___ _

DS41106A

PIC16C712/716

 1999 Microchip Technology Inc. Preliminary DS41106A-page 107

PIC16C712/716 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

* JW Devices are UV erasable and can be programmed to any device configuration. JW Dev ices meet the electrical requirement of

each oscillator type (including LC device s).

Sales and Support

PART NO. -XX X/XX XXX

PatternPackageTemperature

Range

Frequency

Range

Device

Device PIC16C712(1), PIC16C712T(2);VDD range 4.0V to 5.5V

PIC16LC712(1), PIC16LC712T(2);VDD range 2.5V to 5.5V

PIC16C716(1), PIC16C716T(2);VDD range 4.0V to 5.5V

PIC16LC716(1), PIC16LC716T(2);VDD range 2.5V to 5.5V

Frequency Range 04 = 4 MHz

20 = 20 MHz

Temperature Range blank = 0°C to 70°C (Commercial)

I= -40

°C to +85°C (Industrial)

E= -40

°C to +125°C (Extended)

Package JW = Windowed CERDIP

SO = SOIC

P=PDIP

SS = SSOP

Pattern QTP, SQTP, Code or Special Requirements

(blank otherwise)

Examples:

a) PIC16C716 - 04/P 301 = Commercial temp.,

PDIP package, 4 MHz, normal VDD limits, QTP

pattern #301.

b) PIC16LC712 - 04I/SO = Industrial temp., SOIC

package, 200 kHz, Extended VDD limits.

c) PIC16C712 - 20I/P = Industrial temp., PDIP

package, 20MHz, normal VDD limits.

Note 1: C = CMOS

LC = Low Power CMOS

2: T = in tape and reel - SOIC, SSOP

packages only.

3: LC extended temperature device is not

offered.

4: LC is not offered at 20 MHz

Data Sheets

Products supported by a preliminary Data Sheet ma y have an errata sheet describing minor operational differences and recom-

mended workarounds. To deter mine if an errata sheet exists for a part icular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277

3. The Microchip Worldwide Site (www. microch ip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Information cont ai ned in this publi cation reg ardi ng device applications and the like is intended for suggestion only and m ay be s upers eded by updates . No representation or war ran ty is given and no liability is assumed

by Microchip Technology Incorpora ted with respect to the accuracy or use of such information, or infringe ment of patents or ot her intellec tual property rights arising fr om such use or otherwi se. Use of Microc hip’s pro ducts

as critical c om ponents in life support sys tems is not au thorized except with ex pres s written approval by M icrochip. No lic enses ar e co nveyed, impli citly or otherwise, unde r any intellect ual property ri ght s. The M i cr ochip

logo and name are registered trademarks of Micr ochip Technology Inc. in the U. S.A. and ot her countries . Al l rig hts res e rv ed. All other trademar ks men tioned herein are the property of their res pective comp ani es.

 1999 Microchip Technology Inc.

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Korea

Microchip Technology Korea

168-1, Youngbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku

Seoul, Korea

Tel: 82-2-554-7200 Fax: 82-2-558-5934

Shanghai

Microchip Technology

RM 406 Shanghai Golden Bridge Bldg.

2077 Yan’an Road West, Hong Qiao District

Shanghai, PRC 200335

Tel: 86-21-6275-5700 Fax: 86 21-6275-5060

ASIA/PACIFIC (continued)

Singapore

Microchip Technology Singapore Pte Ltd.

200 Middle Road

#07-02 Prime Centre

Singapore 188980

Tel: 65-334-8870 Fax: 65-334-8850

Taiwan, R.O.C

Microchip Technology Taiwan

10F-1C 207

Tung Hua North Road

Tai pe i, Ta iwa n, RO C

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPE

United Kingdom

Arizona Microchip Technology Ltd.

505 Eskdale Road

Winnersh Triangle

Wokingham

Berkshire, England RG41 5TU

Tel: 44 118 921 5858 Fax: 44-118 921-5835

Denmark

Microchip Technology Denmark ApS

Regus Business Centre

Lautrup hoj 1-3

Ballerup DK-2750 Denmark

Tel: 45 4420 9895 Fax: 45 4420 9910

France

Arizona Microchip Technology SARL

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

Batiment A - ler Etage

91300 Massy, France

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany

Arizona Microchip Technology GmbH

Gustav-Heinemann-Ring 125

D-81739 München, Germany

Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

Italy

Arizona Microchip Technology SRL

Centro Direzionale Colleoni

Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Milan, Italy

Tel: 39-039-65791-1 Fax: 39-039-6899883

11/15/99

WORLDWIDE SALES AND SERVICE

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code hopping

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.