DATA SH EET
Product specification
File under Integrated Circuits, IC04 January 1995
INTEGRATED CIRCUITS
HEF4557B
LSI
1-to-64 bit variable length shift
register
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
1-to-64 bit variable length shift register HEF4557B
LSI
DESCRIPTION
The HEF4557B is a static clocked serial shift register
whose length may be programmed to be any number of
bits between 1 and 64. The number of bits selected is
equal to the sum of the subscripts of the enabled length
control inputs (L1, L2, L4, L8, L16 and L32) plus one. Serial
data may be selected from the DAor DBdata inputs with
the A/B select input. This feature is useful for recirculation
purposes. Information on DAor DBis shifted into the first
register position and all the data in the register is shifted
one position to the right on the LOW to HIGH transition of
CP0while CP1is LOW or on the HIGH to LOW transition
of CP1while CP0is HIGH. A HIGH on master reset (MR)
resets the register and forces O to LOW and O to HIGH,
independent of the other inputs.
Fig.1 Functional diagram.
PINNING
DA, DBdata inputs
A/B select data input
CP0clock input
CP1clock enable input
MR asynchronous master reset
L1 to L32 bit-length control inputs
O, O buffered outputs
Fig.2 Pinning diagram.
FAMILY DATA, IDD LIMITS category LSI
See Family Specifications
HEF4557BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4557BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4557BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
January 1995 3
Philips Semiconductors Product specification
1-to-64 bit variable length shift register HEF4557B
LSI
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Fig.3 Logic diagram.
January 1995 4
Philips Semiconductors Product specification
1-to-64 bit variable length shift register HEF4557B
LSI
FUNCTION TABLE
INPUTS OUTPUT
MR A/BD
AD
BCPOCP1O(1)
LLD
1D
2LD
2
LHD
1D
2LD
1
LLD
1D
2HD
2
LHD
1D
2HD
1
HXXX X X L
Notes
1. The moment Dnappears at O depends on the
bit-length shown in the table below.
2. H = HIGH state (the more positive voltage)
3. L = LOW state (the less positive voltage)
4. X = state is immaterial
5. = positive-going transition
6. = negative-going transition
7. Dn= either HIGH or LOW
BIT-LENGTH SELECT FUNCTION TABLE
AC CHARACTERISTICS
VSS = 0 V; Tamb =25°C; input transition times ≤20 ns
L32 L16 L8L4L2L1REGISTER LENGTH
LLLLLL 1-bit
LLLLLH 2-bits
L L L L H L 3-bits
L L L L H H 4-bits
L L L H L L 5-bits
L L L H L H 6-bits
L L L H H L 7-bits
L L L H H H 8-bits
↓↓↓↓↓↓ ↓
LHHHHH 32-bits
HLLLLL 33-bits
HLLLLH 34-bits
↓↓↓↓↓↓ ↓
H H H H L L 61-bits
H H H H L H 62-bits
HHHHHL 63-bits
HHHHHH 64-bits
VDD
VTYPICAL FORMULA FOR P (µW)
Dynamic power 5 3 500 fi+∑(foCL)×VDD2where
dissipation per 10 15 000 fi+∑(foCL)×VDD2fi= input freq. (MHz)
package (P) 15 37 000 fi+∑(foCL)×VDD2fo= output freq. (MHz)
CL= load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
January 1995 5
Philips Semiconductors Product specification
1-to-64 bit variable length shift register HEF4557B
LSI
AC CHARACTERISTICS
VSS = 0 V; Tamb =25°C; CL= 50 pF; input transition times ≤20 ns
Interpolation table (see note next page)
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
VDD
VSYMBOL TYP. MAX. TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP0, CP1→O, O 5 240 480 ns 213 ns +(0,55 ns/pF) CL
HIGH to LOW 10 tPHL 90 180 ns 79 ns +(0,23 ns/pF) CL
15 65 130 ns 57 ns +(0,16 ns/pF) CL
5 240 480 ns 213 ns +(0,55 ns/pF) CL
LOW to HIGH 10 tPLH 90 180 ns 79 ns +(0,23 ns/pF) CL
15 65 130 ns 57 ns +(0,16 ns/pF) CL
MR →O 5 170 340 ns 143 ns +(0,55 ns/pF) CL
HIGH to LOW 10 tPHL 80 160 ns 69 ns +(0,23 ns/pF) CL
15 60 120 ns 52 ns +(0,16 ns/pF) CL
MR →O 5 140 280 ns 113 ns +(0,55 ns/pF) CL
LOW to HIGH 10 tPLH 70 140 ns 59 ns +(0,23 ns/pF) CL
15 55 110 ns 47 ns +(0,16 ns/pF) CL
Output transition times 5 60 120 ns 10 ns +(1,0 ns/pF) CL
HIGH to LOW 10 tTHL 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
5 60 120 ns 10 ns +(1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
LENGTH CONTROL INPUTS MINIMUM
NUMBER OF
BITS SELECTED
SET-UP, HOLD,
RECOVERY
TIMES
L1L2L4L8L16 L32
L L L L L L 1 specified
HLLLLL 2
XHLLLL 3
X X H L L L 5 six equal steps
XXXHLL 9
XXXXHL 17
X X X X X H 33 specified
January 1995 6
Philips Semiconductors Product specification
1-to-64 bit variable length shift register HEF4557B
LSI
AC CHARACTERISTICS
VSS = 0 V; Tamb =25°C; CL= 50 pF; input transition times ≤20 ns; see also waveforms Fig.4
Note
1. The set-up, hold and recovery times vary with the minimum number of bits selected. For other values as specified
one may interpolate as shown in the table (see previous page).
VDD
VSYMBOL MIN. TYP.
Minimum clock
pulse width; 5 tWCPL 180 90 ns
LOW for CP0or 10 or 60 30 ns
HIGH for CP115 tWCPH 40 20 ns
Minimum reset 5 150 75 ns
pulse width; 10 tWMRH 70 35 ns
HIGH 15 50 25 ns
Set-up times
see note
DA, DB, A/B →CP0, 5 360 180 ns
CP110 tsu 140 70 ns
L1to L32 = LOW 15 90 45 ns
540−20 ns
L32 = HIGH 10 tsu 35 −10 ns
15 30 −5ns
Hold times
DA, DB, A/B →CP0,5 −40 −110 ns
CP110 thold −10 −45 ns
L1to L32 = LOW 15 0 −30 ns
59030ns
L
32 = HIGH 10 thold 60 20 ns
15 50 15 ns
Recovery times for MR 5 500 250 ns
L1to L32 = LOW 10 tRMR 250 125 ns
15 150 75 ns
5 110 50 ns
L32 = HIGH 10 tRMR 70 30 ns
15 60 25 ns
Minimum clock 5 2,5 5 MHz
pulse frequency 10 fmax 7 14 MHz
15 10 20 MHz
January 1995 7
Philips Semiconductors Product specification
1-to-64 bit variable length shift register HEF4557B
LSI
Fig.4 Waveforms showing recovery time for MR and minimum CP0, CP1and MR pulse widths, set-up and hold
times for DA, DBand A/B to CP0and CP1. Set-up and hold times are shown as positive values but may
be specified as negative values.
