SN54HC03, SN74HC03 QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-DRAIN OUTPUTS SCLS077C - MARCH 1984 - REVISED NOVEMBER 2002 D D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up to 10 LSTTL Loads Low Power Consumption, 20-A Max ICC Typical tpd = 8 ns 4-mA Output Drive at 5 V Low Input Current of 1 A Max 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1Y NC 2A NC 2B 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 1A 1B 1Y 2A 2B 2Y GND SN54HC03 . . . FK PACKAGE (TOP VIEW) 1B 1A NC VCC 4B SN54HC03 . . . J OR W PACKAGE SN74HC03 . . . D, N, OR NS PACKAGE (TOP VIEW) NC - No internal connection description/ordering information The 'HC03 devices contain four independent 2-input NAND gates. They perform the Boolean function Y = A * B or Y = A + B in positive logic. The open-drain outputs require pullup resistors to perform correctly. They may be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. ORDERING INFORMATION PDIP - N -40C 40C to 85C -55C to 125C ORDERABLE PART NUMBER PACKAGE TA TOP-SIDE MARKING Tube SN74HC03N Tube SN74HC03D Tape and reel SN74HC03DR SOP - NS Tape and reel SN74HC03NSR HC03 CDIP - J Tube SNJ54HC03J SNJ54HC03J CFP - W Tube SNJ54HC03W SNJ54HC03W SOIC - D SN74HC03N HC03 LCCC - FK Tube SNJ54HC03FK SNJ54HC03FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H H L L X H X L H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54HC03, SN74HC03 QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-DRAIN OUTPUTS SCLS077C - MARCH 1984 - REVISED NOVEMBER 2002 logic diagram (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC03 VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage NOM MAX 2 5 6 NOM MAX 2 5 6 1.5 3.15 3.15 VCC = 4.5 V VCC = 6 V 0 Output voltage MIN 1.5 4.2 Input voltage Input transition rise/fall time SN74HC03 MIN 0 VCC = 2 V VCC = 4.5 V UNIT V V 4.2 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC 0 0 VCC VCC 1000 1000 500 500 V V V ns VCC = 6 V 400 400 TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54HC03, SN74HC03 QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-DRAIN OUTPUTS SCLS077C - MARCH 1984 - REVISED NOVEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH VOL II ICC TEST CONDITIONS VI = VIH or VIL, VCC VO = VCC TA = 25C TYP MAX SN54HC03 SN74HC03 MIN MIN MAX MAX UNIT A 6V 0.01 0.5 10 5 2V 0.002 0.1 0.1 0.1 IOL = 20 A 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 IOL = 4 mA IOL = 5.2 mA 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V 0.1 100 1000 1000 nA 2 40 20 A 10 10 10 pF VI = VIH or VIL VI = VCC or 0 VI = VCC or 0, MIN IO = 0 6V Ci 2 V to 6 V 3 V switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) TA = 25C MIN TYP MAX SN54HC03 SN74HC03 MIN MIN PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V 60 105 155 131 tPLH A or B Y 4.5 V 13 25 36 31 6V 10 23 31 27 2V 50 100 150 125 4.5 V 10 20 30 25 6V 8 17 25 21 2V 38 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 tPHL A or B Y tf Y MAX MAX UNIT ns ns ns operating characteristics, TA = 25C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate POST OFFICE BOX 655303 No load * DALLAS, TEXAS 75265 TYP 20 UNIT pF 3 SN54HC03, SN74HC03 QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-DRAIN OUTPUTS SCLS077C - MARCH 1984 - REVISED NOVEMBER 2002 PARAMETER MEASUREMENT INFORMATION VCC RL = 1 k From Output Under Test VCC Test Point Input 50% 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT Input 50% 10% 90% VCC 50% 10% 0 V 90% tr 50% tPHL 90% 10% tPHL Out-of-Phase Output 90% tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES tPLH 50% 10% 10% VOH 50% 10% V OL tf VOH VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MLCC006B - OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL MPDI002C - JANUARY 1995 - REVISED DECEMBER 20002 N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PINS SHOWN PINS ** 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23,37) 1.060 (26,92) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21,59) 0.940 (23,88) MS-100 VARIATION AA BB AC DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 C AD 8 0.070 (1,78) 0.045 (1,14) 0.045 (1,14) 0.030 (0,76) D D 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gauge Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.430 (10,92) MAX 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 14/18 PIN ONLY 20 pin vendor option D 4040049/E 12/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0- 8 A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). 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