@ ee Am27S35/Am27S37 8,192-Bit (1024 x 8) Bipolar Registered PROM with Programmable INITIALIZE Input DISTINCTIVE CHARACTERISTICS @ Slim, 24-pin, 300-mil lateral center package occupies approximately 1/3 the board space required by standard discrete PROM and register Consumes approximately 1/2 the power of separate PROM: register combination for improved system reli- ability @ Versatile programmable asynchronous or synchronous enable for simplified word expansion @ Buffered common Input sither asynchronous (Am27S85) or synchronous (Am27S37) @ Platinum-Silicide fuses guarantee high reliability, fast programming and exceptionally high programming yields (typ > 98%) GENERAL DESCRIPTION The Am27S35 and the Am27S37 (1024-words by 8-bits) are fully decoded, Schottky array, TTL Programmable Read-Only Memories (PROMs), incorporating D-type mas- ter-slave data registers on chip These devices have three- state outputs compatible with low-power Schottky bus standards capable of satisfying the requirements of a variaty of rucroprogrammabie controls and state machines These devices contain an 8-bit parallel data register in the array-to-output path which allows PROM data to be stored while other data is being addressed This meets the requirements for pipelined microprogrammable control stores where instruction execute and instruction fetch ar performed ln parallel To offer the system designer maximum flexibility, these devices contain both asynchronous (G) and synchronous (Gs) output enables These devices contain a single pin initialize function capa- ble of loading any arbitrary microinstruction for system Interrupt or initialization On the Am27S35 this function operates asynchronously, independent of clock The Am27S37 provides synchronous operation of this function Upon power-up the outputs (Qo ~ Q7) will be in a floating or high-impedance state BLOCK DIAGRAM o) e iza_ KI DECODER L-/ PPPIIPE 128 X 64 PROGRAMMABLE ARRAY gio Go yy oo 7 1978 oF COLUMN Pe C>-] DECODER 8~- 1 of 8 MULTIPLEXERS [ [ Ty ty BIT EDGE-TRIGGERED REGISTER PROGRAMMABLE INITIALIZE WORD % a Og 3 04 OG OG Oy BD006351 PRODUCT SELECTOR GUIDE Part Number Asynchronous Initialize Am27S35A Am27S35 Part Number Synchronous Initiailze Am27S37A Am27S37 Address Setup Time 36 ns 40 ns 40 ns 45 ns Clock-to-Output Delay 20 ns 20 ns 25 ns 30 ns Operating Range Cc M c M Publication # Hey, Amendment 03187 c /0 2-121 (Issue Date May 1966 desicuiy /SseszewyCONNECTION DIAGRAMS T p View DIP* cb000741 *Also available in 24-pin Flatpack. Connections identical to DiPs. Note: Pin 1 is marked for orientation. LOGIC SYMBOL i & p000620 Li] a7 AF Phe fit dtd tt 1 Az As Ag Ag Ag Ay Ag Ag TTT L$000172 2-122ORDERING INFORMATION (Cont'd.) Standard Pr ducts AMD standard products are available in sev ral packages and operating rang s. The order number (Valid Combination) is formed by a combination of: A. D vic Numb r B. Speed Option (if applicable) C. Package Type D. Temperature Range E. Optional Processing F. Alternate Packaging Option AM27S35_ A 1 F. ALTERNATE PACKAGING OPTION -S = 28-Pin Ceramic Leadiess Chip Carrier (CLT028) . OPTIONAL PROCESSING Blank = Standard processing 8 = Burn-in D. TEMPERATURE RANGE C = Commercial (0 to + 75C) C. PACKAGE TYPE P = 24-Pin Plastic DIP (PD3024) O = 24-Pin Ceramic OIP (CO3024) L = 32-Pin Rectangular Ceramic Leadless Chip Carrier (CLRO32) B. SPEED OPTION A= 35 ns setup time/20 ns clock-to-output Blank = 40 ns setup time/26 ns clock-to-output -- A, DEVICE NUMBER/DESCRIPTION Am27S35/Am27S37 8,192-Bit (1024 x 8) Bipolar Registered PROM with Programmable 1 Input Am27S35 = Asynchronous Initialize Am27S37 = Synchronous Intaize Valid Combinations Valid Combinations Valid Combinations tist configurations planned to be AM27835 supported in volume for this device. Consult the local AMD AM27S35A BC, DCB, PC, sales office to confirm availability of specific valid AM27S37 tes, wees combinations, to check on newly raleased combinations, and AM27S37A to obtain additional data on AMD's standard military grade products. 2-123ORDERING INFORMATION APL Products AMD products for Aerospace and Def ns_ applications are avatlable in sev ral packages and operating ranges APL (Approved Products List) products are fully compliant with MIL-STD-883C requirements CPL (Controlled Products List) products are processed in accordance with MIL-STD-883C, but are inherently non-compliant because of package, solderabllity, or surface treatment exceptions to those specifications The order number (Valid Combination) for APL products 1s formed by a combination of A. Device Number B. Speed Option (if applicable) C. Device Class D. Package Type . Lead Finish AMe7S35 A | E. LEAD FINISH A=Hot Solder DIP C = Gold O. PACKAGE TYPE L = 24-Pin Ceramic DIP (CO03024) U = 32-Pin Rectangular Ceramic Leadiess Chip Carner (CLRO32) 3 = 28-Pin Ceramic Leadiess Chip Carrier (CLTO28) K = 24-Pin Flatpack (CFM024) C. DEVICE CLASS /B=Class B 6. SPEED OPTION A~40 ns setup time/25 ns clock-to-output Blank ~ 45 ns setup time/30 ns clock-to-output A. DEVICE NUMGER/DESCRIPTION Am27S835/Am27837 8,192-Bit (1024 8) Bipolar Registered PROM with Programmable INITIALIZE Input Am27S35 = Asynchronous Initialize Am27837 = Synchronous Initialize Valid Combinations Valid Combinations Valid Combinations list configurations plann d to be AM27835 supported in volume for this device Consult the local AMD AM27S35A sales office to confirm availability of specific valid /BLA, /BKA AM27S97 /BUC, /B3C combinations or to check for newly released valid AM27S37A combinations 2-124PIN DESCRIPTION Ag-Ag Aiddress Inputs The 10-bi field presented at the address inputs selects one of 1024 inemory locations to b =r ad from K Cl ck The clock Is used to load data into the parallel registers from the memory array Data transfer occurs on the LOW-to- HIGH transition of K Qo9-Q7 Data Output Port Parallel data output from the pipeline register The disabled stat of these outputs ts floating or high impedance Gs Asyn hronous Output Enable Provides direct control of the Q-output, three-state drivers Independent of K Gs Synchronous Output Enable Controls ih state of the Q-output, three-state dnvers in conjuncticn with K This is useful where more than one registerec| PROM is bussed together for word-depth expansion In this case, the enable becomas the most significant address bit and, as such, must be synchronized with the data Asynchr n us Initialize (Am27S35) Control pin used to initialize the output data registers from a programmable word independent of K This can be used to generate any arbitrary microinstruction for system interrupt or tnttalization Ts Synchronous Initialize (Am27S37) Control pin used to initialize the output data registers from a programmable word in conjunction with K This cand used to generate any arbitrary micromstruction for system interrupt or initialization Voc Device Power Supply Pin The most positive of the logic power supply pins GND Device Power Supply Pin The most negative of the logic power supply pins FUNCTIONAL DESCRIPTION The Am27S35A/35 and Am27S37A/37 are Schottky TTL programmatie read only memones (PROMs) incorporating true O-type master-slave data registers on chip These devices feature the versatiia 1024-word by 8-bit organization and are available with three-state outputs Designed to opti- mize system performance, these devices also substantially reduc th cost and size of pipelined microprogrammed systems and other designs where accessed PROM data Is temporanly stored in a register The Am27S35A/35 and Am27S37A/37 also offer maximum flexibilty for memory expansion and data bus control by providing both synchro- nous and asynchronous output enables When Vcc power Is first appled, the synchronous enable (Gs) flip-flop will be in the set condition causing the outputs (Qo-Q7) to be in the OFF or high-impedance state Reading data is accomplished by first applying the binary word address to the address inputs (Ap-Ag) and a logic LOW to the synchronous enable (Gs) Dunng the address setup time, stored data is accessed and loaded into the master flip-flops of the data register Since the synchronous enable setup time ts less than ihe address setup requirement, additional decod- Ing delays rnay occur in the enable path without reducing memory performance Upon the next LOW-to-HIGH transition of the clock (K), data is transferred to the slave flip-flops which drive the ou put buffers Providing the asynchronous enable (G) is also LOW, stored data will appear on the outputs (Qo-Q7) If (Gg) is HIGH when the positive clock edge occurs, outputs go to the OFF or high-impedance state regardless of the value of (G) The outputs may be disabled at any time by switching (G) to a HIGH level Following the positive clock dge, th address and synchronous enable inputs are free to chang , changes will not affect the outputs unt! another positive clock edge occurs This unique feature allows the PROM decoders and sense amplifiers to access the next location while previously addressed data remains stable on the outputs For less complex applications either enab! may be effectively eliminated by tying it to ground These devices also contain a built-in initialize function When activated, the initialize control input (I) causes the contents of an additional (1025th) 8-bit word to be loaded inte th on-chip register This extra word Is user programmable Sinc each bit ts individually programmable, the initialize function can be used to load any desired combination of HIGHs and LOWs into the register In the unprogrammed state, activating | wili perform a register CLEAR (all outputs LOW) If all bits of th initialize word are programmed, activating | performs ar gister PRESET (all outputs HIGH) This ability to tailor the initialize outputs to the system requirements simplifies system design and enhances perfor- mance The initialize function is useful during pow r-up and timeout sequences This flexible feature can also facilitate tmplementaton of other sophisticated functions such as a built-in 'jump-start" address The Am27S35A/35 has an asynchronous tnitialize input (I) Applying a LOW to the T input causes an immediate load of th programmed initialize word into the slave flip-flops of th register independent of all other inputs (including K) The initahze data will appear at the device outputs after the outputs are enabled by bringing the asynchronous enabl (G) LOW The Am27S37A/37 has a synchronous lg input Applying a LOW to the Ig input causes an immediate load of the programmed initialize word into the master flip-flops of the register only independent of all other inputs (including K) To bnng this data to the device outputs, the synchronous enable (Gg) should be held LOW until the next LOW-to-HIGH transition of the clock (K) Following this, the data will app ar on the outputs after the asynchronous enable (G) ts brought LOW 2-125ABSOLUTE MAXIMUM RATINGS Storage Temp rature -65 to + 150C Ambient Temperature with Power Applied Supply Voltag DC Voltage Applied to Outputs (Except During Programming) DBC Voltage Applied to Outputs -~55 to +125C ~O5Vto+70V -05 V to +Voc Max During Programming 21V Output Current into Outputs During Programming (Max Duration of 1 sec) 250 mA DC Input Voltage ~05 Vto +55 V BC input Current -30 mA to +5 mA Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure Functionality at or above these Iimits ts not implied Exposure to absolute maximum ratings for extended penods may affect device OPERATING RANGES Commercial (C) Devices Temperature, Ta Supply Voltage Military (M) Devices* Temperature, To Supply Voltage 0 to +75C +475 V to +525 V -55 to +125C +45 V to +55 V Operating ranges define those limits between which the functronality of the device is guaranteed Military product 100% tested at To = + 25C, + 125C, and -55C rehability OC CHARACTERISTICS over operating range unless otherwise specified* Parameter Parameter Symbol Description Test Conditions Min. Typ. Max. Unite Output HIGH Voc = Min, low =~20 mA Vou Voltage Vin Vin oF VIL 24 Volts Output LOW Voc = Min, lo, = 16 mA You Voltage Vin= Vint OF Vit 050 | Volts Guaranteed input logical HIGH Vid Input HIGH Level voltage for all mputs (Note 1) 20 Volts Guaranteed input logical LOW viL Input LOW Level voltage for all inputs (Note 1) 06 Volts Me Covent Veg = Max, Vin=045 V -0250 | ma lin input HIGH Voc = Max Vin = Voo 40 BA Output Short - - _ _ Isc Curcut Current Voc = Max, Vout =00 V (Note 2) 20 90 mA cc Power Supply All inputs = GND, Voc = Max 185 mA Input Clamp - -_ _ vi Voltage Voc = Min, lin 18 mA 12 Volts \ Output Leakage Voc = Max Vo = Voc 40 BA Cex Current Va~724V Vos04V -40 CIN Input Capacitance Vin = 20 V @ f=1 MHz (Note 3) 5 Fr Cout Catamtance Vout = 20 V @ f=1 MHz (Note 3) 12 P Notes 1 These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise Do not attempt to teat these values without suitable equipment 2 Only one output should be shorted at a time Duration of the short circuit test should not be more than one second 3 These parameters are not 100% tested, but are periodically sampled *See the last page of this spec for Group A Subgroup Testing information 2-126SWITCHING TEST CIRCUITS KEY TO SWITCHING WAVEFORMS WAVEFORM inpuTs outeuTs MUST BE WILL BE seu STEADY STEADY S.B vu * | 4 si WILL BE si MAY CHANGE CHANGING FROMNTOL EROMH TOL 300 0 S280 WILL BE Ouiput Output MAY CHANGE = CH ANGinG FROMLTOH FROM. TOM SQ pF Sean Spr 3eewn DON'T CARE CHANGING ANY CHANGE STATE - ts = > PERMITTED UNKNOWN CENTER 70003442 TC003452 DOES NOT LINE IS HIGH APPLY IMPEDANCE "OFF STATE KS000010 A. Output L ad for All AC Tests 8B. Output Load for TGHQZ and TKHQZ Ex ept TGHQZ and TKHQZ Not s 1 Alt device test loads should be located within 2 of device output pin 2 Sj 1s open for Output Data HIGH to Hi-Z and Hi-Z to Output Data HIGH tests Sy 1s closed for all other AC tests 3 Load capacitance includes ail stray and fixture capacitance 2-127SWITCHING CHARACTERISTICS over operating range unless otherwise specified (Note 1)* "A" Vere! n Standard Vers! n Param ter Parameter N. Symb | D scription Min. Max. Min. Max. Units Address to K HIGH Setup COM'L 35 40 1 TAVKH ns Time MIL 40 45 Address to K HIGH Hold COM'L 9 0 2 TKHAX ns Time MIL 0 0 Delay from K HIGH to uy 3 TKHOV. Output Valid, for initially COM'L 20 26 ns 1 active outputs (HIGH or Low) Mit 25 30 4 TKHKL K Pulse Width (HIGH or COM'L 20 20 a TKLKH Low) MIL 20 20 8 Asynchronous Output Enable COM'L 25 30 5 FGLQV LOW to Output Valid (HIGH ns or LOW) (See Note 3) MIL 30 36 Asynchronous Output Enable COM'L 25 30 6 TGHOQZ HIGH to Output Hi-Z ns (See Notes 2 & 3) MIL 30 a5 Gs to K HIGH Setup Time COM'L 15 15 7 TGSVKH (Sea Note 4) MIL 15 13 ns Gs to K HIGH Hold Time COM'L 5 5 8 TKHGSX {See Note 4) MIL 5 5 ns Delay from K HIGH to COM'L 25 30 9 TKHQV2 Output Valid, for Initially Hi- ns Z outputs (See Note 4) MiL 30 35 Delay from K HIGH to COM'L 25 30 10 TKHOZ Output Hi-Z (See Notes 2 & ns 4) MIL 30 35 Delay from | LOW to Output COM'L 30 35 1 TILQV Valid (HIGH or LOW) (See ns Note 5) MIL 35 40 Asynchronous | Recovery COM'L 20 20 12 TIHKH Time (See Note 5) MIL 20 25 ns Asynchronous | Pulse Width COM'L 25 25 13 TILIK (See Note 5) MIL 20 30 ns Tg to K HIGH Setup Time COM'L 25 30 14 TISVKH (See Note 6) MIL 30 35 ns Tg to K HIGH Hold Time Com't 9 Qo 15 TKHISX (ea Note 6) MIL 9 9 na See also Switching Test Circuits Notes 1 Tests are performed with input transition time of 5 ns or less, timng reference levels of 15 V, and input pulse levels of 0 te 2 anaw 30 V using test toad in A under Switching Test Circuits TGHQZ and TKHOZ are measured at steady state HIGH output voltage -05 V and steady state LOW output voitage +05 V output levels using the test load in B under Switching Test Circuits Applies only when Asynchronous Enable & function is used Applias only when Synchronous Enable (Gs) function 1s used Applies only to the Am27S35 (Asynchronous Initalze (1) version Applies only to the Am27S37 (Synchronous Initialize (Is)) version *See the last page of this spac for Group A Subgroup Testing information 2-128SWITCHING WAVEFORMS (Cont'd.) KKK KKK HHH III IK aeartartra a tellteteltetelatellatleratetrerrn CLOCK ele og Bikar KS =O) aa 8 a OUTPUT VALID OUTPUT OUTPUT ENABLE G WFO021580 Timing Set 1. Using Asynchronous Enable @o CLOCK K JAa @ _ ADDRESS KOO AAA AIK Ag ~ Ag VALID ADGRESS HK Kee VALID ADDRESS +46) a @ ie 5 OUTPUTS Hinz ) Veeco on - a? VALID OUTPUT OUTPUT 7)on(B z OUTPUT ENABLE &s WFO21611 Timing Set 2. Using Synchronous Enable 2-129SWITCHING WAVEFORMS CLOCK @ ADDRESS VOXKKKOA ON S Fa Fe PRR AA_VAL TO sopRESS auto cones SEK + @ ry OUTPUTS VALID Qg - ar VALID OUTPUT VALID OUTPUT OUTPUT S 2 INITIALIZE 1 WFO216580 Timing Set 3. Using Asynchronous Initialize Am27S835 Only ADDRESS Ag ~- Ag aq - a> VALID OUTPUT VALID OUTPUT OUTPUTS INITIALIZE Ts WF021601 Timing Set 4. Using Synchronous Initialize Am27837 Only 2-130DC CHARACTERISTICS Param ter Symbal Subgr ups Vou 1,2, 3 VoL 1, 2,3 Vin 1,2, 3 ViL 1, 2,3 liu 1,2,3 hin 1,2, 3 tsc 1,2, 3 loc 1,2, 3 Icex 1,2,3 GROUP A SUBGROUP TESTING SWITCHING CHARACTERISTICS Parameter Parameter N. Symbol Subgroups No. Symbol Subgroups 1 TAVKH 9, 10, 11 8 TKHQV2 8, 10, 11 TKHAX 9, 10, 11 10 TKHOZ 9, 10, 11 TKHQV1 9, 10, 11 "1 TILQV 9, 10, 11 4 ea 9, 10, 14 12 TIHKH 9, 10, 11 TGLOV 9, 10, 11 13 TILIH 9, 10, 11 TGHQZ 9, 10, 11 14 TISVKH 8, 10, 14 TGSVKH 9, 10, 11 15 TKHISX 9, 10, 11 8 TKHGSX 8, 10, 11 ranctional 7,8 MILITARY BURN-IN Military burn-in is in accordance with the current revision of MIL-STD-883, Test Method 1015, Conditions A through E T st conditions are selected at AMD's option 2-191