LP3986
LP3986 Dual Micropower 150 mA Ultra Low-Dropout CMOS Voltage Regulators in
micro SMD Package
Literature Number: SNVS142T
February 2007
LP3986
Dual Micropower 150 mA Ultra Low-Dropout CMOS Voltage
Regulators in micro SMD Package
General Description
The LP3986 is a 150 mA dual low dropout regulator designed
for portable and wireless applications with demanding perfor-
mance and board space requirements.
The LP3986 is stable with a small 1 µF ±30% ceramic output
capacitor requiring smallest possible board space.
The LP3986's performance is optimized for battery powered
systems to deliver ultra low noise, extremely low dropout volt-
age and low quiescent current independent of load current.
Regulator ground current increases very slightly in dropout,
further prolonging the battery life. Optional external bypass
capacitor reduces the output noise further without slowing
down the load transient response. Fast start-up time is
achieved by utilizing a speed-up circuit that actively pre-
charges the bypass capacitor. Power supply rejection is bet-
ter than 60 dB at low frequencies and 55 dB at 10 kHz. High
power supply rejection is maintained at low input voltage lev-
els common to battery operated circuits.
The LP3986 is available in a micro SMD package. Perfor-
mance is specified for a −40°C to +125°C temperature range.
For single LDO applications, please refer to the LP3985
datasheet.
Features
■Miniature 8-I/O micro SMD package
■Stable with 1µF ceramic and high quality tantalum output
capacitors
■Fast turn-on
■Two independent regulators
■Logic controlled enable
■Over current and thermal protection
Key Specifications
■Guaranteed 150 mA output current per regulator
■1nA typical quiescent current when both regulators in
shutdown mode
■60 mV typical dropout voltage at 150 mA output current
■115 µA typical ground current
■40 µV typical output noise
■200 µs fast turn-on circuit
■−40°C to +125°C junction temperature
Applications
■CDMA cellular handsets
■GSM cellular handsets
■Portable information appliances
■Portable battery applications
Typical Application Circuit
20003401
© 2007 National Semiconductor Corporation 200034 www.national.com
LP3986 Dual Micropower 150 mA Ultra Low-Dropout CMOS Voltage Regulators in micro SMD
Package
Block Diagram
LP3986
20003402
Pin Descriptions
Name *micro SMD Function
VOUT2 A1 Output Voltage of the second LDO
EN2B1 Enable input for the second LDO
BYPASS C1 Bypass capacitor for the bandgap
GND C2 Common ground
GND C3 Common ground
EN1B3 Enable input for the first LDO
VOUT1 A3 Output Voltage of the first LDO
VIN A2 Common input for both LDOs
* Note: The pin numbering scheme for the micro SMD package was revised in April 2002 to conform to JEDEC standard. Only the pin numbers were revised. No
changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete numbering scheme had VOUT2 as pin 1, EN2 as pin 2,
BYPASS as pin 3, GND as pins 4 and 5, EN1 as pin 6, VOUT1 as pin 7, and VIN as pin 8.
Connection Diagram
20003404
Top View
8 Bump micro SMD Package
See NS Package Number TLA08
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LP3986
Ordering Information
For micro SMD Package (TL has thickness of 0.600mm)
Output Voltage
(V) Grade Package
Marking
LP3986 Supplied as 250 Units, Tape
and Reel
LP3986 Supplied as 3000 Units,
Tape and Reel
2.5 2.5 STD 27 LP3986TL-2525 LP3986TLX-2525
2.5 2.8 STD 14 LP3986TL-2528 LP3986TLX-2528
2.5 1.8 STD 30 LP3986TL-2518 LP3986TLX-2518
2.6 2.6 STD 28 LP3986TL-2626 LP3986TLX-2626
2.8 1.8 STD 25 LP3986TL-2818 LP3986TLX-2818
2.8 2.8 STD 10 LP3986TL-2828 LP3986TLX-2828
2.85 2.85 STD 11 LP3986TL-285285 LP3986TLX285285
2.9 2.9 STD 15 LP3986TL-2929 LP3986TLX-2929
3.0 2.8 STD 26 LP3986TL-3028 LP3986TLX-3028
3.0 3.0 STD 12 LP3986TL-3030 LP3986TLX-3030
3.1 3.1 STD 13 LP3986TL-3131 LP3986TLX-3131
3.1 3.3 STD 16 LP3986TL-3133 LP3986TLX-3133
3.3 3.3 STD 17 LP3986TL-3333 LP3986TLX-3333
20003403
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LP3986
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN, VEN −0.3 to 6.5V
VOUT −0.3 to (VIN+0.3V) ≤ 6.5V
Junction Temperature 150°C
Storage Temperature −65°C to +150°C
Pad Temp. (Note 3) 235°C
Maximum Power Dissipation (Note
4) 364mW
ESD Rating (Note 5)
Human Body Model
Machine Model
2kV
200V
Operating Ratings (Notes 1, 2)
VIN 2.7 to 6V
VEN 0 to (VIN+ 0.3V) ≤ 6V
Junction Temperature −40°C to +125°C
Thermal Resistance
θJA 220°C/W
Maximum Power Dissipation (Note 6) 250mW
Electrical Characteristics
Unless otherwise specified: VIN = VOUT(nom) + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF, CBYPASS = 0.01µF. Typical values and
limits appearing in standard typeface are for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature
range for operation, −40°C to +125°C. (Notes 7, 8)
Symbol Parameter Conditions Typ Limit Units
Min Max
ΔVOUT
Output Voltage
Tolerance
IOUT = 1mA −2.5
−3.0
2.5
3.0
% of VOUT
(nom)
Line Regulation Error (Note
9)
VIN = (VOUT(nom) + 0.5V) to 6.0V,
IOUT = 1 mA
0.006 0.092
0.128 %/V
Load Regulation Error (Note
10)
IOUT = 1mA to 150 mA 0.003 0.006
0.01 %/mA
Output AC Line Regulation VIN = VOUT(nom) + 1V,
IOUT = 150 mA (Figure 1)
1.5 mVP-P
PSRR Power Supply Rejection
Ratio
VIN = 3.1V,
f = 1 kHz,
IOUT = 50 mA (Figure 2)
60
dB
VIN = 3.1V,
f = 10 kHz,
IOUT = 50 mA (Figure 2)
50
IQQuiescent Current Both Regulators ON
VEN = 1.4V, IOUT = 0 mA
115 200
µA
Both Regulators ON
VEN = 1.4V, IOUT = 0 to 150 mA
220 320
One Regulator ON
VEN = 1.4V IOUT = 0 mA
75 130
One Regulator ON
VEN = 1.4V IOUT = 0 to 150 mA
130 200
VEN = 0.4V, Both Regulators OFF
(shutdown)
0.001 2
4
Dropout Voltage
(Note 11)
IOUT = 1 mA
IOUT = 150 mA
0.4
60
2
100 mV
ISC Short Circuit Current Limit Output Grounded 600 mA
IOUT(PK) Peak Output Current(Note
15)
VOUT ≥ VOUT(nom) - 5% 500 300 mA
TON Turn-On Time
(Note 12)
CBYPASS = 0.01 µF 200 µs
enOutput Noise Voltage BW = 10 Hz to 100 kHz,
COUT = 1µF
40 µVrms
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LP3986
Symbol Parameter Conditions Typ Limit Units
Min Max
ρn(1/f) Output Noise Density f = 120 Hz,
COUT = 1µF
1 µV/
IEN Maximum Input Current at EN VEN = 0.4 and VIN = 6V ±10 nA
VIL Maximum Low Level Input
Voltage at EN
VIN = 2.7 to 6V 0.4 V
VIH Minimum High Level Input
Voltage at EN
VIN = 2.7 to 6V 1.4 V
Xtalk Crosstalk Rejection
ΔILoad1 = 150 mA at 1KHz rate
ΔILoad2 = 1 mA
ΔVOUT2/ΔVOUT1 −60
dB
ΔILoad2 = 150 mA at 1KHz rate
ΔILoad1 = 1 mA
ΔVOUT2/ΔVOUT1 −60
CIN Input capacitance(Note 13)
All VOUT > = 2.5V, 1 µF
If VOUT = 1.8V,
VIN_MIN>= 2.9V
4.7 µF
COUT Capacitance(Note 13) All VOUT > = 2.5V, 1 22 µF
If VOUT = 1.8V,
VIN_MIN>= 2.9V
2.2 22 µF
ESR (Note 14) 5 500 mΩ
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: Additional information on pad temperature can be found in National Semiconductor Application Note (AN-1112).
Note 4: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula:
PD = (TJ - TA)/θJA,
Where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. The 364mW rating appearing under
Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature, 150°C, for TJ, 70°C for TA, and 220°C/W for θJA. More power
can be dissipated safely at ambient temperatures below 70°C . Less power can be dissipated safely at ambient temperatures above 70°C. The Absolute Maximum
power dissipation can be increased by 4.5mW for each degree below 70°C, and it must be derated by 4.5mW for each degree above 70°C.
Note 5: The human body model is 100pF discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into
each pin.
Note 6: Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 250mW rating
appearing under Operating Ratings results from substituting the maximum junction temperature for operation, 125°C, for TJ, 70°C for TA, and 220°C/W for θJA
into (1) above. More power can be dissipated at ambient temperatures below 70°C . Less power can be dissipated at ambient temperatures above 70°C. The
maximum power dissipation for operation can be increased by 4.5mW for each degree below 70°C, and it must be derated by 4.5mW for each degree above 70°
C.
Note 7: All limits are guaranteed. All electrical characteristics having room temperature limits are tested during production with TJ = 25°C or correlated using
Statistical Quality Control (SQC) methods. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations
and applying statistical process control.
Note 8: The target output voltage, which is labeled VOUT(nom), is the desired voltage option.
Note 9: The output voltage changes slightly with line voltage. An increase in the line voltage results in a slight increase in the output voltage and vice versa.
Note 10: The output voltage changes slightly with load current. An increase in the load current results in a slight decrease in the output voltage and vice versa.
Tested limit applies to Vout 's of 2.5V and greater.
Note 11: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value.
Note 12: Turn-on time is that between the enable input just exceeding VIH and the output voltage just reaching 95% of its nominal value.
Note 13: Range of capacitor values for which the device will remain stable. This electrical specification is guaranteed by design.
Note 14: Range of capacitor ESR values for which the device will remain stable. This electrical specification is guaranteed by design.
Note 15: IPEAK guaranteed for Vout 's of 2.5V and greater.
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LP3986
Test Signals
20003408
FIGURE 1. Line Regulation Input Test Signal
20003409
FIGURE 2. PSRR Input Test Signal
Typical Performance Characteristics Unless otherwise specified, CIN= COUT 1µF Ceramic, C BP= 0.01µ
F, VIN = VOUT + 0.5, TA= 25°C, both enable pins are tied to VIN
Power Supply Rejection Ratio (CBP = 0.001µF)
20003410
Power Supply Rejection Ratio (CBP = 0.01µF)
20003447
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LP3986
Power Supply Rejection Ratio (CBP = 0.1µF)
20003448
Output Noise Spectral Density
20003451
Line Transient Response (CBP = 0.001µF)
20003413
Line Transient Response (CBP = 0.01µF)
20003449
Load Transient & Cross Talk (VIN = VOUT + 0.2V)
20003417
Load Transient & Cross Talk (VIN = VOUT + 0.2V)
20003416
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LP3986
Start-Up Time (CBP = 0.001, 0.01, 0.1µF)
20003411
Enable Response ( VIN = 4.2V )
20003414
Enable Response (VIN = VOUT+ 0.2V)
20003415
Enable Response
20003450
Output Short Circuit Current at VIN = 6V
20003465
Output Short Circuit Current at VIN = 3.3V
20003466
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LP3986
Application Hints
EXTERNAL CAPACITORS
Like any low-dropout regulator, the LP3986 requires external
capacitors for regulator stability. The LP3986 is specifically
designed for portable applications requiring minimum board
space and smallest components. These capacitors must be
correctly selected for good performance.
INPUT CAPACITOR
An input capacitance of ≊ 1µF is required between the
LP3986 input pin and ground (the amount of the capacitance
may be increased without limit).
This capacitor must be located a distance of not more than
1cm from the input pin and returned to a clean analog ground.
Any good quality ceramic, tantalum, or film capacitor may be
used at the input.
Important: Tantalum capacitors can suffer catastrophic fail-
ures due to surge current when connected to a low-
impedance source of power (like a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must
be guaranteed by the manufacturer to have a surge current
rating sufficient for the application.
There are no requirements for the ESR on the input capacitor,
but tolerance and temperature coefficient must be considered
when selecting the capacitor to ensure the capacitance will
be ≊ 1µF over the entire operating temperature range.
OUTPUT CAPACITOR
The LP3986 is designed specifically to work with very small
ceramic output capacitors, any ceramic capacitor (tempera-
ture characteristics X7R, X5R, Z5U or Y5V) in 1 to 22 µF
range with 5mΩ to 500mΩ ESR range is suitable in the
LP3986 application circuit.
It may also be possible to use tantalum or film capacitors at
the output, but these are not as attractive for reasons of size
and cost (see next section Capacitor Characteristics).
The output capacitor must meet the requirement for minimum
amount of capacitance and also have an ESR (Equivalent
Series Resistance) value which is within a stable range.
NO-LOAD STABILITY
The LP3986 will remain stable and in regulation with no-load
(other than the internal voltage divider). This is specially im-
portant in CMOS RAM keep-alive applications.
CAPACITOR CHARACTERISTICS
The LP3986 is designed to work with ceramic capacitors on
the output to take advantage of the benefits they offer: for
capacitance values in the range of 1µF to 4.7µF range, ce-
ramic capacitors are the smallest, least expensive and have
the lowest ESR values (which makes them best for eliminat-
ing high frequency noise). The ESR of a typical 1µF ceramic
capacitor is in the range of 20 mΩ to 40 mΩ, which easily
meets the ESR requirement for stability by the LP3986.
The ceramic capacitor's capacitance can vary with tempera-
ture. The capacitor type X7R, which operates over a temper-
ature range of -55°C to +125°C, will only vary the capacitance
to within ±15%. Most large value ceramic capacitors (≊ 2.2µF)
are manufactured with Z5U or Y5V temperature characteris-
tics. Their capacitance can drop by more than 50% as the
temperature goes from 25°C to 85°C. Therefore, X7R is rec-
ommended over Z5U and Y5 in applications where the am-
bient temperature will change significantly above or below 25°
C.
Tantalum capacitors are less desirable than ceramic for use
as output capacitors because they are more expensive when
comparing equivalent capacitance and voltage ratings in the
1µF to 4.7µF range.
Another important consideration is that tantalum capacitors
have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum capac-
itor with an ESR value within the stable range, it would have
to be larger in capacitance (which means bigger and more
costly ) than a ceramic capacitor with the same ESR value. It
should also be noted that the ESR of a typical tantalum will
increase about 2:1 as the temperature goes from 25°C down
to −40°C, so some guard band must be allowed.
NOISE BYPASS CAPACITOR
Connecting a 0.01µF capacitor between the CBYPASS pin and
ground significantly reduces noise on the regulator output.
This cap is connected directly to a high impedance node in
the band gap reference circuit. Any significant loading on this
node will cause a change on the regulated output voltage. For
this reason, DC leakage current through this pin must be kept
as low as possible for best output voltage accuracy. The use
of this 0.01µF bypass capacitor is strongly recommended to
prevent overshoot on the output during start up.
The types of capacitors best suited for the noise bypass ca-
pacitor are ceramic and film. High-quality ceramic capacitors
with either NPO or COG dielectric typically have very low
leakage. Polypropolene and polycarbonate film capacitors
are available in small surface-mount packages and typically
have extremely low leakage current.
Unlike many other LDO's, addition of a noise reduction ca-
pacitor does not effect the transient response of the device.
ON/OFF INPUT OPERATION
The LP3986 is turned off by pulling the VEN pin low, and turned
on by pulling it high. If this feature is not used, the VEN pin
should be tied to VIN to keep the regulator output on at all
times. To assure proper operation, the signal source used to
drive the VEN input must be able to swing above and below
the specified turn-on/off voltage thresholds listed in the Elec-
trical Characteristics section under VIL and VIH.
FAST ON-TIME
The LP3986 outputs are turned on after Vref voltage reaches
its final value (1.23V nominal). To speed up this process, the
noise reduction capacitor at the bypass pin is charged with an
internal 70µA current source. The current source is turned off
when the bandgap voltage reaches approximately 95% of its
final value. The turn on time is determined by the time con-
stant of the bypass capccitor. The smaller the capacitor value,
the shorter the turn on time, but less noise gets reduced. As
a result, turn on time and noise reduction need to be taken
into design consideration when choosing the value of the by-
pass capacitor.
MICRO SMD MOUNTING
The micro SMD package requires specific mounting tech-
niques which are detailed in National Semiconductor Appli-
cation Note (AN-1112). Referring to the section Surface
Mount Technology (SMT) Assembly Considerations.
For best results during assembly, alignment ordinals on the
PC board may be used to facilitate placement of the micro
SMD device.
9 www.national.com
LP3986
MICRO SMD LIGHT SENSITIVITY
Exposing the micro SMD device to direct sunlight will cause
misoperation of the device. Light sources such as halogen
lamps can effect electrical performance if brought near to the
device.
The wavelengths which have most detrimental effect are reds
and infra-reds, which means that the fluorescent lighting used
inside most buildings has very little effect on performance. A
micro SMD test board was brought to within 1cm of a fluo-
rescent desk lamp and the effect on the regulated output
voltage was negligible, showing a deviation of less than 0.1%
from nominal.
www.national.com 10
LP3986
Physical Dimensions inches (millimeters) unless otherwise noted
micro SMD, 8 Bump
NS Package Number TL08CCA
The dimensions for X1, X2 and X3 are as follows:
X1 = 1.55mm
X2 = 1.55mm
X3 = 0.600mm
11 www.national.com
LP3986
Notes
LP3986 Dual Micropower 150 mA Ultra Low-Dropout CMOS Voltage Regulators in micro SMD
Package
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