KIT8020CRD8FF1217P-1
CREE Silicon Carbide MOSFET
Evaluation Kit
User’s Manual
This document is prepared as a user reference guide to install and operate CREE evaluation
hardware.
Safety Note: Cree designed evaluation hardware is meant to be an evaluation tool in a
lab setting for Cree components and to be handled and operated by highly qualified
technicians or engineers. The hardware is not designed to meet any particular safety
standards and the tool is not a production qualified assembly
1
Subject to change without notice.
www.cree.com
2KIT8020CRD8FF1217P-1_UM Rev -
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1. Introduction
This Evaluation kit is meant to demonstrate the high performance of CREE 1200V SiC
MOSFET and SiC Schottky diodes (SBD) in the standard TO-247 package. It can be
easily configured for several topologies from the basic phase-leg configuration. The
evaluation (EVL) board can be used for the following purposes:
Evaluate the SiC MOSFET performance during switching events and steady
state operation.
Easily configure different topologies with SiC MOSFET and SiC diodes
Functional testing with SiC MOSFET, for example double pulse test to
measure switching losses (Eon and Eoff).
PCB layout example for driving the Cree MOSFET.
Gate drive reference design for a TO-247 packaged Cree MOSFET.
Comparative testing between Cree devices and IGBTs.
This user manual will include information on the EVL board architecture, hardware
configuration, Cree SiC power devices and an example application when using this
board.
2. Package Contents
Item
No.
QTY P/N Description
1 1 CRD8FF1217P-1 Avago Driver version Eval board
2 4 AOS2182471 Ceramic isolation tile, 1.5mm
3 1 57908 Heat sink with mounting holes
5 2 C2M0080120D 80 mohm MOSFET
6 2 C4D20120D 20A Diode
7 1 Copper shorting strip
8 2 74270011 Ferrite Bead
9 8 91166a210 M3 washer, Zn-S, 7mm OD, 3.2mm ID
10 4 92005a129 M3x22mm, Zn-S, Board mounting Screw
11 4 94669a727 Stand offs, Al spacer, 6mm OD x 14mm
12 4 92005a120 M3x10mm, Zn-S, Device mounting screw
13 1 User Guide
3. EVL Board Overview
The EVL board’s general block diagram is shown in Figure 1. There is a phase-leg
which can include two SiC MOSFETs (Q1 and Q2) with half bridge phase-leg
configuration and two anti-parallel SiC schottky diodes (D1 and D3) with Q1 and Q2.
The gate drive block with electrical isolation is designed on the board to drive SiC
MOSFET Q1 and Q2. There are four power trace connectors (CON1, CON2, CON3
and CON5) and one 10 pin signal/supply voltage connector (CON4) on board.
3KIT8020CRD8FF1217P-1_UM Rev -
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Figure 1. General block diagram of Cree Discrete SiC EVL board
Please note that JM1 as shown in Figure 1 is open circuit. It is
necessary to short this with a wire or insert a shunt as shown in
section 6.2 to complete the circuit before operation.
CRD8FF1217P-1 includes two 2.5A gate driver integrating opto-coupler from Avago
ACPL-W346 and two 2W isolation DC/DC converters from Mornsun G1212S-2W for
both high side and low side isolated power. The 2W DC/DC converter with +12V Vcc
input generates +24V Vcc_out output voltage with 6KVDC isolation that is supplying
voltage to W346 on push-pull gate drive of the secondary side as shown in Figure 2.
In this circuit, a 5V zener in parallel with 1uF capacitor is used to generate -5V Vgs
voltage for the SiC MOSFET turn-off and turn-on Vgs voltage is equal to 24V-5V=19V.
Note that SiC MOSFET can be turned off with zero voltage, and the -5V turn-off
voltage helps with faster turn-off and lower turn-off losses and also improves dv/dt
induced self turn-on and noise immunity during transient periods with more margin for
Vgs turn-on threshold voltage. You can implement any PWM signal to drive the SiC
phase leg block, if the board is operating in synchronous mode with high side
MOSFET and low side MOSFET, the input signals must have additional dead time to
avoid shoot through.
CON1
CON3
CON2
CON5
CON4
CRD8FF1217P-1
VCC, Input PWM Signal,
Enable
SiC
Phase-leg
block
ACPL-W346
DC/DC
ACPL-W346
DC/DC
Vcc
Vcc
Vcc_out
Vcc_out
Vg_HS
Vg_LS
HS_I/P
LS_I/P
5V
5V
Vs_LS
Vs_LS
Figure 2. CRD8FF1217P-1 Block diagram with ACPL-W346
4KIT8020CRD8FF1217P-1_UM Rev -
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The EVL board size is 124mmx120mmx40mm (not including heatsink). Different
types of heatsinks can be assembled depending on your cooling requirements. Figure
3 shows the board attached with the heatsink provided in the kit. However, the users
can use any type of heatsink that can work with the standard TO-247 package.
Figure 3. Cree EVL board assembly (see Appendix for assembly instructions).
4. Configurations
The EVL board can be flexible to implement difference topologies when using the
different configurations of SiC MOSFETs and SiC diodes. It is possible to test several
topologies with this board: synchronous Buck, non-synchronous Buck (or high-side
Buck), synchronous Boost, non-synchronous Boost, half phase-leg bridge converter,
H bridge converter (2x EVL boards) and bi-directional buck-boost converters. Table 1
summarizes the possible topologies that can be implemented using this EVL board.
For the phase-leg configuration, it can either use discrete anti-parallel SiC SBD or
body diode of SiC MOSFET, thus body diode of SiC MOSFET can be evaluated
without anti-parallel diode with option one in the below table.
With double EVL boards, H-bridge converter and bi-directional DC/DC converter can
be configured. For H-bridge, with different control architecture, the phase shift full
bridge, resonant LLC ZVS converter and single phase DC/ AC converter can all be
achieved. For bi-directional DC/DC converter, it can achieve either Buck from port 1 to
port 2 or Boost from port2 to port 1. Furthermore, with three EVL boards, it can even
be set up as a three-phase DC/AC inverter for some motor drive or inverter
applications.
Table. 1 The EVL board topology configuration
Option One:
Syn. Buck converter or
Phase-leg bridge
topology without
anti-parallel diodes
Q2
Q1
CON1
CON3
CON2
CON5
HVDC
L
Cout RL
Cin
Step down voltage or
phase leg topology w/o
anti-parallel diodes
SiC Body diode used
Connect inductor L with
CON3 as output
CON1: INPUT
CON3: OUTPUT
5KIT8020CRD8FF1217P-1_UM Rev -
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CON2, CON5: GND
Option Two:
Phase-leg bridge
topology with
anti-parallel SiC SBD
Q2
Q1
CON1
CON3
CON2
CON5
D3
D1
Phase-leg, switching
with external
anti-parallel diode
SiC SBD used
CON1, CON3:
Input/output depends on
which topology apply to
board
CON2, CON5: GND
Option Three:
Non-syn Buck converter
Q2
D1
CON1
CON3
CON2
CON5
HVDC
L
Cout RL
Cin
Step down voltage
Connect inductor L with
CON3 as output
CON1: INPUT
CON3: OUTPUT
CON2, CON5: GND
Option Four:
Syn. Boost converter
L
Cin
RL
Cout
HVDC
Q2
Q1
CON1
CON3
CON2
CON5
Step up voltage
Connect inductor L with
CON3 as input
CON1: OUTPUT
CON3: INPUT
CON2, CON5: GND
Option Five:
Non-syn Boost
converter
L
Cin
RL
Cout
HVDC
D3
Q1
CON1
CON3
CON2
CON5
Step up voltage
Connect inductor L with
CON3 as input
CON1: OUTPUT
CON3: INPUT
CON2, CcON5: GND
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Option Six:
Diode bridge
Bridge diode with SiC
SBD
CON1: OUTPUT
(Positive)
CON3: INPUT
CON2, CON5: OUTPUT
(Negative)
Option Seven:
H bridge topology
configuration using two
EVL boards
Q2
Q1
CON1
CON3
CON2
CON5
HVDC
L
Cout RL
Cin
CON1
CON3
CON2
CON5
Q2
Q1
EVL1
EVL2
Full bridge converter
with Phase shift or
resonant
single phase DC/AC
inverter
Option Eight:
Bi-directional DC/DC
converter
Q2
Q1
CON1
CON3
CON2
CON5
L
C1
CON1
CON3
CON2
CON5
Q2
Q1
EVL1 EVL2
C2
Port1 Port2
Port 1 is input and port 2
is output with Buck
converter, Q2 of EVL2 is
constantly turn-on, and
Q1 of EVL2 is constantly
turn-off
Port 1 is output and port
2 is input with Boost
converter, Q2 of EVL1 is
constantly turn-on and
Q1 of EVL2 is constantly
turn-off
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5. Hardware Description
Figure 4. EVL board showing key connectors and components.
The above figures give top view of the EVL board. The picture highlights key test
points and connectors on the boards.
5.1 Test points
To make testing more effective and easy, the BNC connectors are added on the
board to measure both Vgs and Vds waveforms for SiC MOSFET Q1 and Q2. A
current test point with two unpopulated through-hole contacts is available to measure
the drain current through the low side switch. A jumper wire (not provided in the kit)
with a short loop (JM1) can be inserted to the test point and measure current using
current probe. Another option is to use accurate coaxial shunt resistors, (not provided
in the kit) from T&M Research (www.tandmresearch.com) to make the measurement.
This option can minimize the stray inductance on the switching loops and achieve
accurate switching loss measurement. Lastly, one can also simply short JM1 with the
small shorting strips provided in the kit, if it’s not necessary to measure the current
waveform. Also, some test points are added between gate resistors for measuring the
voltage across the gate resistors. Thus it can estimate the gate current Ig to the SiC
MOSFET.
5.2 Connectors
For the connectors, CON1, CON2, CON3 and CON5 are power trace connectors, and
their definitions are depending on the different topology as described in table 1. CON4
CON3
CON5
CON2
CON1
CON4
G1212S-2W G1212S-2W
W346
8KIT8020CRD8FF1217P-1_UM Rev -
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is for the signal/logic inputs and supply voltage for ICs. The definition of CON4 for
each pin is shown in table 2.
Table. 2 Pin definitions for connector CON4
Connector CON4 Pin CRD8FF1217P-1
Pin1 N/A
Pin2 N/A
Pin3 N/A
Pin4 N/A
Pin5 VCC: +12Vdc
Pin6 VCC_RTN: GND for +12Vdc
Pin7 Input_HS: signal input for Q2
Pin8 Input_HS_RTN: signal ground for Q2
Pin9 Input_LS: signal input for Q1
Pin10 Input_LS_RTN: signal ground for Q1
5.3 Board design
SiC device is a fast switching device, and it is important to maximize SiC’s high
performance and minimize ringing with fast switching. The EVL board introduces
some design approaches to minimize the ringing on the board:
The gate drive and logic signal are put on top of the PCB board, while the main
power trace and switching devices are put on the bottom layer. There is no
crossover or overlap between gate signal and switching power trace, which
can minimize high dv/dt and di/dt noise influence from the switching node to
gate signal.
Four de-coupling film capacitors with value 10nF, 10nF, 0.1uF and 5uFare
placed close to the SiC devices, and it can reduce high frequency switching
loop and bypass noise within switching loop.
The layout of gate drive circuitry is designed with symmetric trace distance,
which can introduce balance impendence on the gate drive. Also, the gate
drive is placed as close as possible to the SiC MOSFETs.
The power trace layout is optimized to reduce the switching loops.
6. CREE Devices
SiC devices including SiC MOSFET and SiC Schottky diodes are recognized as next
generation wide bandgap devices. It can provide fast switching with less loss
compared to conventional Si devices. Cree is the world’s leading manufacturer of
silicon-carbide Schottky diodes and MOSFETs for efficient power conversion. Two
sample 20A, 1200V rated SiC MOSFET devices and two 20A, 1200V rated Schottky
diodes are provided in the kit. However, other samples ranging from 5A to 50A can be
ordered online ( ).
9KIT8020CRD8FF1217P-1_UM Rev -
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7. Example Application and Measurements
7.1 Board Setup
In order to demonstrate the EVL with SiC devices, a synchronous phase-leg Buck
converter configuration is used as an example to evaluate the performance of the SiC
EVL board. This is option one configuration on table 1. The table below gives the
electrical parameters. Please note the switching frequency is at 40KHZ in this case
due to the design limitation of the available inductor, but it does not mean the
switching frequency is limited to 40KHZ. Because of low switching losses of SiC
MOSFET, the switching frequency can increase to higher without sacrificing much
switching losses when using SiC MOSFET. The purpose of 40KHZ setting is
competing with 1200V Si IGBT for inverter application with this phase-leg
configuration, which frequency is normally ranged from 15KHZ to 20KHZ.
In the testing, two 25mohm SiC MOSFETs are assembled on the PCB board with
heatsink for both high side Q2 and low side Q1. The figure gives the test setup with
EVL boards. The signal generators are used to generate high side and low side PWM
signals with Input_HS and Input_LS. Note that the dead time period must be applied
to the input signal between Input_HS and Input_LS.
Table. 3 Electrical parameters
Items Parameters
Input Voltage 600Vdc
Output Voltage 300Vdc
Output RMS Current 30A
Output Power 9KW
Peak MOS current 40A
Switching Frequency 40KHZ
Duty Cycle 50%
Dead time ~450ns
Inductor 400uH
Output Capacitors 300uF
Cree Discrete SiC EVL Board
Gate drive
Q2
Q1
CON1
CON3
CON2
CON5
600V
DC source
400uH
300uF
RL
Cin
Input_LS_RTN
VCC
VCC_RTN
Input_HS
Input_HS_RTN
Input_LS
4.10
4.9
4.8
4.7
4.6
4.5
CON4
PWM signal
generator
+12V
DC supply
CRD8FF1217P-1
Figure 5. Test setup for the EVL boards with CRD8FF1217P-1
10 KIT8020CRD8FF1217P-1_UM Rev -
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Figure 6. Bench test setup of the EVL boards
7.2 Measurements
To maximize the accuracy of the measurements when using the EVL board, some
suggestions are listed below:
Use a highly accurate 0.0131ohm shunt (not provided in the kit) to measure
the low side current waveform as shown below in Figure 7. This can help to
shorten the current sense loop.
Figure 7. Low side current measurement
A BNC probe is connected to measure low-side Vgs waveform, a x100 HV
probe is used to measure low side Vds waveform, and a differential probe is
used to measure high-side Vgs waveform. All probes must be placed as close
as possible to reduce incorrect ringing due to probe placement.
Place the power inductor as close as possible to connect at CON3 to reduce
the switching node loop area, and a 1uF 1200V film capacitors is connected
between the output of inductor and ground connector CON5.
A 12W AC fan is used to cool the heatsink and inductor when measuring
waveforms and taking thermal measurements.
A RC snubber is added on the drain to source to damp high dv/dt ringing on
the switching node and slow the high dv/dt.
A capacitance (1nF) is added between gate to source terminal to shunt the
miller current from drain to gate. This external capacitor will introduce low
impedance path for Cdv/dt from miller capacitance effect and reduce the
ringing on the gate pins.
11 KIT8020CRD8FF1217P-1_UM Rev -
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Use of a ferrite bead (FB) on the gate pin of TO-247 MOSFETs will introduce
high impedance on the gate path for MHz high frequency and reduce the Vgs
ringing.
Reduce the stray capacitance of inductor with single layer structure.
TO-247
TO-247
G
D
S
D
G
S
5ohm
5ohm
1N5819HW
FB
1nF
12ohm
220pF
12ohm
220pF
5ohm
5ohm
FB
1nF
1N5819HW
Figure 8. Gate drive and RC snubber configuration
7.3 Test data
The switching waveforms are shown in the below figures. In the operation of the
synchronous Buck converter, the low-side body diode conducts before low-side
MOSFET is turned on, thus this low-side MOSFET operates in Zero Voltage
Switching (ZVS) mode and high-side MOSFET operates in hard-switching mode.
However, high dv/dt during fast transient of high-side MOSFET will affect the
operational behavior of the low-side MOSFET, and the charge stored in miller
capacitance will be transferred via its gate loop, inducing some spurious gate voltage
in this topology. The above methods mentioned in section 6.2 will help to damp this
noise and reduce the ringing on the gate and drain to source. Note that the incorrect
test method itself may also introduce some noises from oscilloscope measurement,
but it is sometimes not a true representation of the actual transient events on the
switching devices.
12 KIT8020CRD8FF1217P-1_UM Rev -
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Figure 9. Vgs, Id and Vds waveforms at 9KW loading
(Ch1: low-side Vds yellow 200v/div); (Ch2: low-side Id blue 100mv/0.0131ohm/div);
(Ch3: low-side Vgs pink 10v/div); (Ch4: high-side Vgs green 10v/div)
13 KIT8020CRD8FF1217P-1_UM Rev -
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Figure 10. Vgs, Inductor current IL and Vds waveforms at 9KW loading
(Ch1: low-side Vds yellow 200v/div); (Ch2: inductor current IL 10A/div);
(Ch3: low-side Vgs pink 10v/div); (Ch4: high-side Vgs green 10v/div)
The EVL board’s maximum efficiency in this configuration is around 98.9% at 4KW
half load using the Yokogawa WT3000 to measure it. It includes losses from the
inductor, switching devices, and capacitors. Considering the high switching frequency
(40kHz) and high duty cycle (50%), the efficiency is high compared to conventional Si
IGBT solutions.
Figure 11. Efficiency data for this EVL board
Figure 12 shows the thermal performance for this EVL board at full load 9KW after 30
minutes of continuous operation. The test condition is at room temperature with open
frame and 12W fan cooling the heatsink and inductor. It demonstrates high
performance of SiC MOSFET with low temperature, low losses and high switching
frequency.
Figure 12. Thermal imaging of the EVL board while under test.
14 KIT8020CRD8FF1217P-1_UM Rev -
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8. Reference
1. C2M0025120D datasheet, Cree Inc
2. C4D20120D datasheet, Cree Inc
3. ‘Performance Evaluations of Hard-Switching Interleaved DC/DC Boost Converter with New
Generation Silicon Carbide MOSFETs’ Available in Cree website:
http://www.cree.com/Power/Document-Library
4. ‘Design Considerations for Designing with Cree SiC Modules Part 1. Understanding the
Effects of Parasitic Inductance’ Available in Cree website:
http://www.cree.com/Power/Document-Library
5. ‘Design Considerations for Designing with Cree SiC Modules Part 2. Understanding the
Effects of Parasitic Inductance’ Available in Cree website:
http://www.cree.com/Power/Document-Library
15 KIT8020CRD8FF1217P-1_UM Rev -
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9. Appendix
Heatsink assembly instructions:
1. Apply thermal grease to the AlN thermal isolator and place it on the heatsink to
align with the mounting hole.
2. Apply thermal grease to the back side of the device package and align
mounting hole to the thermal isolator and heatsink.
3. Use the M3x10mm screw to secure (0.8 Nm) the device to the heatsink.
4. Attach the EVL board to the heatsink using the 4x standoffs, 4x M3x21mm
mounting screws and 4x washers (1Nm).
5. Solder the MOSFET and Diode devices to the EVL board.
(Reference table for package contents on page 1)
16 KIT8020CRD8FF1217P-1_UM Rev -
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ZD4
24V
SOD-123
R13
5R1 R0603
R14
5R1 R0603
ZD5
5V1
SOD-123
R15
5R1 R0603
R16
5R1 R0603
ZD1
24V
SOD-123
ZD2
5V1
SOD-123
ZD7
25V
SOD-123
TP6
Vd_LS
ZD6
5V1
SOD-123
ZD3
5V1
SOD-123
ZD8
25V SOD-123
R24
1k
R0603
Title
Size Document Number Rev
Date: Sheet of
SiC MOSFET EVL Board (CRD 8FF1217P-1) 1v0
Main board - Avago
A4
1 1
Sunday, September 21, 2014
R11
240
R0603
R1
5R1
R1206
R12
1k
R1206
R10
130
R0603
Q1
SiC MOSFET
TO-247
R7
5R1
R1206
TP7
V_Ig_HS1
C3
0.1uF
C0603
C9
33pF
C0603
JM1
Id
C7
2.2uF
C0603
R4
130
R0603
R8
10k
R1206
C6
1uF C1206
TP2
V_Ig_LS1
D3
C4D20120D
TO-247
1
3
2
R9
1k
R1206
R3
10k
R1206
C11
4.7uF
C1206
C4
1nF
C1206
TP9
GND
TP8
V_Ig_HS2
U2
ACPL-W346
Anode
1
NC
2
Cathode
3Gnd 4
Vout 5
Vcc 6
C8
0.1uF
C0603
D4
1N5819HW
SOD-123
C16
1uF
C0603
TP3
V_Ig_LS2
R6
5R1
R1206
C15
2.2uF
C0603
R5
240
R0603
Q2
SiC MOSFET
TO-247
Input_LS_RTN
Input_LS
D1
C4D20120D
TO-247
1
3
2
C1
1nF
C1206
D2
1N5819HW
SOD-123
CON3
MID-PT
1
CON1
HVDC
1
C2
1uF C1206
CON2
GND
1
R2
5R1
R1206
C12
4.7uF
C1206
C10
0.1uF
C0603
C13
33pF
C0603
U1
ACPL-W346
Anode
1
NC
2
Cathode
3Gnd 4
Vout 5
Vcc 6
C14
0.1uF
C0603
VCC_RTN
VCC
Input_LS_RTN
Input_LS
VCC_RTN
VCC
Input_HS_RTN
Input_HS
Input_HS_RTN
Input_HS
GND
+22V_VCC_LS
VCC
-VEE_LS
VCC_RTN
+22V_VCC_HS
-VEE_LS
-VEE_mid_HS
-VEE_mid_HS
Circuit in
this area,
the ground
is
isolated.
TP1 0
HV_VCC
R17
1M
R1206
R18
1M
R1206
R20
1M
R1206
R21
1M
R1206
GND
CON5
GND
1
C19
0.1uF
C17
10nF
C18
10nF
R19
1M
R1206
R22
1M
R1206
C20
5uF
U4
G1212S-2W
+Vin
1
-Vin
2
+Vout 7
COM 6
-Vout 5
C21
1uF
C0603
U3
G1212S-2W
+Vin
1
-Vin
2
+Vout 7
COM 6
-Vout 5
C5
1uF
C0603
C22
1uF
C0603
TP1
Vg_LS
CON4
Gate Driver input
1
2
3
4
5
6
7
8
9
10
VS_LS
VS_LS
L1
CHOKE CM
1
2
4
3
TP5
Vg_HS
VS_HS
VS_HS
R23
1k
R0603
R25
10R
R4524
C23
220pF
C1210
TP4
Vd_HS
R26
10R
R4524
C24
220pF
C1210
BOM Ver.: A
PCB Ver.: A
BD1
BEAD
Schematic of CRD 8FF1217P-1
17 KIT8020CRD8FF1217P-1_UM Rev -
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Component list of CRD 8FF1217P-1
Part
Ref.
Value Part number Brand Description Type
PCB
Footprint
1 BD1 Bead 74270011 Wurth ferrite bead THR
2 C1 1nF
Ceramic, C0G, 10% SMD C1206
3 C2 1uF
Ceramic, X7R, 10% SMD C1206
4 C3 0.1uF
Ceramic, X7R, 10% SMD C0603
5 C4 1nF
Ceramic, C0G, 10% SMD C1206
6 C5 1uF
Ceramic, C0G, 10% SMD C0603
7 C6 1uF
Ceramic, X7R, 10% SMD C1206
8 C7 2.2uF
Ceramic, X7R, 10% SMD C0603
9 C8 0.1uF
Ceramic, X7R, 10% SMD C0603
10 C9 33pF
Ceramic, C0G, 10% SMD C0603
11 C10 0.1uF
Ceramic, X7R, 10% SMD C0603
12 C11 4.7uF
Ceramic, X7R, 10% SMD C1206
13 C12 4.7uF
Ceramic, X7R, 10% SMD C1206
14 C13 33pF
Ceramic, C0G, 10% SMD C0603
15 C14 0.1uF
Ceramic, X7R, 10% SMD C0603
16 C15 2.2uF
Ceramic, X7R, 10% SMD C0603
17 C16 1uF
Ceramic, X7R, 10% SMD C0603
18 C17 10nF B32653A1103K EPCOS CAP FILM 10nF 1.6KVDC RADIAL, PP THR
19 C18 10nF B32653A1103K EPCOS CAP FILM 10nF 1.6KVDC RADIAL, PP THR
20 C19 0.1uF B32654A1104K EPCOS CAP FILM 0.1UF 1.6KVDC RADIAL, PP
THR
21 C20 5uF B32774D1505K EPCOS CAP FILM 5UF 1.3KVDC RADIAL, PP THR
22 C21 1uF
Ceramic, X7R, 10% SMD C0603
23 C22 1uF
Ceramic, X7R, 10% SMD C0603
24 C23 220pF C1210C221JGGACTU Kemet CAP CER 220PF 2KV 5% NP0 1210 SMD C1210
25 C24 220pF C1210C221JGGACTU Kemet CAP CER 220PF 2KV 5% NP0 1210 SMD C1210
26 CON1 HVDC 7808 Skystone female, M5, 30A, 6P MECH
27 CON2 GND 7808 Skystone female, M5, 30A, 6P MECH
28 CON3 MID-PT 7808 Skystone female, M5, 30A, 6P MECH
29 CON4 Gate Driver input 22-27-2101 Molex 10pin, 2.54mm, male MECH
30 CON5 GND 7808 Skystone female, M5, 30A, 6P MECH
31 D1 C4D20120D C4D20120D CREE 1200V, 20A THR TO-247
32 D2 1N5819HW 1N5819HW-7-F Diodes DIODE SCHOTTKY 40V 1A SOD123 SMD SOD-123
33 D3 C4D20120D C4D20120D CREE 1200V, 20A THR TO-247
34 D4 1N5819HW 1N5819HW-7-F Diodes DIODE SCHOTTKY 40V 1A SOD123 SMD SOD-123
35 JM1 Id
dim. 1.75mm jumper wire x2 for Id
connect to GND
MECH
36 L1 CM CHOKE ACM4520-142-2P-T000 TDK CM choke SMD
37 Q1 SiC MOSFET C2M0025120D CREE 25-mΩ, 1200-V, SiC MOSFET THR TO-247
38 Q2 SiC MOSFET C2M0025120D CREE 25-mΩ, 1200-V, SiC MOSFET THR TO-247
39 R1 5R1
Res, 1% SMD R1206
18 KIT8020CRD8FF1217P-1_UM Rev -
User Manual
40 R2 5R1
Res, 1% SMD R1206
41 R3 10k
Res, 1% SMD R1206
42 R4 130
Res, 1% SMD R0603
43 R5 240
Res, 1% SMD R0603
44 R6 5R1
Res, 1% SMD R1206
45 R7 5R1
Res, 1% SMD R1206
46 R8 10k
Res, 1% SMD R1206
47 R9 1k
Res, 1% SMD R1206
48 R10 130
Res, 1% SMD R0603
49 R11 240
Res, 1% SMD R0603
50 R12 1k
Res, 1% SMD R1206
51 R13 5R1
Res, 1% SMD R0603
52 R14 5R1
Res, 1% SMD R0603
53 R15 5R1
Res, 1% SMD R0603
54 R16 5R1
Res, 1% SMD R0603
55 R17 1M
Res, 1% SMD R1206
56 R18 1M
Res, 1% SMD R1206
57 R19 1M
Res, 1% SMD R1206
58 R20 1M
Res, 1% SMD R1206
59 R21 1M
Res, 1% SMD R1206
60 R22 1M
Res, 1% SMD R1206
61 R23 1k
Res, 1% SMD R0603
62 R24 1k
Res, 1% SMD R0603
63 R25 10R S4-10RF1 Riedon RES 10 OHM 2W 1% WW SMD SMD R4524
64 R26 10R S4-10RF1 Riedon RES 10 OHM 2W 1% WW SMD SMD R4524
65 TP1 Vg_LS 546-4027 RS BNC socket, female MECH
66 TP2 V_Ig_LS1 5020 keystone round, 1pin, test point MECH
67 TP3 V_Ig_LS2 5020 keystone round, 1pin, test point MECH
68 TP4 Vd_HS 546-4027 RS BNC socket, female MECH
69 TP5 Vg_HS 546-4027 RS BNC socket, female MECH
70 TP6 Vd_LS 546-4027 RS BNC socket, female MECH
71 TP7 V_Ig_HS1 5020 keystone round, 1pin, test point MECH
72 TP8 V_Ig_HS2 5020 keystone round, 1pin, test point MECH
73 TP9 GND 5020 keystone round, 1pin, test point MECH
74 TP10 HV_VCC 5020 keystone round, 1pin, test point MECH
75 U1 ACPL-W346 ACPL-W346-060E Avago
SMD
76 U2 ACPL-W346 ACPL-W346-060E Avago
SMD
77 U3 G1212S-2W G1212S-2W Mornsun
THR
78 U4 G1212S-2W G1212S-2W Mornsun
THR
79 ZD1 24V
24V, 350mW, 1% SMD SOD-123
80 ZD2 5.1V
5.1V, 350mW, 1% SMD SOD-123
81 ZD3 5.1V
5.1V, 350mW, 1% SMD SOD-123
82 ZD4 24V
24V, 350mW, 1% SMD SOD-123
19 KIT8020CRD8FF1217P-1_UM Rev -
User Manual
83 ZD5 5.1V
5.1V, 350mW, 1% SMD SOD-123
84 ZD6 5.1V
5.1V, 350mW, 1% SMD SOD-123
85 ZD7 25V
25V, 350mW, 2% SMD SOD-123
86 ZD8 25V
25V, 350mW, 2% SMD SOD-123