PWM
CONTROLLER
+12V
ISOLATION
AND
FEEDBACK
+100V
SECONDARY
SIDE
CIRCUIT
HI
CONTROL
DRIVE
LO
DRIVE
HI
VDD
UCC27200A/1A
VSS
LI
HB
HO
HS
LO
UCC27200A, UCC27201A
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SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
120-V Boot, 3-A Peak, High Frequency, High-Side/Low-Side Driver
Check for Samples: UCC27200A,UCC27201A
1FEATURES CONTENTS
2•Specified from -40 °C to 140 °C
•Drives Two N-Channel MOSFETs in Device Ratings 2
High-Side/Low-Side Configuration Electrical Characteristics 4
•Maximum Boot Voltage 120 V Device Information 11
•Maximum VDD Voltage 20 V Application Information 14
•On-Chip 0.65-V VF, 0.6-ΩRD Bootstrap Diode
•Greater than 1 MHz of Operation Additional References 22
•20-ns Propagation Delay Times
•3-A Sink, 3-A Source Output Currents DESCRIPTION
The UCC27200A/1A family of high frequency
•8-ns Rise/7-ns Fall Time with 1000-pF Load N-Channel MOSFET drivers include a 120-V
•1-ns Delay Matching bootstrap diode and high-side/low-side driver with
•Under Voltage Lockout for High-Side and independent inputs for maximum control flexibility.
Low-Side Driver This allows for N-Channel MOSFET control in
half-bridge, full-bridge, two-switch forward and active
•Offered in 8-Pin SOIC (D), PowerPad™SOIC-8 clamp forward converters. The low-side and the
(DDA), SON-8 (DRM), SON-9 (DRC) and SON-10 high-side gate drivers are independently controlled
(DPR) Packages and matched to 1-ns between the turn-on and turn-off
of each other. The UCC27200A/1A are based on the
APPLICATIONS popular UCC27200/1 drivers, but offer some
•Power Supplies for Telecom, Datacom, and enhancements. In order to improve performance in
noisy power supply environments the UCC27200A/1A
Merchant Markets has an enhanced ESD input structure and also has
•Half-Bridge Applications and Full-Bridge the ability to withstand a maximum of -18 V on its HS
Converters pin.
•Isolated Bus Architecture
•Two-Switch Forward Converters
•Active-Clamp Forward Converters
•High Voltage Synchronous-Buck Converters
•Class-D Audio Amplifiers
Simplified Application Diagram
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPad is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright ©2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
UCC27200A, UCC27201A
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONT.)
An on-chip bootstrap diode eliminates the external discrete diodes. Under-voltage lockout is provided for both the
high-side and the low-side drivers forcing the outputs low if the drive voltage is below the specified threshold.
Two versions of the UCC27200A are offered. The UCC27200A has high noise immune CMOS input thresholds
while the UCC27201A has TTL compatible thresholds.
Both devices are offered in an 8-pin SOIC(D), PowerPad™SOIC-8(DDA), SON-8(DRM) package, a 9-pin
SON-9(DRC) package and a 10-pin SON-10(DPR) package.
ORDERING INFORMATION
PACKAGED DEVICES(1)
TEMPERATURE INPUT PowerPad™SON-8 (DRM)(3) SON-9 (DRC)(4) SON-10 (DPR) (5)
SOIC-8 (D)(2)
RANGE TA= TJCOMPATIBILITY SOIC-8 (DDA)(2)
CMOS UCC27200AD UCC27200ADDA UCC27200ADRM UCC27200ADRC N/A
-40°C to +140°CTTL UCC27201AD UCC27201ADDA UCC27201ADRM UCC27201ADRC UCC27201ADPR
(1) These products are packaged in Lead (Pb)-Free and green lead finish of PdNiAu which is compatible with MSL level 1 at 255-260°C
peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.
(2) D (SOIC-8) and DDA (Power Pad™SOIC-8) packages are available taped and reeled. Add R suffix to device type (e.g.
UCC27200ADR) to order quantities of 2,500 devices per reel.
(3) DRM (SON-8) package comes either in a small reel of 250 pieces as part number UCC27200ADRMT, or larger reels of 3000 pieces as
part number UCC27200A DRMR.
(4) DRC(SON-9) package comes either in a small reel of 250 pieces as part number UCC27200ADRCT, or large reels pieces as part
number UCC27200ADRCR.
(5) DPR(SON-10) package comes either in a small reel of 250 pieces as part number UCC27201ADPRT, or large reels pieces as part
number UCC27201ADPRR.
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SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
DEVICE RATINGS
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature, unless noted, all voltages are with respect to VSS (1)
PARAMETER VALUE UNIT
Supply voltage range, (2) VDD -0.3 to 20
Input voltages on LI and HI, VLI, VHI -0.3 to 20
DC -0.3 to VDD + 0.3,
Output voltage on LO, VLO Repetitive pulse <100 ns(3) -2 to VDD + 0.3
DC VHS –0.3 to VHB + 0.3
Output voltage on HO, VHO V
Repetitive pulse <100 ns(3) VHS - 2 to VHB + 0.3, (VHB - VHS <20)
DC -1 to 120
Voltage on HS, VHS Repetitive pulse <100 ns(3) -18 to 120
Voltage on HB, VHB -0.3 to 120
Voltage On HB-HS -0.3 to 20
Operating virtual junction temperature range, TJ-40 to +150
Storage temperature, TSTG -65 to +150 °C
Lead temperature (soldering, 10 sec.) +300
Power dissipation at TA= 25°C (D package) (4) 1.3
Power dissipation at TA= 25°C (DDA package) (4) 2.7 W
Power dissipation at TA= 25°C (DRM package) (4) 3.3
Power dissipation at TA= 25°C (DRC package) (4) 2.86
Human body model 2000 V
CDM 1000
(1) Stresses beyond those listed under “absolute maximum ratings”may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions”is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to Vss. Currents are positive into, negative out of the specified terminal.
(3) Values are verified by characterization and are not production tested.
(4) This data was taken using the JEDEC proposed high-K test PCB. See the THERMAL CHARACTERISTICS section for details.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
VDD Supply voltage range 8 12 17
VHS Voltage on HS -1 105 V
Voltage on HS, (repetitive pulse <100 ns) -15 110
VHB VHS + 8, VHS + 17,
Voltage on HB VDD –1 115
Voltage slew rate on HS 50 V / ns
TJOperating junction temperature range -40 +140 °C
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UCC27200A, UCC27201A
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
www.ti.com
THERMAL INFORMATION UCC27200A UCC27200A UCC27200A
/UCC27201A /UCC27201A /UCC27201A
THERMAL METRIC(1) (2) UNITS
DRM DRC DPR
8 PINS 9 PINS 10 PINS
θJA Junction-to-ambient thermal resistance 36.2 43.7 34.8
θJCtop Junction-to-case (top) thermal resistance 41.6 49.9 32.1
θJB Junction-to-board thermal resistance 13.2 19.1 11.9 °C/W
ψJT Junction-to-top characterization parameter 0.6 0.6 0.2
ψJB Junction-to-board characterization parameter 13.4 19.3 12.2
θJCbot Junction-to-case (bottom) thermal resistance 3.1 3.8 1.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
THERMAL INFORMATION UCC27200A UCC27200A
/UCC27201A /UCC27201A
THERMAL METRIC(1)(2) UNITS
D DDA
8 PINS 8 PINS
θJA Junction-to-ambient thermal resistance 106.5 40.5
θJCtop Junction-to-case (top) thermal resistance 52.9 49.0
θJB Junction-to-board thermal resistance 46.6 10.2 °C/W
ψJT Junction-to-top characterization parameter 9.6 3.1
ψJB Junction-to-board characterization parameter 46.1 9.7
θJCbot Junction-to-case (bottom) thermal resistance n/a 1.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
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SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA= TJ= -40°C to
+140°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply Currents
IDD VDD quiescent current VLI = VHI = 0 0.4 0.8
UCC27200A f = 500 kHz, CLOAD = 0 2.5 4
IDDO VDD operating current UCC27201A f = 500 kHz, CLOAD = 0 3.8 5.5 mA
IHB Boot voltage quiescent current VLI = VHI = 0 V 0.4 0.8
IHBO Boot voltage operating current f = 500 kHz, CLOAD = 0 2.5 4
IHBS HB to VSS quiescent current VHS = VHB = 110 V 0.0005 1 uA
IHBSO HB to VSS operating current f = 500 kHz, CLOAD = 0 0.1 mA
Input
VHIT Input rising threshold 5.8 8
VLIT Input falling threshold UCC27200A 3 5.4
VIHYS Input voltage hysteresis 0.4 V
VHIT Input voltage threshold 1.7 2.5
VLIT Input voltage threshold UCC27201A 0.8 1.6
VIHYS Input voltage Hysteresis 100 mV
RIN Input pulldown resistance 100 200 350 kΩ
Undervoltage Protection (UVLO)
VDD rising threshold 6.2 7.1 7.8
VDD threshold hysteresis 0.5 V
VHB rising threshold 5.8 6.7 7.2
VHB threshold hysteresis 0.4
Bootstrap Diode
VFLow-current forward voltage I VDD - HB = 100 μA 0.65 0.85 V
VFI High-current forward voltage I VDD - HB = 100 mA 0.85 1.1
IVDD - HB = 100 mA and 80
RDDynamic resistance, ΔVF/ΔI 0.6 1.0 Ω
mA
LO Gate Driver
VLOL Low level output voltage ILO = 100 mA 0.18 0.4
ILO = -100 mA, VLOH = VDD -
TJ= -40 to 125°C 0.25 0.4
VLO V
VLOH High level output voltage ILO = -100 mA, VLOH = VDD -
TJ= -40 to 140°C 0.25 0.42
VLO
Peak pull-up current VLO = 0 V 3 A
Peak pull-down current VLO = 12 V 3
HO Gate Driver
VHOL Low level output voltage IHO = 100 mA 0.18 0.4
IHO = -100 mA, VHOH = VHB-
TJ= -40 to 125°C 0.25 0.4
VHO V
VHOH High level output voltage IHO = -100 mA, VHOH = VHB-
TJ= -40 to 140°C 0.25 0.42
VHO
Peak pull-up current VHO = 0 V 3 A
Peak pull-down current VHO = 12 V 3
Propagation Delays
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SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA= TJ= -40°C to
+140°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ= -40 to 125°C CLOAD = 0 20 45
tDLFF VLI falling to VLO falling TJ= -40 to 140°C CLOAD = 0 20 50
TJ= -40 to 125°C CLOAD = 0 20 45
tDHFF VHI falling to VHO falling TJ= -40 to 140°C CLOAD = 0 20 50 ns
TJ= -40 to 125°C CLOAD = 0 20 45
tDLRR VLI rising to VLO rising TJ= -40 to 140°C CLOAD = 0 20 50
TJ= -40 to 125°C CLOAD = 0 20 45
tDHRR VHI rising to VHO rising TJ= -40 to 140°C CLOAD = 0 20 50
Delay Matching
tMON LI ON, HI OFF 1 7 ns
tMOFF LI OFF, HI ON 1 7
Output Rise and Fall Time
tRLO, HO CLOAD = 1000 pF 8 ns
tFLO, HO CLOAD = 1000 pF 7
tRLO, HO (3 V to 9 V) CLOAD = 0.1 μF 0.35 0.6 us
tFLO, HO (3 V to 9 V) CLOAD = 0.1 μF 0.3 0.6
Miscellaneous
Minimum input pulse width that changes the output 50 ns
Bootstrap diode turn-off time IF= 20 mA, IREV = 0.5 A(1) (2) 20
(1) Typical values for TA= 25°C
(2) IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode.
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1
2
3
4
8
7
6
5
VDD
HB
HO
HS
LO
VSS
LI
HI
SOIC-8(D)
TOP VIEW
1
2
3
4
8
7
6
5
VDD
HB
HO
HS
VSS
Power PadTM SOIC-8(DDA)
TOP VIEW
Exposed
Thermal
Die Pad
LO
LI
HI
1
2
3
4
9
7
6
5
VDD
HB
HO
HS
VSS
SON-9 (DRC)
TOP VIEW
Exposed
Thermal
Die Pad*
LO
LI
HI
8
N/C
1
2
3
4
8
7
6
5
VDD
HB
HO
HS
VSS
SON-8 (DRM)
TOP VIEW
Exposed
Thermal
Die Pad*
LO
LI
HI
Exposed
Thermal
Die Pad
SON-10 (DPR)
TOP VIEW
NC
LO
VSS
LI
HI
NC
VDD 10
HO
HS
HB
8
7
6
9
1
3
4
5
2
UCC27200A, UCC27201A
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SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
DEVICE INFORMATION
NOTE
Pin VSS and the exposed thermal die pad are internally connected.
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Product Folder Link(s): UCC27200A UCC27201A
UCC27200A, UCC27201A
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
www.ti.com
PIN FUNCTIONS
PIN I/O DESCRIPTION
PIN NAME DRM/D/DDA DRC DPR
Positive supply to the lower gate driver. De-couple this pin to
VDD 1 1 1 I VSS (GND). Typical decoupling capacitor range is 0.22 μF to
1.0 μF.
High-side bootstrap supply. The bootstrap diode is on-chip but
the external bootstrap capacitor is required. Connect positive
HB 2 2 2 I side of the bootstrap capacitor to this pin. Typical range of HB
bypass capacitor is 0.022 μF to 0.1 μF, the value is dependant
on the gate charge of the high-side MOSFET however.
High-side output. Connect to the gate of the high-side power
HO 3 3 3 O MOSFET.
High-side source connection. Connect to source of high-side
HS 4 4 4 I power MOSFET. Connect negative side of bootstrap capacitor to
this pin.
HI 5 6 7 I High-side input.
LI 6 7 8 I Low-side input.
Negative supply terminal for the device which is generally
VSS 7 8 9 O grounded.
Low-side output. Connect to the gate of the low-side power
LO 8 9 10 O MOSFET.
N/C - 5 5/6 - No connection. Pins labeled N/C have no connection.
Connect to a large thermal mass trace or GND plane to
PowerPAD™Pad(1) Pad Pad - dramatically improve thermal performance.
(1) Pin VSS and the exposed thermal die pad are internally connected on the DDA and DRM packages only. Electrically referenced to VSS
(GND).
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LEVEL
SHIFT
UVLO
UVLO
5
3
8
4
6 7
2
1
HI
LI
VDD
HB
HO
HS
LO
VSS
Input
(HI, LI)
Output
(HO, LO)
TMON TMOFF
LI
HI
LO
HO
TDLRR, TDHRR
TDLFF, TDHFF
UCC27200A, UCC27201A
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SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
TIMING DIAGRAMS
Figure 2.
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Product Folder Link(s): UCC27200A UCC27201A
10 1000
Frequency - kHz
0.1
10.0
100
1.0
IDDO - Operating Current - mA
-40oC
25oC
150oC
125oC
VDD = 12 V
No Load on Outputs
10 1000
Frequency - kHz
0.1
10.0
100
1.0
IDDO - Operating Current - mA
-40oC
25oC
150oC
125oC
VDD = 12 V
No Load on Outputs
10 1000
Frequency - kHz
0.1
10.0
100
1.0
IHBO - Operating Current - mA
-40oC
25oC
150oC
125oC
HB = 12 V
No Load on Outputs
10 1000
Frequency - kHz
0.001
1.0
100
0.01
IHBSO - Operating Current - mA
-40oC
25oC
150oC
125oC
HB = 12 V
No Load on Outputs
0.1
UCC27200A, UCC27201A
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS
UCC27200A IDD OPERATING CURRENT UCC27201A IDD OPERATING CURRENT
vs vs
FREQUENCY FREQUENCY
Figure 3. Figure 4.
BOOT VOLTAGE OPERATING CURRENT HB TO VSS OPERATING CURRENT
vs vs
FREQUENCY FREQUENCY
Figure 5. Figure 6.
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40
42
44
46
48
50
HI, LI - Input Threshold Voltage/VDD Voltage - %
Rising
Falling
8 10 12 16 20
VDD - Supply Voltage - V
14 18
T = 25oC
UCC27200A, UCC27201A
www.ti.com
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
TYPICAL CHARACTERISTICS (continued)
UCC27200A INPUT THRESHOLD UCC27201A INPUT THRESHOLD
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 7. Figure 8.
UCC27200A INPUT THRESHOLD UCC27201A INPUT THRESHOLD
vs vs
TEMPERATURE TEMPERATURE
Figure 9. Figure 10.
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-50 -25 0 25 100 125
TA- Temperature - oC
0.05
0.15
0.25
0.35
0.45
50 75 150
0.0
0.10
0.20
0.30
0.40 ILO = IHO = 100 mA
VDD = VHB = 16 V
VDD = VHB = 12 V
VDD = VHB = 8 V
VDD = VHB = 20 V
VOL - LO/HO Output Voltage - V
UCC27200A, UCC27201A
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
LO AND HO HIGH LEVEL OUTPUT VOLTAGE LO AND HO LOW LEVEL OUTPUT VOLTAGE
vs vs
TEMPERATURE TEMPERATURE
Figure 11. Figure 12.
UNDERVOLTAGE LOCKOUT THRESHOLD UNDERVOLTAGE LOCKOUT THRESHOLD HYSTERESIS
vs vs
TEMPERATURE TEMPERATURE
Figure 13. Figure 14.
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-50 -25 0 25 100 125
14
18
22
26
32
36
50 75 150
16
20
24
30
34
TA- Temperature - oC
Propagation Delay - ns
28
TDLFF
TDLRR
TDHFF
TDHRR
VDD = VHD = 12 V
14
18
22
26
30
36
16
20
24
28
34
Propagation Delay - ns
-50 -25 0 75 100 125 150
TA- Temperature - oC
25 50
32
TDLFF
TDLRR
TDHFF
TDHRR
VDD = VHB = 12 V
UCC27200A, UCC27201A
www.ti.com
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
TYPICAL CHARACTERISTICS (continued)
UCC27200A PROPAGATION DELAYS UCC27201A PROPAGATION DELAYS
vs vs
TEMPERATURE TEMPERATURE
Figure 15. Figure 16.
UCC27200A PROPAGATION DELAY UCC27201A PROPAGATION DELAY
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 17. Figure 18.
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-50 -25 0 75 125 150
TA- Temperature - ?C
0
7
25 50 100
1
2
Delay Matching - ns
3
4
5
6
VDD = VHB = 12 V
UCC27200ATMON
UCC27200ATMOFF
UCC27201ATMOFF
UCC27201ATMON
0 4 12 20
VDD, VHB - Supply Voltage - V
0
300
400
700
8 16
100
200
500
600
IDD, IHB - Supply Current - mA
IDD
IHB
Inputs Low
T = 25oC
UCC27200A, UCC27201A
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
DELAY MATCHING OUTPUT CURRENT
vs vs
TEMPERATURE OUTPUT VOLTAGE
Figure 19. Figure 20.
DIODE CURRENT QUIESCENT CURRENT
vs vs
DIODE VOLTAGE SUPPLY VOLTAGE
Figure 21. Figure 22.
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SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
APPLICATION INFORMATION
Functional Description
The UCC27200A and UCC27201A are high-side/low-side drivers. The high-side and low-side each have
independent inputs which allow maximum flexibility of input control signals in the application. The boot diode for
the high-side driver bias supply is internal to the UCC27200A and UCC27201A. The UCC27200A is the CMOS
compatible input version and the UCC27201A is the TTL or logic compatible version. The high-side driver is
referenced to the switch node (HS) which is typically the source pin of the high side MOSFET and drain pin of
the low-side MOSFET. The low-side driver is referenced to VSS which is typically ground. The functions
contained are the input stages, UVLO protection, level shift, boot diode, and output driver stages.
NOTE
The term “UCC2720x”applies to both the UCC27200A and UCC27201A.
Input Stages
The input stages provide the interface to the PWM output signals. The input impedance of the UCC27200A is
200 kΩnominal and input capacitance is approximately 2 pF. The 200 kΩis a pull-down resistance to Vss
(ground). The CMOS compatible input of the UCC27200A provides a rising threshold of 48% of VDD and falling
threshold of 45% of VDD. The inputs of the UCC27200A are intended to be driven from 0 to VDD levels.
The input stages of the UCC27201A incorporate an open drain configuration to provide the lower input
thresholds. The input impedance is 200 kΩnominal and input capacitance is approximately 4 pF. The 200 kΩis
a pull-down resistance to VSS (ground). The logic level compatible input provides a rising threshold of 1.7 V and
a falling threshold of 1.6 V.
UVLO (Under Voltage Lockout)
The bias supplies for the high-side and low-side drivers have UVLO protection. VDD as well as VHB to VHS
differential voltages are monitored. The VDD UVLO disables both drivers when VDD is below the specified
threshold. The rising VDD threshold is 7.1 V with 0.5-V hysteresis. The VHB UVLO disables only the high-side
driver when the VHB to VHS differential voltage is below the specified threshold. The VHB UVLO rising threshold
is 6.7 V with 0.4-V hysteresis.
Level Shift
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides
excellent delay matching with the low-side driver.
Boot Diode
The boot diode necessary to generate the high-side bias is included in the UCC2720x family of drivers. The
diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and
the HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The
boot diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and
reliable operation.
Output Stages
The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance and
high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The
low-side output stage is referenced from VDD to VSS and the high-side is referenced from VHB to VHS.
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Product Folder Link(s): UCC27200A UCC27201A
7
8
Vss
1VDD
LO
Cvdd
L bondwire
Rsink
Rsource
L pin
L trace
L bondwire
L bondwire
Driver
Output
Stage
L pin
L pin
L trace
Isink
L trace Cgs
Rg
L trace
ISOURCE
UCC27200A, UCC27201A
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
www.ti.com
Design Tips
Switching the MOSFETs
Achieving optimum drive performance at high frequency efficiently requires special attention to layout and
minimizing parasitic inductances. Care must be taken at the driver die and package level as well as the PCB
layout to reduce parasitic inductances as much as possible. Figure 23 shows the main parasitic inductance
elements and current flow paths during the turn ON and OFF of the MOSFET by charging and discharging its
CGS capacitance.
Figure 23. MOSFET Drive Paths and Circuit Parasitics
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Product Folder Link(s): UCC27200A UCC27201A
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
5
4
3
2
1
0
1
2
3
4
5
6
7
8
9
10
11
12
Voltage
Current
Voltage
Current
t, ns
LO Falling,V or A
2 1 0 1 2 3 4 5
3
2
1
0
1
2
3
4
5
6
7
8
9
10
11
12
LO Current, A
LO Voltage, V
UCC27200A, UCC27201A
www.ti.com
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
The ISOURCE current charges the CGS gate capacitor and the ISINK current discharges it. The rise and fall time of
the voltage across the gate to source defines how quickly the MOSFET can be switched. Based on actual
measurements, the analytical curves in Figure 24 and Figure 25 indicate the output voltage and current of the
drivers during the discharge of the load capacitor. Figure 24 shows voltage and current as a function of time.
Figure 25 indicates the relationship of voltage and current during fast switching. These figures demonstrate the
actual switching process and limitations due to parasitic inductances.
Figure 24. Turn-Off Voltage and Current vs Time Figure 25. Turn-Off Voltage and Current Switching
Diagram
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Product Folder Link(s): UCC27200A UCC27201A
UCC27200A
UCC27200A
UCC27200A, UCC27201A
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
www.ti.com
Turning off the MOSFET needs to be achieved as fast as possible to minimize switching losses. For this reason
the UCC2720x drivers are designed for high peak currents and low output resistance. The sink capability is
specified as 0.18 V at 100-mA dc current implying 1.8-ΩRDS(on). With 12-V drive voltage, no parasitic inductance
and a linear resistance, one would expect initial sink current amplitude of 6.7 A for both high-side and low-side
drivers. Assuming a pure R-C discharge circuit of the gate capacitor, one would expect the voltage and current
waveforms to be exponential. Due to the parasitic inductances and non-linear resistance of the driver
MOSFET’S, the actual waveforms have some ringing and the peak-sink current of the drivers is approximately
3.3 A as shown in Figure 20. The overall parasitic inductance of the drive circuit is estimated at 4 nH. The
internal parasitic inductance of the SOIC-8 package is estimated to be 2 nH including bond wires and leads. The
SON-8 package reduces the internal parasitic inductances by more than 50%.
Actual measured waveforms are shown in Figure 26 and Figure 27. As shown, the typical rise time of 8 ns and
fall time of 7 ns is conservatively rated.
Figure 26. VLO and VHO Rise Time, 1-nF Load, 5 Figure 27. VLO and VHO Fall Time, 1-nF Load,
ns/Div 5-ns/Div
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UCC27200A
UCC27200A
UCC27200A, UCC27201A
www.ti.com
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
Dynamic Switching of the MOSFETs
The true behavior of MOSFETS presents a dynamic capacitive load primarily at the gate to source threshold
voltage. Using the turn off case as the example, when the gate to source threshold voltage is reached the drain
voltage starts rising, the drain to gate parasitic capacitance couples charge into the gate resulting in the turn off
plateau. The relatively low threshold voltages of many MOSFETS and the increased charge that has to be
removed (Miller charge) makes good driver performance necessary for efficient switching. An open loop half
bridge power converter was utilized to evaluate performance in actual applications. The schematic of the
half-bridge converter is shown in Figure 30. The turn off waveforms of the UCC27200A driving two MOSFETs in
parallel is shown in Figure 28 and Figure 29.
Figure 28. VLO Fall Time in Half-Bridge Converter Figure 29. VHO Fall Time in Half-Bridge Converter
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): UCC27200A UCC27201A
+
+ +
UCC27200A, UCC27201A
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
www.ti.com
Figure 30. Open Loop Half-Bridge Converter
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Product Folder Link(s): UCC27200A UCC27201A
UCC27200A, UCC27201A
www.ti.com
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
Delay Matching and Narrow Pulse Widths
The total delays encountered in the PWM, driver and power stage need to be considered for a number of
reasons, primarily delay in current limit response. Also to be considered are differences in delays between the
drivers which can lead to various concerns depending on the topology. The sync-buck topology switching
requires careful selection of dead-time between the high- and low-side switches to avoid 1) cross conduction and
2) excessive body diode conduction. Bridge topologies can be affected by a resulting volt-sec imbalance on the
transformer if there is imbalance in the high and low side pulse widths in a steady state condition.
Narrow pulse width performance is an important consideration when transient and short circuit conditions are
encountered. Although there may be relatively long steady state PWM output-driver-MOSFET signals, very
narrow pulses may be encountered in 1) soft start, 2) large load transients, and 3) short circuit conditions.
The UCC2720x driver family offers excellent performance regarding high and low-side driver delay matching and
narrow pulse width performance. The delay matching waveforms are shown in Figure 31 and Figure 32. The
UCC2720x driver narrow pulse performance is shown in Figure 33 and Figure 34.
Figure 31. VLO and VHO Rising Edge Delay Figure 32. VLO and VHO Falling Edge Delay
Matching Matching
Figure 33. 20-ns Input Pulse Delay Matching Figure 34. 10-ns Input Pulse Delay Matching
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): UCC27200A UCC27201A
UCC27200A, UCC27201A
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
www.ti.com
Boot Diode Performance
The UCC2720x family of drivers incorporates the bootstrap diode necessary to generate the high side bias
internally. The characteristics of this diode are important to achieve efficient, reliable operation. The dc
characteristics to consider are VFand dynamic resistance. A low VFand high dynamic resistance results in a
high forward voltage during charging of the bootstrap capacitor. The UCC2720x has a boot diode rated at 0.65-V
VFand dynamic resistance of 0.6 Ωfor reliable charge transfer to the bootstrap capacitor. The dynamic
characteristics to consider are diode recovery time and stored charge. Diode recovery times that are specified
with no conditions can be misleading. Diode recovery times at no forward current (IF) can be noticeably less than
with forward current applied. The UCC2720x boot diode recovery is specified at 20ns at IF= 20 mA, IREV = 0.5 A.
At 0 mA IFthe reverse recovery time is 15 ns.
Another less obvious consideration is how the stored charge of the diode is affected by applied voltage. On every
switching transition when the HS node transitions from low to high, charge is removed from the boot capacitor to
charge the capacitance of the reverse biased diode. This is a portion of the driver power losses and reduces the
voltage on the HB capacitor. At higher applied voltages, the stored charge of the UCC2720x PN diode is often
less than a comparable Schottky diode.
Layout Recommendations
To improve the switching characteristics and efficiency of a design, the following layout rules should be followed.
•Locate the driver as close as possible to the MOSFETs.
•Locate the VDD and VHB (bootstrap) capacitors as close as possible to the driver.
•Pay close attention to the GND trace. Use the thermal pad of the DDA and DRM package as GND by
connecting it to the VSS pin (GND). Note: The GND trace from the driver goes directly to the source of the
MOSFET but should not be in the high current path of the MOSFET(S) drain or source current.
•Use similar rules for the HS node as for GND for the high side driver.
•Use wide traces for LO and HO closely following the associated GND or HS traces. 60 mil to 100 mil width is
preferable where possible.
•Use as least two or more vias if the driver outputs or SW node needs to be routed from one layer to another.
For GND the number of vias needs to be a consideration of the thermal pad requirements as well as parasitic
inductance.
•Avoid LIand HI(driver input) going close to the HS node or any other high dV/dT traces that can induce
significant noise into the relatively high impedance leads.
•Keep in mind that a poor layout can cause a significant drop in efficiency versus a good PCB layout and can
even lead to decreased reliability of the whole system.
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Product Folder Link(s): UCC27200A UCC27201A
UCC27200A, UCC27201A
www.ti.com
SLUSAF9A –FEBRUARY 2011–REVISED DECEMBER 2011
Figure 35. Example Component Placement
Additional References
These references and links to additional information may be found at www.ti.com.
1. Additional layout guidelines for PCB land patterns may be found in Application Brief SLUA271
2. Additional thermal performance guidelines may be found in Application Reports SLMA002A and SLMA004
SPACER REVISION HISTORY
Changes from Original (February 2011) to Revision A Page
•Added SON-10 (DPR) Package to the List of FEATURES .................................................................................................. 1
•Added SON-10 (DPR) Package to the DESCRIPTION ........................................................................................................ 2
•Added the SON-10 package to the ORDERING INFORMATION table ............................................................................... 2
•Added ordering information for the SON-10 (DPR) .............................................................................................................. 2
•Added note, "DPR(SON-10) package comes either in a small reel of 250 pieces as part number UCC27200ADPRT,
or large reels pieces as part number UCC27200ADPRR.".................................................................................................. 2
•Added the SON-10 package to the THERMAL INFORMATION table ................................................................................. 4
•Changed the "Minimum input pulse width"value From: 50 ns Max To: 50 ns Typ .............................................................. 6
•Added the SON-10 package Pinout ...................................................................................................................................... 7
•Changed the PIN FUNCTIONS table ................................................................................................................................... 8
•Added Additional PIN FUNCTIONS information. .................................................................................................................. 8
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): UCC27200A UCC27201A
PACKAGE OPTION ADDENDUM
www.ti.com 20-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC27200AD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27200ADDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27200ADDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27200ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27200ADRMR ACTIVE VSON DRM 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27200ADRMT ACTIVE VSON DRM 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27201AD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27201ADDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27201ADDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27201ADPRR ACTIVE WSON DPR 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC27201ADPRT ACTIVE WSON DPR 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC27201ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27201ADRCR ACTIVE SON DRC 9 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC27201ADRCT ACTIVE SON DRC 9 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC27201ADRMR ACTIVE VSON DRM 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27201ADRMT ACTIVE VSON DRM 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 20-Mar-2012
Addendum-Page 2
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC27200ADDAR SO
Power
PAD
DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27201ADDAR SO
Power
PAD
DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27201ADPRR WSON DPR 10 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27201ADPRT WSON DPR 10 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27201ADRCR SON DRC 9 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
UCC27201ADRCT SON DRC 9 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
UCC27201ADRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27201ADRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC27200ADDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.0
UCC27201ADDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.0
UCC27201ADPRR WSON DPR 10 3000 367.0 367.0 35.0
UCC27201ADPRT WSON DPR 10 250 210.0 185.0 35.0
UCC27201ADRCR SON DRC 9 3000 367.0 367.0 35.0
UCC27201ADRCT SON DRC 9 250 210.0 185.0 35.0
UCC27201ADRMR VSON DRM 8 3000 367.0 367.0 35.0
UCC27201ADRMT VSON DRM 8 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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