MC74HC175AN - Motorola Semi - Datasheet.Directory

July, 2012 − Rev. 5

1Publication Order Number:

MC74HC175A/D

MC74HC175A

Quad D Flip-Flop with

Common Clock and Reset

High−Performance Silicon−Gate CMOS

The MC74HC175A is identical in pinout to the LS175. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

This device consists of four D flip−flops with common Reset and

Clock inputs, and separate D inputs. Reset (active−low) is

asynchronous and occurs when a low level is applied to the Reset

input. Information at a D input is transferred to the corresponding Q

output on the next positive going edge of the Clock input.

Features

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1 mA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard

No. 7 A

•Chip Complexity 166 FETs or 41.5 Equivalent Gates

•NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

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See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16

DT SUFFIX

CASE 948F

1

16 PDIP−16

N SUFFIX

CASE 648

1

16

1

16

1

16

MC74HC175AN

AWLYYWWG

1

16

HC175AG

AWLYWW

HC

175A

ALYWG

G

1

16

A = Assembly Location

L, WL = Wafer Lot

Y, YY = Year

W, WW = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

MC74HC175A

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2

PIN 16 = VCC

PIN 8 = GND

9

4

5

12

13

CLOCK

D0

D1

D2

D3

RESET 1

DATA

INPUTS

2

3

7

6

10

11

15

14

Q0

Q1

Q2

Q3

INVERTING

AND

NONINVERTING

OUTPUTS

FUNCTION TABLE

Inputs Outputs

Reset Clock D Q Q

LXXLH

HHHL

HLLH

H L X No Change

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

D2

D3

Q3

VCC

CLOCK

Q2

D0

Q0

RESET

GND

Q1

D1

Figure 1. Pin Assignment Figure 2. Logic Diagram

ORDERING INFORMATION

Device Package Shipping†

MC74HC175ANG PDIP−16 500 Units / Rail

MC74HC175ADG SOIC−16

(Pb−Free)

48 Units / Rail

MC74HC175ADR2G SOIC−16

(Pb−Free)

2500 / Tape & Reel

MC74HC175ADTR2G TSSOP−16

(Pb−Free)

2500 / Tape & Reel

NLV74HC175ADTR2G* TSSOP−16

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable

MC74HC175A

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎ

±20

ÎÎÎ

mA

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎ

±25

ÎÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎ

±50

ÎÎÎ

mA

ÎÎÎÎ

PD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎÎ

750

500

450

ÎÎÎ

mW

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

_C

ÎÎÎÎ

TL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

ÎÎÎÎÎ

260

ÎÎÎ

_C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress

ratings only. Functional operation above the Recommended Operating Conditions is not implied.

Extended exposure to stresses above the Recommended Operating Conditions may affect device

reliability.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

V

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

0

ÎÎÎ

VCC

ÎÎÎ

V

ÎÎÎÎ

TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

_C

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 3.0 V

VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

0

ÎÎÎ

1000

600

500

400

ÎÎÎ

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

– 55 to

25_C

ÎÎÎ

v 85_C

ÎÎÎÎ

v 125_C

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum High−Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout| v 20 mA

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎ

1.5

2.1

3.15

4.2

ÎÎÎ

1.5

2.1

3.15

4.2

ÎÎÎÎ

1.5

2.1

3.15

4 2

ÎÎÎ

V

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout| v 20 mA

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎ

0.5

0.9

1.35

1.80

ÎÎÎ

0.5

0.9

1.35

1.80

ÎÎÎÎ

0.5

0.9

1.35

1.80

ÎÎÎ

V

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎ

Minimum High−Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout| v 20 mA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎ

V

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout| v 2.4 mA

|Iout| v 4.0 mA

|Iout| v 5.2 mA

ÎÎÎÎ

3.0

4.5

6.0

ÎÎÎÎ

2.48

3.98

5.48

ÎÎÎ

2.34

3.84

5.34

ÎÎÎÎ

2.20

3.70

5.20

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74HC175A

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4

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎ

Unit

ÎÎÎÎ

v 125_C

ÎÎÎ

v 85_C

ÎÎÎÎ

– 55 to

25_C

ÎÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout| v 20 mA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎÎ

0.1

ÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎ

V

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout| v 2.4 mA

|Iout| v 4.0 mA

|Iout| v 5.2 mA

ÎÎÎÎ

3.0

4.5

6.0

ÎÎÎÎ

0.26

ÎÎÎ

0.33

ÎÎÎÎ

0.40

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎÎ

6.0

ÎÎÎÎ

±0.1

ÎÎÎ

±1.0

ÎÎÎÎ

±1.0

ÎÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply

Current (per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

Iout = 0 mA

ÎÎÎÎ

6.0

ÎÎÎÎ

4

ÎÎÎ

40

ÎÎÎÎ

160

ÎÎÎ

mA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

– 55 to

25_C

ÎÎÎ

v 85_C

ÎÎÎÎ

v 125_C

ÎÎÎÎ

fmax

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎ

6

10

30

35

ÎÎÎ

4.8

8.0

24

28

ÎÎÎÎ

4

6

20

24

ÎÎÎ

MHz

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock to Q or Q

(Figures 1 and 4)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎ

150

75

26

22

ÎÎÎ

190

90

32

28

ÎÎÎÎ

225

110

38

33

ÎÎÎ

ns

ÎÎÎÎ

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Reset to Q or Q

(Figures 2 and 4)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎ

125

70

22

19

ÎÎÎ

155

85

27

24

ÎÎÎÎ

190

110

34

30

ÎÎÎ

ns

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎ

75

27

15

13

ÎÎÎ

95

32

19

16

ÎÎÎÎ

110

36

22

19

ÎÎÎ

ns

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎ

—

ÎÎÎÎ

10

ÎÎÎ

10

ÎÎÎÎ

10

ÎÎÎ

pF

CPD Power Dissipation Capacitance (Per Flip−Flop)*

Typical @ 25°C, VCC = 5.0 V

pF

35

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.

MC74HC175A

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5

TIMING REQUIREMENTS (Input tr = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

– 55 to

25_C

ÎÎÎ

v 85_C

ÎÎÎÎ

v 125_C

ÎÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Data to Clock

(Figure 3)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎ

100

45

20

17

ÎÎÎ

125

65

25

21

ÎÎÎÎ

150

85

30

26

ÎÎÎ

ns

ÎÎÎÎ

th

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock to Data

(Figure 3)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎ

5

3

ÎÎÎ

5

3

ÎÎÎÎ

5

3

ÎÎÎ

ns

ÎÎÎÎ

trec

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time, Reset Inactive to Clock

(Figure 2)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎ

100

45

20

17

ÎÎÎ

125

65

25

21

ÎÎÎÎ

150

85

30

26

ÎÎÎ

ns

ÎÎÎÎ

tw

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Clock

(Figure 1)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎ

80

45

16

14

ÎÎÎ

100

65

20

17

ÎÎÎÎ

120

85

24

20

ÎÎÎ

ns

ÎÎÎÎ

tw

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Reset

(Figure 2)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎ

80

45

16

14

ÎÎÎ

100

65

20

17

ÎÎÎÎ

120

85

24

20

ÎÎÎ

ns

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall Times

(Figure 1)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎ

1000

800

500

400

ÎÎÎ

1000

800

500

400

ÎÎÎÎ

1000

800

500

400

ÎÎÎ

ns

MC74HC175A

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6

SWITCHING WAVEFORMS

Figure 3.

50%

VCC

GND

RESET

Q

CLOCK

tPLH

tPHL

50%

DATA

CLOCK

VCC

GND

Figure 4.

GND

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 5.

1/fmax

CLOCK

Q or Q

tftr

VCC

GND

90%

50%

10%

90%

50%

10%

tPLH tPHL

tTLH tTHL

tw

trec

VALID

th

tsu

TEST CIRCUIT

Figure 6.

MC74HC175A

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7

DQ

C

CR

D0

CLOCK

D1

D2

D3

RESET 1

13

12

5

9

42

3

7

6

10

11

15

14

Q0

Q1

Q2

Q3

EXPANDED LOGIC DIAGRAM

DQ

C

CR

DQ

C

CR

DQ

C

CR

MC74HC175A

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8

PACKAGE DIMENSIONS

PDIP−16

CASE 648−08

ISSUE T

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

B

FC

S

H

GD

J

L

M

16 PL

SEATING

18

916

K

PLANE

−T−

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

MC74HC175A

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9

PACKAGE DIMENSIONS

SOIC−16

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

RX 45_

G

8 PLP

−B−

−A−

M

0.25 (0.010) B S

−T−

D

K

C

16 PL

S

B

M

0.25 (0.010) A S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

16

89

8X

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC74HC175A

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10

PACKAGE DIMENSIONS

TSSOP−16

CASE 948F−01

ISSUE B

ÇÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.18 0.28 0.007 0.011

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

SECTION N−N

SEATING

PLANE

IDENT.

PIN 1

18

16 9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

ÉÉÉ

DETAIL E

F

M

L

2X L/2

−U−

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V S

T

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

16X REFK

N

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC74HC175A

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11

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