FEBRUARY 1996 VOLUME VI NUMBER 1
continued on page 3
New LTC1435–LTC1439
DC/DC Controllers
Feature Value
and Performance
by Randy Flatness, Steve Hobrecht
and Milton Wilcox
Introduction
The new LTC1435–LTC1439 multiple-
output DC/DC controllers bring
unprecedented levels of value to sup-
plies for notebook computers and
other battery-powered equipment,
while eliminating previous perfor-
mance barriers. For example, a new
Adaptive Power™ output stage allows
two previously incompatible param-
eters, constant frequency operation
and good low current efficiency, to
coexist in the same power supply. A
second breakthrough allows N-chan-
nel power MOSFETs to be used
exclusively, while maintaining low
dropout operation previously avail-
able only with P-channel MOSFETs.
Other innovations include an auxiliary
linear regulator loop, a phase-locked
loop (PLL) to synchronize the oscillator
to an external source, a self-contained
power-on-reset (POR) timer and pro-
grammable run delays useful for
staging output voltages.
Excellent system functionality
means that 1-, 2-, 3- or even 4-output
power supplies are easily constructed
using a minimum number of induc-
tors. Table 1 illustrates a few of the
many possible output combinations
and the magnetics required.
For maximum flexibility, internal
resistive feedback dividers are select-
able via programming pins for 3.3V,
5V and 12V output voltages, or a
regulator may be configured with an
adjustable output voltage to meet any
processor requirement.
snoitanibmocegatlovtuptuoelbissopfoselpmaxE.1elbaT
rebmuNtraPegakcaPsegatloVtuptuO*scitengaM
5341CTLOSnip-61V9V5.1elbatsujdAL)1(
6341CTLPOSQnip-42V9.2/V3.3L)1(
7341CTLPOSSnip-82V21/V5T)1(
8341CTLPOSSnip-82V3.3/V5L)2(
9341CTLPOSSnip-63V9.2/V3.3/V5L)2(
V21/V9.2/V3.3/V5T)1(,L)1(
remrofsnarT=T,rotcudnI=L*
, LTC and LT are registered trademarks of Linear Technology Corporation.
Adaptive Power, Burst Mode and C-Load are trademarks of Linear Technology Corporation.
IN THIS ISSUE . . .
COVER ARTICLE
New LTC
®
1435–LTC1439 DC/DC
Controllers Feature Value
and Performance................. 1
Randy Flatness, Steve Hobrecht
and Milton Wilcox
Editor’s Page....................... 2
Richard Markell
LTC in the News .................. 2
DESIGN FEATURES
New 12-Bit ADC Squeezes
100ksps from 10mW ........... 7
William C. Rempfer and Ringo Lee
The LT
®
1511 3A Battery
Charger Charges All Battery
Types, Including Lithium-Ion
......................................... 11
Chiawei Liao
LTC1520 High Speed Line
Receiver Provides Precision
Propagation Delay and Skew
......................................... 14
Victor Fleury
The LTC1446 and LTC1446L:
World’s First Dual 12-Bit DACs
in SO-8 Packages .............. 16
Hassan Malik and Jim Brubaker
LT1490/LT1491 Over-the-Top
Dual and Quad Micropower
Rail-to-Rail Op Amps ......... 18
Jim Coelho-Sousae
LT1512/LT1513 Battery
Chargers Operate with Input
Voltages Above or Below the
Battery Voltage ................. 20
Bob Essaff
DESIGN IDEAS ............. 24–35
(complete list on page 24)
DESIGN INFORMATION
Simple Resistive Surge
Protection for
Interface Circuits .............. 36
Bryan Nevins
New Device Cameos ........... 38
LINEAR TECHNOLOGY
LINEAR TECHNOLOGY
LINEAR TECHNOLOGY
2
Linear Technology Magazine • February 1996
EDITOR'S PAGE
On Breadboarding
New integrated circuits don’t come
easy these days. Marketeers would
have you build a new Pentium
®
Pro
class microprocessor in a few months.
Never mind the half-million transis-
tors that all have to work correctly for
the product to come out right the first
time.
Simulation may be the way to go
when faced with one-half million tran-
sistors and a year’s time to market,
but what about in the analog world
where LTC excels? No analog product
in this or perhaps even the next cen-
tury will have one-tenth the transistor
count of a microprocessor. The semi-
conductor world has come to rely
heavily on simulations; and, in fact,
we at LTC do our share of simula-
tions; but, as the photo shows, we
also do our share of breadboarding.
It may be that the mere mention of
breadboarding shows my age. What
could be simpler than building a cir-
cuit from discrete transistors, diodes,
resistors, chewing gum and piano
wire? Once built, the circuit can be
tested node by node, and after the
design is proven to work over its
required electrical and environmen-
tal parameters, it can be put into
production.
In the IC design world, the simula-
tion is king because breadboarding is
hard. Transistors don’t come out of a
catalog; instead they are “kit parts”—
the types of transistors that can be
made on a particular wafer-fab pro-
cess. All capacitors must be small
values, since only these are supported
by the IC process; and so forth and so
on. The implementation is not easy,
but the reward justifies the labors.
What is the reward?
The reward is an IC that works the
first time—or at least the second time.
Breadboarding makes you look at the
circuit from a system point of view.
Can it be integrated into the system in
which it is intended to work? Are all
the hooks there? Breadboarding is
not always an option because of the
increased complexity of today’s ICs,
but we try to use it whenever we can
to complement simulation. Bread-
boarding helps us get it right “the first
time.”
This issue of Linear Technology
begins our sixth year of publication.
We have expanded our publishing
schedule to four times per year. We
continue to ask for feedback from our
readership. Call, FAX or write to us at
the numbers on the back page.
by Richard Markell
Figure 1. Breadboard of upcoming LTC microprocessor product?
continued on page 22
LTC in the News...
The only company in the history of
Silicon Valley to achieve continuous
sales growth over 40 consecutive
quarters is Linear Technology Corp.
In January, LTC announced record
second-quarter net sales of more than
$96 million, an increase of 55% over
the same quarter of 1995.
“This solid 10-year record vali-
dates both the strength of our market
and the effectiveness of our strategy
to be a broad-based supplier of high
performance analog circuits,” said
Robert Swanson, president and CEO.
“We attained record levels of sales
and profits and generated an addi-
tional $20 million in cash,” he said.
Shortly before LTC ended its sec-
ond fiscal quarter, Forbes magazine
again listed the company on its “Honor
Roll” of “The Best Small Companies
in America.” It was the sixth year in
a row in which Linear Technology
was included among “only a handful
of companies (that) have what it takes
to be a long-term repeater on our 200
Best Small Companies in America
list.” The magazine made special
mention of LTC and observed that a
$10,000 investment in Linear six
years ago would be worth about
$170,000 today.
“All chip companies are not cre-
ated equal,” said the influential Cabot
Market Letter for investors in its De-
cember 1, 1995, issue. “Linear
Technology is ... the leader in its
market. (The company’s) chips don’t
deal with data. They interact with the
real world to monitor, amplify or
transform continuous analog signals
associated with real-world phenom-
ena like temperature, pressure,
weight, position, height, speed or
sound.
“That’s diversity in the extreme.
In fact, LTC markets over 4,700
different products to over 9,000
manufacturers worldwide. Industrial
applications use 40% of the firm’s
output, computers 30%, telecom-
munications 15%, military 10% and
other 5%. International sales ac-
count for about half of the total.”
Pentium is a registered trademark of Intel Corporation.
Linear Technology Magazine • February 1996
3
A Brief History of High
Efficiency DC/DC Conversion
The 90% efficiency barrier was de-
molished several years ago, at least at
high output currents, by DC/DC con-
trollers adapted to drive external
synchronous power MOSFETs, which
largely eliminated the catch-diode
losses. However, the efficiency of these
converters plummeted when the out-
put current dropped, because the
fixed-gate-charge losses for the large
MOSFETs became an increasing per-
centage of the power delivered to the
load. Expressed differently, the qui-
escent (unloaded) current was
unacceptably high—often over 10mA.
Linear Technology’s LTC1148 fam-
ily of DC/DC controllers introduced
in late 1992 was the first in the indus-
try to extend high efficiency operation
over the entire load range required by
notebook computers and other por-
table electronics. This breakthrough
was achieved through Burst Mode™
operation, which turns both synchro-
nous MOSFETs off for increasing
periods as the load current drops. In
this way, the gate charge losses are
made proportional to the load cur-
rent, thus maintaining high efficiency.
Along with the gate-charge savings
came an attendant reduction in qui-
escent current, to less than 200µA for
the LTC1148.
Burst Mode operation received
immediate acceptance and is in use
today in a wide range of battery-
powered electronics. However, the
approach of intermittently operating
large power MOSFETs at low output
currents carries one drawback: the
operating frequency must inherently
be variable, and will enter the audio
range at some currents. This draw-
back, while not a problem in many
applications, is becoming an increas-
ing concern as communications and
multimedia features are added to
portable computers.
The LTC143X family controllers use
a constant frequency, current mode
PWM architecture in which the user
can set the oscillator frequency from
50kHz to 400kHz via an external ca-
pacitor. But how to break through the
constant frequency/low current effi-
ciency barrier?
Adaptive Power Mode—
Constant Frequency
without the Efficiency Hit
Adaptive Power mode, available in all
family members except the LTC1435
and LTC1438, optimizes efficiency
without changing frequency by auto-
matically switching between the two
output stages shown in Figure 1. The
first stage uses large synchronous N-
channel MOSFETs when operating at
high currents, and the second uses a
small (0.5) N-channel MOSFET and
Schottky diode when operating at low
currents. The transition point between
the two output stages scales with the
maximum current, which is set by
the current sense resistor for each
regulator. The large MOSFETs oper-
ate above approximately 5% of the
maximum output current, whereas
the small MOSFET operates below
this current level, but at the same
constant frequency.
Because the low current “baby”
MOSFET (available in SOT-23) has
much lower gate charge than the large
synchronous MOSFETs, far less effi-
ciency loss is incurred as the load
current drops. Eventually, as the load
current is reduced below approxi-
mately 1% of the maximum current,
the loop begins skipping cycles and
the frequency does begin to decrease.
However, it does not enter the audio
region until the load current has fallen
even further. This performance comes
at little penalty in quiescent current,
which, at around 200µA, is nearly as
low as that of the LTC1148.
Burst Mode operation is also pos-
sible in all LTC1435–LTC1439
controllers for even higher efficien-
cies at the expense of more frequency
variability. To activate Burst Mode
operation, the small MOSFET is sim-
ply not installed. When the load
current falls to where both large
MOSFETs are turned off, the output
capacitor supports the load until the
error amplifier increases the I
TH
pin
+
SWITCH
DRIVE
SWITCH
NODE
SYNCHRONOUS
MOSFET
DRIVERS
HIGH
CURRENT
OPERATION
LOW
CURRENT
OPERATION
VIN
VOUT
COUT
SMALL
MOSFET
DRIVER
LR
SENSE
OUTPUT CURRENT
50
100
90
80
70
60
EFFICIENCY (%)
10A1mA 10mA 1A100mA
(1)
(2)
(3)
Figure 1. Adaptive Power output stage automatically switches to efficiency-saving small
MOSFET at low currents, while continuing to operate at a constant frequency.
Figure 2. 10V to 5V conversion efficiency
versus output current for three operating
modes: 1) forced continuous operation; 2)
Adaptive Power mode (constant frequency);
and 3) Burst Mode.
LTC1435–LTC1439, continued from page 1
DESIGN FEATURES
4
Linear Technology Magazine • February 1996
voltage to 0.6V, at which point the
large MOSFETs resume operation.
Whether in Adaptive Power mode
or Burst Mode, the large MOSFETs
can always be forced into continuous
operation, independent of load cur-
rent, by forcing the SFB pin low (more
on this later). Figure 2 gives a com-
parison of efficiencies in a 3A regulator
for the three possible operating modes:
forced continuous operation, Adap-
tive Power mode and Burst Mode.
Low Dropout without
P-Channel MOSFETs
An important feature of the LTC1148
family is its ability to stay in regula-
tion with the input voltage only slightly
above the output, a condition known
as low dropout. The LTC1148 achieves
this by using a P-channel MOSFET
switch that can operate at up to 100%
duty cycle; in other words, it can
connect the output to the input in
dropout mode. This feature is impor-
tant because it allows the maximum
energy to be extracted from low volt-
age battery packs such as two
lithium-ion cells (5.4V typical end-of-
life voltage).
The LTC143X family changes to an
all N-channel output stage to accrue
the benefits of lower R
DS(ON)
and lower
cost than corresponding P-channel
MOSFETs. Driving N-channel MOS-
FETs requires the floating high-side
driver shown in Figure 3; however,
the bootstrap capacitor powering the
floating driver requires periodic re-
charging, which can occur only when
the top MOSFET is turned off and the
bottom MOSFET is turned on. In past
N-channel controllers, this recharge
interval was guaranteed by forcing a
minimum off-time during every oscil-
lator cycle.
To relieve the duty cycle limitation
resulting from minimum off-time con-
trol, the LTC1435–LTC1439 detect
the onset of dropout by counting the
number of oscillator pulses that have
passed without the top MOSFET turn-
ing off. Only when the count reaches
10 is a minimum off-time forced. This
extends the duty cycle capability from
around 90% to 99% while still guar-
anteeing that the top MOSFET
bootstrap capacitor remains charged.
Thus, dropout performance compa-
rable to the LTC1148 can be achieved.
Auxiliary Output
Voltages Made Easy
The new LTC143X family of DC/DC
controllers has also been designed
with many “hooks” to make the addi-
tion of extra output voltages easy, as
can be seen from two representative
applications. The first, shown in Fig-
ure 4, is a cost effective LTC1437
switcher/linear combination with 5V/
3A and 12V/200mA outputs. The
main switcher loop is set to 5V by
strapping the V
PROG
pin high. Other
output options include 3.3V (V
PROG
low) and adjustable (V
PROG
open).
The 12V output in Figure 4’s cir-
cuit is provided by the auxiliary linear
regulator operating in conjunction
with a secondary winding feedback
loop using the SFB pin mentioned
earlier. The turns ratio for the trans-
former is 1:2.2, resulting in a
secondary output voltage of approxi-
mately 15V. The secondary resistive
divider causes the SFB pin voltage to
drop below the internal 1.19V refer-
ence if the secondary output is loaded
and the 5V output has little or no
load. This forces continuous opera-
tion as necessary to guarantee
sufficient headroom for the linear
regulator to maintain 12V regulation
independent of the 5V load. The aux-
iliary output is turned on and off with
the AUX ON pin.
The auxiliary regulator can also be
used in an adjustable mode, deter-
mined by the voltage on the AUX DR
pin. When the AUX DR voltage is
higher than 9.5V, as is the case in
Figure 4, the regulator automatically
configures itself for fixed 12V opera-
tion using an internal AUX FB
resistive divider. When AUX DR is
less than 8.5V, the internal divider is
removed and the user can adjust the
output voltage via an external divider
referenced to 1.19V. The external aux-
iliary regulator PNP pass transistor is
sized for the desired output current;
+
SWITCH
DRIVE
FORCED MINIMUM
OFF-TIME
LOW-SIDE
DRIVER
BOOTSTRAP
CAPACITOR
FLOATING
HIGH-SIDE
DRIVER
VOUT
COUT
LR
SENSE
÷10 COUNTER
CLOCK
RESET
OSCILLATOR
INT VCC VIN
Figure 3. Operation at up to 99% duty cycle is made possible by
÷
10 counter logic, which ensures low dropout.
DESIGN FEATURES
Linear Technology Magazine • February 1996
5
in this case a SOT-223 device is used
to deliver up to 200mA.
Synchronizable, Triple-
Output, Low Dropout Supply
The LTC1439-based supply shown in
Figure 5 is an example of how three
logic supply voltages, 5V, 3.3V and
2.9V, can be easily derived using only
two simple inductors. The two main
DC/DC controller loops are used to
supply 5V/3A and 3.3V/5.5A. Up to
2.5A of the 3.3V output current is
then used to supply a 2.9V output
using the adjustable capability of the
auxiliary linear regulator.
The 2.9V output also illustrates
the use of an external NPN pass tran-
sistor with the auxiliary regulator.
Because only 0.4V is dropped across
the NPN transistor, 2.9V efficiency
remains in the 85% range. And thanks
to the 99% duty cycle capability of the
switcher loops, Figure 5’s supply can
maintain all three output voltages in
regulation down to V
IN
= 5.2V with a
2A load on the 5V output.
The phase-locked loops built into
the LTC1437 and LTC1439 offer a
convenient means of synchronization
for the applications in Figures 4 and
5. The internal oscillator is actually a
voltage-controlled oscillator (VCO)
controlled by the voltage on the PLL
LPF pin. When no PLL IN signal is
present, the PLL LPF goes low, caus-
ing the oscillator to run at its minimum
frequency (f
MIN
= 180kHz with C
OSC
=
56pF). Applying a 3.3V or 5V logic
signal of any duty cycle to the PLL IN
pin will cause the oscillator frequency
to lock to the logic signal frequency
and to track it up to a maximum of
f
MAX
= 2 × f
MIN
. A logic signal may also
be coupled to PLL LPF to effect a 2:1
frequency shift, provided that the ini-
tial frequency has been set to less
than 200kHz.
Starting Up in Sequence
Power supply sequencing upon initial
application of input power is a critical
issue. This is particularly true in ap-
plications where the controllers are
left on continually, which will fre-
quently be the case since the quiescent
current is very low. The LTC143X
family has unique combined run and
soft-start pins and power-on-reset
10k 0.01µF
10k
51pF
V
IN
28V (MAX)
C
OSC
PLL IN
V
PROG
PLL LPF
RUN/SS
LBO
POR
SFB
I
TH
LBI
BG
SENSE+
SW
TGS
TGL
SENSE
V
O SENSE
EXT V
CC
AUX FB
AUX DR
BOOST
INT V
CC
V
IN
DR V
CC
SGND PGND AUX ON
T1 = DALE LPE-8562-A092
*CENTRAL SEMICONDUCTOR
LTC1436
0.1µF
EXT.
CLOCK
56pF
510pF
+
IRF7403
IRLML2803
IRF7403
MBRS140
*CMDSH-3
1000pF
2.2µF
0.033
V
OUT1
5V/3A
V
OUT2
12V/200mA
100µF
10V
×2
+
4.7µF
25V
0.1µF
+
+
3.3µF
35V
+
22µF
35V
×2
0.1µF
100
100
T1 MBRS1100
100k
47k
1MEG
ZETEX
FZT749
26V
Figure 4. High efficiency, constant-frequency, dual-output supply delivers 3A at 5V and 250mA at 12V.
DESIGN FEATURES
6
Linear Technology Magazine • February 1996
10
V
IN
5.2V-25V
BG1
SENSE1+
SW1
BG1
TGS1
TGL1
SENSE1
EXT V
CC
PLL IN
I
TH1
PLL LPF
RUN/SS1
C
OSC
BOOST1
BG2
SENSE2+
SW2
TGS2
TGL2
SENSE2
V
O SENSE2
AUX ON
I
TH2
AUX FB
RUN/SS2
AUX DR
BOOST2
SFB1 INT V
CC
V
IN
V
PROG1
V
PROG2
LB1 LB0 SGND PGND POR2
+
Si4412
IRLML2803
Si4412
MBRS140
*CMDSH-3
1000pF
0.1µF
1000pF
0.033
100µF
10V
×2
+
22µF
35V
×2
0.1µF
100
100
10k 1000pF
LTC1439
0.1µF
EXT.
CLOCK
10µH
220pF
10k 0.01µF
56pF
+
Si4410
IRLML2803
Si4410
MBRS140
*CMDSH-3
1000pF
4.7nF
2.2µF
0.02
V
OUT2
3.3V/3A
V
OUT3
2.9V/2.5A
V
OUT1
5V/3A
221k
47k
100
100µF
10V
×2
+
330µF
6.3V
0.1µF
+
+
22µF
35V
×2
0.1µF
100
100
10k
1000pF
0.05µF
10µH
220pF
51pF
316k
20
ZETEX
ZTX849
MMBT2907ALT1
*CENTRAL SEMICONDUCTOR
outputs that greatly ease start-up
sequencing and reset issues.
The RUN/SS pins have internal
3µA pull-ups whenever V
IN
is present.
An external capacitor to ground is
charged by this current to provide
both a start delay and soft-start char-
acteristic. At initial application of
input power, or following a shutdown,
the RUN/SS voltage will be low. As
the RUN/SS voltage ramps up, the
associated controller remains shut
down until the voltage reaches 1.3V.
Thus by using different value capaci-
tors for the two RUN/SS pins in an
LTC1438 or LTC1439, one controller
can be forced to always start before
the other.
Once the RUN/SS voltage passes
1.3V, the controller starts with the
initial peak inductor current at ap-
proximately one third of its maxi-
mum value and ramps up from there,
reaching normal operation at 3V. Fig-
ure 6 is a photograph showing the
3.3V output staged to start 10ms
before the 5V output when power is
first applied to Figure 5’s circuit.
Power-On Reset
Monitor Included
An internal regulation monitor is
continually monitoring the main con-
troller output in the LTC1436/
LTC1437, and the controller 2 output
(3.3V in Figure 5) in the LTC1438/
LTC1439. When out of regulation or
in shutdown mode, the POR open
drain output pulls low. At start-up,
once the output voltage has reached
5% of its final value, an internal timer
is started, after which the POR pin is
released. The timer is accomplished
by counting 2
16
oscillator cycles, yield-
ing a delay-to-release reset of
approximately 300ms in a typical ap-
plication.
Figure 5. High efficiency, constant-frequency, triple-output logic supply features 200mV dropout.
Figure 6. Start-up of 3.3V and 5V supplies is
easily staged upon initial application of input
power.
DESIGN FEATURES
continued on page 22
Linear Technology Magazine • February 1996
7
New 12-Bit ADC Squeezes
100ksps from 10mW by William C. Rempfer
and Ringo Lee
Until now, 12-bit 100ksps ADCs
have needed as much as 100mW to do
their jobs. That has changed with the
new LTC1274 and LTC1277. These
complete, parallel-output 12-bit ADCs
sample at 100ksps while drawing only
10mW. They have some new features
that make them very attractive for
applications in the 100ksps range
and below:
Complete ADC with reference
and sample-and-hold
10mW power dissipation from 5V
or ±5V supplies
Nap and Sleep power-down
modes
Reference Ready (REFRDY) signal
indicating wake-up from Sleep
mode
Unipolar/bipolar conversions
Separate conversion-start input
High-Z analog inputs can be
MUXed or AC coupled
12-bit or 2-byte parallel I/O
3V logic supply interface
(LTC1277)
This article will describe the new
devices and show how they can be
used to save power, improve perfor-
mance and simplify the design of new
systems.
10mW, 100ksps and More
As Figure 1 shows, the LTC1274 and
LTC1277 come complete with a
switched capacitor ADC, a very wide
band sample-and-hold, a reference
and power-down circuitry. They pro-
vide parallel I/O in a 12-bit (LTC1274)
or 8-bit (LTC1277) format. In addi-
tion to the normal microprocessor
interface signals, they have conver-
sion start inputs and data ready
outputs for latching the parallel data
when the conversion is complete. Two
power-down modes are available: Nap
mode drops the supply current from
2mA to 160µA and provides instant
wake-up. Sleep mode drops supply
12-BIT
SWITCHED CAP
ADC
OUTPUT
LATCHES
CONTROL
LOGIC
AND
TIMING
POWER DOWN
CIRCUITRY
REFERENCE
SLEEPREFRDY
V
REF
2.42V
0V TO 4.096V
OR
±2.048V
D11
D0
1212
LTC1274
BUSY
CS
RD
CONVST
A
IN
+SAMPLE-
AND-HOLD
12-BIT
SWITCHED CAP
ADC
OUTPUT
LATCHES
CONTROL
LOGIC
AND
TIMING
POWER DOWN
CIRCUITRY
REFERENCE
NAP SLEEP
V
LOGIC
3V OR 5V
REFRDY
V
REF
2.42V
0V TO 4.096V
OR
±2.048V
D7
D0/D8
LTC1277
BUSY
CS
RD
CONVST
HBEN
A
IN
+
A
IN
SAMPLE-
AND-HOLD 1212
current below 1µA, and has a longer
wake-up time. A power-good signal
(REFRDY) is provided to indicate when
wake-up from Sleep has been achieved
and to ensure that the system is oper-
ating correctly. The devices are
available in 24-pin SO-packages in
commercial and industrial tempera-
ture ranges.
New Features Save Power
Figure 2 shows how the LTC1274 and
LTC1277 add to LTC’s low power,
high speed ADC family. At 10mW,
these new ADCs have the lowest power
dissipation available today. In
Figure 1. The new ADCs come complete with wideband sample-and-hold and reference. They
sample at 100ksps on 10mW and provide novel power-down options.
DESIGN FEATURES
MAXIMUM SAMPLING RATE (sps)
0
100
200
POWER DISSIPATION (mW)
1.5M1M100k 500k
LTC 12-BIT PARALLEL SAMPLING ADCs
LTC1410
LTC1279
160mW + NAP/SLEEP
60mW + NAP
LTC1274/7
10mW + NAP/SLEEP
Figure 2. The LTC1274/LTC1277 offer very
low power consumption for applications at
100ksps and below.
8
Linear Technology Magazine • February 1996
addition, they have two power-down
modes that save even more power.
Take a Nap and
Wake Up Quickly
Table 1 shows the shutdown options
available. Nap mode allows the
LTC1277 to be powered down and
reawakened quickly. When NAP is
taken low, everything but the refer-
ence shuts down and the supply
current drops from 2mA to 160µA.
When NAP is brought back high, the
device wakes up instantly (400ns typi-
cal). Figure 3 shows the conversion
timing when using Nap mode. First,
NAP is taken high and one or more
conversions are performed. After the
last conversion, the NAP pin is taken
back low. This method can reduce the
power dissipation by a factor of up to
12.5 for slower sample rates (see Fig-
ure 4). At sample rates below 10ksps,
the current flattens out at the Nap-
mode value of 160µA.
Sleep Mode: More Restful
but Slower Wake-Up.
Power drain can be reduced even
further with Sleep mode. Taking
SLEEP low invokes a complete shut-
down of the ADC. The internal
reference powers off and the supply
current drops to less than 1µA. When
the reference is turned off, its output
bypass capacitor starts to discharge.
Bringing SLEEP high powers the
device back up. A wake-up time is
required for the internal reference to
slew its output back to the desired
value and settle. This time is rela-
tively slow and variable. It depends
on the reference bypassing and load-
ing, on the slewing current of the
internal reference and on how far the
reference has fallen away from its
desired value. The longer the device is
shut down, the farther the reference
output will discharge and the longer
the wake-up time will be. Depending
on these factors, Sleep-mode wake-
up time can vary from less than 1ms
to 40ms. conversion results may have been
erroneous.
The LTC1274 and LTC1277 solve
both problems with a new output
signal called REFRDY (reference
ready), which monitors the internal
reference and indicates when it has
settled. This signal tells the user ex-
actly when the system is ready to
convert. No extra power need be
wasted in some arbitrarily long delay
time. Also, full assurance is given
that the device is ready to go and that
the results will be accurate. Figure 5
shows the power-up sequence from
Sleep mode. The REFRDY signal indi-
cates readiness to convert.
Power the Reference
First, Then the ADC
The LTC1277 can save even more
power during wake-up from Sleep
mode. If a converter is awakened from
Sleep mode directly to full-power
mode, it draws its full supply current
as the reference slews. This is unnec-
essary and wastes power. The
NAP POWER OFF POWER ON POWER OFF
CONVST
WAKEUP TIME (400ns TYP.)
BUSY
CONVERSION TIME (6µs TYP.)
DATA OUTPUT OLD DATA AVAILABLE NEW DATA AVAILABLE
SAMPLE RATE (ksps)
160µA
1mA
2mA
SUPPLY CURRENT
100050
NAP MODE
BETWEEN
CONVERSIONS
ACTIVE MODE
Figure 3. The LTC1277 wakes up from Nap mode quickly, converts and is
then powered down. Data can be read at any time, even in shutdown.
Figure 4. Using Nap mode between conver-
sions cuts power by a factor of up to 12.5 as
the sample rate is reduced. Sleep mode cuts
power even more.
DESIGN FEATURES
How Do I Know You’re
Awake?... REFRDY!
In the past, ADCs with complete shut-
down (including the reference) have
offered no indication of when the
converter’s reference was powered up
and ready to operate. Users had to
wait some arbitrarily long time to
allow a worst-case device to wake up
under worst-case conditions. This
caused two problems: first, the full-
power drain of the converter was
wasted during this long delay time.
Even worse, since no assurance was
given that enough time had elapsed,
The LTC1274 and LTC1277
are attractive new
converters. They bring new
levels of power savings,
performance and versatility
to the 12-bit 100ksps
ADC arena
LTC1277 
LOGIC INPUTS
 OPERATING SUPPLY WAKE-UP
NAP SLEEP MODE CURRENT TIME
1 1 ACTIVE 2mA —
0 1 NAP 160 µA 400ns
X 0 SLEEP 0.3 µA 4ms
Table 1. LTC1277 Shutdown Options
Linear Technology Magazine • February 1996
9
LTC1277 can prevent this waste if the
REFRDY output is tied to the NAP
input (see Figure 6). This connection
allows the device to go from Sleep
mode to Nap mode until the reference
is ready. REFRDY then releases the
ADC from Nap mode and the device is
ready to convert. Figure 6 shows how
the converter draws only 160µA dur-
ing the reference settling time instead
of the full 2mA current. This can cut
power dissipation by a factor of two to
four in applications where Sleep mode
is used.
Unbeatable AC and DC
The LTC1274 and LTC1277 bring
unusually high performance to the
100ksps speed range. They offer ex-
cellent DC and AC specifications and
an extremely linear, wideband sample-
and-hold, which is suitable for
undersampling. DC specifications
include maximum INL and DNL of
±1LSB with no missing codes guaran-
teed. Figure 7 shows a typical linearity
of far better than 12 bits (typically 14
bits). Drift of the internal reference is
30ppm/°C max.
AC specifications such as signal to
noise and distortion (SINAD) and THD
are specified at 71dB and 76dB
minimum. These are very good speci-
fications for a 12-bit ADC, but the
impressive thing is that they are speci-
fied at twice the Nyquist frequency.
This AC performance is made pos-
sible by an extremely linear, wideband
sample-and-hold design. Figure 8
shows a plot of the ADC performance
as the analog input frequency is in-
creased. This is the real test of a
sample-and-hold because, as the
input frequency increases, the
sample-and-hold must slew faster
without distortion in order to track
the signal accurately. Also, at high
input slew rates, any excess aperture
jitter of the sample-and-hold shows
up as a degradation of the noise floor.
As the Figure shows, the devices excel
in this area with good noise and dis-
tortion at 1, 2, 5 or even 10 times the
Nyquist frequency.
SLEEP POWER OFF POWER ON POWER OFF
CONVST
V
REF
REFRDY
Simplify the System Design
The new converters have both analog
and digital features that make them
easier to use and eliminate external
hardware.
SLEEP
NAPV
REF
10µFREFRDY
SLEEP
REFRDY
LTC1277
OUTPUT CODE
0
1.00
INTEGRAL NONLINEARITY ERROR (LSB)
0.50
0
0.50
1.00
512 1024 1536 2048 2560 3072 3584 4096
f
SAMPLE
= 100kHz
SLEEP
ADC CURRENT
DRAIN
SLEEP
0.3µANAP
160µAPOWER ON
2mA 0.3µA
CONVST
V
REF
REFRDY = NAP
Figure 5. On power-up from Sleep mode, the REFRDY signal indicates when the ADC’s
reference has fully awakened from sleep mode and is ready for conversions.
Figure 7. Typical linearity is better than 12
bits (typically 14 bits). Linearity is guaran-
teed to be
±
1LSB maximum over temperature.
Figure 8. The LTC1274/LTC1277 can
accurately sample very wideband input
signals. Their SINAD and THD are nearly
theoretical at up to five times Nyquist and
still usable at ten times Nyquist.
INPUT FREQUENCY (Hz)
0
90
2 X NYQUIST
80
70
60
50
30
40
10
20
SIGNAL/(NOISE + DISTORTION), SINAD, (dB)
2M10k 100k 1M
THD
SINAD
VIN = 0dB
VIN = 20dB
VIN = 60dB
fSAMPLE = 100kHz
5 X NYQUIST
10 X NYQUISTNYQUIST
DESIGN FEATURES
Figure 6. Tying the LTC1277’s NAP input to its REFRDY output saves
power by delaying the turn-on of power until the reference is settled.
10
Linear Technology Magazine • February 1996
Analog Flexibility
Figure 9 shows some of the analog
features of the ADCs. Both devices
contain a sample and hold. The
LTC1277 has a differential input that
allows the input range to be offset.
The input range for both converters
automatically switches from 0V–
4.096V unipolar with V
SS
grounded,
to ±2.048V bipolar when V
SS
is tied to
5V. The internal reference can be
overdriven with an external 2.5V ref-
erence to improve the full-scale
temperature coefficient. In bipolar
mode, the reference pin can be driven
with an op amp to provide a 2:1 AGC
function.
The analog inputs are high imped-
ance, making them easy to multiplex
with an inexpensive CMOS MUX. No
errors are caused because no DC
currents are drawn through the MUX’s
on resistance. The high-Z inputs also
eliminate the AC-coupling problems
found on competitive devices. (Many
of these other converters use inter-
nal, resistive level shifters to generate
bipolar input spans. These internal
resistors charge up the AC-coupling
cap and pull the input up toward full
scale; as a result, part of the signal
gets clipped.) To AC couple the
LTC1274 and LTC1277, simply use a
series C and an R to ground (or to
wherever you desire the DC level to
be) on the analog input.
Digital Simplicity
The digital interface is shown in Fig-
ure 10. In addition to the well known
microprocessor interface signals (CS,
RD, etc.), the LTC1274 and LTC1277
provide several new signals. A sepa-
rate convert-start input (CONVST)
allows operation from an external
sample clock, if desired. This frees
the microprocessor from having to
request conversions at precise sample
intervals, which is often impossible.
In this mode, the sample signal starts
a conversion. When it is complete, the
ADC interrupts the microprocessor
(with the BUSY signal) and the
microprocessor reads the data asyn-
AC COUPLING
CD4051
OR
LTC1391
Hi Z
MUXABLE
INPUT A
IN
+
A
IN
OFFSET
BIPOLAR
MODE
UNIPOLAR
MODE
V
REF
INTERNAL
REFERENCE
EXTERNAL
REFERENCE
2.5V TO 5V
2:1 AGC 
GAIN ADJUST
2.5V
–5V
V
SS
LTC1277
+
DATA
OUTPUTS
BUSY
V
LOGIC
REFRDY
8-BIT BUS (1277)
OR
12-BIT DATA (1274)
INTERRUPT TO µP
OR LATCH SIGNAL FOR
DATA OUTPUT
3V LOGIC INTERFACE
SUPPLY (1277)
CONVERSION READY
SIGNAL TO µP
f
s
CONVST
OPERATES FROM
EXTERNAL SAMPLE
CLOCK OR µP
Figure 9. Analog flexibility includes easy AC coupling and MUXing, offsetting the input span,
unipolar or bipolar inputs and a reference pin that can be overdriven.
chronously. Alternatively, CONVST
can be tied to RD, which allows the
microprocessor to read data and start
conversions in the old fashioned way.
Output data is available as a 12-bit
word (LTC1274) or as two 8-bit bytes
(LTC1277). Both converters have
BUSY signals that indicate when out-
put data is ready to be latched. An
output logic supply allows the
LTC1277 to interface directly to 3V
systems.
Conclusion
The LTC1274 and LTC1277 are at-
tractive new converters. They bring
new levels of power savings, perfor-
mance and versatility to the 12-bit
100ksps ADC arena. Their 10mW
power levels and novel shutdown
modes must be considered by power-
sensitive designers. The clean
wideband sampling capability and low
noise make them ideal for signal-
capture applications. And the flexible
feature set can simplify the system
design. These devices are a “must
see” for users of sampling ADCs.
DESIGN FEATURES
Figure 10. The digital hookup is simple, with
an external conversion start input, 8- or 12-
bit data outputs, data-ready signal (BUSY),
reference-ready signal (REFRDY) and a 3V
logic-interface supply (LTC1277).
Authors can be contacted
at (408) 432-1900
Linear Technology Magazine • February 1996
11
The LT1511 3A Battery Charger
Charges All Battery Types,
Including Lithium-Ion by Chiawei Liao
The LT1511 current mode PWM
battery charger is the simplest, most
efficient solution for fast charging
modern rechargeable batteries,
including lithium-ion (Li-Ion),
nickel-metal-hydride (NiMH) and
nickel-cadmium (NiCd) that require
constant-current and/or constant-
voltage charging. The internal switch
is capable of delivering 3A DC current
(4A peak current). Full charging cur-
rent can be programmed by resistors
or by a DAC to within 5%, and the
trickle charge current can be pro-
grammed to 10% accuracy. With
0.5% reference voltage accuracy,
the LT1511 meets the critical
+
+
+
+
+
V
SW
0.7V
1.5V
V
BAT
V
REF
V
C
GND
UV
SLOPE COMPENSATION
R2
R3
C1
PWM
B1
CA2
+
+
CA1
VA
+
+
+
6.7V
+
V
REF
2.465V
SHUTDOWN
200kHz
OSCILLATOR
S
R
R
R
R1
1k
R
PROG
V
CC
UV
OUT
V
CC
BOOST
SW
SENSE
SPIN
BAT
I
PROG
R
S3
R
S2
R
S1
I
BAT
0VP
BAT
PROG
I
PROG
I
BAT
= (I
PROG
)(R
S2
)
R
S1
C
PROG
75k
Q
SW
V
CC
g
m
= 0.64
+
CL1
CLP
100mV
CLN
COMP1
COMP2
+
=
(R
S3
= R
S2
)
2.465V
R
PROG
R
S2
R
S1
(())
Figure 1. LT1511 block diagram
DESIGN FEATURES
12
Linear Technology Magazine • February 1996
100mV
+
500
CLP
CLN
V
CC
UV
R5
LT1511
R6
1µF
+
R
S4
*
+
V
IN
CL1
AC ADAPTER
OUTPUT
*R
S4
= 100mV
ADAPTER CURRENT LIMIT
Figure 2. Adapter current limiting
Figure 3. PWM current programming
lower current, I
PROG
, fed into the PROG
pin. Amplifier CA2 compares the out-
put of CA1 with the programmed
current and drives the PWM loop to
force them to be equal. High DC accu-
racy is achieved with averaging
capacitor C
PROG
. Note that I
PROG
has
both AC and DC components. I
PROG
goes through R1 and generates a ramp
signal that is fed to the PWM control
comparator C1 through buffer B1 and
level-shift resistors R2 and R3, form-
ing the current mode inner loop. The
Boost pin drives the switch NPN Q
SW
into saturation and reduces power
loss. For batteries such as lithium-
ion that require both constant-current
and constant-voltage charging, the
0.5%, 2.465V reference and the am-
plifier VA reduce the charging current
when the battery voltage reaches the
preset level. For NiMH and NiCd, VA
can be used for overvoltage protec-
tion. When the input voltage is not
present, the charger goes into low
current (3µA typically) sleep mode as
the input drops 0.7V below the bat-
tery voltage. To shut down the charger,
simply pull the V
C
pin low with a
transistor.
Adapter Limiting
An important feature of the LT1511 is
the ability to automatically adjust
charging current to a level that avoids
overloading the wall adapter. This
allows the product to operate at the
same time that batteries are being
charged, without requiring complex
load-management algorithms. Addi-
tionally, batteries will automatically
be charged at the maximum possible
rate of which the adapter is capable.
This feature is created by sensing
total adapter output current and ad-
justing charging current downward if
a preset adapter-current limit is ex-
ceeded. True analog control is used,
with closed-loop feedback ensuring
that adapter load current remains
within limits. Amplifier CL1 in Figure
2 senses the voltage across R
S4
. When
this voltage exceeds 100mV, the am-
plifier will override the programmed
charging current and limit adapter
current to 100mV/R
S4
. A lowpass fil-
ter formed by 500 and 1µF is required
to eliminate switching noise.
Charging Current
Programming
The basic formula for charging cur-
rent is
I
BAT
= I
PROG
R
S2
R
S1
R
S2
R
S1
2.465V
R
PROG
=
where R
PROG
is the total resistance
from PROG pin to ground.
For example, 3A charging current
is needed. To have low power dissipa-
tion in R
S1
and enough signal to drive
the amplifier CA1, let R
S1
= 100mV/
3A = 0.0033. This limits R
S1
power
to 0.3W. Let R
PROG
= 5k, then
R
S2
= R
S3
= (I
BAT
)(R
PROG
)(R
S1
)
2.465V
(3A)(5k)(0.033)
2.465V
== 200
Charging current can also be pro-
grammed by pulse-width modulating
I
PROG
at a frequency higher than a few
kHz (Figure 3). Charging current will
be proportional to the duty cycle of
the switch, with full current at 100%
duty cycle.
PWM
R
PROG
4.7k
300
PROG
C
PROG
1µF
Q1
VN2222
5V
0V
LT1511
I
BAT
= (DC)(3A)
constant-voltage charging require-
ment for lithium cells.
The LT1511 is equipped with a
voltage-control loop to control charg-
ing voltage and a current-control loop
to control charging current. A third
control loop is provided to regulate
the current drawn from the AC
adapter. This allows simultaneous
equipment operation and battery
charging without overloading the
adapter. Charging current is reduced
to keep the adapter current within
specified levels.
The LT1511 can charge batteries
ranging from 1V to 20V. Ground sens-
ing of current is not required and the
battery’s negative terminal can be
tied directly to ground. A saturating
switch running at 200kHz gives high
charging efficiency and small induc-
tor size. A blocking diode is not
required between the chip and the
battery because the chip goes into
sleep mode and drains only 3µA when
the wall adapter is unplugged. Soft-
start and shutdown features are also
provided. The LT1511 is available in
a 24-pin fused-lead power SO wide
package with a thermal resistance of
30°C/W.
Operation
The LT1511 is a current mode PWM
step-down (buck) switcher. The DC
battery-charging current is pro-
grammed by a resistor, R
PROG
(or by a
DAC output current), at the PROG
pin (see the block diagram in Figure
1). Amplifier CA1 converts the charg-
ing current through R
S1
to a much
DESIGN FEATURES
Linear Technology Magazine • February 1996
13
R2
5.49k
R1
49.3k
1k
PROG
0.33µFQ1
VN2222
LT1511
Lithium-Ion Charging
The 3A lithium battery charger (Fig-
ure 4) charges lithium-ion batteries
at a constant 3A until the battery
voltage reaches a limit set by R3 and
R4. The charger will then automati-
cally go into a constant-voltage mode,
with the current decreasing to zero
over time as the battery reaches full
charge. This is the normal regimen
for lithium-ion charging, with the
charger holding the battery at “float”
voltage indefinitely. In this case no
external sensing of full charge is
needed.
Current though the R3/R4 divider
is set at 15µA to minimize battery
drain when the charger is off. The
input current to the OVP pin is 3nA
and this error can be neglected.
With divider current set at 15µA,
R4 = 2.465/15mA = 162k and
R3 = (R4)(V
BAT
2.465) 162k(8.4 2.465)
2.465 2.465
= 390k
=
Lithium-ion batteries typically re-
quire float-voltage accuracy of 1% to
2%. The accuracy of the LT1511 OVP
voltage is ±0.5% at 25°C and ±1% over
full temperature. This leads to the
possibility that very accurate (0.1%)
resistors might be needed for R3 and
R4. Actually, the temperature of the
LT1511 will rarely exceed 50°C in
float mode because charging currents
have tapered off to a low level, so
0.25% will normally provide the re-
quired level of overall accuracy.
Nickel-Cadmium and Nickel-
Metal-Hydride Charging
The circuit in the 3A lithium battery
charger (Figure 4) can be modified as
shown in Figure 5 to charge NiCd or
NiMH batteries. For example, two-
level charging is needed; 2A when Q1
is on and 200mA when Q1 is off. For
2A full current, the current sense
resistor (R
S1
) should be increased to
0.05, so that enough signal (10mV)
will be across R
S1
at 0.2A trickle charge
to keep charging current accurate.
For a two-level charger, R1 and R2
are found from
R1 = R2 =
(2.465)(4000) (2.465)(4000)
I
LOW
I
HI
I
LOW
All battery chargers with fast charge
rates require some means to detect
the full-charge state in the battery in
order to terminate the high charging
current. NiCd batteries are typically
charged at high current until tem-
perature rise or battery voltage
decrease is detected as an indication
of nearly full charge. The charging
current is then reduced to a much
lower value and maintained as a con- Figure 5. 2-step charging
SW
BOOST
COMP1
CLN
UV
PROG
V
C
OVP SENSE BAT
C1
1µF
R
S4
ADAPTER CURRENT SENSE
R7
500
R5
UNDERVOLTAGE LOCKOUT
R6
5k
D
IN
V
IN
(ADAPTER INPUT)
11V TO 25V
V
BAT
10µF
+
C
PROG
1µF
C
IN
*
10µF
+
300R
PROG
4.93k
1%
0.33µF
1k
0.47µF
R
S3
200
1%
R
S2
200
1%
L1**
10µH
D2
1N4148 200pF
R
S1
0.033
BATTERY CURRENT
SENSE
R3
390k
0.25%
BATTERY 
VOLTAGE SENSE
R4
162k
0.25%
50pF
C
OUT
22µF
TANT
+
4.2V
4.2V
+
+
LT1511
NOTE: COMPLETE LITHIUM-ION CHARGER,
NO TERMINATION REQUIRED. R
S4
, R7 
AND C1 ARE OPTIONAL FOR I
IN
LIMITING
*TOKIN 25V CERAMIC SURFACE MOUNT
**10µH COILTRONICS CTX10-4
CONSULT LT1151 DATA SHEET FOR R5 VALUE
V
CC
TO MAIN SYSTEM POWER
SPIN
D1
MBR340
GND CLP
2 Li-Ion
Figure 4. 3 Amp lithium-ion battery charger
stant trickle charge. An intermediate
“top off” current may be used for a
fixed time period to reduce 100%
charge time.
NiMH batteries are similar in chem-
istry to NiCd but have two differences
related to charging. First, the inflec-
tion characteristic in battery voltage
as full charge is approached is not
nearly as pronounced. This makes it
more difficult to use dV/dt as an
indicator of full charge, and tempera-
ture change is more often used, with
a temperature sensor in the battery
pack. Second, constant trickle charge
may not be recommended. Instead, a
moderate level of current is used on a
pulse basis (1% to 5% duty cycle) with
the time-averaged value substituting
for a constant low trickle.
If overvoltage protection is needed,
R3 and R4 should be calculated ac-
cording to the procedure described in
lithium-ion charging section. The OVP
DESIGN FEATURES
continued on page 22
14
Linear Technology Magazine • February 1996
LTC1520 High Speed Line Receiver
Provides Precision Propagation Delay
and Skew by Victor Fleury
Introduction
The LTC1520 is a 50Mbit/s, low
power, precision quad line receiver
that translates differential input sig-
nals into CMOS/TTL output logic
levels. The receivers employ a unique
architecture that guarantees excel-
lent performance over process and
temperature, with propagation delay
of 18ns ±2ns. The architecture af-
fords low same-channel skew (|t
PHL
-
t
PLH
| < 600ps), and low channel-to-
channel propagation-delay variation
(< 600ps). A new short-circuit detec-
tion technique permits indefinite
shorts to power or ground.
Circuit Description
Short-channel CMOS circuitry typi-
cally has very wide performance
variations. This is due in part to the
large percentage variation in channel
length and to second-order mobility
and threshold effects. Increasing
channel length not only decreases
the drive capability of CMOS devices,
but also increases the devices’ gate
capacitance (less current charging
more capacitance). In effect, we see
CMOS propagation delays varying as
L
2
(square of the channel length). For
example, the propagation delay of
typical CMOS line receivers can vary
as much as 500% over process and
temperature. In applications where
high speed clock and data waveforms
are sent over long distances, propa-
gation delay and skew uncertainties
pose system design constraints. The
LTC1520 addresses this problem. The
propagation delays change by ±20%,
a better than 10 times performance
improvement.
The design was fabricated using
Linear Technology’s high performance
CMOS process. The CMOS design
makes it possible to achieve high speed
and low DC power consumption with-
out sacrificing ruggedness against
overload or ESD damage. CMOS also
allows for tighter propagation-delay
skew. Figure 1 shows a block diagram
of the LTC1520 signal path. The in-
put differential pair amplifies the
minimum 500mV (at speed) input
signal level. Note the input resistor
network, which expands the input
common mode range (the LTC1520
has an input common mode range
extending from 0V to 5V, whereas the
LTC1518 and LTC1519 are future
products that will have an input com-
mon mode range from7V to +12V).
The output is fed into another differ-
ential amplifier that switches a
specified amount of current into its
load capacitance. These two stages
must have enough gain to switch all
the available current. The output of
the second stage is a valid logic level
that feeds inverters.
High Data Rates
The LTC1520 can propagate pulses
(Figure 2) of shorter duration than its
propagation delay (20ns maximum).
To obtain this high data rate (through-
put), it is necessary to distribute the
total propagation delay as evenly as
possible between the stages. This al-
lows rail-to-rail swing at the output of
each stage. For example, if the output
of the second stage has a 3V to 5V
output swing, the succeeding inverter
will never trip high. The minimum
number of stages is also limited by
the maximum rise/fall times allowed
at the output (~3.5ns). However, the
+
+
IN+
V
CC
DIFF
BIAS 4BIASTRIM
+
GM OUT OUTPUT
IN
V
CC
PROPTRIM
3
Figure 1. LTC1520 block diagram
DESIGN FEATURES
Linear Technology Magazine • February 1996
15
maximum number of stages is limited
by the maximum propagation delay
(latency).
Consistent
Propagation Delay
The inherent temperature and pro-
cess tolerance, along with bias and
delay trimming, make it possible to
guarantee a propagation delay win-
dow more than an order of magnitude
tighter than that of the typical CMOS
line receiver.
Temperature Stability
For large V
GS
and a given channel
length, the propagation delay of in-
verters increases with temperature.
To keep temperature stability, the
first two stages must have a delay
that decreases with temperature. This
was accomplished via a current source
whose current is inversely pro-
portional to mobility. Therefore,
with increasing temperatures, the
inverter’s delay goes up as the delays
of the first two stages go down.
Process Tolerance
At a given temperature and V
GS
, the
inverter delays vary as µC
OX
W/L. The
delays of the first and second stages
vary inversely with µC
OX
W/L. The
effect of process variations on total
propagation delay are canceled out to
the extent that we are able to match
the µC
OX
W/L of the bias, inverters
and differential stages. We include
trims in both the bias network and in
the signal path. For short channel
length processes, we add capacitance
evenly between one inverter and the
second differential stage to maintain
temperature stability.
Low Skew
Skew is typically caused by the un-
equal charging versus discharging of
both internal and external capaci-
tances. Unequal excitation of high
frequency zeroes also contributes to
skew. Therefore, it is necessary to
keep the signal in differential form as
much as possible. The first stage is
differential-in/differential-out. It
switches a multiple of the tail current
into its capacitive load. Two differen-
tial stages are used to maintain
charging versus discharging symme-
try and to equalize feedthrough effects.
Figure 3 shows two adjacent channels.
Low Overshoot
The LTC1520 can achieve maximum
speeds with all four receivers operat-
ing simultaneously (500mV input
differential signal), while maintain-
ing low output overshoot. Small
on-chip resistors help mitigate the
effect of parasitic bond wire and lead-
frame inductances. Note that the
system designer also needs to mini-
mize printed circuit board parasitic
inductances by placing surface mount
ceramic bypass capacitors very close
to the LTC1520. Low overshoot and
ringing is desirable to reduce electro-
magnetic interference.
Short-Circuit Protection
and Automatic Reset
Typical foldback short-circuit protec-
tion can lead to oscillation, slower
rise/fall times and exaggerated skew.
This family’s novel short-circuit pro-
tection method avoids these problems
by sensing the output voltage. If the
output remains in the wrong state for
longer than about 60ns, the output is
shut off and a small, known current
(~20mA, positive or negative, depend-
ing on V
CC
/Gnd short) is dumped into
the output. The circuit then detects
when the short is removed and takes
itself out of short-circuit mode. This
avoids having to power the part up/
down after detecting a short.
NOTE: STUBS CONNECTED TO R
T
MUST BE EQUIDISTANT AND SHORT.
MC10116
TWISTED PAIR
5V
100
100
100
100
120R
T
1/4
LTC1520
1/4
LTC1520
1/4
LTC1520
5V
5V
Figure 2. Typical propagation delay: V
IN
=
500mV, 15ns pulse width Figure 3. Typical channel-to-channel
propagation delay is <600ps. (Two channels
are overlaid here; the differences cannot be
distinguished on this oscillograph.)
Figure 4. Typical LTC1520 application
DESIGN FEATURES
continued on page 23
5ns/DIV
16
Linear Technology Magazine • February 1996
The LTC1446 and LTC1446L:
World’s First Dual 12-Bit DACs
in SO-8 Packages by Hassan Malik and
Jim Brubaker
Dual 12-Bit Rail-to-Rail
Performance in a Tiny SO-8
The LTC1446 and LTC1446L are dual
12-bit, single-supply, rail-to-rail
voltage output digital-to-analog con-
verters. Both of these parts include
an internal reference and two DACs
with rail-to-rail output buffer amplifi-
ers, packed in a small, space-saving
8-pin SO or PDIP package. These are
12-bit monotonic DACs with DNL
guaranteed to be less than 0.5LSB.
They have an easy-to-use SPI-com-
patible interface, with a digital output
pin that allows several DACs to be
daisy-chained to save board space. A
power-on reset initializes the outputs
to zero-scale at power-up.
The LTC1446 has an output swing
of 0V to 4.095V, making each LSB
equal to 1mV. It operates from a single
4.5V to 5.5V supply, dissipating
3.5mW (I
CC
typical = 700µA). The
LTC1446L has an output swing of 0V
to 2.5V. It can operate on a single
supply with a wide range of 2.7V to
5.5V. It dissipates 1.35mW (I
CC
typi-
cal = 450µA) at a 3V supply.
Circuit Topology
Complete Stand-Alone
Performance
Figure 1 shows a block and pin dia-
gram of the LTC1446 and LTC1446L.
Both parts have rail-to-rail output
buffer amplifiers and an internal ref-
erence, offering the user convenient
stand-alone performance. The data
inputs for both DAC A and DAC B are
clocked into one 24-bit shift register.
The first 12-bit segment is for DAC A
and the second is for DAC B. The MSB
is loaded first and LSB last in both of
these 12-bit segments. The data is
latched into the shift register on the
rising edge of clock. The clock pin has
a hysteresis of about 150mV to make
it less sensitive to noise. When all the
data has been shifted in, it is loaded
into the DAC registers when CS/LD
goes high. This also updates both 12-
bit DACs and internally disables the
CLK signal. Data in the 24-bit shift
register is also available on the D
OUT
pin, allowing the user to daisy-chain
several DACs together. An internal
power-on reset clears the shift regis-
+
24-BIT
SHIFT
REGISTER
POWER ON
RESET
DAC
B
REGISTER
LD
DAC
A
REGISTER
LD
REFERENCE
8
12-BIT
DAC-B V
OUTB
7V
CC
+
5
12-BIT
DAC-A V
OUTA
6 GND
1CLK
2D
IN
4D
OUT
3CS/LD
Figure 1. 12-bit rail-to-rail performance in an SO-8 package
DESIGN FEATURES
Linear Technology Magazine • February 1996
17
ters and DAC registers to all zeros
and forces both the buffer amplifier
outputs to zero-scale. The LTC1446L
has an internal reference of 1.22V
and the amplifier gain is about 2.05,
giving a convenient full scale of 2.5V.
The LTC1446 reference is 2.048V and
the amplifier gain is 2.0, giving it a full
scale of 4.095V.
Patented Architecture
Guarantees Monotonicity
The LTC1446 family uses a propri-
etary architecture that was first used
in the LTC1257 and is described in
more detail in Volume III, Number 3 of
Linear Technology. This novel archi-
tecture is inherently monotonic and
has excellent 12-bit DNL, with a maxi-
mum specification of 0.5LSB.
LTC1296
V
CC
50k
74HC04
5V
5V
CS
22µF
µPCLK
8 ANALOG
INPUT CHANNELS
D
OUT
D
IN
CH0
COM
SSO REF
CH7
REF+
50k
0.1µF
100
100
LTC1446
CS/LD
CLK
D
OUT
D
IN
V
OUTB
GND
V
CC
V
OUTA
0.1µF
0.1µF
Figure 2. Typical application for the LTC1446L or LTC1446
Figure 3. An autoranging 8-channel ADC with shutdown
LTC1446L/1446
CLK LTC1446L: 0V TO 2.5V
LTC1446: 0V TO 4.095V
LTC1446L: 2.7V TO 5.5V
LTC1446: 4.5V TO 5.5V
LTC1446L: 0V TO 2.5V
LTC1446: 0V TO 4.095V
0.1µF
µP
CS/LD
D
IN
D
OUT
V
OUTB
GND
V
CC
V
OUTA
High Performance
Rail-to-Rail Buffers
The rail-to-rail amplifiers on these
parts can swing to within a few milli-
volts of either rail when unloaded,
giving them true rail-to-rail perfor-
mance. When swinging close to the
rails, the effective output impedance
is about 50. The op amps are ca-
pable of sinking or sourcing over 5mA
at a 5V supply. The mid-scale glitch at
the output is 20nV-s and the digital
feedthrough is a negligible 0.15nV-s.
DESIGN FEATURES
continued on page 23
The LTC1446 and
LTC1446L are the world’s
only DACs that offer dual
12-bit stand-alone
performance in an 8-pin
SO or PDIP package.
…these DACs
do not compromise
on performance…
A Wide Range of Applications
Some of the typical applications for
these parts include digital calibra-
tion, industrial process control,
automatic test equipment, cellular
telephones and portable, battery-pow-
ered applications. Figure 2 shows how
these parts are typically used.
An Autoranging 8-Channel
ADC with Shutdown
Figure 3 shows how to use one
LTC1446 to make an autoranging
ADC. The microprocessor sets the
reference span and the common pin
for the analog input by loading the
appropriate digital code into the
LTC1446. V
OUT A
controls the com-
mon pin for the analog inputs to the
LTC1296 and V
OUT B
controls the ref-
erence span by setting the REF+ pin
on the LTC1296. The LTC1296 has a
shutdown pin that goes low in shut-
down mode. This will turn off the PNP
transistor supplying power to the
LTC1446. The resistor and capacitor
on the LTC1446 outputs act as a
lowpass filter for noise.
18
Linear Technology Magazine • February 1996
LT1490/LT1491 Over-the-Top
Dual and Quad Micropower
Rail-to-Rail Op Amps by Jim Coelho-Sousae
Introduction
The LT1490 is Linear Technology’s
lowest power, lowest cost and small-
est dual rail-to-rail input and output
operational amplifier. The ability to
operate with its inputs above V
CC
, its
high performance-to-price ratio and
its availability in the MSOP package,
sets the LT1490 apart from other
amplifiers. A unique input stage al-
lows the LT1490 to operate with input
common mode voltages up to 30V
above the positive supply. The LT1490
has a quiescent current of less than
50µA per amplifier, and can operate
with supply voltages from 2.5V to
44V. The ability to withstand reverse
supply voltages of up to 25V is an-
other unique feature of the LT1490.
For single 5V supply operation, typi-
cal specifications include 300µV input
offset voltage, 3nA input bias cur-
rent, 200pA input offset current,
open-loop voltage gain of one million
into a 10k load, 0.07V/µs slew rate,
100dB common mode rejection ratio
and 98dB power supply rejection ra-
tio. The output can swing to within
22mV of either rail with no load. The
output current drive is typically
±20mA, and the part is stable with
capacitive loads of up to 5000pF.
Additional performance specifications
are shown in Table 1.
The LT1490 dual is available with
industry-standard pinout in 8-pin
MSOP, 8-pin SO or 8-pin mini-DIP
packages. The LT1491 quad is avail-
able with industry-standard pinout
in 14-pin SO or 14-pin mini-DIP
packages.
Going Over the Top
Key to the unique operation of the
LT1490 is the input stage, shown in
Figure 1. Similar to other rail-to-rail
op amps, the LT1490 uses two input
stages to achieve input rail-to-rail
operation. Device Q7 controls which
stage is active by steering the tail
current between the two stages as a
function of the input common mode
voltage. The LT1490 has three modes
of operation.
Mode 1: V
EE
< V
CM
< V
CC
1V
For input common mode voltages
between V
EE
and V
CC
1V, the PNP
stage (Q5–Q6) is active, and Q7 and
the NPN stage (Q1–Q4) are off. Since
Q7 is off, 2µA of current flows through
Q5–Q6. The input bias current is the
base current of Q5 or Q6, typically
4nA, as shown in Figure 2. The input
offset voltage for this stage is trimmed
to less than 300µV.
Mode 2: V
CC
1V < V
CM
< V
CC
When the input common mode volt-
age reaches V
CC
1V, Q7 turns on,
diverting the current from Q5–Q6 to
the NPN stage. When the PNP stage is
completely off, 2µA flows through the
2× current mirror D3–Q8. The 4µA
current through Q8 sets the bias for
the NPN input stage. In this mode,
Q1–Q2 act as emitter followers, driv-
ing a differential amplifier formed by
Q3–Q4. The input bias current for
this mode of operation is the base
current of Q1 or Q2, typically 20nA.
When the common mode voltage
reaches V
CC
0.2V, Q1–Q2 begin to
saturate due to the forward voltage of
D1–D2, as shown in Figure 2. This
DESIGN FEATURES
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CC
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MC
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EE
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CC
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V=
EE
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EE
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Linear Technology Magazine • February 1996
19
causes the input bias current to in-
crease. At V
CM
= V
CC
the input bias
current is typically 200nA. The input
offset voltage of the NPN stage is not
trimmed, but is typically 600µV.
Mode 3: V
CC
< V
CM
< V
CC
+ 44V
As Figure 2 shows, when V
CM
= V
CC
the NPN input stage is beginning to
saturate but is not yet fully satu-
rated. When V
CM
is approximately
equal to V
CC
+ 0.2V, Schottky diodes
D1–D2 reverse bias, causing Q1–Q2
to fully saturate. In this condition,
the base current of Q1–Q2 is equal to
the emitter current, typically 4µA.
The Schottkys, in combination with
special geometries for the input de-
vices Q1–Q2, are the key to the unique
above-the-rail operation of the
LT1490. The input offset voltage for
this mode of operation is typically
600µV.
Reverse Battery Protection
The LT1490 can withstand reverse
supply voltages of up to 25V. The
inputs are also protected for excur-
sions below V
EE
. The protection
consists of a 1k resistor in series with
each input, which limits the current
through the associated substrate di-
ode. The part will not be damaged if
the current through the substrate
diode is less than 10mA.
An Over-the-Top Application
The battery current monitor circuit
shown in Figure 3 demonstrates the
LT1491’s ability to operate with its
inputs above the positive supply rail.
COMMON MODE VOLTAGE (V)
–10nA
20nA
10nA
0nA
30nA
4µA
2µA
6µA
INPUT BIAS CURRENT
5.63.8 4.0 4.2 4.4 4.8 5.0 5.2 5.44.6
MODE 3
MODE 1
MODE 2
V
S
= 5V, 0V
Q1
D3
TO SECOND STAGE
V
EE
Q4 Q7
Q5
1k
–IN
V
CC
D1 D2 2µA
Q3 V
CC
1.0V
Q2 Q6
Q8
1k
+IN
In this application, a conventional
amplifier would be limited to a battery
voltage between 5V and ground, but
the LT1491 can handle battery volt-
ages as high as 44V. The LT1491 can
be shut down by removing V
CC
. With
V
CC
removed the input leakage is less
than 0.1nA. No damage to the LT1491
will result from inserting the 12V
battery backward.
When the battery is charging, Amp
B senses the voltage drop across RS.
The output of Amp B causes QB to
drain sufficient current through RB
to balance the inputs of Amp B. Like-
wise, Amp A and QA form a closed
loop when the battery is discharging.
The current through QA or QB is
proportional to the current in RS; this
current flows into RG, which converts
it back to a voltage. Amp D buffers
and amplifies the voltage across RG.
Amp C compares the output of Amp A
+
+
1/4
LT1491
A
+
1/4
LT1491
C
RA
2k
RS
0.2
QA
CHARGER
VOLTAGE
V
BATTERY
= 12V
V
SUPPLY
= 5V, 0V
LOGIC
RA'
2k
+
1/4
LT1491
B
+
1/4
LT1491
D
RB
2k
RB'
2k
90.9k
R
L
RG
10k
10k
S1 S1 = OPEN, GAIN = 1
S1 = CLOSED, GAIN = 10
LOGIC HIGH (5V) = CHARGING
LOGIC LOW (0V) = DISCHARGING
NOTE: RA = RB
QB
V
OUT
V
OUT
RS RG/RA GAIN
V
OUT
GAIN
()
()
(
)
I
BATTERY
= = AMPS
Figure 1. LT1490 input stage
Figure 2. Input bias current characteristics
over all three modes of operation
Figure 3. LT1491 battery current monitor—an “over-the-top” application
DESIGN FEATURES
continued on page 22
20
Linear Technology Magazine • February 1996
LT1512/LT1513 Battery Chargers
Operate with Input Voltages Above or
Below the Battery Voltage by Bob Essaff
Introduction
The LT1512 and LT1513 form a
unique family of constant-current,
constant-voltage battery chargers that
can charge batteries from input volt-
ages above or below the battery
voltage. This feature can help sim-
plify system design and add product
flexibility by allowing battery charg-
ing from multiple sources, such as a
wall adapter, a 12V automotive sys-
tem or a 5V power supply, all with the
same circuit. The constant-current,
constant-voltage architecture makes
the LT1512 and LT1513 well suited
for charging NiCd, NiMH, lead-acid or
lithium-ion batteries.
Both devices are current mode
switching regulators that operate at a
fixed frequency of 500kHz. Product
features include a ±1% reference-volt-
age tolerance, 2.7V minimum input
voltage, easy external synchroniza-
tion and 12µA supply current in
shutdown mode. The LT1512 and
LT1513 also include low loss on-chip
power switches rated for 1.5 Amps
and 3 Amps respectively. High fre-
quency switching allows the use of
small surface mount inductors and
capacitors, and the battery can be
directly grounded.
Operation
The LT1512 and LT1513 are specifi-
cally optimized to use the SEPIC
converter topology, which is shown in
Figure 1’s typical application. The
SEPIC (single-ended primary induc-
tance converter) topology has several
advantages for battery-charging ap-
one inductor core, although two sepa-
rate inductors can be used.
The topology is essentially identi-
cal to a 1:1 transformer-flyback circuit
except for the addition of capacitor
C2, which forces identical AC volt-
ages across both windings. This
capacitor performs three tasks: it
eliminates the power loss and voltage
spikes usually caused by a flyback-
converter’s leakage inductance; it
forces the input current and the cur-
rent in resistor R3 to be a triangle
wave riding on top of a DC component
instead of forming a large amplitude
square wave; and it eliminates the
voltage spikes across the output di-
ode when the switch turns on.
When the battery is below its float
voltage, set by R1 and R2, the charger
is in the constant-current mode. The
suggested value for R2 is 12.4k. R1 is
calculated from:
R1 = V
OUT
1.245
1.245
R2 + (3 × 10
7
)
where V
OUT
= battery float voltage
Charging current in the battery,
which also flows through R3, devel-
ops a voltage on the I
FB
pin. The I
FB
pin’s 100mV sense voltage sets the
LT1512
CHARGE
SHUTDOWN I
FB
V
C
V
IN
L1A*
L1B*
0.5A
13
2
8
5
4
76
GND
V
FB
V
SW
WALL
ADAPTER
INPUT
S/S
C3
22µF
25V
C2**
1µF
× 2
C5
0.1µF
*
**
L1A, L1B ARE TWO 33µH WINDINGS ON A
COMMON CORE: COILTRONICS CTX33-3
AVX1206Y2105KAT1A
C4
0.1µF
R4
24
+
R1
R2
R3
0.2
C1
22µF
25V
+
D1
MBRS130LT3
INDUCTOR = 33µH
LT1513
LT1512
INPUT VOLTAGE (V)
0
1.2
1.0
0.8
0.6
0.4
0.2
1.4
1.6
2.0
1.8
2.2
2.4
CURRENT (A)
300 5 10 20 2515
SINGLE LITHIUM 
CELL (4.1V)
SINGLE LITHIUM 
CELL (4.1V)
DOUBLE LITHIUM 
CELL (8.2V)
DOUBLE LITHIUM 
CELL (8.2V)
Figure 1. Battery charger with 0.5A output current
Figure 2. Maximum charging current
DESIGN FEATURES
The LT1512 and LT1513
form a unique family of
constant-current, constant-
voltage battery chargers
that can charge batteries
from input voltages above or
below the battery voltage.
This feature can help
simplify system design and
add product flexibility…
plications. It will operate with input
voltages above or below the battery
voltage, has no path for battery
discharge when turned off, and elimi-
nates the snubber losses of flyback
designs. It also has a current sense
point that is ground referred and need
not be connected directly to the bat-
tery. The two inductors shown are
actually two identical windings on
Linear Technology Magazine • February 1996
21
programmed charging current to I
CHG
= 100mV/R3. The RC filter formed by
R4 and C4 smoothes the signal pre-
sented to the I
FB
pin.
Charging current remains constant
until the battery reaches its float volt-
age, at which point the LT1512/
LT1513 changes to the constant-
voltage mode. In this mode, the
charging current will taper off as re-
quired to keep the battery at its float
voltage. The circuit’s maximum in-
put voltage is partly determined by
the battery voltage. When the switch
is off, the voltage on the V
SW
pin is
equal to the input voltage, which is
stored across C2, plus the battery
voltage. Both the LT1512 and LT1513
have a maximum input voltage rating
of 30V and a maximum rated switch
voltage of 35V, thereby limiting input
voltage to 30V or 35V minus the bat-
tery voltage, whichever is less.
Figure 2 shows the maximum avail-
able charging current for a single-cell
or double-cell lithium battery pack.
Note that the actual programmed
charging current will be independent
of the input voltage if it does not
exceed the values shown.
Figure 4. Shutdown controlled disconnect
LT1512
I
FB
V
C
V
IN
L1A
L1B
13
2
8
5
4
76
GND
V
FB
V
SW
V
IN
S/S
22µF
25V
C2
1µF
× 2
0.47µF
Q1 = SILICONIX Si9410DY
C2 = AVX1206Y2105KAT1A
0.1µF
24
+
R3B
0.24
R1
R2
Q1
R3A
2
C1
22µF
25V
+
MBRS130LT3
HI CHARGE
LOW CHARGE
CHARGE
SHUTDOWN
Figure 3. 50mA/400mA programmable battery charger
LT1512/LT1513
CHARGE
SHUTDOWN
GND
VFB
S/S
R1
Q1
VN2222
BATTERY
R2
Programming
the Charge Current
As mentioned earlier, charging cur-
rent is set by R3, where I
CHG
= 100mV/
R3. The charge current is programmed
by changing the effective value of R3,
as shown in Figure 3. In the low
charge mode, Q1 is off, setting charge
current to I
CHG LOW
= 100mV/R3A, or
100mV/2 = 50mA. In the high-
charge mode, Q1 is on, and charge
current is I
CHG HI
= 100mV/R3A +
100mV/(R3B + Q1’s R
DS(ON)
), or
100mV/2 + 100mV/(0.24 + 0.04))
= 50mA + 357mA = 407mA. Note that
Q1’s R
DS(ON)
is a factor in the high-
charge mode, requiring the use of a
low R
DS(ON)
FET.
Off-State Leakage
Charging can be terminated by placing
the LT1512/LT1513 into shutdown
mode. If the battery remains con-
nected to the charger when in the off
state, two leakage paths that load the
battery must be considered.
The first is the 100µA resistor-
divider feedback current that flows
through R1 and R2. This current can
be eliminated with the addition of a
FET, Q1, between R1 and the R2/V
FB
junction, as shown in Figure 4. In this
example, pulling the charge/shut-
down input above 3.75V will activate
charging and turn on Q1, whereas
driving the charge/shutdown input
below 0.6V will shut down the
LT1512/LT1513 and turn off Q1.
The second leakage path to con-
sider is in the output diode, D1 (Figure
1). When the charger is in the off
state, the output diode sees a reverse
voltage equal to the battery voltage.
Though the Schottky diode reverse
leakage may typically be only 10µA,
its guaranteed specifications are
much worse, up to 1mA. One solution
is to change the output diode to an
ultra-fast silicon diode, such as an
MUR-110. The higher forward voltage
of the silicon diode will decrease the
circuit’s efficiency, but these diodes
have reverse leakage specifications
below 5µA.
Conclusion
With the ability to operate from input
voltages above or below the battery
voltage, the LT1512 and LT1513 bat-
tery chargers offer increased flexibility
for portable systems.
DESIGN FEATURES
Authors can be contacted
at (408) 432-1900
22
Linear Technology Magazine • February 1996
The POR output can also help stage
output voltages. For example, if the
auxiliary regulator is on in Figure 5,
the 2.9V output will come up simulta-
neously with the 3.3V output. In other
applications, however, the POR out-
put could be used to hold the AUX ON
pin low, thus delaying the auxiliary
start-up until POR releases.
EXT V
CC
Pin
Reduces Quiescent Current
Power for the top and bottom MOS-
FET drivers and for most of the other
control circuitry is derived from the
INT V
CC
pin. When the EXT V
CC
pin is
open or at a low voltage, an internal
5V low dropout regulator supplies
INT V
CC
power from V
IN
. If EXT V
CC
is
taken above 4.7V, the 5V regulator is
In this issue we introduce the
LTC1439. This IC is a constant-fre-
quency, synchronous, triple output
DC/DC converter optimized for bat-
tery operated applications. The part
(and its brethren) are the next-gen-
eration of ICs designed for the rapidly
expanding portable computer and
equipment marketplace. These de-
Editor's Page, continued from page 2
and Amp B to determine the polarity
of the current through RS. The scale
factor for V
OUT
with S1 open is 1V/A.
With S1 closed the scale factor is 1V/
100mA, and current as low as 5mA
can be measured.
Conclusion
The LT1490 provides features not
previously available in an operational
amplifier. The combination of “Over-
the-Top” operation, reverse battery
protection, micropower operation and
MSOP package enables the LT1490/
LT1491 to solve application problems
beyond the reach of previous opera-
tional amplifiers.
LT1490, continued from page 19
turned off and an internal switch is
turned on to connect EXT V
CC
to INT
V
CC
.
The EXT V
CC
pin is normally con-
nected to the 5V output to allow INT
V
CC
power to be derived from the
regulator itself. Quiescent current is
then reduced because driver and con-
trol currents are scaled by a factor
approximately equal to the 5V con-
troller duty cycle. EXT V
CC
can also be
connected to other external high effi-
ciency sources, up to a maximum of
10V.
In addition to the other features
discussed above, most versions of the
LTC143X family also contain an un-
committed comparator referenced to
1.19V with an open-drain output pin,
useful in a wide variety of applica-
tions. The auxiliary regulator error
amplifier is also usable as a second
comparator.
Conclusion
The LTC1435–LTC1439 multiple out-
put DC/DC controllers offer a
tremendous amount of flexibility and
functionality while removing many of
the trade-offs that previously existed
in battery-powered supplies. With
these new controllers it is possible to
have high efficiency and low quies-
cent current without giving up
constant frequency operation, and to
have low dropout without giving up
N-channel MOSFETs. The wide vari-
ety of output voltage and current levels
achievable using minimum magnet-
ics makes these parts the logical
choice for next-generation designs.
DESIGN FEATURES
LTC1435–LTC1439, continued from page 6
pin should be grounded if not used.
When a microprocessor DAC output
is used to control charging current, it
must be capable of sinking current at
a compliance up to 2.5V if connected
directly to the PROG pin.
Conclusion
The LT1511 is a simple, cost effective
solution for charging batteries at cur-
rents of up to 3A. Battery packs
ranging from 1V to 20V can
be charged, independent of their
chemistry.
LT1511, continued from page 13
vices were developed in conjunction
with many customers and incorpo-
rate many requested features. We
continue to highlight new products in
the Design Features section. In this
issue, we spotlight several new bat-
tery-charging products, including the
LT1511, LT1512 and LT1513. Also
featured are some new converter
products, the LTC1446 and
LTC1446L D-to-A converters, and the
LTC1277 and LTC1273 A-to-D con-
verters. Many other products are
introduced in this issue. We also in-
clude our usual complement of circuit
ideas and applications.
…a royally screwed-up circuit
represents a learning opportunity…
—Derek Bowers
A circuit always works the way it is
supposed to. It never disobeys any
laws of physics…
—Tom Fredericksen
The circuit doesn’t care about fair.
—Jim Williams
There is always a way out.
—George Philbrick
From Analog Circuit Design:
Art, Science and Personalities.
Edited by Jim Williams. Butterworth-
Hienemann, 1991.