TC74AC161,163P/F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC161P,TC74AC161F,TC74AC161FT TC74AC163P,TC74AC163F,TC74AC163FT Synchronous Presettable 4-Bit Binary Counter TC74AC161P/F/FT Asynchronous Clear TC74AC163P/F/FT Synchronous Clear TC74AC161P, TC74AC163P The TC74AC161 and 163 are advanced high speed CMOS SYNCHRONOUS PRESETTABLE COUNTERs fabricated with silicon gate and double-layer metal wiring C2MOS technology. They achieve the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The CK input is active on the rising edge. Both LOAD and CLR inputs are active on low logic level. Presetting of these IC's is synchronous to the rising edge of CK. The clear function of the TC74AC163 is synchronous to CK, while the TC74AC161 are cleared asynchronously. Two enable inputs (ENP and ENT) and CARRY OUTPUT are provided to enable easy cascading of counters, which facilitates easy implementation of n-bit counters without using external gates. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74AC161F, TC74AC163F TC74AC161FT, TC74AC163FT Features * High speed: fmax = 170 MHz (typ.) at VCC = 5 V * Low power dissipation: ICC = 8 A (max) at Ta = 25C * High noise immunity: VNIH = VNIL = 28% VCC (min) * Symmetrical output impedance: |IOH| = IOL = 24 mA (min) * Capability of driving 50 transmission lines. tpHL Balanced propagation delays: tpLH - * Wide operating voltage range: VCC (opr) = 2 to 5.5 V * Pin and function compatible with 74F161/163 1 Weight DIP16-P-300-2.54A SOP16-P-300-1.27A TSSOP16-P-0044-0.65A : 1.00 g (typ.) : 0.18 g (typ.) : 0.06 g (typ.) 2012-02-29 TC74AC161,163P/F/FT Pin Assignment CLR 1 16 VCC CK 2 15 Carry Output A 3 14 QA B 4 13 QB C 5 12 QC D 6 11 QD ENP 7 10 ENT GND 8 9 LOAD (top view) IEC Logic Symbol CLR LOAD (1) (9) TC74AC161 CTRDIV 16 CT = 0 M2 ENT ENP CK A B C D (10) (7) (2) (3) (4) 3CT = 15 G3 (15) Carry Output C5/2, 3, 4+ (14) (1) (13) (2) (5) (12) (4) (6) (11) (8) (9) ENT ENP CK G4 1, 5D (1) CLR LOAD M1 QA A QB B QC C D QD TC74AC163 CTRDIV 16 5CT = 0 M1 M2 3CT = 15 G3 G4 (10) (7) (2) (15) Carry Output C5/2, 3, 4+ (3) 1, 5D (4) (1) (2) (4) (8) (5) (6) (14) (13) (12) (11) QA QB QC QD Truth Table (Note) Inputs Outputs CLR (163) LOAD ENP ENT CK (161) L L X X X X H H L X X H H H X L No Change No Count H H H L X No Change No Count H H H H H Count Up H X X X X No Change Note: CK (163) Function CLR (161) QA QB QC QD L L L L Reset to "0" A B C D Preset Data Count No Count X: Don't care A, B, C, D: Logic level of data inputs Carry: Carry = ENT*QA*QB*QC*QD 2 2012-02-29 TC74AC161,163P/F/FT Timing Chart CLR LOAD A Data Inputs DON'T CARE UNTIL LOAD GOES LOW B C D CK ENP ENT QA QB Outputs QC QD Carry Output 12 13 ASYNC SYNC PRESET CLEAR CLEAR (161) (163) 14 15 0 COUNT 3 1 2 INHIBIT 2012-02-29 TC74AC161,163P/F/FT System Diagram 1 CLR 10 ENT 7 ENP LOAD E E 9 L L 15 Carry Out 3 A L (Note) 2) (Note D R Q L E CK Q 14 QA E 4 B (Note) (Note 2) L L E D R Q E CK Q QB 5 C (Note) (Note 2) L L E D R Q E CK Q 12 QC 6 D (Note) (Note 2) L L E D R Q E CK Note: 13 CK 2 Q 11 QD Truth table of internal F/F TC74AC161 TC74AC163 D CK R Q Q D R Q Q X X H L H X H L H L L L H L L L H H L H L H L H L X L X L No Change CK No Change X: Don't care 4 2012-02-29 TC74AC161,163P/F/FT Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Supply voltage range VCC -0.5 to 7.0 V DC input voltage VIN -0.5 to VCC + 0.5 V VOUT -0.5 to VCC + 0.5 V Input diode current IIK 20 mA Output diode current IOK 50 mA DC output current IOUT 50 mA DC VCC/ground current ICC 125 mA Power dissipation PD 500 (DIP) (Note 2)/180 (SOP/TSSOP) mW Storage temperature Tstg -65 to 150 C DC output voltage Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = -40 to 65C. From Ta = 65 to 85C a derating factor of -10 mW/C should be applied up to 300 mW. Operating Ranges (Note) Characteristics Symbol Rating Unit Supply voltage VCC 2.0 to 5.5 V Input voltage VIN 0 to VCC V VOUT 0 to VCC V Operating temperature Topr -40 to 85 C Input rise and fall time dt/dV Output voltage Note: 0 to 100 (VCC = 3.3 0.3 V) 0 to 20 (VCC = 5 0.5 V) ns/V The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. 5 2012-02-29 TC74AC161,163P/F/FT Electrical Characteristics DC Characteristics Ta = -40 to 85C Ta = 25C Characteristics High-level input voltage Low-level input voltage High-level output voltage Symbol VIH VIL VOH Test Condition Typ. Max Min Max 2.0 1.50 1.50 3.0 2.10 2.10 5.5 3.85 3.85 2.0 0.50 0.50 3.0 0.90 0.90 5.5 1.65 1.65 2.0 1.9 2.0 1.9 3.0 2.9 3.0 2.9 VIN = VIH or IOH = -4 mA VIL 4.5 4.4 4.5 4.4 3.0 2.58 2.48 4.5 3.94 3.80 5.5 3.85 2.0 0.0 0.1 0.1 IOL = 50 A 3.0 0.0 0.1 0.1 VIN = VIH or IOL = 12 mA VIL 4.5 0.0 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 1.65 IOH = -75 mA VOL Min IOH = -50 A IOH = -24 mA Low-level output voltage VCC (V) (Note) IOL = 24 mA IOL = 75 mA (Note) Unit V V V V Input leakage current IIN VIN = VCC or GND 5.5 0.1 1.0 A Quiescent supply current ICC VIN = VCC or GND 5.5 8.0 80.0 A Note: This spec indicates the capability of driving 50 transmission lines. One output should be tested at a time for a 10 ms maximum duration. 6 2012-02-29 TC74AC161,163P/F/FT Timing Requirements (input: tr = tf = 3 ns) Characteristics Symbol Minimum pulse width tw (L) (CK) tw (H) Minimum pulse width ( CLR ) (Note 1) Minimum set-up time ( LOAD , ENP, ENT) Minimum set-up time (A, B, C, D) Minimum set-up time ( CLR ) (Note 2) Minimum hold time Minimum removal time ( CLR ) (Note 1) tw (L) Ta = -40 to 85C VCC (V) Limit Limit 3.3 0.3 7.0 7.0 5.0 0.5 5.0 5.0 3.3 0.3 7.0 7.0 5.0 0.5 5.0 5.0 3.3 0.3 11.0 13.0 5.0 0.5 7.0 7.0 3.3 0.3 8.0 8.0 5.0 0.5 4.0 4.0 3.3 0.3 6.0 6.0 5.0 0.5 4.0 4.0 3.3 0.3 1.0 1.0 5.0 0.5 1.0 1.0 3.3 0.3 6.0 6.0 5.0 0.5 4.0 4.0 Test Condition Figure 1 Figure 4 ts Figure 2, Figure 3 ts Figure 2 ts Figure 5 th Figure 2, Figure 3, Figure 5 trem Ta = 25C Figure 4 Unit ns ns ns ns ns ns ns Note 1: For TC74AC161 only Note 2: For TC74AC163 only 7 2012-02-29 TC74AC161,163P/F/FT AC Characteristics (CL = 50 pF, RL = 500 , input: tr = tf = 3 ns) Characteristics Symbol Propagation delay time tpLH (CK-Q) tpHL Propagation delay time (CK-carry, count mode) Propagation delay time tpLH tpHL tpLH (CK-carry, preset mode) tpHL Propagation delay time tpLH (ENT-carry) tpHL Propagation delay time ( CLR -Q) Figure 1 Figure 1 Figure 2 Figure 6 tpHL Figure 4 tpHL Figure 4 (Note 1) Propagation delay time ( CLR -carry) Ta = -40 to 85C Ta = 25C Test Condition Unit VCC (V) Min Typ. Max Min Max 3.3 0.3 8.8 15.8 1.0 18.0 5.0 0.5 6.5 9.6 1.0 11.0 3.3 0.3 10.4 18.4 1.0 21.6 5.0 0.5 8.1 11.8 1.0 13.5 3.3 0.3 12.9 22.4 1.0 25.5 5.0 0.5 9.1 13.2 1.0 15.0 3.3 0.3 7.5 13.2 1.0 15.0 5.0 0.5 5.8 8.3 1.0 9.5 3.3 0.3 10.6 18.4 1.0 21.0 5.0 0.5 7.7 11.4 1.0 13.0 3.3 0.3 12.0 21.0 1.0 24.0 5.0 0.5 8.6 12.7 1.0 14.5 3.3 0.3 50 110 50 5.0 0.5 90 140 90 5 10 10 pF 85 pF ns ns ns ns ns ns (Note 1) Maximum clock frequency fmax Input capacitance CIN Power dissipation capacitance CPD (Note 2 MHz Note 1: For TC74AC161 only Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD*VCC*fIN + ICC When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ICC which is obtained from the following formula: C C C C C ICC = fCK VCC QA + QB + QC + QD + CO 4 8 16 16 2 CQA to CQD and CCO are the capacitances at QA to QD and CARRY OUT, respectively. fCK is the input frequency of the CK. 8 2012-02-29 TC74AC161,163P/F/FT Switching Characteristics Test Waveform twL twH CK VCC VCC 50% 50% 50% CLR GND GND twL VOH Q, Carry VCC 50% 50% CK 50% VOL tpLH VOH Q, Carry Figure 1 GND trem tpHL Count Mode 0.5 VCC tpHL Figure 4 VOL Clear Mode (TC74AC161) VCC LOAD 50% ts 50% th ts GND th VCC 50% A to D ts 50% CLR th ts 50% GND th VCC CK 50% VCC 50% CK 50% GND GND tpLH, tpHL VOH Q, Carry VOL Figure 2 ENP, ENT VOH Q, Carry 0.5 VCC Preset Mode VOL Figure 5 Clear Mode (TC74AC163) VCC VCC 50% ts CK ENT 50% th 50% ts th 50% 50% GND GND VCC VOH 50% Carry GND tpLH 0.5 VCC 0.5 VCC tpHL VOL VOH Q VOL Figure 3 Count Enable Mode Figure 6 Cascade Mode (fix maximum count) 9 2012-02-29 TC74AC161,163P/F/FT Typical Application Parallel Carry N-Bit Counter H: COUNT L: DISABLE INPUTS LD A B C INPUTS D ENP H: COUNT L: DISABLE ENT LD A B C INPUTS D ENP Carry LD A B C D ENP ENT Carry ENT Carry CK CK CK CLR QA QB QC QD CLR QA QB QC QD CLR QA QB QC QD OUTPUTS OUTPUTS NEXT STAGE OUTPUTS CLR CK 10 2012-02-29 TC74AC161,163P/F/FT Package Dimensions Weight: 1.00 g (typ.) 11 2012-02-29 TC74AC161,163P/F/FT Package Dimensions Weight: 0.18 g (typ.) 12 2012-02-29 TC74AC161,163P/F/FT Package Dimensions Weight: 0.06 g (typ.) 13 2012-02-29 TC74AC161,163P/F/FT RESTRICTIONS ON PRODUCT USE * Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. * This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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