DS04-28216-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP For Video Applications
CMOS
8-bit 100 MSPS A/D Converter
MB40C328
■DESCRIPTION
MB40C328 is a high-speed A/D converter using a fast CMOS technology.
■FEATURES
• Resolution : 8 bit
• Linearity error : ±0.40% (standard)
• Maximum conversion rate : 100 MSPS (minimum)
• Power supply voltage : 3.3 V single (standard)
• Digital input/output voltage range: CMOS level compatible
• Analog input voltage range : 0 to 3.0 V (2 Vp-p)
• Analog input capacitance : 22 pF (standard)
• Power dissipation : 210 mW (standard)
• Additional features : Reference voltage generator circuit: VREFT = 3.0 V, VREFB = 1.0 V
High impedance output, power down function
1:2 demultiplex output enable (RESET action enable)
1/2 deviding clock output
Cross sampling at 50 MHz (two-phase CLK) enable (CLKA, CLKB)
• Package : LQFP48 (7 mm × 7 mm, lead pitch 0.5 mm)
■PACKAGE
48-pin plastic LQFP
(FPT-48P-M05)
2
MB40C328
■PIN ASSIGNMENT
(TOP VIEW)
VR2
VR1
AVDD
AVSS
VREFB
VRB
AVSS
VINA
AVDD
CKSEL
CE
AVSS
1
2
3
4
5
6
7
8
9
10
11
12
VR3
VREFT
VRT
AVDD
AVSS
DVDD
CLKOA
DVSS
DA0 (LSB)
DA1
DA2
DA3
48
47
46
45
44
43
42
41
40
39
38
37
AVDD
OE
DSEL
DVDD
CLKOB
DVSS
(MSB) DB7
DB6
DB5
DB4
DB3
DB2
13
14
15
16
17
18
19
20
21
22
23
24
DA4
DA5
DA6
DA7 (MSB)
DVSS
CLKA
CLKB
CLK
RESET
DVDD
DB0 (LSB)
DB1
36
35
34
33
32
31
30
29
28
27
26
25
3
MB40C328
■PIN DESCRIPTION
The values in parentheses are standard.
■PRECAUTIONS ON USE
• Be sure to ground the pins of AVDD, DVDD, VRT, VRB, VR1, VR2, and VR3 via high-frequency capacitor.
Place the high-frequency capacitor as close as possible to the pin.
• To avoid gener ation of undesired current o wing to indetermination of internal logic, set CE to “H” at pow ering
on and input more than five clock pulses just after operation (CE: “H” → “L”).
Pin No. Symbol Description
3, 9, 13, 45 AVDD Analog power supply (+3.3 V)
16, 27, 43 DVDD Digital power supply (+3.3 V)
4, 7, 12, 44 AVSS Analog power supply ground pin (0 V)
18, 32, 41 DVSS Digital power supply ground pin (0 V)
33 to 40 DA7 to DA0 Digital output pin (Port A) DA7: MSB, DA0: LSB
19 to 26 DB7 to DB0 Digital output pin (Port B) DB7: MSB, DB0: LSB
11 CE Power down at CE input “H” (internal pull-up resistor)
14 OE Digital output (Both Port A, B) and clock output (CLKOA, CLKOB) are high
impedance at OE input “H”.
10 CKSEL Mode of operation setting input pin (Refer to ■ MODE SETTING)
15 DSEL
28 RESET Dividing circuit reset input pin (See ■ TIMING CHART 2, 3)
29 CLK Clock input pin (max 100 MHz)
31 CLKA A ch clock input pin (max 50 MHz)
30 CLKB B ch clock input pin (max 50 MHz)
42 CLKOA Clock output pin (See ■ TIMING CHART 1 to 4)
17 CLKOB Clock output pin (See ■ TIMING CHART 1 to 4)
8V
INA Analog input pin
Input range is VRT to VRB (0 V to 3.0 V: 2 Vp-p)
2
1
48
VR1
VR2
VR3
Reference 1/4 voltage output pin (Add 0.1 µF for AVSS)
Reference 1/2 voltage output pin (Add 0.1 µF for AVSS)
Reference 3/4 voltage output pin (Add 0.1 µF for AVSS)
46 VRT Reference voltage input pin on top side
47 VREFT Reference voltage output pin
By connecting to VRT, 0.9 × AVDD ( 3 V) is generated.
6VRB Reference voltage input pin on bottom side
5V
REFB Reference voltage output pin
By connecting to VRB, 0.3 × AVDD ( 1 V) is generated.
..
=
..
=
4
MB40C328
■BLOCK DIAGRAM
CLKA
CLK
CLKB
RESET CE CLKOB AVSS DVSS OE VREFB
AVSS
AVDD VRB
DB0 to DB7
DA0 to DA7
VRT
AVDD
VREFTDVDDAVDD
CLKOA
A ch
VR3
VR2
VR1
B ch
FF
FF
VINADSELCKSEL
Timing
circuit
Timing
circuit
A output
buffer
B output
buffer
Mode
setting
CLK
select
Output selector
5
MB40C328
■ABSOLUTE MAXIMUM RATINGS
* :Do not exceed +4.0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Rating Unit
Min. Max.
Power supply voltage AVDD, DVDD –0.3 +4.0 V
Input/output voltage
VINA, VRT, VRB,
VREFT, VREFB,
VR1, VR2, VR3, CE,
CKSEL –0.3 AVDD+0.3* V
DA0 to D A7, DB0 to DB7,
CLKOA, CLKOB,
CLKA, CLKB,
CLK, DSEL, OE,
RESET
–0.3 DVDD+0.3* V
Storage temperature TSTG –55 +125 °C
6
MB40C328
■RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Value Unit
Min. Typ. Max.
Power supply voltage AVDD, DVDD 3.00 3.30 3.60 V
Analog input voltage VINA VRB —VRT V
Analog reference voltage: T VRT — — 3.00 V
Analog reference voltage: B VRB 0.00 — — V
Analog reference voltage range VRT – VRB 1.90 2.00 2.10 V
Digital “H” level
input voltage
OE, DSEL, RESET,
CLK, CLKA, CLKB VIHD DVDD – 0.5 — — V
CKSEL, CE AVDD – 0.5 — — V
Digital “L” level input
voltage
OE, DSEL, RESET,
CLK, CLKA, CLKB VILD ——0.5V
CKSEL, CE ——0.5V
Digital input current IID –20 — 5 µA
Single-phase clock frequency fCLK 0.1 — 100 MHz
Two-phase clock frequency fCLKA, fCLKB 0.1 — 50 MHz
Minimum clock pulse width (single-phase) tWS+, tWS–4.0 5.0 — ns
Minimum clock pulse width (two-phase) tWD+, tWD–8.0 10.0 — ns
Clock pulse rising/falling time tr, tf—2.0—ns
RESET signal setup time ts3.0 — — ns
RESET signal hold time th3.0 — — ns
Operating temperature range Ta –20 — 70 °C
7
MB40C328
■ELECTRICAL CHARACTERISTICS
• DC Characteristics in Analog Section
(AVDD = DVDD = 3.00 V to 3.60 V, Ta = –20°C to +70°C)
• DC Characteristics in Digital Section
(AVDD = DVDD = 3.00 V to 3.60 V, Ta = –20°C to +70°C)
Parameter Symbol Value Unit
Min. Typ. Max.
Resolution — — 8 — bit
Linearity error LE — ±0.40 ±0.6 %
Differential linearity error DLE — ±0.20 ±0.36 %
Analog input capacity CINA —22—pF
Reference voltage: T VREFT 0.88 × AVDD 0.91 × AVDD 0.94 × AVDD V
Reference voltage: B VREFB 0.27 × AVDD 0.3 × AVDD 0.33 × AVDD V
Reference current IRB –15 –10 — mA
Analog supply current AIDD —42.085.0mA
Digital supply current DIDD —20.040.0mA
Standby current ISB — 100 — mA
Parameter Symbol Value Unit
Min. Typ. Max.
Digital “H” level output voltage VOHD DVDD – 0.4 — DVDD V
Digital “L” level output voltage VOLD ——0.4V
Digital “H” level output current IOHD –400 — — µA
Digital “L” level output current IOLD ——1.6mA
8
MB40C328
• Switching Characteristics
(AVDD = DVDD = 3.00 V to 3.60 V, Ta = –20°C to +70°C)
■DIGITAL OUTPUT BUFFER LOAD CIRCUIT
■MODE SETTING
Parameter Symbol Value Unit
Min. Typ. Max.
Maximum conversion rate fS100 — — MSPS
Aperture time tAD —1.7—ns
Digital output
delay time
Timing chart 1 tpdS 2.5 6.0 9.0 ns
tpdSO tWS+ + 2.5 tWS+ + 6.0 tWS+ + 10 ns
Timing chart 2 tpdM1 2.5 5.5 10 ns
tpdM1O T + 2.5 T + 5.5 T + 10 ns
Timing chart 3 tpdM2 2.5 5.5 10 ns
tpdM2O T + 2.5 T + 5.5 T + 10 ns
Timing chart 4 tpdD 2.5 6.5 11 ns
tpdDO tWD+ + 2.5 tWD+ + 6.5 tWD+ + 11 ns
CKCEL DCEL Mode Timing Chart
H H CLK input-straight output mode Timing chart 1
H L CLK input-demultiplex output (in-phase) mode Timing chart 2
L H CLK input-demultiplex output (two-phase) mode Timing chart 3
L L Two-phase CLK input mode (CLKA, CLKB) Timing chart 4
DVSS
CL = 18 pF
Measurement point
To the
measurement
point
Note: CL includes a stray capacitance of a probe and a fixture.
9
MB40C328
■TIMING CHART 1
CLK input-straight output mode
• CLK = 100 MHz (max)
• CLKA = CLKB = “L” (DVSS)
• CKSEL = “H” (AVDD)
•DSEL = “H” (DVDD)
• RESET = “H” (DVDD)
•CE
= “L” (AVSS)
•OE
= “L” (DVSS)
•V
INA input — Sampling at CLK rising
•D
A0 to DA7 — Output (after 5 CLK + tpdS from Sampling) at CLK rising
VIHD
VIHD
VOHD
VOLD
DA0 to DA7
VOHD
VOLD
DB0 to DB7
VOHD
VOLD
CLKOA
VOHD
VOLD
CLKOB
DVDDI − 0.5 V
0.5 V
0.4 V
N
N + 1
DVDD − 0.4 V
0.4 V
tAD
tftrtWS+tWS−
N − 3N − 2N − 1N − 4N − 5N − 6N − 7
N − 1N + 1N + 2N + 3N + 4N + 5N + 6N + 7N
tpdSO(typ)
tpdSO(min)
tpdSO(max)
DVDD − 0.4 V
tpdS (min)
1.5 V
tpdS (max)
tpdS (typ)
CLK input
ALL “L” fix
ALL “L” fix
VINA input
10
MB40C328
■TIMING CHART 2
CLK input-demultiplex output (in-phase) mode
• CLK = 100 MHz (max)
• CLKA = CLKB = “L” (DVSS)
• CKSEL = “H” (AVDD)
• DSEL = “L” (DVSS)
•CE = “L” (AVSS)
•OE
= “L” (DVSS)
•V
INA input — Sampling at CLK rising
•DA0 to DA7 — Output (after 5 CLK + tpdM1 from Sampling) at CLK rising
•DB0 to DB7 — Output (after 6 CLK + tpdM1 from Sampling) at CLK rising
VOHD
VOLD
DA0 to DA7
VOHD
VOLD
N − 10
or N − 11 N − 10
or N − 9
N − 9
or N − 10 N − 9
or N − 8
N − 8
or N − 9 N − 8
or N − 7 N − 6
or N − 7 N − 4
or N − 5 N − 2
N + 1
N
or N − 3
N − 1
or N − 2
N − 3
or N − 4
N − 5
or N − 6
N − 7
or N − 8
DB0 to DB7
VOHD
VOLD
CLKOA
VOHD
VOLD
CLKOB
VIHD
VILD
VIHD
VILD
thtSthtS
1.5 V
1.5 V
DVDD − 0.4 V
0.4 V
tpdM1O(typ)
tpdM1O(max)
tpdM1O(min)
tpdM1(typ)
tpdM1(min)
tpdM1(max)
tpdM1(typ)
tpdM1(max)
tpdM1(min)
N + 2
N + 3
DVDD − 0.4 V
0.4V
DVDD − 0.4 V
0.4V
trtfTtWS+tWS−
tAD
N
N − 1 N − 2 N − 1 N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9 N + 10
0.5 V
DVDD − 0.5 V
CLK input
ALL “L” fix
RESET input
VINA input
11
MB40C328
■TIMING CHART 3
CLK input-demultiplex output (two-phase) mode
• CLK = 100 MHz (max)
• CLKA = CLKB = “L” (DVSS)
• CKSEL = “L” (AVSS)
•DSEL = “H” (DVDD)
•CE = “L” (AVSS)
•OE
= “L” (DVSS)
•V
INA input — Sampling at CLK rising
•D
A0 to DA7 — Output (after 5 CLK + tpdM2 from Sampling) at CLK rising
•DB0 to DB7 — Output (after 5 CLK + tpdM2 from Sampling) at CLK rising
VIHD
VILD
VOHD
VOLD
VOHD
VOLD
DB0 to DB7
DA0 to DA7
VOHD
VOLD
CLKOA
VOHD
VOLD
CLKOB
VIHD
VILD
tr
tAD
DVDD − 0.5 V
tf
N + 1N + 2N + 3N + 4N + 5N + 10
N + 9N + 8N + 7N + 6
tWS+
thtSthtS
tWS−
N
N
0.5 V 1.5 V
T
or N − 10
or N − 9
or N − 8N − 7
or N − 8N − 5
or N − 6N − 3
or N − 4N − 1
or N − 20.4 V
DVDD − 0.4 V
tpdM2(max)
tpdM2(typ)
0.4 V
DVDD−0.4 V
tpdM2(max)
tpdM2(typ)
tpdM2(min)
0.4 V
DVDD − 0.4 V
tpdM2O(max)
tpdM2O(typ)
tpdM2O(min)
0.4 V
DVDD − 0.4 V
tpdM2O(max)
tpdM2O(typ)
tpdM2O(min)
N − 10 or N − 9
N − 8or N − 7
N − 8
or N − 7
N − 6or N − 5
N − 4or N − 3
N − 2
1.5 V
tpdM2(min) N + 1
N − 3N − 1
N − 2
N − 9N − 9
N + 3
N + 2
CLK input
RESET input
VINA input
12
MB40C328
■TIMING CHART 4
Two-phase CLK input mode (CLKA, CLKB)
• CLK = “L” (DVSS) or “H” (DVDD)
• CLKA = CLKB = 50 MHz (max)
• CKSEL = “L” (AVSS)
• DSEL = “L” (DVSS)
• RESET = “H” (DVDD) or “L” (DVSS)
•CE
= “L” (AVSS)
•OE
= “L” (DVSS)
•V
INA input — Sampling (A ch) at CLKA falling
Sampling (B ch) at CLKB falling
•DA0 to DA7 — Output (after 2.5 CLK + tpdD from Sampling) at CLKA rising
•D
B0 to DB7 — Output (after 2.5 CLK + tpdD from Sampling) at CLKB rising
tpdD(max)
tpdD(typ)
tpdD(min)
tpdD(max)
tpdD(typ)
tpdD(min)
VIHD
VILD
VIHD
VILD
VOHD
VOLD
DA0 to DA7
VOHD
VOLD
DB0 to DB7
VOHD
VOLD
CLKOA
VOHD
VOLD
CLKOB
tWD−tWD+
tWD+
tAD
N(Ach) N + 1(Bch)
N − 6
N − 5N − 3N − 1
N + 1
N − 4N − 2
N + 2(Ach) N + 3(Bch) N + 4(Ach) N + 5(Bch) N + 6(Ach) N + 7(Bch)
tAD
tWD−
trtf
0.5 V
trtf
0.5 V
1.5 V
1.5 V
N
DVDD−0.4 V
0.4 V
DVDD − 0.4 V
0.4 V
0.4 V
DVDD − 0.4 V
tpdDO(max)
tpdDO(min)
tpdDO(typ)
tpdDO(max.)
tpdDO(min.)
0.4 V
tpdDO(typ)
DVDD − 0.4 V
DVDD − 0.5 V
DVDD − 0.5 V
DA0 to DA7
CLKA input
CLKB input
VINA input
13
MB40C328
■TYPICAL CONNECTION EXAMPLE
+
+
VR2
VR1
AVDD
AVSS
VREFB
VRB
AVSS
VINA
AVDD
CKSEL
CE
AVSS
1
2
3
4
5
6
7
8
9
10
11
12
DA4
DA5
DA6
(MSB)DA7
DVSS
CLKA
CLKB
CLK
RESET
DVDD
(LSB)DB0
DB1
DA4
DA5
DA6
DA7(MSB)
CLKA
CLKB
CLK
RESET
DB0(LSB)
DB1
36
35
34
33
32
31
30
29
28
27
26
25
AVDD
OE
DSEL
DVDD
CLKOB
DVSS
DB7(MSB)
DB6
DB5
DB4
DB3
DB2
13
14
15
16
17
18
19
20
21
22
23
24
OE
DSEL
CLKOB
(MSB)DB7
DB6
DB5
DB4
DB3
DB2
VR3
VREFT
VRT
AVDD
AVSS
DVDD
CLKOA
DVSS
(LSB)DA0
DA1
DA2
DA3
CLKOA
DA0(LSB)
DA1
DA2
DA3
48
47
46
45
44
43
42
41
40
39
38
37
(TOP VIEW)
+3.3 V +3.3 V
VRB
VINA
CKSEL
CE
VRT
+
0.1 µF
To avoid voltage fluctuation at operation of reference voltage generator circuit (VREFT, VREFB)
VREFT: 150 µF, VREFB: 330 µF
14
MB40C328
■ORDERING INFORMATION
Part number Package Remark
MB40C328PFV 48-pin Plastic LQFP
(FPT-48P-M05)
15
MB40C328
■PACKAGE DIMENSION
C
1998 FUJITSU LIMITED F48013S-3C-6
0.08(.003)
0.50±0.08
(.020±.003)
9.00±0.20(.354±.008)SQ
.007 –.001
+.003
–0.03
+0.08
0.18
.059 –.004
+.008
–0.10
+0.20
1.50
7.00±0.10(.276±.004)SQ
"A"
Details of "A" part
0~8°
25
24
13
121
48
37
36
INDEX
(Mounting height)
0.145±0.055
(.006±.002)
0.50±0.20
(.020±.008)
0.45/0.75
(.018/.030) 0.25(.010)
(.004±.004)
0.10±0.10
M
0.08(.003)
(Stand off)
LEAD No.
Dimensions in mm (inches).
48-pin Plastic LQFP
(FPT-48P-M05) Note ) Pins width and pins thickness include plating thickness.
MB40C328
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0001
FUJITSU LIMITED Printed in Japan
